1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/cpu/icc_bus.h" 57 #include "hw/boards.h" 58 #include "hw/pci/pci_host.h" 59 60 /* debug PC/ISA interrupts */ 61 //#define DEBUG_IRQ 62 63 #ifdef DEBUG_IRQ 64 #define DPRINTF(fmt, ...) \ 65 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 66 #else 67 #define DPRINTF(fmt, ...) 68 #endif 69 70 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 71 #define ACPI_DATA_SIZE 0x10000 72 #define BIOS_CFG_IOPORT 0x510 73 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 74 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 75 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 76 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 77 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 78 79 #define E820_NR_ENTRIES 16 80 81 struct e820_entry { 82 uint64_t address; 83 uint64_t length; 84 uint32_t type; 85 } QEMU_PACKED __attribute((__aligned__(4))); 86 87 struct e820_table { 88 uint32_t count; 89 struct e820_entry entry[E820_NR_ENTRIES]; 90 } QEMU_PACKED __attribute((__aligned__(4))); 91 92 static struct e820_table e820_table; 93 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 94 95 void gsi_handler(void *opaque, int n, int level) 96 { 97 GSIState *s = opaque; 98 99 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 100 if (n < ISA_NUM_IRQS) { 101 qemu_set_irq(s->i8259_irq[n], level); 102 } 103 qemu_set_irq(s->ioapic_irq[n], level); 104 } 105 106 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 107 unsigned size) 108 { 109 } 110 111 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 112 { 113 return 0xffffffffffffffffULL; 114 } 115 116 /* MSDOS compatibility mode FPU exception support */ 117 static qemu_irq ferr_irq; 118 119 void pc_register_ferr_irq(qemu_irq irq) 120 { 121 ferr_irq = irq; 122 } 123 124 /* XXX: add IGNNE support */ 125 void cpu_set_ferr(CPUX86State *s) 126 { 127 qemu_irq_raise(ferr_irq); 128 } 129 130 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 131 unsigned size) 132 { 133 qemu_irq_lower(ferr_irq); 134 } 135 136 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 137 { 138 return 0xffffffffffffffffULL; 139 } 140 141 /* TSC handling */ 142 uint64_t cpu_get_tsc(CPUX86State *env) 143 { 144 return cpu_get_ticks(); 145 } 146 147 /* SMM support */ 148 149 static cpu_set_smm_t smm_set; 150 static void *smm_arg; 151 152 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 153 { 154 assert(smm_set == NULL); 155 assert(smm_arg == NULL); 156 smm_set = callback; 157 smm_arg = arg; 158 } 159 160 void cpu_smm_update(CPUX86State *env) 161 { 162 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 163 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 164 } 165 } 166 167 168 /* IRQ handling */ 169 int cpu_get_pic_interrupt(CPUX86State *env) 170 { 171 int intno; 172 173 intno = apic_get_interrupt(env->apic_state); 174 if (intno >= 0) { 175 return intno; 176 } 177 /* read the irq from the PIC */ 178 if (!apic_accept_pic_intr(env->apic_state)) { 179 return -1; 180 } 181 182 intno = pic_read_irq(isa_pic); 183 return intno; 184 } 185 186 static void pic_irq_request(void *opaque, int irq, int level) 187 { 188 CPUState *cs = first_cpu; 189 X86CPU *cpu = X86_CPU(cs); 190 CPUX86State *env = &cpu->env; 191 192 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 193 if (env->apic_state) { 194 while (cs) { 195 cpu = X86_CPU(cs); 196 env = &cpu->env; 197 if (apic_accept_pic_intr(env->apic_state)) { 198 apic_deliver_pic_intr(env->apic_state, level); 199 } 200 cs = cs->next_cpu; 201 } 202 } else { 203 if (level) { 204 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 205 } else { 206 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 207 } 208 } 209 } 210 211 /* PC cmos mappings */ 212 213 #define REG_EQUIPMENT_BYTE 0x14 214 215 static int cmos_get_fd_drive_type(FDriveType fd0) 216 { 217 int val; 218 219 switch (fd0) { 220 case FDRIVE_DRV_144: 221 /* 1.44 Mb 3"5 drive */ 222 val = 4; 223 break; 224 case FDRIVE_DRV_288: 225 /* 2.88 Mb 3"5 drive */ 226 val = 5; 227 break; 228 case FDRIVE_DRV_120: 229 /* 1.2 Mb 5"5 drive */ 230 val = 2; 231 break; 232 case FDRIVE_DRV_NONE: 233 default: 234 val = 0; 235 break; 236 } 237 return val; 238 } 239 240 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 241 int16_t cylinders, int8_t heads, int8_t sectors) 242 { 243 rtc_set_memory(s, type_ofs, 47); 244 rtc_set_memory(s, info_ofs, cylinders); 245 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 246 rtc_set_memory(s, info_ofs + 2, heads); 247 rtc_set_memory(s, info_ofs + 3, 0xff); 248 rtc_set_memory(s, info_ofs + 4, 0xff); 249 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 250 rtc_set_memory(s, info_ofs + 6, cylinders); 251 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 252 rtc_set_memory(s, info_ofs + 8, sectors); 253 } 254 255 /* convert boot_device letter to something recognizable by the bios */ 256 static int boot_device2nibble(char boot_device) 257 { 258 switch(boot_device) { 259 case 'a': 260 case 'b': 261 return 0x01; /* floppy boot */ 262 case 'c': 263 return 0x02; /* hard drive boot */ 264 case 'd': 265 return 0x03; /* CD-ROM boot */ 266 case 'n': 267 return 0x04; /* Network boot */ 268 } 269 return 0; 270 } 271 272 static int set_boot_dev(ISADevice *s, const char *boot_device) 273 { 274 #define PC_MAX_BOOT_DEVICES 3 275 int nbds, bds[3] = { 0, }; 276 int i; 277 278 nbds = strlen(boot_device); 279 if (nbds > PC_MAX_BOOT_DEVICES) { 280 error_report("Too many boot devices for PC"); 281 return(1); 282 } 283 for (i = 0; i < nbds; i++) { 284 bds[i] = boot_device2nibble(boot_device[i]); 285 if (bds[i] == 0) { 286 error_report("Invalid boot device for PC: '%c'", 287 boot_device[i]); 288 return(1); 289 } 290 } 291 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 292 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 293 return(0); 294 } 295 296 static int pc_boot_set(void *opaque, const char *boot_device) 297 { 298 return set_boot_dev(opaque, boot_device); 299 } 300 301 typedef struct pc_cmos_init_late_arg { 302 ISADevice *rtc_state; 303 BusState *idebus[2]; 304 } pc_cmos_init_late_arg; 305 306 static void pc_cmos_init_late(void *opaque) 307 { 308 pc_cmos_init_late_arg *arg = opaque; 309 ISADevice *s = arg->rtc_state; 310 int16_t cylinders; 311 int8_t heads, sectors; 312 int val; 313 int i, trans; 314 315 val = 0; 316 if (ide_get_geometry(arg->idebus[0], 0, 317 &cylinders, &heads, §ors) >= 0) { 318 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 319 val |= 0xf0; 320 } 321 if (ide_get_geometry(arg->idebus[0], 1, 322 &cylinders, &heads, §ors) >= 0) { 323 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 324 val |= 0x0f; 325 } 326 rtc_set_memory(s, 0x12, val); 327 328 val = 0; 329 for (i = 0; i < 4; i++) { 330 /* NOTE: ide_get_geometry() returns the physical 331 geometry. It is always such that: 1 <= sects <= 63, 1 332 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 333 geometry can be different if a translation is done. */ 334 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 335 &cylinders, &heads, §ors) >= 0) { 336 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 337 assert((trans & ~3) == 0); 338 val |= trans << (i * 2); 339 } 340 } 341 rtc_set_memory(s, 0x39, val); 342 343 qemu_unregister_reset(pc_cmos_init_late, opaque); 344 } 345 346 typedef struct RTCCPUHotplugArg { 347 Notifier cpu_added_notifier; 348 ISADevice *rtc_state; 349 } RTCCPUHotplugArg; 350 351 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 352 { 353 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 354 cpu_added_notifier); 355 ISADevice *s = arg->rtc_state; 356 357 /* increment the number of CPUs */ 358 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 359 } 360 361 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 362 const char *boot_device, 363 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 364 ISADevice *s) 365 { 366 int val, nb, i; 367 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 368 static pc_cmos_init_late_arg arg; 369 static RTCCPUHotplugArg cpu_hotplug_cb; 370 371 /* various important CMOS locations needed by PC/Bochs bios */ 372 373 /* memory size */ 374 /* base memory (first MiB) */ 375 val = MIN(ram_size / 1024, 640); 376 rtc_set_memory(s, 0x15, val); 377 rtc_set_memory(s, 0x16, val >> 8); 378 /* extended memory (next 64MiB) */ 379 if (ram_size > 1024 * 1024) { 380 val = (ram_size - 1024 * 1024) / 1024; 381 } else { 382 val = 0; 383 } 384 if (val > 65535) 385 val = 65535; 386 rtc_set_memory(s, 0x17, val); 387 rtc_set_memory(s, 0x18, val >> 8); 388 rtc_set_memory(s, 0x30, val); 389 rtc_set_memory(s, 0x31, val >> 8); 390 /* memory between 16MiB and 4GiB */ 391 if (ram_size > 16 * 1024 * 1024) { 392 val = (ram_size - 16 * 1024 * 1024) / 65536; 393 } else { 394 val = 0; 395 } 396 if (val > 65535) 397 val = 65535; 398 rtc_set_memory(s, 0x34, val); 399 rtc_set_memory(s, 0x35, val >> 8); 400 /* memory above 4GiB */ 401 val = above_4g_mem_size / 65536; 402 rtc_set_memory(s, 0x5b, val); 403 rtc_set_memory(s, 0x5c, val >> 8); 404 rtc_set_memory(s, 0x5d, val >> 16); 405 406 /* set the number of CPU */ 407 rtc_set_memory(s, 0x5f, smp_cpus - 1); 408 /* init CPU hotplug notifier */ 409 cpu_hotplug_cb.rtc_state = s; 410 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 411 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 412 413 if (set_boot_dev(s, boot_device)) { 414 exit(1); 415 } 416 417 /* floppy type */ 418 if (floppy) { 419 for (i = 0; i < 2; i++) { 420 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 421 } 422 } 423 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 424 cmos_get_fd_drive_type(fd_type[1]); 425 rtc_set_memory(s, 0x10, val); 426 427 val = 0; 428 nb = 0; 429 if (fd_type[0] < FDRIVE_DRV_NONE) { 430 nb++; 431 } 432 if (fd_type[1] < FDRIVE_DRV_NONE) { 433 nb++; 434 } 435 switch (nb) { 436 case 0: 437 break; 438 case 1: 439 val |= 0x01; /* 1 drive, ready for boot */ 440 break; 441 case 2: 442 val |= 0x41; /* 2 drives, ready for boot */ 443 break; 444 } 445 val |= 0x02; /* FPU is there */ 446 val |= 0x04; /* PS/2 mouse installed */ 447 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 448 449 /* hard drives */ 450 arg.rtc_state = s; 451 arg.idebus[0] = idebus0; 452 arg.idebus[1] = idebus1; 453 qemu_register_reset(pc_cmos_init_late, &arg); 454 } 455 456 #define TYPE_PORT92 "port92" 457 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 458 459 /* port 92 stuff: could be split off */ 460 typedef struct Port92State { 461 ISADevice parent_obj; 462 463 MemoryRegion io; 464 uint8_t outport; 465 qemu_irq *a20_out; 466 } Port92State; 467 468 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 469 unsigned size) 470 { 471 Port92State *s = opaque; 472 473 DPRINTF("port92: write 0x%02x\n", val); 474 s->outport = val; 475 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 476 if (val & 1) { 477 qemu_system_reset_request(); 478 } 479 } 480 481 static uint64_t port92_read(void *opaque, hwaddr addr, 482 unsigned size) 483 { 484 Port92State *s = opaque; 485 uint32_t ret; 486 487 ret = s->outport; 488 DPRINTF("port92: read 0x%02x\n", ret); 489 return ret; 490 } 491 492 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 493 { 494 Port92State *s = PORT92(dev); 495 496 s->a20_out = a20_out; 497 } 498 499 static const VMStateDescription vmstate_port92_isa = { 500 .name = "port92", 501 .version_id = 1, 502 .minimum_version_id = 1, 503 .minimum_version_id_old = 1, 504 .fields = (VMStateField []) { 505 VMSTATE_UINT8(outport, Port92State), 506 VMSTATE_END_OF_LIST() 507 } 508 }; 509 510 static void port92_reset(DeviceState *d) 511 { 512 Port92State *s = PORT92(d); 513 514 s->outport &= ~1; 515 } 516 517 static const MemoryRegionOps port92_ops = { 518 .read = port92_read, 519 .write = port92_write, 520 .impl = { 521 .min_access_size = 1, 522 .max_access_size = 1, 523 }, 524 .endianness = DEVICE_LITTLE_ENDIAN, 525 }; 526 527 static void port92_initfn(Object *obj) 528 { 529 Port92State *s = PORT92(obj); 530 531 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 532 533 s->outport = 0; 534 } 535 536 static void port92_realizefn(DeviceState *dev, Error **errp) 537 { 538 ISADevice *isadev = ISA_DEVICE(dev); 539 Port92State *s = PORT92(dev); 540 541 isa_register_ioport(isadev, &s->io, 0x92); 542 } 543 544 static void port92_class_initfn(ObjectClass *klass, void *data) 545 { 546 DeviceClass *dc = DEVICE_CLASS(klass); 547 548 dc->no_user = 1; 549 dc->realize = port92_realizefn; 550 dc->reset = port92_reset; 551 dc->vmsd = &vmstate_port92_isa; 552 } 553 554 static const TypeInfo port92_info = { 555 .name = TYPE_PORT92, 556 .parent = TYPE_ISA_DEVICE, 557 .instance_size = sizeof(Port92State), 558 .instance_init = port92_initfn, 559 .class_init = port92_class_initfn, 560 }; 561 562 static void port92_register_types(void) 563 { 564 type_register_static(&port92_info); 565 } 566 567 type_init(port92_register_types) 568 569 static void handle_a20_line_change(void *opaque, int irq, int level) 570 { 571 X86CPU *cpu = opaque; 572 573 /* XXX: send to all CPUs ? */ 574 /* XXX: add logic to handle multiple A20 line sources */ 575 x86_cpu_set_a20(cpu, level); 576 } 577 578 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 579 { 580 int index = le32_to_cpu(e820_table.count); 581 struct e820_entry *entry; 582 583 if (index >= E820_NR_ENTRIES) 584 return -EBUSY; 585 entry = &e820_table.entry[index++]; 586 587 entry->address = cpu_to_le64(address); 588 entry->length = cpu_to_le64(length); 589 entry->type = cpu_to_le32(type); 590 591 e820_table.count = cpu_to_le32(index); 592 return index; 593 } 594 595 /* Calculates the limit to CPU APIC ID values 596 * 597 * This function returns the limit for the APIC ID value, so that all 598 * CPU APIC IDs are < pc_apic_id_limit(). 599 * 600 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 601 */ 602 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 603 { 604 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 605 } 606 607 static FWCfgState *bochs_bios_init(void) 608 { 609 FWCfgState *fw_cfg; 610 uint8_t *smbios_table; 611 size_t smbios_len; 612 uint64_t *numa_fw_cfg; 613 int i, j; 614 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 615 616 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 617 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 618 * 619 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 620 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 621 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 622 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 623 * may see". 624 * 625 * So, this means we must not use max_cpus, here, but the maximum possible 626 * APIC ID value, plus one. 627 * 628 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 629 * the APIC ID, not the "CPU index" 630 */ 631 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 632 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 633 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 634 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 635 acpi_tables, acpi_tables_len); 636 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 637 638 smbios_table = smbios_get_table(&smbios_len); 639 if (smbios_table) 640 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 641 smbios_table, smbios_len); 642 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 643 &e820_table, sizeof(e820_table)); 644 645 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 646 /* allocate memory for the NUMA channel: one (64bit) word for the number 647 * of nodes, one word for each VCPU->node and one word for each node to 648 * hold the amount of memory. 649 */ 650 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 651 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 652 for (i = 0; i < max_cpus; i++) { 653 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 654 assert(apic_id < apic_id_limit); 655 for (j = 0; j < nb_numa_nodes; j++) { 656 if (test_bit(i, node_cpumask[j])) { 657 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 658 break; 659 } 660 } 661 } 662 for (i = 0; i < nb_numa_nodes; i++) { 663 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); 664 } 665 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 666 (1 + apic_id_limit + nb_numa_nodes) * 667 sizeof(*numa_fw_cfg)); 668 669 return fw_cfg; 670 } 671 672 static long get_file_size(FILE *f) 673 { 674 long where, size; 675 676 /* XXX: on Unix systems, using fstat() probably makes more sense */ 677 678 where = ftell(f); 679 fseek(f, 0, SEEK_END); 680 size = ftell(f); 681 fseek(f, where, SEEK_SET); 682 683 return size; 684 } 685 686 static void load_linux(FWCfgState *fw_cfg, 687 const char *kernel_filename, 688 const char *initrd_filename, 689 const char *kernel_cmdline, 690 hwaddr max_ram_size) 691 { 692 uint16_t protocol; 693 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 694 uint32_t initrd_max; 695 uint8_t header[8192], *setup, *kernel, *initrd_data; 696 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 697 FILE *f; 698 char *vmode; 699 700 /* Align to 16 bytes as a paranoia measure */ 701 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 702 703 /* load the kernel header */ 704 f = fopen(kernel_filename, "rb"); 705 if (!f || !(kernel_size = get_file_size(f)) || 706 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 707 MIN(ARRAY_SIZE(header), kernel_size)) { 708 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 709 kernel_filename, strerror(errno)); 710 exit(1); 711 } 712 713 /* kernel protocol version */ 714 #if 0 715 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 716 #endif 717 if (ldl_p(header+0x202) == 0x53726448) { 718 protocol = lduw_p(header+0x206); 719 } else { 720 /* This looks like a multiboot kernel. If it is, let's stop 721 treating it like a Linux kernel. */ 722 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 723 kernel_cmdline, kernel_size, header)) { 724 return; 725 } 726 protocol = 0; 727 } 728 729 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 730 /* Low kernel */ 731 real_addr = 0x90000; 732 cmdline_addr = 0x9a000 - cmdline_size; 733 prot_addr = 0x10000; 734 } else if (protocol < 0x202) { 735 /* High but ancient kernel */ 736 real_addr = 0x90000; 737 cmdline_addr = 0x9a000 - cmdline_size; 738 prot_addr = 0x100000; 739 } else { 740 /* High and recent kernel */ 741 real_addr = 0x10000; 742 cmdline_addr = 0x20000; 743 prot_addr = 0x100000; 744 } 745 746 #if 0 747 fprintf(stderr, 748 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 749 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 750 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 751 real_addr, 752 cmdline_addr, 753 prot_addr); 754 #endif 755 756 /* highest address for loading the initrd */ 757 if (protocol >= 0x203) { 758 initrd_max = ldl_p(header+0x22c); 759 } else { 760 initrd_max = 0x37ffffff; 761 } 762 763 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 764 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 765 766 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 767 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 768 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 769 770 if (protocol >= 0x202) { 771 stl_p(header+0x228, cmdline_addr); 772 } else { 773 stw_p(header+0x20, 0xA33F); 774 stw_p(header+0x22, cmdline_addr-real_addr); 775 } 776 777 /* handle vga= parameter */ 778 vmode = strstr(kernel_cmdline, "vga="); 779 if (vmode) { 780 unsigned int video_mode; 781 /* skip "vga=" */ 782 vmode += 4; 783 if (!strncmp(vmode, "normal", 6)) { 784 video_mode = 0xffff; 785 } else if (!strncmp(vmode, "ext", 3)) { 786 video_mode = 0xfffe; 787 } else if (!strncmp(vmode, "ask", 3)) { 788 video_mode = 0xfffd; 789 } else { 790 video_mode = strtol(vmode, NULL, 0); 791 } 792 stw_p(header+0x1fa, video_mode); 793 } 794 795 /* loader type */ 796 /* High nybble = B reserved for QEMU; low nybble is revision number. 797 If this code is substantially changed, you may want to consider 798 incrementing the revision. */ 799 if (protocol >= 0x200) { 800 header[0x210] = 0xB0; 801 } 802 /* heap */ 803 if (protocol >= 0x201) { 804 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 805 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 806 } 807 808 /* load initrd */ 809 if (initrd_filename) { 810 if (protocol < 0x200) { 811 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 812 exit(1); 813 } 814 815 initrd_size = get_image_size(initrd_filename); 816 if (initrd_size < 0) { 817 fprintf(stderr, "qemu: error reading initrd %s\n", 818 initrd_filename); 819 exit(1); 820 } 821 822 initrd_addr = (initrd_max-initrd_size) & ~4095; 823 824 initrd_data = g_malloc(initrd_size); 825 load_image(initrd_filename, initrd_data); 826 827 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 828 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 829 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 830 831 stl_p(header+0x218, initrd_addr); 832 stl_p(header+0x21c, initrd_size); 833 } 834 835 /* load kernel and setup */ 836 setup_size = header[0x1f1]; 837 if (setup_size == 0) { 838 setup_size = 4; 839 } 840 setup_size = (setup_size+1)*512; 841 kernel_size -= setup_size; 842 843 setup = g_malloc(setup_size); 844 kernel = g_malloc(kernel_size); 845 fseek(f, 0, SEEK_SET); 846 if (fread(setup, 1, setup_size, f) != setup_size) { 847 fprintf(stderr, "fread() failed\n"); 848 exit(1); 849 } 850 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 851 fprintf(stderr, "fread() failed\n"); 852 exit(1); 853 } 854 fclose(f); 855 memcpy(setup, header, MIN(sizeof(header), setup_size)); 856 857 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 858 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 859 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 860 861 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 862 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 863 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 864 865 option_rom[nb_option_roms].name = "linuxboot.bin"; 866 option_rom[nb_option_roms].bootindex = 0; 867 nb_option_roms++; 868 } 869 870 #define NE2000_NB_MAX 6 871 872 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 873 0x280, 0x380 }; 874 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 875 876 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 877 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; 878 879 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 880 { 881 static int nb_ne2k = 0; 882 883 if (nb_ne2k == NE2000_NB_MAX) 884 return; 885 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 886 ne2000_irq[nb_ne2k], nd); 887 nb_ne2k++; 888 } 889 890 DeviceState *cpu_get_current_apic(void) 891 { 892 if (current_cpu) { 893 X86CPU *cpu = X86_CPU(current_cpu); 894 return cpu->env.apic_state; 895 } else { 896 return NULL; 897 } 898 } 899 900 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 901 { 902 X86CPU *cpu = opaque; 903 904 if (level) { 905 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 906 } 907 } 908 909 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 910 DeviceState *icc_bridge, Error **errp) 911 { 912 X86CPU *cpu; 913 Error *local_err = NULL; 914 915 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 916 if (local_err != NULL) { 917 error_propagate(errp, local_err); 918 return NULL; 919 } 920 921 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 922 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 923 924 if (local_err) { 925 error_propagate(errp, local_err); 926 object_unref(OBJECT(cpu)); 927 cpu = NULL; 928 } 929 return cpu; 930 } 931 932 static const char *current_cpu_model; 933 934 void pc_hot_add_cpu(const int64_t id, Error **errp) 935 { 936 DeviceState *icc_bridge; 937 int64_t apic_id = x86_cpu_apic_id_from_index(id); 938 939 if (id < 0) { 940 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 941 return; 942 } 943 944 if (cpu_exists(apic_id)) { 945 error_setg(errp, "Unable to add CPU: %" PRIi64 946 ", it already exists", id); 947 return; 948 } 949 950 if (id >= max_cpus) { 951 error_setg(errp, "Unable to add CPU: %" PRIi64 952 ", max allowed: %d", id, max_cpus - 1); 953 return; 954 } 955 956 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 957 TYPE_ICC_BRIDGE, NULL)); 958 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 959 } 960 961 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 962 { 963 int i; 964 X86CPU *cpu = NULL; 965 Error *error = NULL; 966 967 /* init CPUs */ 968 if (cpu_model == NULL) { 969 #ifdef TARGET_X86_64 970 cpu_model = "qemu64"; 971 #else 972 cpu_model = "qemu32"; 973 #endif 974 } 975 current_cpu_model = cpu_model; 976 977 for (i = 0; i < smp_cpus; i++) { 978 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 979 icc_bridge, &error); 980 if (error) { 981 fprintf(stderr, "%s\n", error_get_pretty(error)); 982 error_free(error); 983 exit(1); 984 } 985 } 986 987 /* map APIC MMIO area if CPU has APIC */ 988 if (cpu && cpu->env.apic_state) { 989 /* XXX: what if the base changes? */ 990 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 991 APIC_DEFAULT_ADDRESS, 0x1000); 992 } 993 } 994 995 /* pci-info ROM file. Little endian format */ 996 typedef struct PcRomPciInfo { 997 uint64_t w32_min; 998 uint64_t w32_max; 999 uint64_t w64_min; 1000 uint64_t w64_max; 1001 } PcRomPciInfo; 1002 1003 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info) 1004 { 1005 PcRomPciInfo *info; 1006 Object *pci_info; 1007 bool ambiguous = false; 1008 1009 if (!guest_info->has_pci_info || !guest_info->fw_cfg) { 1010 return; 1011 } 1012 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1013 g_assert(!ambiguous); 1014 if (!pci_info) { 1015 return; 1016 } 1017 1018 info = g_malloc(sizeof *info); 1019 info->w32_min = cpu_to_le64(object_property_get_int(pci_info, 1020 PCI_HOST_PROP_PCI_HOLE_START, NULL)); 1021 info->w32_max = cpu_to_le64(object_property_get_int(pci_info, 1022 PCI_HOST_PROP_PCI_HOLE_END, NULL)); 1023 info->w64_min = cpu_to_le64(object_property_get_int(pci_info, 1024 PCI_HOST_PROP_PCI_HOLE64_START, NULL)); 1025 info->w64_max = cpu_to_le64(object_property_get_int(pci_info, 1026 PCI_HOST_PROP_PCI_HOLE64_END, NULL)); 1027 /* Pass PCI hole info to guest via a side channel. 1028 * Required so guest PCI enumeration does the right thing. */ 1029 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info); 1030 } 1031 1032 typedef struct PcGuestInfoState { 1033 PcGuestInfo info; 1034 Notifier machine_done; 1035 } PcGuestInfoState; 1036 1037 static 1038 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1039 { 1040 PcGuestInfoState *guest_info_state = container_of(notifier, 1041 PcGuestInfoState, 1042 machine_done); 1043 pc_fw_cfg_guest_info(&guest_info_state->info); 1044 } 1045 1046 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1047 ram_addr_t above_4g_mem_size) 1048 { 1049 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1050 PcGuestInfo *guest_info = &guest_info_state->info; 1051 1052 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1053 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1054 return guest_info; 1055 } 1056 1057 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start, 1058 uint64_t pci_hole64_size) 1059 { 1060 if ((sizeof(hwaddr) == 4) || (!pci_hole64_size)) { 1061 return; 1062 } 1063 /* 1064 * BIOS does not set MTRR entries for the 64 bit window, so no need to 1065 * align address to power of two. Align address at 1G, this makes sure 1066 * it can be exactly covered with a PAT entry even when using huge 1067 * pages. 1068 */ 1069 pci_info->w64.begin = ROUND_UP(pci_hole64_start, 0x1ULL << 30); 1070 pci_info->w64.end = pci_info->w64.begin + pci_hole64_size; 1071 assert(pci_info->w64.begin <= pci_info->w64.end); 1072 } 1073 1074 void pc_acpi_init(const char *default_dsdt) 1075 { 1076 char *filename; 1077 1078 if (acpi_tables != NULL) { 1079 /* manually set via -acpitable, leave it alone */ 1080 return; 1081 } 1082 1083 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1084 if (filename == NULL) { 1085 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1086 } else { 1087 char *arg; 1088 QemuOpts *opts; 1089 Error *err = NULL; 1090 1091 arg = g_strdup_printf("file=%s", filename); 1092 1093 /* creates a deep copy of "arg" */ 1094 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1095 g_assert(opts != NULL); 1096 1097 acpi_table_add(opts, &err); 1098 if (err) { 1099 fprintf(stderr, "WARNING: failed to load %s: %s\n", filename, 1100 error_get_pretty(err)); 1101 error_free(err); 1102 } 1103 g_free(arg); 1104 g_free(filename); 1105 } 1106 } 1107 1108 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 1109 const char *kernel_filename, 1110 const char *kernel_cmdline, 1111 const char *initrd_filename, 1112 ram_addr_t below_4g_mem_size, 1113 ram_addr_t above_4g_mem_size, 1114 MemoryRegion *rom_memory, 1115 MemoryRegion **ram_memory, 1116 PcGuestInfo *guest_info) 1117 { 1118 int linux_boot, i; 1119 MemoryRegion *ram, *option_rom_mr; 1120 MemoryRegion *ram_below_4g, *ram_above_4g; 1121 FWCfgState *fw_cfg; 1122 1123 linux_boot = (kernel_filename != NULL); 1124 1125 /* Allocate RAM. We allocate it as a single memory region and use 1126 * aliases to address portions of it, mostly for backwards compatibility 1127 * with older qemus that used qemu_ram_alloc(). 1128 */ 1129 ram = g_malloc(sizeof(*ram)); 1130 memory_region_init_ram(ram, NULL, "pc.ram", 1131 below_4g_mem_size + above_4g_mem_size); 1132 vmstate_register_ram_global(ram); 1133 *ram_memory = ram; 1134 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1135 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1136 0, below_4g_mem_size); 1137 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1138 if (above_4g_mem_size > 0) { 1139 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1140 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1141 below_4g_mem_size, above_4g_mem_size); 1142 memory_region_add_subregion(system_memory, 0x100000000ULL, 1143 ram_above_4g); 1144 } 1145 1146 1147 /* Initialize PC system firmware */ 1148 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1149 1150 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1151 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); 1152 vmstate_register_ram_global(option_rom_mr); 1153 memory_region_add_subregion_overlap(rom_memory, 1154 PC_ROM_MIN_VGA, 1155 option_rom_mr, 1156 1); 1157 1158 fw_cfg = bochs_bios_init(); 1159 rom_set_fw(fw_cfg); 1160 1161 if (linux_boot) { 1162 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 1163 } 1164 1165 for (i = 0; i < nb_option_roms; i++) { 1166 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1167 } 1168 guest_info->fw_cfg = fw_cfg; 1169 return fw_cfg; 1170 } 1171 1172 qemu_irq *pc_allocate_cpu_irq(void) 1173 { 1174 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1175 } 1176 1177 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1178 { 1179 DeviceState *dev = NULL; 1180 1181 if (pci_bus) { 1182 PCIDevice *pcidev = pci_vga_init(pci_bus); 1183 dev = pcidev ? &pcidev->qdev : NULL; 1184 } else if (isa_bus) { 1185 ISADevice *isadev = isa_vga_init(isa_bus); 1186 dev = isadev ? DEVICE(isadev) : NULL; 1187 } 1188 return dev; 1189 } 1190 1191 static void cpu_request_exit(void *opaque, int irq, int level) 1192 { 1193 CPUState *cpu = current_cpu; 1194 1195 if (cpu && level) { 1196 cpu_exit(cpu); 1197 } 1198 } 1199 1200 static const MemoryRegionOps ioport80_io_ops = { 1201 .write = ioport80_write, 1202 .read = ioport80_read, 1203 .endianness = DEVICE_NATIVE_ENDIAN, 1204 .impl = { 1205 .min_access_size = 1, 1206 .max_access_size = 1, 1207 }, 1208 }; 1209 1210 static const MemoryRegionOps ioportF0_io_ops = { 1211 .write = ioportF0_write, 1212 .read = ioportF0_read, 1213 .endianness = DEVICE_NATIVE_ENDIAN, 1214 .impl = { 1215 .min_access_size = 1, 1216 .max_access_size = 1, 1217 }, 1218 }; 1219 1220 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1221 ISADevice **rtc_state, 1222 ISADevice **floppy, 1223 bool no_vmport) 1224 { 1225 int i; 1226 DriveInfo *fd[MAX_FD]; 1227 DeviceState *hpet = NULL; 1228 int pit_isa_irq = 0; 1229 qemu_irq pit_alt_irq = NULL; 1230 qemu_irq rtc_irq = NULL; 1231 qemu_irq *a20_line; 1232 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1233 qemu_irq *cpu_exit_irq; 1234 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1235 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1236 1237 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1238 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1239 1240 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1241 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1242 1243 /* 1244 * Check if an HPET shall be created. 1245 * 1246 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1247 * when the HPET wants to take over. Thus we have to disable the latter. 1248 */ 1249 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1250 hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); 1251 1252 if (hpet) { 1253 for (i = 0; i < GSI_NUM_PINS; i++) { 1254 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1255 } 1256 pit_isa_irq = -1; 1257 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1258 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1259 } 1260 } 1261 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1262 1263 qemu_register_boot_set(pc_boot_set, *rtc_state); 1264 1265 if (!xen_enabled()) { 1266 if (kvm_irqchip_in_kernel()) { 1267 pit = kvm_pit_init(isa_bus, 0x40); 1268 } else { 1269 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1270 } 1271 if (hpet) { 1272 /* connect PIT to output control line of the HPET */ 1273 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1274 } 1275 pcspk_init(isa_bus, pit); 1276 } 1277 1278 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1279 if (serial_hds[i]) { 1280 serial_isa_init(isa_bus, i, serial_hds[i]); 1281 } 1282 } 1283 1284 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1285 if (parallel_hds[i]) { 1286 parallel_init(isa_bus, i, parallel_hds[i]); 1287 } 1288 } 1289 1290 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1291 i8042 = isa_create_simple(isa_bus, "i8042"); 1292 i8042_setup_a20_line(i8042, &a20_line[0]); 1293 if (!no_vmport) { 1294 vmport_init(isa_bus); 1295 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1296 } else { 1297 vmmouse = NULL; 1298 } 1299 if (vmmouse) { 1300 DeviceState *dev = DEVICE(vmmouse); 1301 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1302 qdev_init_nofail(dev); 1303 } 1304 port92 = isa_create_simple(isa_bus, "port92"); 1305 port92_init(port92, &a20_line[1]); 1306 1307 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1308 DMA_init(0, cpu_exit_irq); 1309 1310 for(i = 0; i < MAX_FD; i++) { 1311 fd[i] = drive_get(IF_FLOPPY, 0, i); 1312 } 1313 *floppy = fdctrl_init_isa(isa_bus, fd); 1314 } 1315 1316 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1317 { 1318 int i; 1319 1320 for (i = 0; i < nb_nics; i++) { 1321 NICInfo *nd = &nd_table[i]; 1322 1323 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1324 pc_init_ne2k_isa(isa_bus, nd); 1325 } else { 1326 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1327 } 1328 } 1329 } 1330 1331 void pc_pci_device_init(PCIBus *pci_bus) 1332 { 1333 int max_bus; 1334 int bus; 1335 1336 max_bus = drive_get_max_bus(IF_SCSI); 1337 for (bus = 0; bus <= max_bus; bus++) { 1338 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1339 } 1340 } 1341 1342 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1343 { 1344 DeviceState *dev; 1345 SysBusDevice *d; 1346 unsigned int i; 1347 1348 if (kvm_irqchip_in_kernel()) { 1349 dev = qdev_create(NULL, "kvm-ioapic"); 1350 } else { 1351 dev = qdev_create(NULL, "ioapic"); 1352 } 1353 if (parent_name) { 1354 object_property_add_child(object_resolve_path(parent_name, NULL), 1355 "ioapic", OBJECT(dev), NULL); 1356 } 1357 qdev_init_nofail(dev); 1358 d = SYS_BUS_DEVICE(dev); 1359 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1360 1361 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1362 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1363 } 1364 } 1365