1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/visitor.h" 81 #include "hw/core/cpu.h" 82 #include "hw/usb.h" 83 #include "hw/i386/intel_iommu.h" 84 #include "hw/net/ne2000-isa.h" 85 #include "standard-headers/asm-x86/bootparam.h" 86 #include "hw/virtio/virtio-pmem-pci.h" 87 #include "hw/virtio/virtio-mem-pci.h" 88 #include "hw/mem/memory-device.h" 89 #include "sysemu/replay.h" 90 #include "qapi/qmp/qerror.h" 91 #include "e820_memory_layout.h" 92 #include "fw_cfg.h" 93 #include "trace.h" 94 #include CONFIG_DEVICES 95 96 GlobalProperty pc_compat_6_1[] = {}; 97 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 98 99 GlobalProperty pc_compat_6_0[] = { 100 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 101 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 102 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 103 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 104 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 105 }; 106 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 107 108 GlobalProperty pc_compat_5_2[] = { 109 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 110 }; 111 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 112 113 GlobalProperty pc_compat_5_1[] = { 114 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 115 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 116 }; 117 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 118 119 GlobalProperty pc_compat_5_0[] = { 120 }; 121 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 122 123 GlobalProperty pc_compat_4_2[] = { 124 { "mch", "smbase-smram", "off" }, 125 }; 126 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 127 128 GlobalProperty pc_compat_4_1[] = {}; 129 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 130 131 GlobalProperty pc_compat_4_0[] = {}; 132 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 133 134 GlobalProperty pc_compat_3_1[] = { 135 { "intel-iommu", "dma-drain", "off" }, 136 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 137 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 138 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 139 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 140 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 141 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 142 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 143 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 144 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 145 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 146 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 147 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 148 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 149 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 150 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 151 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 152 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 153 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 154 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 155 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 156 }; 157 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 158 159 GlobalProperty pc_compat_3_0[] = { 160 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 161 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 162 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 163 }; 164 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 165 166 GlobalProperty pc_compat_2_12[] = { 167 { TYPE_X86_CPU, "legacy-cache", "on" }, 168 { TYPE_X86_CPU, "topoext", "off" }, 169 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 170 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 171 }; 172 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 173 174 GlobalProperty pc_compat_2_11[] = { 175 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 176 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 177 }; 178 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 179 180 GlobalProperty pc_compat_2_10[] = { 181 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 182 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 183 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 184 }; 185 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 186 187 GlobalProperty pc_compat_2_9[] = { 188 { "mch", "extended-tseg-mbytes", "0" }, 189 }; 190 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 191 192 GlobalProperty pc_compat_2_8[] = { 193 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 194 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 195 { "ICH9-LPC", "x-smi-broadcast", "off" }, 196 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 197 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 198 }; 199 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 200 201 GlobalProperty pc_compat_2_7[] = { 202 { TYPE_X86_CPU, "l3-cache", "off" }, 203 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 204 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 205 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 206 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 207 { "isa-pcspk", "migrate", "off" }, 208 }; 209 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 210 211 GlobalProperty pc_compat_2_6[] = { 212 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 213 { "vmxnet3", "romfile", "" }, 214 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 215 { "apic-common", "legacy-instance-id", "on", } 216 }; 217 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 218 219 GlobalProperty pc_compat_2_5[] = {}; 220 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 221 222 GlobalProperty pc_compat_2_4[] = { 223 PC_CPU_MODEL_IDS("2.4.0") 224 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 225 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 226 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 227 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 228 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 229 { TYPE_X86_CPU, "check", "off" }, 230 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 231 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 232 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 233 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 234 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 235 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 236 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 237 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 238 }; 239 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 240 241 GlobalProperty pc_compat_2_3[] = { 242 PC_CPU_MODEL_IDS("2.3.0") 243 { TYPE_X86_CPU, "arat", "off" }, 244 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 245 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 246 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 247 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 248 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 249 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 250 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 251 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 254 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 255 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 256 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 257 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 258 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 259 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 260 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 261 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 262 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 263 }; 264 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 265 266 GlobalProperty pc_compat_2_2[] = { 267 PC_CPU_MODEL_IDS("2.2.0") 268 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 275 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 276 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 277 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 278 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 279 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 280 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 281 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 282 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 283 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 284 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 285 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 286 }; 287 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 288 289 GlobalProperty pc_compat_2_1[] = { 290 PC_CPU_MODEL_IDS("2.1.0") 291 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 292 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 293 }; 294 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 295 296 GlobalProperty pc_compat_2_0[] = { 297 PC_CPU_MODEL_IDS("2.0.0") 298 { "virtio-scsi-pci", "any_layout", "off" }, 299 { "PIIX4_PM", "memory-hotplug-support", "off" }, 300 { "apic", "version", "0x11" }, 301 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 302 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 303 { "pci-serial", "prog_if", "0" }, 304 { "pci-serial-2x", "prog_if", "0" }, 305 { "pci-serial-4x", "prog_if", "0" }, 306 { "virtio-net-pci", "guest_announce", "off" }, 307 { "ICH9-LPC", "memory-hotplug-support", "off" }, 308 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 309 { "ioh3420", COMPAT_PROP_PCP, "off" }, 310 }; 311 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 312 313 GlobalProperty pc_compat_1_7[] = { 314 PC_CPU_MODEL_IDS("1.7.0") 315 { TYPE_USB_DEVICE, "msos-desc", "no" }, 316 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 317 { "hpet", HPET_INTCAP, "4" }, 318 }; 319 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 320 321 GlobalProperty pc_compat_1_6[] = { 322 PC_CPU_MODEL_IDS("1.6.0") 323 { "e1000", "mitigation", "off" }, 324 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 325 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 326 { "i440FX-pcihost", "short_root_bus", "1" }, 327 { "q35-pcihost", "short_root_bus", "1" }, 328 }; 329 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 330 331 GlobalProperty pc_compat_1_5[] = { 332 PC_CPU_MODEL_IDS("1.5.0") 333 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 334 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 335 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 336 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 337 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 338 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 339 { "virtio-net-pci", "any_layout", "off" }, 340 { TYPE_X86_CPU, "pmu", "on" }, 341 { "i440FX-pcihost", "short_root_bus", "0" }, 342 { "q35-pcihost", "short_root_bus", "0" }, 343 }; 344 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 345 346 GlobalProperty pc_compat_1_4[] = { 347 PC_CPU_MODEL_IDS("1.4.0") 348 { "scsi-hd", "discard_granularity", "0" }, 349 { "scsi-cd", "discard_granularity", "0" }, 350 { "ide-hd", "discard_granularity", "0" }, 351 { "ide-cd", "discard_granularity", "0" }, 352 { "virtio-blk-pci", "discard_granularity", "0" }, 353 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 354 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 355 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 356 { "e1000", "romfile", "pxe-e1000.rom" }, 357 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 358 { "pcnet", "romfile", "pxe-pcnet.rom" }, 359 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 360 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 361 { "486-" TYPE_X86_CPU, "model", "0" }, 362 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 363 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 364 }; 365 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 366 367 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 368 { 369 GSIState *s; 370 371 s = g_new0(GSIState, 1); 372 if (kvm_ioapic_in_kernel()) { 373 kvm_pc_setup_irq_routing(pci_enabled); 374 } 375 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 376 377 return s; 378 } 379 380 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 381 unsigned size) 382 { 383 } 384 385 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 386 { 387 return 0xffffffffffffffffULL; 388 } 389 390 /* MSDOS compatibility mode FPU exception support */ 391 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 392 unsigned size) 393 { 394 if (tcg_enabled()) { 395 cpu_set_ignne(); 396 } 397 } 398 399 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 400 { 401 return 0xffffffffffffffffULL; 402 } 403 404 /* PC cmos mappings */ 405 406 #define REG_EQUIPMENT_BYTE 0x14 407 408 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 409 int16_t cylinders, int8_t heads, int8_t sectors) 410 { 411 rtc_set_memory(s, type_ofs, 47); 412 rtc_set_memory(s, info_ofs, cylinders); 413 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 414 rtc_set_memory(s, info_ofs + 2, heads); 415 rtc_set_memory(s, info_ofs + 3, 0xff); 416 rtc_set_memory(s, info_ofs + 4, 0xff); 417 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 418 rtc_set_memory(s, info_ofs + 6, cylinders); 419 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 420 rtc_set_memory(s, info_ofs + 8, sectors); 421 } 422 423 /* convert boot_device letter to something recognizable by the bios */ 424 static int boot_device2nibble(char boot_device) 425 { 426 switch(boot_device) { 427 case 'a': 428 case 'b': 429 return 0x01; /* floppy boot */ 430 case 'c': 431 return 0x02; /* hard drive boot */ 432 case 'd': 433 return 0x03; /* CD-ROM boot */ 434 case 'n': 435 return 0x04; /* Network boot */ 436 } 437 return 0; 438 } 439 440 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 441 { 442 #define PC_MAX_BOOT_DEVICES 3 443 int nbds, bds[3] = { 0, }; 444 int i; 445 446 nbds = strlen(boot_device); 447 if (nbds > PC_MAX_BOOT_DEVICES) { 448 error_setg(errp, "Too many boot devices for PC"); 449 return; 450 } 451 for (i = 0; i < nbds; i++) { 452 bds[i] = boot_device2nibble(boot_device[i]); 453 if (bds[i] == 0) { 454 error_setg(errp, "Invalid boot device for PC: '%c'", 455 boot_device[i]); 456 return; 457 } 458 } 459 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 460 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 461 } 462 463 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 464 { 465 set_boot_dev(opaque, boot_device, errp); 466 } 467 468 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 469 { 470 int val, nb, i; 471 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 472 FLOPPY_DRIVE_TYPE_NONE }; 473 474 /* floppy type */ 475 if (floppy) { 476 for (i = 0; i < 2; i++) { 477 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 478 } 479 } 480 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 481 cmos_get_fd_drive_type(fd_type[1]); 482 rtc_set_memory(rtc_state, 0x10, val); 483 484 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 485 nb = 0; 486 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 487 nb++; 488 } 489 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 490 nb++; 491 } 492 switch (nb) { 493 case 0: 494 break; 495 case 1: 496 val |= 0x01; /* 1 drive, ready for boot */ 497 break; 498 case 2: 499 val |= 0x41; /* 2 drives, ready for boot */ 500 break; 501 } 502 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 503 } 504 505 typedef struct pc_cmos_init_late_arg { 506 ISADevice *rtc_state; 507 BusState *idebus[2]; 508 } pc_cmos_init_late_arg; 509 510 typedef struct check_fdc_state { 511 ISADevice *floppy; 512 bool multiple; 513 } CheckFdcState; 514 515 static int check_fdc(Object *obj, void *opaque) 516 { 517 CheckFdcState *state = opaque; 518 Object *fdc; 519 uint32_t iobase; 520 Error *local_err = NULL; 521 522 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 523 if (!fdc) { 524 return 0; 525 } 526 527 iobase = object_property_get_uint(obj, "iobase", &local_err); 528 if (local_err || iobase != 0x3f0) { 529 error_free(local_err); 530 return 0; 531 } 532 533 if (state->floppy) { 534 state->multiple = true; 535 } else { 536 state->floppy = ISA_DEVICE(obj); 537 } 538 return 0; 539 } 540 541 static const char * const fdc_container_path[] = { 542 "/unattached", "/peripheral", "/peripheral-anon" 543 }; 544 545 /* 546 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 547 * and ACPI objects. 548 */ 549 ISADevice *pc_find_fdc0(void) 550 { 551 int i; 552 Object *container; 553 CheckFdcState state = { 0 }; 554 555 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 556 container = container_get(qdev_get_machine(), fdc_container_path[i]); 557 object_child_foreach(container, check_fdc, &state); 558 } 559 560 if (state.multiple) { 561 warn_report("multiple floppy disk controllers with " 562 "iobase=0x3f0 have been found"); 563 error_printf("the one being picked for CMOS setup might not reflect " 564 "your intent"); 565 } 566 567 return state.floppy; 568 } 569 570 static void pc_cmos_init_late(void *opaque) 571 { 572 pc_cmos_init_late_arg *arg = opaque; 573 ISADevice *s = arg->rtc_state; 574 int16_t cylinders; 575 int8_t heads, sectors; 576 int val; 577 int i, trans; 578 579 val = 0; 580 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 581 &cylinders, &heads, §ors) >= 0) { 582 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 583 val |= 0xf0; 584 } 585 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 586 &cylinders, &heads, §ors) >= 0) { 587 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 588 val |= 0x0f; 589 } 590 rtc_set_memory(s, 0x12, val); 591 592 val = 0; 593 for (i = 0; i < 4; i++) { 594 /* NOTE: ide_get_geometry() returns the physical 595 geometry. It is always such that: 1 <= sects <= 63, 1 596 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 597 geometry can be different if a translation is done. */ 598 if (arg->idebus[i / 2] && 599 ide_get_geometry(arg->idebus[i / 2], i % 2, 600 &cylinders, &heads, §ors) >= 0) { 601 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 602 assert((trans & ~3) == 0); 603 val |= trans << (i * 2); 604 } 605 } 606 rtc_set_memory(s, 0x39, val); 607 608 pc_cmos_init_floppy(s, pc_find_fdc0()); 609 610 qemu_unregister_reset(pc_cmos_init_late, opaque); 611 } 612 613 void pc_cmos_init(PCMachineState *pcms, 614 BusState *idebus0, BusState *idebus1, 615 ISADevice *s) 616 { 617 int val; 618 static pc_cmos_init_late_arg arg; 619 X86MachineState *x86ms = X86_MACHINE(pcms); 620 621 /* various important CMOS locations needed by PC/Bochs bios */ 622 623 /* memory size */ 624 /* base memory (first MiB) */ 625 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 626 rtc_set_memory(s, 0x15, val); 627 rtc_set_memory(s, 0x16, val >> 8); 628 /* extended memory (next 64MiB) */ 629 if (x86ms->below_4g_mem_size > 1 * MiB) { 630 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 631 } else { 632 val = 0; 633 } 634 if (val > 65535) 635 val = 65535; 636 rtc_set_memory(s, 0x17, val); 637 rtc_set_memory(s, 0x18, val >> 8); 638 rtc_set_memory(s, 0x30, val); 639 rtc_set_memory(s, 0x31, val >> 8); 640 /* memory between 16MiB and 4GiB */ 641 if (x86ms->below_4g_mem_size > 16 * MiB) { 642 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 643 } else { 644 val = 0; 645 } 646 if (val > 65535) 647 val = 65535; 648 rtc_set_memory(s, 0x34, val); 649 rtc_set_memory(s, 0x35, val >> 8); 650 /* memory above 4GiB */ 651 val = x86ms->above_4g_mem_size / 65536; 652 rtc_set_memory(s, 0x5b, val); 653 rtc_set_memory(s, 0x5c, val >> 8); 654 rtc_set_memory(s, 0x5d, val >> 16); 655 656 object_property_add_link(OBJECT(pcms), "rtc_state", 657 TYPE_ISA_DEVICE, 658 (Object **)&x86ms->rtc, 659 object_property_allow_set_link, 660 OBJ_PROP_LINK_STRONG); 661 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 662 &error_abort); 663 664 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 665 666 val = 0; 667 val |= 0x02; /* FPU is there */ 668 val |= 0x04; /* PS/2 mouse installed */ 669 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 670 671 /* hard drives and FDC */ 672 arg.rtc_state = s; 673 arg.idebus[0] = idebus0; 674 arg.idebus[1] = idebus1; 675 qemu_register_reset(pc_cmos_init_late, &arg); 676 } 677 678 static void handle_a20_line_change(void *opaque, int irq, int level) 679 { 680 X86CPU *cpu = opaque; 681 682 /* XXX: send to all CPUs ? */ 683 /* XXX: add logic to handle multiple A20 line sources */ 684 x86_cpu_set_a20(cpu, level); 685 } 686 687 #define NE2000_NB_MAX 6 688 689 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 690 0x280, 0x380 }; 691 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 692 693 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 694 { 695 static int nb_ne2k = 0; 696 697 if (nb_ne2k == NE2000_NB_MAX) 698 return; 699 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 700 ne2000_irq[nb_ne2k], nd); 701 nb_ne2k++; 702 } 703 704 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 705 { 706 X86CPU *cpu = opaque; 707 708 if (level) { 709 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 710 } 711 } 712 713 /* 714 * This function is very similar to smp_parse() 715 * in hw/core/machine.c but includes CPU die support. 716 */ 717 static void pc_smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp) 718 { 719 unsigned cpus = config->has_cpus ? config->cpus : 0; 720 unsigned sockets = config->has_sockets ? config->sockets : 0; 721 unsigned dies = config->has_dies ? config->dies : 1; 722 unsigned cores = config->has_cores ? config->cores : 0; 723 unsigned threads = config->has_threads ? config->threads : 0; 724 725 /* compute missing values, prefer sockets over cores over threads */ 726 if (cpus == 0 || sockets == 0) { 727 cores = cores > 0 ? cores : 1; 728 threads = threads > 0 ? threads : 1; 729 if (cpus == 0) { 730 sockets = sockets > 0 ? sockets : 1; 731 cpus = cores * threads * dies * sockets; 732 } else { 733 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 734 sockets = ms->smp.max_cpus / (cores * threads * dies); 735 } 736 } else if (cores == 0) { 737 threads = threads > 0 ? threads : 1; 738 cores = cpus / (sockets * dies * threads); 739 cores = cores > 0 ? cores : 1; 740 } else if (threads == 0) { 741 threads = cpus / (cores * dies * sockets); 742 threads = threads > 0 ? threads : 1; 743 } else if (sockets * dies * cores * threads < cpus) { 744 error_setg(errp, "cpu topology: " 745 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 746 "smp_cpus (%u)", 747 sockets, dies, cores, threads, cpus); 748 return; 749 } 750 751 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 752 753 if (ms->smp.max_cpus < cpus) { 754 error_setg(errp, "maxcpus must be equal to or greater than smp"); 755 return; 756 } 757 758 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 759 error_setg(errp, "Invalid CPU topology deprecated: " 760 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 761 "!= maxcpus (%u)", 762 sockets, dies, cores, threads, 763 ms->smp.max_cpus); 764 return; 765 } 766 767 ms->smp.cpus = cpus; 768 ms->smp.cores = cores; 769 ms->smp.threads = threads; 770 ms->smp.sockets = sockets; 771 ms->smp.dies = dies; 772 } 773 774 static 775 void pc_machine_done(Notifier *notifier, void *data) 776 { 777 PCMachineState *pcms = container_of(notifier, 778 PCMachineState, machine_done); 779 X86MachineState *x86ms = X86_MACHINE(pcms); 780 781 /* set the number of CPUs */ 782 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 783 784 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 785 786 acpi_setup(); 787 if (x86ms->fw_cfg) { 788 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 789 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 790 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 791 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 792 } 793 794 795 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 796 !kvm_irqchip_in_kernel()) { 797 error_report("current -smp configuration requires kernel " 798 "irqchip support."); 799 exit(EXIT_FAILURE); 800 } 801 } 802 803 void pc_guest_info_init(PCMachineState *pcms) 804 { 805 X86MachineState *x86ms = X86_MACHINE(pcms); 806 807 x86ms->apic_xrupt_override = true; 808 pcms->machine_done.notify = pc_machine_done; 809 qemu_add_machine_init_done_notifier(&pcms->machine_done); 810 } 811 812 /* setup pci memory address space mapping into system address space */ 813 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 814 MemoryRegion *pci_address_space) 815 { 816 /* Set to lower priority than RAM */ 817 memory_region_add_subregion_overlap(system_memory, 0x0, 818 pci_address_space, -1); 819 } 820 821 void xen_load_linux(PCMachineState *pcms) 822 { 823 int i; 824 FWCfgState *fw_cfg; 825 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 826 X86MachineState *x86ms = X86_MACHINE(pcms); 827 828 assert(MACHINE(pcms)->kernel_filename != NULL); 829 830 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 831 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 832 rom_set_fw(fw_cfg); 833 834 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 835 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 836 for (i = 0; i < nb_option_roms; i++) { 837 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 838 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 839 !strcmp(option_rom[i].name, "pvh.bin") || 840 !strcmp(option_rom[i].name, "multiboot.bin")); 841 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 842 } 843 x86ms->fw_cfg = fw_cfg; 844 } 845 846 void pc_memory_init(PCMachineState *pcms, 847 MemoryRegion *system_memory, 848 MemoryRegion *rom_memory, 849 MemoryRegion **ram_memory) 850 { 851 int linux_boot, i; 852 MemoryRegion *option_rom_mr; 853 MemoryRegion *ram_below_4g, *ram_above_4g; 854 FWCfgState *fw_cfg; 855 MachineState *machine = MACHINE(pcms); 856 MachineClass *mc = MACHINE_GET_CLASS(machine); 857 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 858 X86MachineState *x86ms = X86_MACHINE(pcms); 859 860 assert(machine->ram_size == x86ms->below_4g_mem_size + 861 x86ms->above_4g_mem_size); 862 863 linux_boot = (machine->kernel_filename != NULL); 864 865 /* 866 * Split single memory region and use aliases to address portions of it, 867 * done for backwards compatibility with older qemus. 868 */ 869 *ram_memory = machine->ram; 870 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 871 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 872 0, x86ms->below_4g_mem_size); 873 memory_region_add_subregion(system_memory, 0, ram_below_4g); 874 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 875 if (x86ms->above_4g_mem_size > 0) { 876 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 877 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 878 machine->ram, 879 x86ms->below_4g_mem_size, 880 x86ms->above_4g_mem_size); 881 memory_region_add_subregion(system_memory, 0x100000000ULL, 882 ram_above_4g); 883 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 884 } 885 886 if (!pcmc->has_reserved_memory && 887 (machine->ram_slots || 888 (machine->maxram_size > machine->ram_size))) { 889 890 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 891 mc->name); 892 exit(EXIT_FAILURE); 893 } 894 895 /* always allocate the device memory information */ 896 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 897 898 /* initialize device memory address space */ 899 if (pcmc->has_reserved_memory && 900 (machine->ram_size < machine->maxram_size)) { 901 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 902 903 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 904 error_report("unsupported amount of memory slots: %"PRIu64, 905 machine->ram_slots); 906 exit(EXIT_FAILURE); 907 } 908 909 if (QEMU_ALIGN_UP(machine->maxram_size, 910 TARGET_PAGE_SIZE) != machine->maxram_size) { 911 error_report("maximum memory size must by aligned to multiple of " 912 "%d bytes", TARGET_PAGE_SIZE); 913 exit(EXIT_FAILURE); 914 } 915 916 machine->device_memory->base = 917 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 918 919 if (pcmc->enforce_aligned_dimm) { 920 /* size device region assuming 1G page max alignment per slot */ 921 device_mem_size += (1 * GiB) * machine->ram_slots; 922 } 923 924 if ((machine->device_memory->base + device_mem_size) < 925 device_mem_size) { 926 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 927 machine->maxram_size); 928 exit(EXIT_FAILURE); 929 } 930 931 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 932 "device-memory", device_mem_size); 933 memory_region_add_subregion(system_memory, machine->device_memory->base, 934 &machine->device_memory->mr); 935 } 936 937 /* Initialize PC system firmware */ 938 pc_system_firmware_init(pcms, rom_memory); 939 940 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 941 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 942 &error_fatal); 943 if (pcmc->pci_enabled) { 944 memory_region_set_readonly(option_rom_mr, true); 945 } 946 memory_region_add_subregion_overlap(rom_memory, 947 PC_ROM_MIN_VGA, 948 option_rom_mr, 949 1); 950 951 fw_cfg = fw_cfg_arch_create(machine, 952 x86ms->boot_cpus, x86ms->apic_id_limit); 953 954 rom_set_fw(fw_cfg); 955 956 if (pcmc->has_reserved_memory && machine->device_memory->base) { 957 uint64_t *val = g_malloc(sizeof(*val)); 958 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 959 uint64_t res_mem_end = machine->device_memory->base; 960 961 if (!pcmc->broken_reserved_end) { 962 res_mem_end += memory_region_size(&machine->device_memory->mr); 963 } 964 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 965 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 966 } 967 968 if (linux_boot) { 969 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 970 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 971 } 972 973 for (i = 0; i < nb_option_roms; i++) { 974 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 975 } 976 x86ms->fw_cfg = fw_cfg; 977 978 /* Init default IOAPIC address space */ 979 x86ms->ioapic_as = &address_space_memory; 980 981 /* Init ACPI memory hotplug IO base address */ 982 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 983 } 984 985 /* 986 * The 64bit pci hole starts after "above 4G RAM" and 987 * potentially the space reserved for memory hotplug. 988 */ 989 uint64_t pc_pci_hole64_start(void) 990 { 991 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 992 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 993 MachineState *ms = MACHINE(pcms); 994 X86MachineState *x86ms = X86_MACHINE(pcms); 995 uint64_t hole64_start = 0; 996 997 if (pcmc->has_reserved_memory && ms->device_memory->base) { 998 hole64_start = ms->device_memory->base; 999 if (!pcmc->broken_reserved_end) { 1000 hole64_start += memory_region_size(&ms->device_memory->mr); 1001 } 1002 } else { 1003 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1004 } 1005 1006 return ROUND_UP(hole64_start, 1 * GiB); 1007 } 1008 1009 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1010 { 1011 DeviceState *dev = NULL; 1012 1013 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1014 if (pci_bus) { 1015 PCIDevice *pcidev = pci_vga_init(pci_bus); 1016 dev = pcidev ? &pcidev->qdev : NULL; 1017 } else if (isa_bus) { 1018 ISADevice *isadev = isa_vga_init(isa_bus); 1019 dev = isadev ? DEVICE(isadev) : NULL; 1020 } 1021 rom_reset_order_override(); 1022 return dev; 1023 } 1024 1025 static const MemoryRegionOps ioport80_io_ops = { 1026 .write = ioport80_write, 1027 .read = ioport80_read, 1028 .endianness = DEVICE_NATIVE_ENDIAN, 1029 .impl = { 1030 .min_access_size = 1, 1031 .max_access_size = 1, 1032 }, 1033 }; 1034 1035 static const MemoryRegionOps ioportF0_io_ops = { 1036 .write = ioportF0_write, 1037 .read = ioportF0_read, 1038 .endianness = DEVICE_NATIVE_ENDIAN, 1039 .impl = { 1040 .min_access_size = 1, 1041 .max_access_size = 1, 1042 }, 1043 }; 1044 1045 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1046 { 1047 int i; 1048 DriveInfo *fd[MAX_FD]; 1049 qemu_irq *a20_line; 1050 ISADevice *fdc, *i8042, *port92, *vmmouse; 1051 1052 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1053 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1054 1055 for (i = 0; i < MAX_FD; i++) { 1056 fd[i] = drive_get(IF_FLOPPY, 0, i); 1057 create_fdctrl |= !!fd[i]; 1058 } 1059 if (create_fdctrl) { 1060 fdc = isa_new(TYPE_ISA_FDC); 1061 if (fdc) { 1062 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1063 isa_fdc_init_drives(fdc, fd); 1064 } 1065 } 1066 1067 i8042 = isa_create_simple(isa_bus, "i8042"); 1068 if (!no_vmport) { 1069 isa_create_simple(isa_bus, TYPE_VMPORT); 1070 vmmouse = isa_try_new("vmmouse"); 1071 } else { 1072 vmmouse = NULL; 1073 } 1074 if (vmmouse) { 1075 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1076 &error_abort); 1077 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1078 } 1079 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1080 1081 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1082 i8042_setup_a20_line(i8042, a20_line[0]); 1083 qdev_connect_gpio_out_named(DEVICE(port92), 1084 PORT92_A20_LINE, 0, a20_line[1]); 1085 g_free(a20_line); 1086 } 1087 1088 void pc_basic_device_init(struct PCMachineState *pcms, 1089 ISABus *isa_bus, qemu_irq *gsi, 1090 ISADevice **rtc_state, 1091 bool create_fdctrl, 1092 uint32_t hpet_irqs) 1093 { 1094 int i; 1095 DeviceState *hpet = NULL; 1096 int pit_isa_irq = 0; 1097 qemu_irq pit_alt_irq = NULL; 1098 qemu_irq rtc_irq = NULL; 1099 ISADevice *pit = NULL; 1100 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1101 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1102 1103 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1104 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1105 1106 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1107 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1108 1109 /* 1110 * Check if an HPET shall be created. 1111 * 1112 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1113 * when the HPET wants to take over. Thus we have to disable the latter. 1114 */ 1115 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1116 kvm_has_pit_state2())) { 1117 hpet = qdev_try_new(TYPE_HPET); 1118 if (!hpet) { 1119 error_report("couldn't create HPET device"); 1120 exit(1); 1121 } 1122 /* 1123 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1124 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1125 * IRQ2. 1126 */ 1127 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1128 HPET_INTCAP, NULL); 1129 if (!compat) { 1130 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1131 } 1132 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1133 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1134 1135 for (i = 0; i < GSI_NUM_PINS; i++) { 1136 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1137 } 1138 pit_isa_irq = -1; 1139 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1140 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1141 } 1142 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1143 1144 qemu_register_boot_set(pc_boot_set, *rtc_state); 1145 1146 if (!xen_enabled() && pcms->pit_enabled) { 1147 if (kvm_pit_in_kernel()) { 1148 pit = kvm_pit_init(isa_bus, 0x40); 1149 } else { 1150 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1151 } 1152 if (hpet) { 1153 /* connect PIT to output control line of the HPET */ 1154 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1155 } 1156 pcspk_init(pcms->pcspk, isa_bus, pit); 1157 } 1158 1159 i8257_dma_init(isa_bus, 0); 1160 1161 /* Super I/O */ 1162 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1163 } 1164 1165 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1166 { 1167 int i; 1168 1169 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1170 for (i = 0; i < nb_nics; i++) { 1171 NICInfo *nd = &nd_table[i]; 1172 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1173 1174 if (g_str_equal(model, "ne2k_isa")) { 1175 pc_init_ne2k_isa(isa_bus, nd); 1176 } else { 1177 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1178 } 1179 } 1180 rom_reset_order_override(); 1181 } 1182 1183 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1184 { 1185 qemu_irq *i8259; 1186 1187 if (kvm_pic_in_kernel()) { 1188 i8259 = kvm_i8259_init(isa_bus); 1189 } else if (xen_enabled()) { 1190 i8259 = xen_interrupt_controller_init(); 1191 } else { 1192 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1193 } 1194 1195 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1196 i8259_irqs[i] = i8259[i]; 1197 } 1198 1199 g_free(i8259); 1200 } 1201 1202 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1203 Error **errp) 1204 { 1205 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1206 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1207 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1208 const MachineState *ms = MACHINE(hotplug_dev); 1209 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1210 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1211 Error *local_err = NULL; 1212 1213 /* 1214 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1215 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1216 * addition to cover this case. 1217 */ 1218 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1219 error_setg(errp, 1220 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1221 return; 1222 } 1223 1224 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1225 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1226 return; 1227 } 1228 1229 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1230 if (local_err) { 1231 error_propagate(errp, local_err); 1232 return; 1233 } 1234 1235 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1236 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1237 } 1238 1239 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1240 DeviceState *dev, Error **errp) 1241 { 1242 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1243 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1244 MachineState *ms = MACHINE(hotplug_dev); 1245 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1246 1247 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1248 1249 if (is_nvdimm) { 1250 nvdimm_plug(ms->nvdimms_state); 1251 } 1252 1253 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1254 } 1255 1256 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1257 DeviceState *dev, Error **errp) 1258 { 1259 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1260 1261 /* 1262 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1263 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1264 * addition to cover this case. 1265 */ 1266 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1267 error_setg(errp, 1268 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1269 return; 1270 } 1271 1272 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1273 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1274 return; 1275 } 1276 1277 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1278 errp); 1279 } 1280 1281 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1282 DeviceState *dev, Error **errp) 1283 { 1284 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1285 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1286 Error *local_err = NULL; 1287 1288 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1289 if (local_err) { 1290 goto out; 1291 } 1292 1293 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1294 qdev_unrealize(dev); 1295 out: 1296 error_propagate(errp, local_err); 1297 } 1298 1299 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1300 DeviceState *dev, Error **errp) 1301 { 1302 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1303 Error *local_err = NULL; 1304 1305 if (!hotplug_dev2 && dev->hotplugged) { 1306 /* 1307 * Without a bus hotplug handler, we cannot control the plug/unplug 1308 * order. We should never reach this point when hotplugging on x86, 1309 * however, better add a safety net. 1310 */ 1311 error_setg(errp, "hotplug of virtio based memory devices not supported" 1312 " on this bus."); 1313 return; 1314 } 1315 /* 1316 * First, see if we can plug this memory device at all. If that 1317 * succeeds, branch of to the actual hotplug handler. 1318 */ 1319 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1320 &local_err); 1321 if (!local_err && hotplug_dev2) { 1322 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1323 } 1324 error_propagate(errp, local_err); 1325 } 1326 1327 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1328 DeviceState *dev, Error **errp) 1329 { 1330 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1331 Error *local_err = NULL; 1332 1333 /* 1334 * Plug the memory device first and then branch off to the actual 1335 * hotplug handler. If that one fails, we can easily undo the memory 1336 * device bits. 1337 */ 1338 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1339 if (hotplug_dev2) { 1340 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1341 if (local_err) { 1342 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1343 } 1344 } 1345 error_propagate(errp, local_err); 1346 } 1347 1348 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1349 DeviceState *dev, Error **errp) 1350 { 1351 /* We don't support hot unplug of virtio based memory devices */ 1352 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1353 } 1354 1355 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1356 DeviceState *dev, Error **errp) 1357 { 1358 /* We don't support hot unplug of virtio based memory devices */ 1359 } 1360 1361 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1362 DeviceState *dev, Error **errp) 1363 { 1364 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1365 pc_memory_pre_plug(hotplug_dev, dev, errp); 1366 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1367 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1368 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1369 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1370 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1371 } 1372 } 1373 1374 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1375 DeviceState *dev, Error **errp) 1376 { 1377 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1378 pc_memory_plug(hotplug_dev, dev, errp); 1379 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1380 x86_cpu_plug(hotplug_dev, dev, errp); 1381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1382 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1383 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1384 } 1385 } 1386 1387 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1388 DeviceState *dev, Error **errp) 1389 { 1390 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1391 pc_memory_unplug_request(hotplug_dev, dev, errp); 1392 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1393 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1394 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1395 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1396 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1397 } else { 1398 error_setg(errp, "acpi: device unplug request for not supported device" 1399 " type: %s", object_get_typename(OBJECT(dev))); 1400 } 1401 } 1402 1403 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1404 DeviceState *dev, Error **errp) 1405 { 1406 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1407 pc_memory_unplug(hotplug_dev, dev, errp); 1408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1409 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1410 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1411 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1412 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1413 } else { 1414 error_setg(errp, "acpi: device unplug for not supported device" 1415 " type: %s", object_get_typename(OBJECT(dev))); 1416 } 1417 } 1418 1419 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1420 DeviceState *dev) 1421 { 1422 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1423 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1424 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1425 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1426 return HOTPLUG_HANDLER(machine); 1427 } 1428 1429 return NULL; 1430 } 1431 1432 static void 1433 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1434 const char *name, void *opaque, 1435 Error **errp) 1436 { 1437 MachineState *ms = MACHINE(obj); 1438 int64_t value = 0; 1439 1440 if (ms->device_memory) { 1441 value = memory_region_size(&ms->device_memory->mr); 1442 } 1443 1444 visit_type_int(v, name, &value, errp); 1445 } 1446 1447 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1448 void *opaque, Error **errp) 1449 { 1450 PCMachineState *pcms = PC_MACHINE(obj); 1451 OnOffAuto vmport = pcms->vmport; 1452 1453 visit_type_OnOffAuto(v, name, &vmport, errp); 1454 } 1455 1456 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1457 void *opaque, Error **errp) 1458 { 1459 PCMachineState *pcms = PC_MACHINE(obj); 1460 1461 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1462 } 1463 1464 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1465 { 1466 PCMachineState *pcms = PC_MACHINE(obj); 1467 1468 return pcms->smbus_enabled; 1469 } 1470 1471 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1472 { 1473 PCMachineState *pcms = PC_MACHINE(obj); 1474 1475 pcms->smbus_enabled = value; 1476 } 1477 1478 static bool pc_machine_get_sata(Object *obj, Error **errp) 1479 { 1480 PCMachineState *pcms = PC_MACHINE(obj); 1481 1482 return pcms->sata_enabled; 1483 } 1484 1485 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1486 { 1487 PCMachineState *pcms = PC_MACHINE(obj); 1488 1489 pcms->sata_enabled = value; 1490 } 1491 1492 static bool pc_machine_get_pit(Object *obj, Error **errp) 1493 { 1494 PCMachineState *pcms = PC_MACHINE(obj); 1495 1496 return pcms->pit_enabled; 1497 } 1498 1499 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1500 { 1501 PCMachineState *pcms = PC_MACHINE(obj); 1502 1503 pcms->pit_enabled = value; 1504 } 1505 1506 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1507 { 1508 PCMachineState *pcms = PC_MACHINE(obj); 1509 1510 return pcms->hpet_enabled; 1511 } 1512 1513 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1514 { 1515 PCMachineState *pcms = PC_MACHINE(obj); 1516 1517 pcms->hpet_enabled = value; 1518 } 1519 1520 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1521 { 1522 PCMachineState *pcms = PC_MACHINE(obj); 1523 1524 return pcms->default_bus_bypass_iommu; 1525 } 1526 1527 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1528 Error **errp) 1529 { 1530 PCMachineState *pcms = PC_MACHINE(obj); 1531 1532 pcms->default_bus_bypass_iommu = value; 1533 } 1534 1535 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1536 const char *name, void *opaque, 1537 Error **errp) 1538 { 1539 PCMachineState *pcms = PC_MACHINE(obj); 1540 uint64_t value = pcms->max_ram_below_4g; 1541 1542 visit_type_size(v, name, &value, errp); 1543 } 1544 1545 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1546 const char *name, void *opaque, 1547 Error **errp) 1548 { 1549 PCMachineState *pcms = PC_MACHINE(obj); 1550 uint64_t value; 1551 1552 if (!visit_type_size(v, name, &value, errp)) { 1553 return; 1554 } 1555 if (value > 4 * GiB) { 1556 error_setg(errp, 1557 "Machine option 'max-ram-below-4g=%"PRIu64 1558 "' expects size less than or equal to 4G", value); 1559 return; 1560 } 1561 1562 if (value < 1 * MiB) { 1563 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1564 "BIOS may not work with less than 1MiB", value); 1565 } 1566 1567 pcms->max_ram_below_4g = value; 1568 } 1569 1570 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1571 const char *name, void *opaque, 1572 Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 uint64_t value = pcms->max_fw_size; 1576 1577 visit_type_size(v, name, &value, errp); 1578 } 1579 1580 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1581 const char *name, void *opaque, 1582 Error **errp) 1583 { 1584 PCMachineState *pcms = PC_MACHINE(obj); 1585 Error *error = NULL; 1586 uint64_t value; 1587 1588 visit_type_size(v, name, &value, &error); 1589 if (error) { 1590 error_propagate(errp, error); 1591 return; 1592 } 1593 1594 /* 1595 * We don't have a theoretically justifiable exact lower bound on the base 1596 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1597 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1598 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1599 * size. 1600 */ 1601 if (value > 16 * MiB) { 1602 error_setg(errp, 1603 "User specified max allowed firmware size %" PRIu64 " is " 1604 "greater than 16MiB. If combined firwmare size exceeds " 1605 "16MiB the system may not boot, or experience intermittent" 1606 "stability issues.", 1607 value); 1608 return; 1609 } 1610 1611 pcms->max_fw_size = value; 1612 } 1613 1614 1615 static void pc_machine_initfn(Object *obj) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 1619 #ifdef CONFIG_VMPORT 1620 pcms->vmport = ON_OFF_AUTO_AUTO; 1621 #else 1622 pcms->vmport = ON_OFF_AUTO_OFF; 1623 #endif /* CONFIG_VMPORT */ 1624 pcms->max_ram_below_4g = 0; /* use default */ 1625 /* acpi build is enabled by default if machine supports it */ 1626 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1627 pcms->smbus_enabled = true; 1628 pcms->sata_enabled = true; 1629 pcms->pit_enabled = true; 1630 pcms->max_fw_size = 8 * MiB; 1631 #ifdef CONFIG_HPET 1632 pcms->hpet_enabled = true; 1633 #endif 1634 pcms->default_bus_bypass_iommu = false; 1635 1636 pc_system_flash_create(pcms); 1637 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1638 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1639 OBJECT(pcms->pcspk), "audiodev"); 1640 } 1641 1642 static void pc_machine_reset(MachineState *machine) 1643 { 1644 CPUState *cs; 1645 X86CPU *cpu; 1646 1647 qemu_devices_reset(); 1648 1649 /* Reset APIC after devices have been reset to cancel 1650 * any changes that qemu_devices_reset() might have done. 1651 */ 1652 CPU_FOREACH(cs) { 1653 cpu = X86_CPU(cs); 1654 1655 if (cpu->apic_state) { 1656 device_legacy_reset(cpu->apic_state); 1657 } 1658 } 1659 } 1660 1661 static void pc_machine_wakeup(MachineState *machine) 1662 { 1663 cpu_synchronize_all_states(); 1664 pc_machine_reset(machine); 1665 cpu_synchronize_all_post_reset(); 1666 } 1667 1668 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1669 { 1670 X86IOMMUState *iommu = x86_iommu_get_default(); 1671 IntelIOMMUState *intel_iommu; 1672 1673 if (iommu && 1674 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1675 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1676 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1677 if (!intel_iommu->caching_mode) { 1678 error_setg(errp, "Device assignment is not allowed without " 1679 "enabling caching-mode=on for Intel IOMMU."); 1680 return false; 1681 } 1682 } 1683 1684 return true; 1685 } 1686 1687 static void pc_machine_class_init(ObjectClass *oc, void *data) 1688 { 1689 MachineClass *mc = MACHINE_CLASS(oc); 1690 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1691 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1692 1693 pcmc->pci_enabled = true; 1694 pcmc->has_acpi_build = true; 1695 pcmc->rsdp_in_ram = true; 1696 pcmc->smbios_defaults = true; 1697 pcmc->smbios_uuid_encoded = true; 1698 pcmc->gigabyte_align = true; 1699 pcmc->has_reserved_memory = true; 1700 pcmc->kvmclock_enabled = true; 1701 pcmc->enforce_aligned_dimm = true; 1702 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1703 * to be used at the moment, 32K should be enough for a while. */ 1704 pcmc->acpi_data_size = 0x20000 + 0x8000; 1705 pcmc->linuxboot_dma_enabled = true; 1706 pcmc->pvh_enabled = true; 1707 pcmc->kvmclock_create_always = true; 1708 assert(!mc->get_hotplug_handler); 1709 mc->get_hotplug_handler = pc_get_hotplug_handler; 1710 mc->hotplug_allowed = pc_hotplug_allowed; 1711 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1712 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1713 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1714 mc->auto_enable_numa_with_memhp = true; 1715 mc->auto_enable_numa_with_memdev = true; 1716 mc->has_hotpluggable_cpus = true; 1717 mc->default_boot_order = "cad"; 1718 mc->smp_parse = pc_smp_parse; 1719 mc->block_default_type = IF_IDE; 1720 mc->max_cpus = 255; 1721 mc->reset = pc_machine_reset; 1722 mc->wakeup = pc_machine_wakeup; 1723 hc->pre_plug = pc_machine_device_pre_plug_cb; 1724 hc->plug = pc_machine_device_plug_cb; 1725 hc->unplug_request = pc_machine_device_unplug_request_cb; 1726 hc->unplug = pc_machine_device_unplug_cb; 1727 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1728 mc->nvdimm_supported = true; 1729 mc->default_ram_id = "pc.ram"; 1730 1731 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1732 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1733 NULL, NULL); 1734 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1735 "Maximum ram below the 4G boundary (32bit boundary)"); 1736 1737 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1738 pc_machine_get_device_memory_region_size, NULL, 1739 NULL, NULL); 1740 1741 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1742 pc_machine_get_vmport, pc_machine_set_vmport, 1743 NULL, NULL); 1744 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1745 "Enable vmport (pc & q35)"); 1746 1747 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1748 pc_machine_get_smbus, pc_machine_set_smbus); 1749 1750 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1751 pc_machine_get_sata, pc_machine_set_sata); 1752 1753 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1754 pc_machine_get_pit, pc_machine_set_pit); 1755 1756 object_class_property_add_bool(oc, "hpet", 1757 pc_machine_get_hpet, pc_machine_set_hpet); 1758 1759 object_class_property_add_bool(oc, "default_bus_bypass_iommu", 1760 pc_machine_get_default_bus_bypass_iommu, 1761 pc_machine_set_default_bus_bypass_iommu); 1762 1763 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1764 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1765 NULL, NULL); 1766 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1767 "Maximum combined firmware size"); 1768 } 1769 1770 static const TypeInfo pc_machine_info = { 1771 .name = TYPE_PC_MACHINE, 1772 .parent = TYPE_X86_MACHINE, 1773 .abstract = true, 1774 .instance_size = sizeof(PCMachineState), 1775 .instance_init = pc_machine_initfn, 1776 .class_size = sizeof(PCMachineClass), 1777 .class_init = pc_machine_class_init, 1778 .interfaces = (InterfaceInfo[]) { 1779 { TYPE_HOTPLUG_HANDLER }, 1780 { } 1781 }, 1782 }; 1783 1784 static void pc_machine_register_types(void) 1785 { 1786 type_register_static(&pc_machine_info); 1787 } 1788 1789 type_init(pc_machine_register_types) 1790