1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/cxl/cxl.h" 79 #include "hw/cxl/cxl_host.h" 80 #include "qapi/error.h" 81 #include "qapi/qapi-visit-common.h" 82 #include "qapi/qapi-visit-machine.h" 83 #include "qapi/visitor.h" 84 #include "hw/core/cpu.h" 85 #include "hw/usb.h" 86 #include "hw/i386/intel_iommu.h" 87 #include "hw/net/ne2000-isa.h" 88 #include "standard-headers/asm-x86/bootparam.h" 89 #include "hw/virtio/virtio-iommu.h" 90 #include "hw/virtio/virtio-pmem-pci.h" 91 #include "hw/virtio/virtio-mem-pci.h" 92 #include "hw/mem/memory-device.h" 93 #include "sysemu/replay.h" 94 #include "target/i386/cpu.h" 95 #include "e820_memory_layout.h" 96 #include "fw_cfg.h" 97 #include "trace.h" 98 #include CONFIG_DEVICES 99 100 /* 101 * Helper for setting model-id for CPU models that changed model-id 102 * depending on QEMU versions up to QEMU 2.4. 103 */ 104 #define PC_CPU_MODEL_IDS(v) \ 105 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 106 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 107 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 108 109 GlobalProperty pc_compat_7_2[] = { 110 { "ICH9-LPC", "noreboot", "true" }, 111 }; 112 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 113 114 GlobalProperty pc_compat_7_1[] = {}; 115 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 116 117 GlobalProperty pc_compat_7_0[] = {}; 118 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 119 120 GlobalProperty pc_compat_6_2[] = { 121 { "virtio-mem", "unplugged-inaccessible", "off" }, 122 }; 123 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 124 125 GlobalProperty pc_compat_6_1[] = { 126 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 127 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 128 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 129 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 130 }; 131 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 132 133 GlobalProperty pc_compat_6_0[] = { 134 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 135 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 136 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 137 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 138 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 139 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 140 }; 141 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 142 143 GlobalProperty pc_compat_5_2[] = { 144 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 145 }; 146 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 147 148 GlobalProperty pc_compat_5_1[] = { 149 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 150 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 151 }; 152 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 153 154 GlobalProperty pc_compat_5_0[] = { 155 }; 156 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 157 158 GlobalProperty pc_compat_4_2[] = { 159 { "mch", "smbase-smram", "off" }, 160 }; 161 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 162 163 GlobalProperty pc_compat_4_1[] = {}; 164 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 165 166 GlobalProperty pc_compat_4_0[] = {}; 167 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 168 169 GlobalProperty pc_compat_3_1[] = { 170 { "intel-iommu", "dma-drain", "off" }, 171 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 172 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 173 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 174 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 175 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 176 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 177 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 178 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 179 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 180 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 181 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 182 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 183 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 184 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 185 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 186 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 187 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 190 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 191 }; 192 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 193 194 GlobalProperty pc_compat_3_0[] = { 195 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 196 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 197 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 198 }; 199 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 200 201 GlobalProperty pc_compat_2_12[] = { 202 { TYPE_X86_CPU, "legacy-cache", "on" }, 203 { TYPE_X86_CPU, "topoext", "off" }, 204 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 205 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 206 }; 207 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 208 209 GlobalProperty pc_compat_2_11[] = { 210 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 211 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 212 }; 213 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 214 215 GlobalProperty pc_compat_2_10[] = { 216 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 217 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 218 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 219 }; 220 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 221 222 GlobalProperty pc_compat_2_9[] = { 223 { "mch", "extended-tseg-mbytes", "0" }, 224 }; 225 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 226 227 GlobalProperty pc_compat_2_8[] = { 228 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 229 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 230 { "ICH9-LPC", "x-smi-broadcast", "off" }, 231 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 232 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 233 }; 234 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 235 236 GlobalProperty pc_compat_2_7[] = { 237 { TYPE_X86_CPU, "l3-cache", "off" }, 238 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 239 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 240 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 241 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 242 { "isa-pcspk", "migrate", "off" }, 243 }; 244 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 245 246 GlobalProperty pc_compat_2_6[] = { 247 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 248 { "vmxnet3", "romfile", "" }, 249 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 250 { "apic-common", "legacy-instance-id", "on", } 251 }; 252 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 253 254 GlobalProperty pc_compat_2_5[] = {}; 255 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 256 257 GlobalProperty pc_compat_2_4[] = { 258 PC_CPU_MODEL_IDS("2.4.0") 259 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 260 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 261 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 262 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 263 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 264 { TYPE_X86_CPU, "check", "off" }, 265 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 266 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 267 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 268 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 269 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 270 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 271 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 272 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 273 }; 274 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 275 276 GlobalProperty pc_compat_2_3[] = { 277 PC_CPU_MODEL_IDS("2.3.0") 278 { TYPE_X86_CPU, "arat", "off" }, 279 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 280 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 281 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 282 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 283 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 284 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 285 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 286 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 287 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 288 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 289 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 290 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 291 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 292 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 293 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 294 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 295 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 296 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 297 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 298 }; 299 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 300 301 GlobalProperty pc_compat_2_2[] = { 302 PC_CPU_MODEL_IDS("2.2.0") 303 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 307 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 308 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 309 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 310 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 311 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 312 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 313 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 314 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 315 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 316 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 317 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 318 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 319 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 320 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 321 }; 322 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 323 324 GlobalProperty pc_compat_2_1[] = { 325 PC_CPU_MODEL_IDS("2.1.0") 326 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 327 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 328 }; 329 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 330 331 GlobalProperty pc_compat_2_0[] = { 332 PC_CPU_MODEL_IDS("2.0.0") 333 { "virtio-scsi-pci", "any_layout", "off" }, 334 { "PIIX4_PM", "memory-hotplug-support", "off" }, 335 { "apic", "version", "0x11" }, 336 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 337 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 338 { "pci-serial", "prog_if", "0" }, 339 { "pci-serial-2x", "prog_if", "0" }, 340 { "pci-serial-4x", "prog_if", "0" }, 341 { "virtio-net-pci", "guest_announce", "off" }, 342 { "ICH9-LPC", "memory-hotplug-support", "off" }, 343 }; 344 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 345 346 GlobalProperty pc_compat_1_7[] = { 347 PC_CPU_MODEL_IDS("1.7.0") 348 { TYPE_USB_DEVICE, "msos-desc", "no" }, 349 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 350 { "hpet", HPET_INTCAP, "4" }, 351 }; 352 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 353 354 GlobalProperty pc_compat_1_6[] = { 355 PC_CPU_MODEL_IDS("1.6.0") 356 { "e1000", "mitigation", "off" }, 357 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 358 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 359 { "i440FX-pcihost", "short_root_bus", "1" }, 360 { "q35-pcihost", "short_root_bus", "1" }, 361 }; 362 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 363 364 GlobalProperty pc_compat_1_5[] = { 365 PC_CPU_MODEL_IDS("1.5.0") 366 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 367 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 368 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 369 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 370 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 371 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 372 { "virtio-net-pci", "any_layout", "off" }, 373 { TYPE_X86_CPU, "pmu", "on" }, 374 { "i440FX-pcihost", "short_root_bus", "0" }, 375 { "q35-pcihost", "short_root_bus", "0" }, 376 }; 377 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 378 379 GlobalProperty pc_compat_1_4[] = { 380 PC_CPU_MODEL_IDS("1.4.0") 381 { "scsi-hd", "discard_granularity", "0" }, 382 { "scsi-cd", "discard_granularity", "0" }, 383 { "ide-hd", "discard_granularity", "0" }, 384 { "ide-cd", "discard_granularity", "0" }, 385 { "virtio-blk-pci", "discard_granularity", "0" }, 386 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 387 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 388 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 389 { "e1000", "romfile", "pxe-e1000.rom" }, 390 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 391 { "pcnet", "romfile", "pxe-pcnet.rom" }, 392 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 393 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 394 { "486-" TYPE_X86_CPU, "model", "0" }, 395 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 396 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 397 }; 398 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 399 400 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 401 { 402 GSIState *s; 403 404 s = g_new0(GSIState, 1); 405 if (kvm_ioapic_in_kernel()) { 406 kvm_pc_setup_irq_routing(pci_enabled); 407 } 408 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 409 410 return s; 411 } 412 413 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 414 unsigned size) 415 { 416 } 417 418 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 419 { 420 return 0xffffffffffffffffULL; 421 } 422 423 /* MSDOS compatibility mode FPU exception support */ 424 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 425 unsigned size) 426 { 427 if (tcg_enabled()) { 428 cpu_set_ignne(); 429 } 430 } 431 432 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 433 { 434 return 0xffffffffffffffffULL; 435 } 436 437 /* PC cmos mappings */ 438 439 #define REG_EQUIPMENT_BYTE 0x14 440 441 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 442 int16_t cylinders, int8_t heads, int8_t sectors) 443 { 444 rtc_set_memory(s, type_ofs, 47); 445 rtc_set_memory(s, info_ofs, cylinders); 446 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 447 rtc_set_memory(s, info_ofs + 2, heads); 448 rtc_set_memory(s, info_ofs + 3, 0xff); 449 rtc_set_memory(s, info_ofs + 4, 0xff); 450 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 451 rtc_set_memory(s, info_ofs + 6, cylinders); 452 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 453 rtc_set_memory(s, info_ofs + 8, sectors); 454 } 455 456 /* convert boot_device letter to something recognizable by the bios */ 457 static int boot_device2nibble(char boot_device) 458 { 459 switch(boot_device) { 460 case 'a': 461 case 'b': 462 return 0x01; /* floppy boot */ 463 case 'c': 464 return 0x02; /* hard drive boot */ 465 case 'd': 466 return 0x03; /* CD-ROM boot */ 467 case 'n': 468 return 0x04; /* Network boot */ 469 } 470 return 0; 471 } 472 473 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 474 { 475 #define PC_MAX_BOOT_DEVICES 3 476 int nbds, bds[3] = { 0, }; 477 int i; 478 479 nbds = strlen(boot_device); 480 if (nbds > PC_MAX_BOOT_DEVICES) { 481 error_setg(errp, "Too many boot devices for PC"); 482 return; 483 } 484 for (i = 0; i < nbds; i++) { 485 bds[i] = boot_device2nibble(boot_device[i]); 486 if (bds[i] == 0) { 487 error_setg(errp, "Invalid boot device for PC: '%c'", 488 boot_device[i]); 489 return; 490 } 491 } 492 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 493 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 494 } 495 496 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 497 { 498 set_boot_dev(opaque, boot_device, errp); 499 } 500 501 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 502 { 503 int val, nb, i; 504 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 505 FLOPPY_DRIVE_TYPE_NONE }; 506 507 /* floppy type */ 508 if (floppy) { 509 for (i = 0; i < 2; i++) { 510 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 511 } 512 } 513 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 514 cmos_get_fd_drive_type(fd_type[1]); 515 rtc_set_memory(rtc_state, 0x10, val); 516 517 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 518 nb = 0; 519 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 520 nb++; 521 } 522 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 523 nb++; 524 } 525 switch (nb) { 526 case 0: 527 break; 528 case 1: 529 val |= 0x01; /* 1 drive, ready for boot */ 530 break; 531 case 2: 532 val |= 0x41; /* 2 drives, ready for boot */ 533 break; 534 } 535 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 536 } 537 538 typedef struct pc_cmos_init_late_arg { 539 ISADevice *rtc_state; 540 BusState *idebus[2]; 541 } pc_cmos_init_late_arg; 542 543 typedef struct check_fdc_state { 544 ISADevice *floppy; 545 bool multiple; 546 } CheckFdcState; 547 548 static int check_fdc(Object *obj, void *opaque) 549 { 550 CheckFdcState *state = opaque; 551 Object *fdc; 552 uint32_t iobase; 553 Error *local_err = NULL; 554 555 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 556 if (!fdc) { 557 return 0; 558 } 559 560 iobase = object_property_get_uint(obj, "iobase", &local_err); 561 if (local_err || iobase != 0x3f0) { 562 error_free(local_err); 563 return 0; 564 } 565 566 if (state->floppy) { 567 state->multiple = true; 568 } else { 569 state->floppy = ISA_DEVICE(obj); 570 } 571 return 0; 572 } 573 574 static const char * const fdc_container_path[] = { 575 "/unattached", "/peripheral", "/peripheral-anon" 576 }; 577 578 /* 579 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 580 * and ACPI objects. 581 */ 582 static ISADevice *pc_find_fdc0(void) 583 { 584 int i; 585 Object *container; 586 CheckFdcState state = { 0 }; 587 588 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 589 container = container_get(qdev_get_machine(), fdc_container_path[i]); 590 object_child_foreach(container, check_fdc, &state); 591 } 592 593 if (state.multiple) { 594 warn_report("multiple floppy disk controllers with " 595 "iobase=0x3f0 have been found"); 596 error_printf("the one being picked for CMOS setup might not reflect " 597 "your intent"); 598 } 599 600 return state.floppy; 601 } 602 603 static void pc_cmos_init_late(void *opaque) 604 { 605 pc_cmos_init_late_arg *arg = opaque; 606 ISADevice *s = arg->rtc_state; 607 int16_t cylinders; 608 int8_t heads, sectors; 609 int val; 610 int i, trans; 611 612 val = 0; 613 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 614 &cylinders, &heads, §ors) >= 0) { 615 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 616 val |= 0xf0; 617 } 618 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 619 &cylinders, &heads, §ors) >= 0) { 620 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 621 val |= 0x0f; 622 } 623 rtc_set_memory(s, 0x12, val); 624 625 val = 0; 626 for (i = 0; i < 4; i++) { 627 /* NOTE: ide_get_geometry() returns the physical 628 geometry. It is always such that: 1 <= sects <= 63, 1 629 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 630 geometry can be different if a translation is done. */ 631 if (arg->idebus[i / 2] && 632 ide_get_geometry(arg->idebus[i / 2], i % 2, 633 &cylinders, &heads, §ors) >= 0) { 634 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 635 assert((trans & ~3) == 0); 636 val |= trans << (i * 2); 637 } 638 } 639 rtc_set_memory(s, 0x39, val); 640 641 pc_cmos_init_floppy(s, pc_find_fdc0()); 642 643 qemu_unregister_reset(pc_cmos_init_late, opaque); 644 } 645 646 void pc_cmos_init(PCMachineState *pcms, 647 BusState *idebus0, BusState *idebus1, 648 ISADevice *s) 649 { 650 int val; 651 static pc_cmos_init_late_arg arg; 652 X86MachineState *x86ms = X86_MACHINE(pcms); 653 654 /* various important CMOS locations needed by PC/Bochs bios */ 655 656 /* memory size */ 657 /* base memory (first MiB) */ 658 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 659 rtc_set_memory(s, 0x15, val); 660 rtc_set_memory(s, 0x16, val >> 8); 661 /* extended memory (next 64MiB) */ 662 if (x86ms->below_4g_mem_size > 1 * MiB) { 663 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 664 } else { 665 val = 0; 666 } 667 if (val > 65535) 668 val = 65535; 669 rtc_set_memory(s, 0x17, val); 670 rtc_set_memory(s, 0x18, val >> 8); 671 rtc_set_memory(s, 0x30, val); 672 rtc_set_memory(s, 0x31, val >> 8); 673 /* memory between 16MiB and 4GiB */ 674 if (x86ms->below_4g_mem_size > 16 * MiB) { 675 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 676 } else { 677 val = 0; 678 } 679 if (val > 65535) 680 val = 65535; 681 rtc_set_memory(s, 0x34, val); 682 rtc_set_memory(s, 0x35, val >> 8); 683 /* memory above 4GiB */ 684 val = x86ms->above_4g_mem_size / 65536; 685 rtc_set_memory(s, 0x5b, val); 686 rtc_set_memory(s, 0x5c, val >> 8); 687 rtc_set_memory(s, 0x5d, val >> 16); 688 689 object_property_add_link(OBJECT(pcms), "rtc_state", 690 TYPE_ISA_DEVICE, 691 (Object **)&x86ms->rtc, 692 object_property_allow_set_link, 693 OBJ_PROP_LINK_STRONG); 694 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 695 &error_abort); 696 697 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 698 699 val = 0; 700 val |= 0x02; /* FPU is there */ 701 val |= 0x04; /* PS/2 mouse installed */ 702 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 703 704 /* hard drives and FDC */ 705 arg.rtc_state = s; 706 arg.idebus[0] = idebus0; 707 arg.idebus[1] = idebus1; 708 qemu_register_reset(pc_cmos_init_late, &arg); 709 } 710 711 static void handle_a20_line_change(void *opaque, int irq, int level) 712 { 713 X86CPU *cpu = opaque; 714 715 /* XXX: send to all CPUs ? */ 716 /* XXX: add logic to handle multiple A20 line sources */ 717 x86_cpu_set_a20(cpu, level); 718 } 719 720 #define NE2000_NB_MAX 6 721 722 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 723 0x280, 0x380 }; 724 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 725 726 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 727 { 728 static int nb_ne2k = 0; 729 730 if (nb_ne2k == NE2000_NB_MAX) 731 return; 732 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 733 ne2000_irq[nb_ne2k], nd); 734 nb_ne2k++; 735 } 736 737 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 738 { 739 X86CPU *cpu = opaque; 740 741 if (level) { 742 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 743 } 744 } 745 746 static 747 void pc_machine_done(Notifier *notifier, void *data) 748 { 749 PCMachineState *pcms = container_of(notifier, 750 PCMachineState, machine_done); 751 X86MachineState *x86ms = X86_MACHINE(pcms); 752 753 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 754 &error_fatal); 755 756 if (pcms->cxl_devices_state.is_enabled) { 757 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 758 } 759 760 /* set the number of CPUs */ 761 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 762 763 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 764 765 acpi_setup(); 766 if (x86ms->fw_cfg) { 767 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 768 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 769 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 770 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 771 } 772 } 773 774 void pc_guest_info_init(PCMachineState *pcms) 775 { 776 X86MachineState *x86ms = X86_MACHINE(pcms); 777 778 x86ms->apic_xrupt_override = true; 779 pcms->machine_done.notify = pc_machine_done; 780 qemu_add_machine_init_done_notifier(&pcms->machine_done); 781 } 782 783 /* setup pci memory address space mapping into system address space */ 784 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 785 MemoryRegion *pci_address_space) 786 { 787 /* Set to lower priority than RAM */ 788 memory_region_add_subregion_overlap(system_memory, 0x0, 789 pci_address_space, -1); 790 } 791 792 void xen_load_linux(PCMachineState *pcms) 793 { 794 int i; 795 FWCfgState *fw_cfg; 796 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 797 X86MachineState *x86ms = X86_MACHINE(pcms); 798 799 assert(MACHINE(pcms)->kernel_filename != NULL); 800 801 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 802 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 803 rom_set_fw(fw_cfg); 804 805 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 806 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 807 for (i = 0; i < nb_option_roms; i++) { 808 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 809 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 810 !strcmp(option_rom[i].name, "pvh.bin") || 811 !strcmp(option_rom[i].name, "multiboot.bin") || 812 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 813 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 814 } 815 x86ms->fw_cfg = fw_cfg; 816 } 817 818 #define PC_ROM_MIN_VGA 0xc0000 819 #define PC_ROM_MIN_OPTION 0xc8000 820 #define PC_ROM_MAX 0xe0000 821 #define PC_ROM_ALIGN 0x800 822 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 823 824 static hwaddr pc_above_4g_end(PCMachineState *pcms) 825 { 826 X86MachineState *x86ms = X86_MACHINE(pcms); 827 828 if (pcms->sgx_epc.size != 0) { 829 return sgx_epc_above_4g_end(&pcms->sgx_epc); 830 } 831 832 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 833 } 834 835 static void pc_get_device_memory_range(PCMachineState *pcms, 836 hwaddr *base, 837 ram_addr_t *device_mem_size) 838 { 839 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 840 MachineState *machine = MACHINE(pcms); 841 ram_addr_t size; 842 hwaddr addr; 843 844 size = machine->maxram_size - machine->ram_size; 845 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 846 847 if (pcmc->enforce_aligned_dimm) { 848 /* size device region assuming 1G page max alignment per slot */ 849 size += (1 * GiB) * machine->ram_slots; 850 } 851 852 *base = addr; 853 *device_mem_size = size; 854 } 855 856 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 857 { 858 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 859 hwaddr cxl_base; 860 ram_addr_t size; 861 862 if (pcmc->has_reserved_memory) { 863 pc_get_device_memory_range(pcms, &cxl_base, &size); 864 cxl_base += size; 865 } else { 866 cxl_base = pc_above_4g_end(pcms); 867 } 868 869 return cxl_base; 870 } 871 872 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 873 { 874 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 875 876 if (pcms->cxl_devices_state.fixed_windows) { 877 GList *it; 878 879 start = ROUND_UP(start, 256 * MiB); 880 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 881 CXLFixedWindow *fw = it->data; 882 start += fw->size; 883 } 884 } 885 886 return start; 887 } 888 889 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 890 { 891 X86CPU *cpu = X86_CPU(first_cpu); 892 893 /* 32-bit systems don't have hole64 thus return max CPU address */ 894 if (cpu->phys_bits <= 32) { 895 return ((hwaddr)1 << cpu->phys_bits) - 1; 896 } 897 898 return pc_pci_hole64_start() + pci_hole64_size - 1; 899 } 900 901 /* 902 * AMD systems with an IOMMU have an additional hole close to the 903 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 904 * on kernel version, VFIO may or may not let you DMA map those ranges. 905 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 906 * with certain memory sizes. It's also wrong to use those IOVA ranges 907 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 908 * The ranges reserved for Hyper-Transport are: 909 * 910 * FD_0000_0000h - FF_FFFF_FFFFh 911 * 912 * The ranges represent the following: 913 * 914 * Base Address Top Address Use 915 * 916 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 917 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 918 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 919 * FD_F910_0000h FD_F91F_FFFFh System Management 920 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 921 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 922 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 923 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 924 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 925 * FE_2000_0000h FF_FFFF_FFFFh Reserved 926 * 927 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 928 * Table 3: Special Address Controls (GPA) for more information. 929 */ 930 #define AMD_HT_START 0xfd00000000UL 931 #define AMD_HT_END 0xffffffffffUL 932 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 933 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 934 935 void pc_memory_init(PCMachineState *pcms, 936 MemoryRegion *system_memory, 937 MemoryRegion *rom_memory, 938 MemoryRegion **ram_memory, 939 uint64_t pci_hole64_size) 940 { 941 int linux_boot, i; 942 MemoryRegion *option_rom_mr; 943 MemoryRegion *ram_below_4g, *ram_above_4g; 944 FWCfgState *fw_cfg; 945 MachineState *machine = MACHINE(pcms); 946 MachineClass *mc = MACHINE_GET_CLASS(machine); 947 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 948 X86MachineState *x86ms = X86_MACHINE(pcms); 949 hwaddr maxphysaddr, maxusedaddr; 950 hwaddr cxl_base, cxl_resv_end = 0; 951 X86CPU *cpu = X86_CPU(first_cpu); 952 953 assert(machine->ram_size == x86ms->below_4g_mem_size + 954 x86ms->above_4g_mem_size); 955 956 linux_boot = (machine->kernel_filename != NULL); 957 958 /* 959 * The HyperTransport range close to the 1T boundary is unique to AMD 960 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 961 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 962 * older machine types (<= 7.0) for compatibility purposes. 963 */ 964 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 965 /* Bail out if max possible address does not cross HT range */ 966 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 967 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 968 } 969 970 /* 971 * Advertise the HT region if address space covers the reserved 972 * region or if we relocate. 973 */ 974 if (cpu->phys_bits >= 40) { 975 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 976 } 977 } 978 979 /* 980 * phys-bits is required to be appropriately configured 981 * to make sure max used GPA is reachable. 982 */ 983 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 984 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 985 if (maxphysaddr < maxusedaddr) { 986 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 987 " phys-bits too low (%u)", 988 maxphysaddr, maxusedaddr, cpu->phys_bits); 989 exit(EXIT_FAILURE); 990 } 991 992 /* 993 * Split single memory region and use aliases to address portions of it, 994 * done for backwards compatibility with older qemus. 995 */ 996 *ram_memory = machine->ram; 997 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 998 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 999 0, x86ms->below_4g_mem_size); 1000 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1001 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1002 if (x86ms->above_4g_mem_size > 0) { 1003 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1004 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1005 machine->ram, 1006 x86ms->below_4g_mem_size, 1007 x86ms->above_4g_mem_size); 1008 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1009 ram_above_4g); 1010 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1011 E820_RAM); 1012 } 1013 1014 if (pcms->sgx_epc.size != 0) { 1015 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1016 } 1017 1018 if (!pcmc->has_reserved_memory && 1019 (machine->ram_slots || 1020 (machine->maxram_size > machine->ram_size))) { 1021 1022 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1023 mc->name); 1024 exit(EXIT_FAILURE); 1025 } 1026 1027 /* always allocate the device memory information */ 1028 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1029 1030 /* initialize device memory address space */ 1031 if (pcmc->has_reserved_memory && 1032 (machine->ram_size < machine->maxram_size)) { 1033 ram_addr_t device_mem_size; 1034 1035 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1036 error_report("unsupported amount of memory slots: %"PRIu64, 1037 machine->ram_slots); 1038 exit(EXIT_FAILURE); 1039 } 1040 1041 if (QEMU_ALIGN_UP(machine->maxram_size, 1042 TARGET_PAGE_SIZE) != machine->maxram_size) { 1043 error_report("maximum memory size must by aligned to multiple of " 1044 "%d bytes", TARGET_PAGE_SIZE); 1045 exit(EXIT_FAILURE); 1046 } 1047 1048 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1049 1050 if ((machine->device_memory->base + device_mem_size) < 1051 device_mem_size) { 1052 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1053 machine->maxram_size); 1054 exit(EXIT_FAILURE); 1055 } 1056 1057 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1058 "device-memory", device_mem_size); 1059 memory_region_add_subregion(system_memory, machine->device_memory->base, 1060 &machine->device_memory->mr); 1061 } 1062 1063 if (pcms->cxl_devices_state.is_enabled) { 1064 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1065 hwaddr cxl_size = MiB; 1066 1067 cxl_base = pc_get_cxl_range_start(pcms); 1068 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1069 memory_region_add_subregion(system_memory, cxl_base, mr); 1070 cxl_resv_end = cxl_base + cxl_size; 1071 if (pcms->cxl_devices_state.fixed_windows) { 1072 hwaddr cxl_fmw_base; 1073 GList *it; 1074 1075 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1076 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1077 CXLFixedWindow *fw = it->data; 1078 1079 fw->base = cxl_fmw_base; 1080 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1081 "cxl-fixed-memory-region", fw->size); 1082 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1083 cxl_fmw_base += fw->size; 1084 cxl_resv_end = cxl_fmw_base; 1085 } 1086 } 1087 } 1088 1089 /* Initialize PC system firmware */ 1090 pc_system_firmware_init(pcms, rom_memory); 1091 1092 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1093 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1094 &error_fatal); 1095 if (pcmc->pci_enabled) { 1096 memory_region_set_readonly(option_rom_mr, true); 1097 } 1098 memory_region_add_subregion_overlap(rom_memory, 1099 PC_ROM_MIN_VGA, 1100 option_rom_mr, 1101 1); 1102 1103 fw_cfg = fw_cfg_arch_create(machine, 1104 x86ms->boot_cpus, x86ms->apic_id_limit); 1105 1106 rom_set_fw(fw_cfg); 1107 1108 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1109 uint64_t *val = g_malloc(sizeof(*val)); 1110 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1111 uint64_t res_mem_end = machine->device_memory->base; 1112 1113 if (!pcmc->broken_reserved_end) { 1114 res_mem_end += memory_region_size(&machine->device_memory->mr); 1115 } 1116 1117 if (pcms->cxl_devices_state.is_enabled) { 1118 res_mem_end = cxl_resv_end; 1119 } 1120 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1121 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1122 } 1123 1124 if (linux_boot) { 1125 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1126 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 1127 } 1128 1129 for (i = 0; i < nb_option_roms; i++) { 1130 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1131 } 1132 x86ms->fw_cfg = fw_cfg; 1133 1134 /* Init default IOAPIC address space */ 1135 x86ms->ioapic_as = &address_space_memory; 1136 1137 /* Init ACPI memory hotplug IO base address */ 1138 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1139 } 1140 1141 /* 1142 * The 64bit pci hole starts after "above 4G RAM" and 1143 * potentially the space reserved for memory hotplug. 1144 */ 1145 uint64_t pc_pci_hole64_start(void) 1146 { 1147 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1148 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1149 MachineState *ms = MACHINE(pcms); 1150 uint64_t hole64_start = 0; 1151 ram_addr_t size = 0; 1152 1153 if (pcms->cxl_devices_state.is_enabled) { 1154 hole64_start = pc_get_cxl_range_end(pcms); 1155 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1156 pc_get_device_memory_range(pcms, &hole64_start, &size); 1157 if (!pcmc->broken_reserved_end) { 1158 hole64_start += size; 1159 } 1160 } else { 1161 hole64_start = pc_above_4g_end(pcms); 1162 } 1163 1164 return ROUND_UP(hole64_start, 1 * GiB); 1165 } 1166 1167 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1168 { 1169 DeviceState *dev = NULL; 1170 1171 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1172 if (pci_bus) { 1173 PCIDevice *pcidev = pci_vga_init(pci_bus); 1174 dev = pcidev ? &pcidev->qdev : NULL; 1175 } else if (isa_bus) { 1176 ISADevice *isadev = isa_vga_init(isa_bus); 1177 dev = isadev ? DEVICE(isadev) : NULL; 1178 } 1179 rom_reset_order_override(); 1180 return dev; 1181 } 1182 1183 static const MemoryRegionOps ioport80_io_ops = { 1184 .write = ioport80_write, 1185 .read = ioport80_read, 1186 .endianness = DEVICE_NATIVE_ENDIAN, 1187 .impl = { 1188 .min_access_size = 1, 1189 .max_access_size = 1, 1190 }, 1191 }; 1192 1193 static const MemoryRegionOps ioportF0_io_ops = { 1194 .write = ioportF0_write, 1195 .read = ioportF0_read, 1196 .endianness = DEVICE_NATIVE_ENDIAN, 1197 .impl = { 1198 .min_access_size = 1, 1199 .max_access_size = 1, 1200 }, 1201 }; 1202 1203 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1204 bool create_i8042, bool no_vmport) 1205 { 1206 int i; 1207 DriveInfo *fd[MAX_FD]; 1208 qemu_irq *a20_line; 1209 ISADevice *fdc, *i8042, *port92, *vmmouse; 1210 1211 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1212 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1213 1214 for (i = 0; i < MAX_FD; i++) { 1215 fd[i] = drive_get(IF_FLOPPY, 0, i); 1216 create_fdctrl |= !!fd[i]; 1217 } 1218 if (create_fdctrl) { 1219 fdc = isa_new(TYPE_ISA_FDC); 1220 if (fdc) { 1221 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1222 isa_fdc_init_drives(fdc, fd); 1223 } 1224 } 1225 1226 if (!create_i8042) { 1227 return; 1228 } 1229 1230 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1231 if (!no_vmport) { 1232 isa_create_simple(isa_bus, TYPE_VMPORT); 1233 vmmouse = isa_try_new("vmmouse"); 1234 } else { 1235 vmmouse = NULL; 1236 } 1237 if (vmmouse) { 1238 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1239 &error_abort); 1240 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1241 } 1242 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1243 1244 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1245 i8042_setup_a20_line(i8042, a20_line[0]); 1246 qdev_connect_gpio_out_named(DEVICE(port92), 1247 PORT92_A20_LINE, 0, a20_line[1]); 1248 g_free(a20_line); 1249 } 1250 1251 void pc_basic_device_init(struct PCMachineState *pcms, 1252 ISABus *isa_bus, qemu_irq *gsi, 1253 ISADevice **rtc_state, 1254 bool create_fdctrl, 1255 uint32_t hpet_irqs) 1256 { 1257 int i; 1258 DeviceState *hpet = NULL; 1259 int pit_isa_irq = 0; 1260 qemu_irq pit_alt_irq = NULL; 1261 qemu_irq rtc_irq = NULL; 1262 ISADevice *pit = NULL; 1263 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1264 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1265 X86MachineState *x86ms = X86_MACHINE(pcms); 1266 1267 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1268 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1269 1270 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1271 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1272 1273 /* 1274 * Check if an HPET shall be created. 1275 * 1276 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1277 * when the HPET wants to take over. Thus we have to disable the latter. 1278 */ 1279 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1280 kvm_has_pit_state2())) { 1281 hpet = qdev_try_new(TYPE_HPET); 1282 if (!hpet) { 1283 error_report("couldn't create HPET device"); 1284 exit(1); 1285 } 1286 /* 1287 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1288 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1289 * IRQ2. 1290 */ 1291 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1292 HPET_INTCAP, NULL); 1293 if (!compat) { 1294 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1295 } 1296 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1297 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1298 1299 for (i = 0; i < GSI_NUM_PINS; i++) { 1300 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1301 } 1302 pit_isa_irq = -1; 1303 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1304 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1305 } 1306 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1307 1308 qemu_register_boot_set(pc_boot_set, *rtc_state); 1309 1310 if (!xen_enabled() && 1311 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1312 if (kvm_pit_in_kernel()) { 1313 pit = kvm_pit_init(isa_bus, 0x40); 1314 } else { 1315 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1316 } 1317 if (hpet) { 1318 /* connect PIT to output control line of the HPET */ 1319 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1320 } 1321 pcspk_init(pcms->pcspk, isa_bus, pit); 1322 } 1323 1324 /* Super I/O */ 1325 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1326 pcms->vmport != ON_OFF_AUTO_ON); 1327 } 1328 1329 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1330 { 1331 int i; 1332 1333 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1334 for (i = 0; i < nb_nics; i++) { 1335 NICInfo *nd = &nd_table[i]; 1336 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1337 1338 if (g_str_equal(model, "ne2k_isa")) { 1339 pc_init_ne2k_isa(isa_bus, nd); 1340 } else { 1341 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1342 } 1343 } 1344 rom_reset_order_override(); 1345 } 1346 1347 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1348 { 1349 qemu_irq *i8259; 1350 1351 if (kvm_pic_in_kernel()) { 1352 i8259 = kvm_i8259_init(isa_bus); 1353 } else if (xen_enabled()) { 1354 i8259 = xen_interrupt_controller_init(); 1355 } else { 1356 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1357 } 1358 1359 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1360 i8259_irqs[i] = i8259[i]; 1361 } 1362 1363 g_free(i8259); 1364 } 1365 1366 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1367 Error **errp) 1368 { 1369 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1370 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1371 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1372 const MachineState *ms = MACHINE(hotplug_dev); 1373 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1374 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1375 Error *local_err = NULL; 1376 1377 /* 1378 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1379 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1380 * addition to cover this case. 1381 */ 1382 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1383 error_setg(errp, 1384 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1385 return; 1386 } 1387 1388 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1389 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1390 return; 1391 } 1392 1393 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1394 if (local_err) { 1395 error_propagate(errp, local_err); 1396 return; 1397 } 1398 1399 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1400 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1401 } 1402 1403 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1404 DeviceState *dev, Error **errp) 1405 { 1406 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1407 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1408 MachineState *ms = MACHINE(hotplug_dev); 1409 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1410 1411 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1412 1413 if (is_nvdimm) { 1414 nvdimm_plug(ms->nvdimms_state); 1415 } 1416 1417 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1418 } 1419 1420 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1421 DeviceState *dev, Error **errp) 1422 { 1423 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1424 1425 /* 1426 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1427 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1428 * addition to cover this case. 1429 */ 1430 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1431 error_setg(errp, 1432 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1433 return; 1434 } 1435 1436 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1437 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1438 return; 1439 } 1440 1441 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1442 errp); 1443 } 1444 1445 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1446 DeviceState *dev, Error **errp) 1447 { 1448 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1449 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1450 Error *local_err = NULL; 1451 1452 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1453 if (local_err) { 1454 goto out; 1455 } 1456 1457 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1458 qdev_unrealize(dev); 1459 out: 1460 error_propagate(errp, local_err); 1461 } 1462 1463 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1464 DeviceState *dev, Error **errp) 1465 { 1466 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1467 Error *local_err = NULL; 1468 1469 if (!hotplug_dev2 && dev->hotplugged) { 1470 /* 1471 * Without a bus hotplug handler, we cannot control the plug/unplug 1472 * order. We should never reach this point when hotplugging on x86, 1473 * however, better add a safety net. 1474 */ 1475 error_setg(errp, "hotplug of virtio based memory devices not supported" 1476 " on this bus."); 1477 return; 1478 } 1479 /* 1480 * First, see if we can plug this memory device at all. If that 1481 * succeeds, branch of to the actual hotplug handler. 1482 */ 1483 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1484 &local_err); 1485 if (!local_err && hotplug_dev2) { 1486 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1487 } 1488 error_propagate(errp, local_err); 1489 } 1490 1491 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1492 DeviceState *dev, Error **errp) 1493 { 1494 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1495 Error *local_err = NULL; 1496 1497 /* 1498 * Plug the memory device first and then branch off to the actual 1499 * hotplug handler. If that one fails, we can easily undo the memory 1500 * device bits. 1501 */ 1502 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1503 if (hotplug_dev2) { 1504 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1505 if (local_err) { 1506 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1507 } 1508 } 1509 error_propagate(errp, local_err); 1510 } 1511 1512 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1513 DeviceState *dev, Error **errp) 1514 { 1515 /* We don't support hot unplug of virtio based memory devices */ 1516 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1517 } 1518 1519 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1520 DeviceState *dev, Error **errp) 1521 { 1522 /* We don't support hot unplug of virtio based memory devices */ 1523 } 1524 1525 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1526 DeviceState *dev, Error **errp) 1527 { 1528 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1529 pc_memory_pre_plug(hotplug_dev, dev, errp); 1530 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1531 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1532 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1533 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1534 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1535 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1536 /* Declare the APIC range as the reserved MSI region */ 1537 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1538 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1539 1540 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1541 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1542 resv_prop_str, errp); 1543 g_free(resv_prop_str); 1544 } 1545 1546 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1547 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1548 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1549 1550 if (pcms->iommu) { 1551 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1552 "for x86 yet."); 1553 return; 1554 } 1555 pcms->iommu = dev; 1556 } 1557 } 1558 1559 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1560 DeviceState *dev, Error **errp) 1561 { 1562 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1563 pc_memory_plug(hotplug_dev, dev, errp); 1564 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1565 x86_cpu_plug(hotplug_dev, dev, errp); 1566 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1567 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1568 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1569 } 1570 } 1571 1572 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1573 DeviceState *dev, Error **errp) 1574 { 1575 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1576 pc_memory_unplug_request(hotplug_dev, dev, errp); 1577 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1578 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1579 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1580 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1581 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1582 } else { 1583 error_setg(errp, "acpi: device unplug request for not supported device" 1584 " type: %s", object_get_typename(OBJECT(dev))); 1585 } 1586 } 1587 1588 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1589 DeviceState *dev, Error **errp) 1590 { 1591 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1592 pc_memory_unplug(hotplug_dev, dev, errp); 1593 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1594 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1595 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1596 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1597 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1598 } else { 1599 error_setg(errp, "acpi: device unplug for not supported device" 1600 " type: %s", object_get_typename(OBJECT(dev))); 1601 } 1602 } 1603 1604 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1605 DeviceState *dev) 1606 { 1607 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1608 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1609 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1610 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1611 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1612 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1613 return HOTPLUG_HANDLER(machine); 1614 } 1615 1616 return NULL; 1617 } 1618 1619 static void 1620 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1621 const char *name, void *opaque, 1622 Error **errp) 1623 { 1624 MachineState *ms = MACHINE(obj); 1625 int64_t value = 0; 1626 1627 if (ms->device_memory) { 1628 value = memory_region_size(&ms->device_memory->mr); 1629 } 1630 1631 visit_type_int(v, name, &value, errp); 1632 } 1633 1634 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1635 void *opaque, Error **errp) 1636 { 1637 PCMachineState *pcms = PC_MACHINE(obj); 1638 OnOffAuto vmport = pcms->vmport; 1639 1640 visit_type_OnOffAuto(v, name, &vmport, errp); 1641 } 1642 1643 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1644 void *opaque, Error **errp) 1645 { 1646 PCMachineState *pcms = PC_MACHINE(obj); 1647 1648 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1649 } 1650 1651 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1652 { 1653 PCMachineState *pcms = PC_MACHINE(obj); 1654 1655 return pcms->smbus_enabled; 1656 } 1657 1658 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1659 { 1660 PCMachineState *pcms = PC_MACHINE(obj); 1661 1662 pcms->smbus_enabled = value; 1663 } 1664 1665 static bool pc_machine_get_sata(Object *obj, Error **errp) 1666 { 1667 PCMachineState *pcms = PC_MACHINE(obj); 1668 1669 return pcms->sata_enabled; 1670 } 1671 1672 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1673 { 1674 PCMachineState *pcms = PC_MACHINE(obj); 1675 1676 pcms->sata_enabled = value; 1677 } 1678 1679 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1680 { 1681 PCMachineState *pcms = PC_MACHINE(obj); 1682 1683 return pcms->hpet_enabled; 1684 } 1685 1686 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1687 { 1688 PCMachineState *pcms = PC_MACHINE(obj); 1689 1690 pcms->hpet_enabled = value; 1691 } 1692 1693 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1694 { 1695 PCMachineState *pcms = PC_MACHINE(obj); 1696 1697 return pcms->i8042_enabled; 1698 } 1699 1700 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1701 { 1702 PCMachineState *pcms = PC_MACHINE(obj); 1703 1704 pcms->i8042_enabled = value; 1705 } 1706 1707 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1708 { 1709 PCMachineState *pcms = PC_MACHINE(obj); 1710 1711 return pcms->default_bus_bypass_iommu; 1712 } 1713 1714 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1715 Error **errp) 1716 { 1717 PCMachineState *pcms = PC_MACHINE(obj); 1718 1719 pcms->default_bus_bypass_iommu = value; 1720 } 1721 1722 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1723 void *opaque, Error **errp) 1724 { 1725 PCMachineState *pcms = PC_MACHINE(obj); 1726 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1727 1728 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1729 } 1730 1731 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1732 void *opaque, Error **errp) 1733 { 1734 PCMachineState *pcms = PC_MACHINE(obj); 1735 1736 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1737 } 1738 1739 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1740 const char *name, void *opaque, 1741 Error **errp) 1742 { 1743 PCMachineState *pcms = PC_MACHINE(obj); 1744 uint64_t value = pcms->max_ram_below_4g; 1745 1746 visit_type_size(v, name, &value, errp); 1747 } 1748 1749 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1750 const char *name, void *opaque, 1751 Error **errp) 1752 { 1753 PCMachineState *pcms = PC_MACHINE(obj); 1754 uint64_t value; 1755 1756 if (!visit_type_size(v, name, &value, errp)) { 1757 return; 1758 } 1759 if (value > 4 * GiB) { 1760 error_setg(errp, 1761 "Machine option 'max-ram-below-4g=%"PRIu64 1762 "' expects size less than or equal to 4G", value); 1763 return; 1764 } 1765 1766 if (value < 1 * MiB) { 1767 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1768 "BIOS may not work with less than 1MiB", value); 1769 } 1770 1771 pcms->max_ram_below_4g = value; 1772 } 1773 1774 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1775 const char *name, void *opaque, 1776 Error **errp) 1777 { 1778 PCMachineState *pcms = PC_MACHINE(obj); 1779 uint64_t value = pcms->max_fw_size; 1780 1781 visit_type_size(v, name, &value, errp); 1782 } 1783 1784 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1785 const char *name, void *opaque, 1786 Error **errp) 1787 { 1788 PCMachineState *pcms = PC_MACHINE(obj); 1789 uint64_t value; 1790 1791 if (!visit_type_size(v, name, &value, errp)) { 1792 return; 1793 } 1794 1795 /* 1796 * We don't have a theoretically justifiable exact lower bound on the base 1797 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1798 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1799 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1800 * size. 1801 */ 1802 if (value > 16 * MiB) { 1803 error_setg(errp, 1804 "User specified max allowed firmware size %" PRIu64 " is " 1805 "greater than 16MiB. If combined firwmare size exceeds " 1806 "16MiB the system may not boot, or experience intermittent" 1807 "stability issues.", 1808 value); 1809 return; 1810 } 1811 1812 pcms->max_fw_size = value; 1813 } 1814 1815 1816 static void pc_machine_initfn(Object *obj) 1817 { 1818 PCMachineState *pcms = PC_MACHINE(obj); 1819 1820 #ifdef CONFIG_VMPORT 1821 pcms->vmport = ON_OFF_AUTO_AUTO; 1822 #else 1823 pcms->vmport = ON_OFF_AUTO_OFF; 1824 #endif /* CONFIG_VMPORT */ 1825 pcms->max_ram_below_4g = 0; /* use default */ 1826 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1827 1828 /* acpi build is enabled by default if machine supports it */ 1829 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1830 pcms->smbus_enabled = true; 1831 pcms->sata_enabled = true; 1832 pcms->i8042_enabled = true; 1833 pcms->max_fw_size = 8 * MiB; 1834 #ifdef CONFIG_HPET 1835 pcms->hpet_enabled = true; 1836 #endif 1837 pcms->default_bus_bypass_iommu = false; 1838 1839 pc_system_flash_create(pcms); 1840 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1841 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1842 OBJECT(pcms->pcspk), "audiodev"); 1843 cxl_machine_init(obj, &pcms->cxl_devices_state); 1844 } 1845 1846 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1847 { 1848 CPUState *cs; 1849 X86CPU *cpu; 1850 1851 qemu_devices_reset(reason); 1852 1853 /* Reset APIC after devices have been reset to cancel 1854 * any changes that qemu_devices_reset() might have done. 1855 */ 1856 CPU_FOREACH(cs) { 1857 cpu = X86_CPU(cs); 1858 1859 x86_cpu_after_reset(cpu); 1860 } 1861 } 1862 1863 static void pc_machine_wakeup(MachineState *machine) 1864 { 1865 cpu_synchronize_all_states(); 1866 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1867 cpu_synchronize_all_post_reset(); 1868 } 1869 1870 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1871 { 1872 X86IOMMUState *iommu = x86_iommu_get_default(); 1873 IntelIOMMUState *intel_iommu; 1874 1875 if (iommu && 1876 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1877 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1878 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1879 if (!intel_iommu->caching_mode) { 1880 error_setg(errp, "Device assignment is not allowed without " 1881 "enabling caching-mode=on for Intel IOMMU."); 1882 return false; 1883 } 1884 } 1885 1886 return true; 1887 } 1888 1889 static void pc_machine_class_init(ObjectClass *oc, void *data) 1890 { 1891 MachineClass *mc = MACHINE_CLASS(oc); 1892 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1893 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1894 1895 pcmc->pci_enabled = true; 1896 pcmc->has_acpi_build = true; 1897 pcmc->rsdp_in_ram = true; 1898 pcmc->smbios_defaults = true; 1899 pcmc->smbios_uuid_encoded = true; 1900 pcmc->gigabyte_align = true; 1901 pcmc->has_reserved_memory = true; 1902 pcmc->kvmclock_enabled = true; 1903 pcmc->enforce_aligned_dimm = true; 1904 pcmc->enforce_amd_1tb_hole = true; 1905 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1906 * to be used at the moment, 32K should be enough for a while. */ 1907 pcmc->acpi_data_size = 0x20000 + 0x8000; 1908 pcmc->pvh_enabled = true; 1909 pcmc->kvmclock_create_always = true; 1910 assert(!mc->get_hotplug_handler); 1911 mc->get_hotplug_handler = pc_get_hotplug_handler; 1912 mc->hotplug_allowed = pc_hotplug_allowed; 1913 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1914 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1915 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1916 mc->auto_enable_numa_with_memhp = true; 1917 mc->auto_enable_numa_with_memdev = true; 1918 mc->has_hotpluggable_cpus = true; 1919 mc->default_boot_order = "cad"; 1920 mc->block_default_type = IF_IDE; 1921 mc->max_cpus = 255; 1922 mc->reset = pc_machine_reset; 1923 mc->wakeup = pc_machine_wakeup; 1924 hc->pre_plug = pc_machine_device_pre_plug_cb; 1925 hc->plug = pc_machine_device_plug_cb; 1926 hc->unplug_request = pc_machine_device_unplug_request_cb; 1927 hc->unplug = pc_machine_device_unplug_cb; 1928 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1929 mc->nvdimm_supported = true; 1930 mc->smp_props.dies_supported = true; 1931 mc->default_ram_id = "pc.ram"; 1932 1933 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1934 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1935 NULL, NULL); 1936 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1937 "Maximum ram below the 4G boundary (32bit boundary)"); 1938 1939 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1940 pc_machine_get_device_memory_region_size, NULL, 1941 NULL, NULL); 1942 1943 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1944 pc_machine_get_vmport, pc_machine_set_vmport, 1945 NULL, NULL); 1946 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1947 "Enable vmport (pc & q35)"); 1948 1949 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1950 pc_machine_get_smbus, pc_machine_set_smbus); 1951 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1952 "Enable/disable system management bus"); 1953 1954 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1955 pc_machine_get_sata, pc_machine_set_sata); 1956 object_class_property_set_description(oc, PC_MACHINE_SATA, 1957 "Enable/disable Serial ATA bus"); 1958 1959 object_class_property_add_bool(oc, "hpet", 1960 pc_machine_get_hpet, pc_machine_set_hpet); 1961 object_class_property_set_description(oc, "hpet", 1962 "Enable/disable high precision event timer emulation"); 1963 1964 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1965 pc_machine_get_i8042, pc_machine_set_i8042); 1966 1967 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1968 pc_machine_get_default_bus_bypass_iommu, 1969 pc_machine_set_default_bus_bypass_iommu); 1970 1971 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1972 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1973 NULL, NULL); 1974 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1975 "Maximum combined firmware size"); 1976 1977 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1978 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1979 NULL, NULL); 1980 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1981 "SMBIOS Entry Point type [32, 64]"); 1982 } 1983 1984 static const TypeInfo pc_machine_info = { 1985 .name = TYPE_PC_MACHINE, 1986 .parent = TYPE_X86_MACHINE, 1987 .abstract = true, 1988 .instance_size = sizeof(PCMachineState), 1989 .instance_init = pc_machine_initfn, 1990 .class_size = sizeof(PCMachineClass), 1991 .class_init = pc_machine_class_init, 1992 .interfaces = (InterfaceInfo[]) { 1993 { TYPE_HOTPLUG_HANDLER }, 1994 { } 1995 }, 1996 }; 1997 1998 static void pc_machine_register_types(void) 1999 { 2000 type_register_static(&pc_machine_info); 2001 } 2002 2003 type_init(pc_machine_register_types) 2004