1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/qtest.h" 62 #include "sysemu/reset.h" 63 #include "sysemu/runstate.h" 64 #include "kvm_i386.h" 65 #include "hw/xen/xen.h" 66 #include "hw/xen/start_info.h" 67 #include "ui/qemu-spice.h" 68 #include "exec/memory.h" 69 #include "exec/address-spaces.h" 70 #include "sysemu/arch_init.h" 71 #include "qemu/bitmap.h" 72 #include "qemu/config-file.h" 73 #include "qemu/error-report.h" 74 #include "qemu/option.h" 75 #include "qemu/cutils.h" 76 #include "hw/acpi/acpi.h" 77 #include "hw/acpi/cpu_hotplug.h" 78 #include "hw/boards.h" 79 #include "acpi-build.h" 80 #include "hw/mem/pc-dimm.h" 81 #include "hw/mem/nvdimm.h" 82 #include "qapi/error.h" 83 #include "qapi/qapi-visit-common.h" 84 #include "qapi/visitor.h" 85 #include "hw/core/cpu.h" 86 #include "hw/usb.h" 87 #include "hw/i386/intel_iommu.h" 88 #include "hw/net/ne2000-isa.h" 89 #include "standard-headers/asm-x86/bootparam.h" 90 #include "hw/virtio/virtio-pmem-pci.h" 91 #include "hw/virtio/virtio-mem-pci.h" 92 #include "hw/mem/memory-device.h" 93 #include "sysemu/replay.h" 94 #include "qapi/qmp/qerror.h" 95 #include "e820_memory_layout.h" 96 #include "fw_cfg.h" 97 #include "trace.h" 98 #include CONFIG_DEVICES 99 100 GlobalProperty pc_compat_5_1[] = {}; 101 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 102 103 GlobalProperty pc_compat_5_0[] = { 104 }; 105 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 106 107 GlobalProperty pc_compat_4_2[] = { 108 { "mch", "smbase-smram", "off" }, 109 }; 110 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 111 112 GlobalProperty pc_compat_4_1[] = {}; 113 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 114 115 GlobalProperty pc_compat_4_0[] = {}; 116 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 117 118 GlobalProperty pc_compat_3_1[] = { 119 { "intel-iommu", "dma-drain", "off" }, 120 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 121 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 122 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 123 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 124 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 125 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 126 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 127 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 128 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 129 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 130 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 131 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 132 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 133 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 136 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 137 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 138 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 139 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 140 }; 141 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 142 143 GlobalProperty pc_compat_3_0[] = { 144 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 145 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 146 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 147 }; 148 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 149 150 GlobalProperty pc_compat_2_12[] = { 151 { TYPE_X86_CPU, "legacy-cache", "on" }, 152 { TYPE_X86_CPU, "topoext", "off" }, 153 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 154 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 155 }; 156 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 157 158 GlobalProperty pc_compat_2_11[] = { 159 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 160 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 161 }; 162 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 163 164 GlobalProperty pc_compat_2_10[] = { 165 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 166 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 167 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 168 }; 169 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 170 171 GlobalProperty pc_compat_2_9[] = { 172 { "mch", "extended-tseg-mbytes", "0" }, 173 }; 174 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 175 176 GlobalProperty pc_compat_2_8[] = { 177 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 178 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 179 { "ICH9-LPC", "x-smi-broadcast", "off" }, 180 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 181 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 182 }; 183 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 184 185 GlobalProperty pc_compat_2_7[] = { 186 { TYPE_X86_CPU, "l3-cache", "off" }, 187 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 188 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 189 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 190 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 191 { "isa-pcspk", "migrate", "off" }, 192 }; 193 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 194 195 GlobalProperty pc_compat_2_6[] = { 196 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 197 { "vmxnet3", "romfile", "" }, 198 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 199 { "apic-common", "legacy-instance-id", "on", } 200 }; 201 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 202 203 GlobalProperty pc_compat_2_5[] = {}; 204 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 205 206 GlobalProperty pc_compat_2_4[] = { 207 PC_CPU_MODEL_IDS("2.4.0") 208 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 209 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 210 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 211 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 212 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 213 { TYPE_X86_CPU, "check", "off" }, 214 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 215 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 216 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 217 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 218 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 219 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 220 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 221 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 222 }; 223 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 224 225 GlobalProperty pc_compat_2_3[] = { 226 PC_CPU_MODEL_IDS("2.3.0") 227 { TYPE_X86_CPU, "arat", "off" }, 228 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 229 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 230 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 231 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 232 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 233 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 234 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 235 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 236 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 247 }; 248 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 249 250 GlobalProperty pc_compat_2_2[] = { 251 PC_CPU_MODEL_IDS("2.2.0") 252 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 267 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 268 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 269 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 270 }; 271 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 272 273 GlobalProperty pc_compat_2_1[] = { 274 PC_CPU_MODEL_IDS("2.1.0") 275 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 276 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 277 }; 278 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 279 280 GlobalProperty pc_compat_2_0[] = { 281 PC_CPU_MODEL_IDS("2.0.0") 282 { "virtio-scsi-pci", "any_layout", "off" }, 283 { "PIIX4_PM", "memory-hotplug-support", "off" }, 284 { "apic", "version", "0x11" }, 285 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 286 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 287 { "pci-serial", "prog_if", "0" }, 288 { "pci-serial-2x", "prog_if", "0" }, 289 { "pci-serial-4x", "prog_if", "0" }, 290 { "virtio-net-pci", "guest_announce", "off" }, 291 { "ICH9-LPC", "memory-hotplug-support", "off" }, 292 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 293 { "ioh3420", COMPAT_PROP_PCP, "off" }, 294 }; 295 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 296 297 GlobalProperty pc_compat_1_7[] = { 298 PC_CPU_MODEL_IDS("1.7.0") 299 { TYPE_USB_DEVICE, "msos-desc", "no" }, 300 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 301 { "hpet", HPET_INTCAP, "4" }, 302 }; 303 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 304 305 GlobalProperty pc_compat_1_6[] = { 306 PC_CPU_MODEL_IDS("1.6.0") 307 { "e1000", "mitigation", "off" }, 308 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 309 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 310 { "i440FX-pcihost", "short_root_bus", "1" }, 311 { "q35-pcihost", "short_root_bus", "1" }, 312 }; 313 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 314 315 GlobalProperty pc_compat_1_5[] = { 316 PC_CPU_MODEL_IDS("1.5.0") 317 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 318 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 319 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 320 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 321 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 322 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 323 { "virtio-net-pci", "any_layout", "off" }, 324 { TYPE_X86_CPU, "pmu", "on" }, 325 { "i440FX-pcihost", "short_root_bus", "0" }, 326 { "q35-pcihost", "short_root_bus", "0" }, 327 }; 328 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 329 330 GlobalProperty pc_compat_1_4[] = { 331 PC_CPU_MODEL_IDS("1.4.0") 332 { "scsi-hd", "discard_granularity", "0" }, 333 { "scsi-cd", "discard_granularity", "0" }, 334 { "scsi-disk", "discard_granularity", "0" }, 335 { "ide-hd", "discard_granularity", "0" }, 336 { "ide-cd", "discard_granularity", "0" }, 337 { "ide-drive", "discard_granularity", "0" }, 338 { "virtio-blk-pci", "discard_granularity", "0" }, 339 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 340 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 341 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 342 { "e1000", "romfile", "pxe-e1000.rom" }, 343 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 344 { "pcnet", "romfile", "pxe-pcnet.rom" }, 345 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 346 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 347 { "486-" TYPE_X86_CPU, "model", "0" }, 348 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 349 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 350 }; 351 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 352 353 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 354 { 355 GSIState *s; 356 357 s = g_new0(GSIState, 1); 358 if (kvm_ioapic_in_kernel()) { 359 kvm_pc_setup_irq_routing(pci_enabled); 360 } 361 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 362 363 return s; 364 } 365 366 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 367 unsigned size) 368 { 369 } 370 371 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 372 { 373 return 0xffffffffffffffffULL; 374 } 375 376 /* MSDOS compatibility mode FPU exception support */ 377 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 378 unsigned size) 379 { 380 if (tcg_enabled()) { 381 cpu_set_ignne(); 382 } 383 } 384 385 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 386 { 387 return 0xffffffffffffffffULL; 388 } 389 390 /* PC cmos mappings */ 391 392 #define REG_EQUIPMENT_BYTE 0x14 393 394 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 395 int16_t cylinders, int8_t heads, int8_t sectors) 396 { 397 rtc_set_memory(s, type_ofs, 47); 398 rtc_set_memory(s, info_ofs, cylinders); 399 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 400 rtc_set_memory(s, info_ofs + 2, heads); 401 rtc_set_memory(s, info_ofs + 3, 0xff); 402 rtc_set_memory(s, info_ofs + 4, 0xff); 403 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 404 rtc_set_memory(s, info_ofs + 6, cylinders); 405 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 406 rtc_set_memory(s, info_ofs + 8, sectors); 407 } 408 409 /* convert boot_device letter to something recognizable by the bios */ 410 static int boot_device2nibble(char boot_device) 411 { 412 switch(boot_device) { 413 case 'a': 414 case 'b': 415 return 0x01; /* floppy boot */ 416 case 'c': 417 return 0x02; /* hard drive boot */ 418 case 'd': 419 return 0x03; /* CD-ROM boot */ 420 case 'n': 421 return 0x04; /* Network boot */ 422 } 423 return 0; 424 } 425 426 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 427 { 428 #define PC_MAX_BOOT_DEVICES 3 429 int nbds, bds[3] = { 0, }; 430 int i; 431 432 nbds = strlen(boot_device); 433 if (nbds > PC_MAX_BOOT_DEVICES) { 434 error_setg(errp, "Too many boot devices for PC"); 435 return; 436 } 437 for (i = 0; i < nbds; i++) { 438 bds[i] = boot_device2nibble(boot_device[i]); 439 if (bds[i] == 0) { 440 error_setg(errp, "Invalid boot device for PC: '%c'", 441 boot_device[i]); 442 return; 443 } 444 } 445 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 446 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 447 } 448 449 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 450 { 451 set_boot_dev(opaque, boot_device, errp); 452 } 453 454 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 455 { 456 int val, nb, i; 457 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 458 FLOPPY_DRIVE_TYPE_NONE }; 459 460 /* floppy type */ 461 if (floppy) { 462 for (i = 0; i < 2; i++) { 463 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 464 } 465 } 466 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 467 cmos_get_fd_drive_type(fd_type[1]); 468 rtc_set_memory(rtc_state, 0x10, val); 469 470 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 471 nb = 0; 472 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 473 nb++; 474 } 475 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 476 nb++; 477 } 478 switch (nb) { 479 case 0: 480 break; 481 case 1: 482 val |= 0x01; /* 1 drive, ready for boot */ 483 break; 484 case 2: 485 val |= 0x41; /* 2 drives, ready for boot */ 486 break; 487 } 488 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 489 } 490 491 typedef struct pc_cmos_init_late_arg { 492 ISADevice *rtc_state; 493 BusState *idebus[2]; 494 } pc_cmos_init_late_arg; 495 496 typedef struct check_fdc_state { 497 ISADevice *floppy; 498 bool multiple; 499 } CheckFdcState; 500 501 static int check_fdc(Object *obj, void *opaque) 502 { 503 CheckFdcState *state = opaque; 504 Object *fdc; 505 uint32_t iobase; 506 Error *local_err = NULL; 507 508 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 509 if (!fdc) { 510 return 0; 511 } 512 513 iobase = object_property_get_uint(obj, "iobase", &local_err); 514 if (local_err || iobase != 0x3f0) { 515 error_free(local_err); 516 return 0; 517 } 518 519 if (state->floppy) { 520 state->multiple = true; 521 } else { 522 state->floppy = ISA_DEVICE(obj); 523 } 524 return 0; 525 } 526 527 static const char * const fdc_container_path[] = { 528 "/unattached", "/peripheral", "/peripheral-anon" 529 }; 530 531 /* 532 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 533 * and ACPI objects. 534 */ 535 ISADevice *pc_find_fdc0(void) 536 { 537 int i; 538 Object *container; 539 CheckFdcState state = { 0 }; 540 541 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 542 container = container_get(qdev_get_machine(), fdc_container_path[i]); 543 object_child_foreach(container, check_fdc, &state); 544 } 545 546 if (state.multiple) { 547 warn_report("multiple floppy disk controllers with " 548 "iobase=0x3f0 have been found"); 549 error_printf("the one being picked for CMOS setup might not reflect " 550 "your intent"); 551 } 552 553 return state.floppy; 554 } 555 556 static void pc_cmos_init_late(void *opaque) 557 { 558 pc_cmos_init_late_arg *arg = opaque; 559 ISADevice *s = arg->rtc_state; 560 int16_t cylinders; 561 int8_t heads, sectors; 562 int val; 563 int i, trans; 564 565 val = 0; 566 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 567 &cylinders, &heads, §ors) >= 0) { 568 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 569 val |= 0xf0; 570 } 571 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 572 &cylinders, &heads, §ors) >= 0) { 573 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 574 val |= 0x0f; 575 } 576 rtc_set_memory(s, 0x12, val); 577 578 val = 0; 579 for (i = 0; i < 4; i++) { 580 /* NOTE: ide_get_geometry() returns the physical 581 geometry. It is always such that: 1 <= sects <= 63, 1 582 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 583 geometry can be different if a translation is done. */ 584 if (arg->idebus[i / 2] && 585 ide_get_geometry(arg->idebus[i / 2], i % 2, 586 &cylinders, &heads, §ors) >= 0) { 587 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 588 assert((trans & ~3) == 0); 589 val |= trans << (i * 2); 590 } 591 } 592 rtc_set_memory(s, 0x39, val); 593 594 pc_cmos_init_floppy(s, pc_find_fdc0()); 595 596 qemu_unregister_reset(pc_cmos_init_late, opaque); 597 } 598 599 void pc_cmos_init(PCMachineState *pcms, 600 BusState *idebus0, BusState *idebus1, 601 ISADevice *s) 602 { 603 int val; 604 static pc_cmos_init_late_arg arg; 605 X86MachineState *x86ms = X86_MACHINE(pcms); 606 607 /* various important CMOS locations needed by PC/Bochs bios */ 608 609 /* memory size */ 610 /* base memory (first MiB) */ 611 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 612 rtc_set_memory(s, 0x15, val); 613 rtc_set_memory(s, 0x16, val >> 8); 614 /* extended memory (next 64MiB) */ 615 if (x86ms->below_4g_mem_size > 1 * MiB) { 616 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 617 } else { 618 val = 0; 619 } 620 if (val > 65535) 621 val = 65535; 622 rtc_set_memory(s, 0x17, val); 623 rtc_set_memory(s, 0x18, val >> 8); 624 rtc_set_memory(s, 0x30, val); 625 rtc_set_memory(s, 0x31, val >> 8); 626 /* memory between 16MiB and 4GiB */ 627 if (x86ms->below_4g_mem_size > 16 * MiB) { 628 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 629 } else { 630 val = 0; 631 } 632 if (val > 65535) 633 val = 65535; 634 rtc_set_memory(s, 0x34, val); 635 rtc_set_memory(s, 0x35, val >> 8); 636 /* memory above 4GiB */ 637 val = x86ms->above_4g_mem_size / 65536; 638 rtc_set_memory(s, 0x5b, val); 639 rtc_set_memory(s, 0x5c, val >> 8); 640 rtc_set_memory(s, 0x5d, val >> 16); 641 642 object_property_add_link(OBJECT(pcms), "rtc_state", 643 TYPE_ISA_DEVICE, 644 (Object **)&x86ms->rtc, 645 object_property_allow_set_link, 646 OBJ_PROP_LINK_STRONG); 647 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 648 &error_abort); 649 650 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 651 652 val = 0; 653 val |= 0x02; /* FPU is there */ 654 val |= 0x04; /* PS/2 mouse installed */ 655 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 656 657 /* hard drives and FDC */ 658 arg.rtc_state = s; 659 arg.idebus[0] = idebus0; 660 arg.idebus[1] = idebus1; 661 qemu_register_reset(pc_cmos_init_late, &arg); 662 } 663 664 static void handle_a20_line_change(void *opaque, int irq, int level) 665 { 666 X86CPU *cpu = opaque; 667 668 /* XXX: send to all CPUs ? */ 669 /* XXX: add logic to handle multiple A20 line sources */ 670 x86_cpu_set_a20(cpu, level); 671 } 672 673 #define NE2000_NB_MAX 6 674 675 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 676 0x280, 0x380 }; 677 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 678 679 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 680 { 681 static int nb_ne2k = 0; 682 683 if (nb_ne2k == NE2000_NB_MAX) 684 return; 685 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 686 ne2000_irq[nb_ne2k], nd); 687 nb_ne2k++; 688 } 689 690 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 691 { 692 X86CPU *cpu = opaque; 693 694 if (level) { 695 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 696 } 697 } 698 699 /* 700 * This function is very similar to smp_parse() 701 * in hw/core/machine.c but includes CPU die support. 702 */ 703 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 704 { 705 X86MachineState *x86ms = X86_MACHINE(ms); 706 707 if (opts) { 708 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 709 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 710 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 711 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 712 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 713 714 /* compute missing values, prefer sockets over cores over threads */ 715 if (cpus == 0 || sockets == 0) { 716 cores = cores > 0 ? cores : 1; 717 threads = threads > 0 ? threads : 1; 718 if (cpus == 0) { 719 sockets = sockets > 0 ? sockets : 1; 720 cpus = cores * threads * dies * sockets; 721 } else { 722 ms->smp.max_cpus = 723 qemu_opt_get_number(opts, "maxcpus", cpus); 724 sockets = ms->smp.max_cpus / (cores * threads * dies); 725 } 726 } else if (cores == 0) { 727 threads = threads > 0 ? threads : 1; 728 cores = cpus / (sockets * dies * threads); 729 cores = cores > 0 ? cores : 1; 730 } else if (threads == 0) { 731 threads = cpus / (cores * dies * sockets); 732 threads = threads > 0 ? threads : 1; 733 } else if (sockets * dies * cores * threads < cpus) { 734 error_report("cpu topology: " 735 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 736 "smp_cpus (%u)", 737 sockets, dies, cores, threads, cpus); 738 exit(1); 739 } 740 741 ms->smp.max_cpus = 742 qemu_opt_get_number(opts, "maxcpus", cpus); 743 744 if (ms->smp.max_cpus < cpus) { 745 error_report("maxcpus must be equal to or greater than smp"); 746 exit(1); 747 } 748 749 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 750 error_report("cpu topology: " 751 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 752 "maxcpus (%u)", 753 sockets, dies, cores, threads, 754 ms->smp.max_cpus); 755 exit(1); 756 } 757 758 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 759 warn_report("Invalid CPU topology deprecated: " 760 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 761 "!= maxcpus (%u)", 762 sockets, dies, cores, threads, 763 ms->smp.max_cpus); 764 } 765 766 ms->smp.cpus = cpus; 767 ms->smp.cores = cores; 768 ms->smp.threads = threads; 769 ms->smp.sockets = sockets; 770 x86ms->smp_dies = dies; 771 } 772 773 if (ms->smp.cpus > 1) { 774 Error *blocker = NULL; 775 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 776 replay_add_blocker(blocker); 777 } 778 } 779 780 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 781 { 782 X86MachineState *x86ms = X86_MACHINE(ms); 783 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); 784 Error *local_err = NULL; 785 786 if (id < 0) { 787 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 788 return; 789 } 790 791 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 792 error_setg(errp, "Unable to add CPU: %" PRIi64 793 ", resulting APIC ID (%" PRIi64 ") is too large", 794 id, apic_id); 795 return; 796 } 797 798 799 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); 800 if (local_err) { 801 error_propagate(errp, local_err); 802 return; 803 } 804 } 805 806 static 807 void pc_machine_done(Notifier *notifier, void *data) 808 { 809 PCMachineState *pcms = container_of(notifier, 810 PCMachineState, machine_done); 811 X86MachineState *x86ms = X86_MACHINE(pcms); 812 PCIBus *bus = pcms->bus; 813 814 /* set the number of CPUs */ 815 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 816 817 if (bus) { 818 int extra_hosts = 0; 819 820 QLIST_FOREACH(bus, &bus->child, sibling) { 821 /* look for expander root buses */ 822 if (pci_bus_is_root(bus)) { 823 extra_hosts++; 824 } 825 } 826 if (extra_hosts && x86ms->fw_cfg) { 827 uint64_t *val = g_malloc(sizeof(*val)); 828 *val = cpu_to_le64(extra_hosts); 829 fw_cfg_add_file(x86ms->fw_cfg, 830 "etc/extra-pci-roots", val, sizeof(*val)); 831 } 832 } 833 834 acpi_setup(); 835 if (x86ms->fw_cfg) { 836 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 837 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 838 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 839 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 840 } 841 842 if (x86ms->apic_id_limit > 255 && !xen_enabled()) { 843 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 844 845 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 846 iommu->intr_eim != ON_OFF_AUTO_ON) { 847 error_report("current -smp configuration requires " 848 "Extended Interrupt Mode enabled. " 849 "You can add an IOMMU using: " 850 "-device intel-iommu,intremap=on,eim=on"); 851 exit(EXIT_FAILURE); 852 } 853 } 854 } 855 856 void pc_guest_info_init(PCMachineState *pcms) 857 { 858 int i; 859 MachineState *ms = MACHINE(pcms); 860 X86MachineState *x86ms = X86_MACHINE(pcms); 861 862 x86ms->apic_xrupt_override = kvm_allows_irq0_override(); 863 pcms->numa_nodes = ms->numa_state->num_nodes; 864 pcms->node_mem = g_malloc0(pcms->numa_nodes * 865 sizeof *pcms->node_mem); 866 for (i = 0; i < ms->numa_state->num_nodes; i++) { 867 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 868 } 869 870 pcms->machine_done.notify = pc_machine_done; 871 qemu_add_machine_init_done_notifier(&pcms->machine_done); 872 } 873 874 /* setup pci memory address space mapping into system address space */ 875 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 876 MemoryRegion *pci_address_space) 877 { 878 /* Set to lower priority than RAM */ 879 memory_region_add_subregion_overlap(system_memory, 0x0, 880 pci_address_space, -1); 881 } 882 883 void xen_load_linux(PCMachineState *pcms) 884 { 885 int i; 886 FWCfgState *fw_cfg; 887 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 888 X86MachineState *x86ms = X86_MACHINE(pcms); 889 890 assert(MACHINE(pcms)->kernel_filename != NULL); 891 892 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 893 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 894 rom_set_fw(fw_cfg); 895 896 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 897 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 898 for (i = 0; i < nb_option_roms; i++) { 899 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 900 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 901 !strcmp(option_rom[i].name, "pvh.bin") || 902 !strcmp(option_rom[i].name, "multiboot.bin")); 903 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 904 } 905 x86ms->fw_cfg = fw_cfg; 906 } 907 908 void pc_memory_init(PCMachineState *pcms, 909 MemoryRegion *system_memory, 910 MemoryRegion *rom_memory, 911 MemoryRegion **ram_memory) 912 { 913 int linux_boot, i; 914 MemoryRegion *option_rom_mr; 915 MemoryRegion *ram_below_4g, *ram_above_4g; 916 FWCfgState *fw_cfg; 917 MachineState *machine = MACHINE(pcms); 918 MachineClass *mc = MACHINE_GET_CLASS(machine); 919 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 920 X86MachineState *x86ms = X86_MACHINE(pcms); 921 922 assert(machine->ram_size == x86ms->below_4g_mem_size + 923 x86ms->above_4g_mem_size); 924 925 linux_boot = (machine->kernel_filename != NULL); 926 927 /* 928 * Split single memory region and use aliases to address portions of it, 929 * done for backwards compatibility with older qemus. 930 */ 931 *ram_memory = machine->ram; 932 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 933 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 934 0, x86ms->below_4g_mem_size); 935 memory_region_add_subregion(system_memory, 0, ram_below_4g); 936 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 937 if (x86ms->above_4g_mem_size > 0) { 938 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 939 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 940 machine->ram, 941 x86ms->below_4g_mem_size, 942 x86ms->above_4g_mem_size); 943 memory_region_add_subregion(system_memory, 0x100000000ULL, 944 ram_above_4g); 945 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 946 } 947 948 if (!pcmc->has_reserved_memory && 949 (machine->ram_slots || 950 (machine->maxram_size > machine->ram_size))) { 951 952 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 953 mc->name); 954 exit(EXIT_FAILURE); 955 } 956 957 /* always allocate the device memory information */ 958 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 959 960 /* initialize device memory address space */ 961 if (pcmc->has_reserved_memory && 962 (machine->ram_size < machine->maxram_size)) { 963 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 964 965 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 966 error_report("unsupported amount of memory slots: %"PRIu64, 967 machine->ram_slots); 968 exit(EXIT_FAILURE); 969 } 970 971 if (QEMU_ALIGN_UP(machine->maxram_size, 972 TARGET_PAGE_SIZE) != machine->maxram_size) { 973 error_report("maximum memory size must by aligned to multiple of " 974 "%d bytes", TARGET_PAGE_SIZE); 975 exit(EXIT_FAILURE); 976 } 977 978 machine->device_memory->base = 979 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 980 981 if (pcmc->enforce_aligned_dimm) { 982 /* size device region assuming 1G page max alignment per slot */ 983 device_mem_size += (1 * GiB) * machine->ram_slots; 984 } 985 986 if ((machine->device_memory->base + device_mem_size) < 987 device_mem_size) { 988 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 989 machine->maxram_size); 990 exit(EXIT_FAILURE); 991 } 992 993 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 994 "device-memory", device_mem_size); 995 memory_region_add_subregion(system_memory, machine->device_memory->base, 996 &machine->device_memory->mr); 997 } 998 999 /* Initialize PC system firmware */ 1000 pc_system_firmware_init(pcms, rom_memory); 1001 1002 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1003 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1004 &error_fatal); 1005 if (pcmc->pci_enabled) { 1006 memory_region_set_readonly(option_rom_mr, true); 1007 } 1008 memory_region_add_subregion_overlap(rom_memory, 1009 PC_ROM_MIN_VGA, 1010 option_rom_mr, 1011 1); 1012 1013 fw_cfg = fw_cfg_arch_create(machine, 1014 x86ms->boot_cpus, x86ms->apic_id_limit); 1015 1016 rom_set_fw(fw_cfg); 1017 1018 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1019 uint64_t *val = g_malloc(sizeof(*val)); 1020 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1021 uint64_t res_mem_end = machine->device_memory->base; 1022 1023 if (!pcmc->broken_reserved_end) { 1024 res_mem_end += memory_region_size(&machine->device_memory->mr); 1025 } 1026 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1027 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1028 } 1029 1030 if (linux_boot) { 1031 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1032 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 1033 } 1034 1035 for (i = 0; i < nb_option_roms; i++) { 1036 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1037 } 1038 x86ms->fw_cfg = fw_cfg; 1039 1040 /* Init default IOAPIC address space */ 1041 x86ms->ioapic_as = &address_space_memory; 1042 1043 /* Init ACPI memory hotplug IO base address */ 1044 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1045 } 1046 1047 /* 1048 * The 64bit pci hole starts after "above 4G RAM" and 1049 * potentially the space reserved for memory hotplug. 1050 */ 1051 uint64_t pc_pci_hole64_start(void) 1052 { 1053 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1054 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1055 MachineState *ms = MACHINE(pcms); 1056 X86MachineState *x86ms = X86_MACHINE(pcms); 1057 uint64_t hole64_start = 0; 1058 1059 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1060 hole64_start = ms->device_memory->base; 1061 if (!pcmc->broken_reserved_end) { 1062 hole64_start += memory_region_size(&ms->device_memory->mr); 1063 } 1064 } else { 1065 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1066 } 1067 1068 return ROUND_UP(hole64_start, 1 * GiB); 1069 } 1070 1071 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1072 { 1073 DeviceState *dev = NULL; 1074 1075 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1076 if (pci_bus) { 1077 PCIDevice *pcidev = pci_vga_init(pci_bus); 1078 dev = pcidev ? &pcidev->qdev : NULL; 1079 } else if (isa_bus) { 1080 ISADevice *isadev = isa_vga_init(isa_bus); 1081 dev = isadev ? DEVICE(isadev) : NULL; 1082 } 1083 rom_reset_order_override(); 1084 return dev; 1085 } 1086 1087 static const MemoryRegionOps ioport80_io_ops = { 1088 .write = ioport80_write, 1089 .read = ioport80_read, 1090 .endianness = DEVICE_NATIVE_ENDIAN, 1091 .impl = { 1092 .min_access_size = 1, 1093 .max_access_size = 1, 1094 }, 1095 }; 1096 1097 static const MemoryRegionOps ioportF0_io_ops = { 1098 .write = ioportF0_write, 1099 .read = ioportF0_read, 1100 .endianness = DEVICE_NATIVE_ENDIAN, 1101 .impl = { 1102 .min_access_size = 1, 1103 .max_access_size = 1, 1104 }, 1105 }; 1106 1107 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1108 { 1109 int i; 1110 DriveInfo *fd[MAX_FD]; 1111 qemu_irq *a20_line; 1112 ISADevice *fdc, *i8042, *port92, *vmmouse; 1113 1114 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1115 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1116 1117 for (i = 0; i < MAX_FD; i++) { 1118 fd[i] = drive_get(IF_FLOPPY, 0, i); 1119 create_fdctrl |= !!fd[i]; 1120 } 1121 if (create_fdctrl) { 1122 fdc = isa_new(TYPE_ISA_FDC); 1123 if (fdc) { 1124 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1125 isa_fdc_init_drives(fdc, fd); 1126 } 1127 } 1128 1129 i8042 = isa_create_simple(isa_bus, "i8042"); 1130 if (!no_vmport) { 1131 isa_create_simple(isa_bus, TYPE_VMPORT); 1132 vmmouse = isa_try_new("vmmouse"); 1133 } else { 1134 vmmouse = NULL; 1135 } 1136 if (vmmouse) { 1137 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1138 &error_abort); 1139 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1140 } 1141 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1142 1143 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1144 i8042_setup_a20_line(i8042, a20_line[0]); 1145 qdev_connect_gpio_out_named(DEVICE(port92), 1146 PORT92_A20_LINE, 0, a20_line[1]); 1147 g_free(a20_line); 1148 } 1149 1150 void pc_basic_device_init(struct PCMachineState *pcms, 1151 ISABus *isa_bus, qemu_irq *gsi, 1152 ISADevice **rtc_state, 1153 bool create_fdctrl, 1154 uint32_t hpet_irqs) 1155 { 1156 int i; 1157 DeviceState *hpet = NULL; 1158 int pit_isa_irq = 0; 1159 qemu_irq pit_alt_irq = NULL; 1160 qemu_irq rtc_irq = NULL; 1161 ISADevice *pit = NULL; 1162 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1163 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1164 1165 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1166 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1167 1168 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1169 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1170 1171 /* 1172 * Check if an HPET shall be created. 1173 * 1174 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1175 * when the HPET wants to take over. Thus we have to disable the latter. 1176 */ 1177 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1178 hpet = qdev_try_new(TYPE_HPET); 1179 if (hpet) { 1180 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1181 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1182 * IRQ8 and IRQ2. 1183 */ 1184 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1185 HPET_INTCAP, NULL); 1186 if (!compat) { 1187 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1188 } 1189 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1190 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1191 1192 for (i = 0; i < GSI_NUM_PINS; i++) { 1193 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1194 } 1195 pit_isa_irq = -1; 1196 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1197 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1198 } 1199 } 1200 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1201 1202 qemu_register_boot_set(pc_boot_set, *rtc_state); 1203 1204 if (!xen_enabled() && pcms->pit_enabled) { 1205 if (kvm_pit_in_kernel()) { 1206 pit = kvm_pit_init(isa_bus, 0x40); 1207 } else { 1208 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1209 } 1210 if (hpet) { 1211 /* connect PIT to output control line of the HPET */ 1212 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1213 } 1214 pcspk_init(pcms->pcspk, isa_bus, pit); 1215 } 1216 1217 i8257_dma_init(isa_bus, 0); 1218 1219 /* Super I/O */ 1220 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1221 } 1222 1223 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1224 { 1225 int i; 1226 1227 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1228 for (i = 0; i < nb_nics; i++) { 1229 NICInfo *nd = &nd_table[i]; 1230 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1231 1232 if (g_str_equal(model, "ne2k_isa")) { 1233 pc_init_ne2k_isa(isa_bus, nd); 1234 } else { 1235 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1236 } 1237 } 1238 rom_reset_order_override(); 1239 } 1240 1241 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1242 { 1243 qemu_irq *i8259; 1244 1245 if (kvm_pic_in_kernel()) { 1246 i8259 = kvm_i8259_init(isa_bus); 1247 } else if (xen_enabled()) { 1248 i8259 = xen_interrupt_controller_init(); 1249 } else { 1250 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1251 } 1252 1253 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1254 i8259_irqs[i] = i8259[i]; 1255 } 1256 1257 g_free(i8259); 1258 } 1259 1260 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1261 Error **errp) 1262 { 1263 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1264 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1265 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1266 const MachineState *ms = MACHINE(hotplug_dev); 1267 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1268 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1269 Error *local_err = NULL; 1270 1271 /* 1272 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1273 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1274 * addition to cover this case. 1275 */ 1276 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1277 error_setg(errp, 1278 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1279 return; 1280 } 1281 1282 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1283 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1284 return; 1285 } 1286 1287 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1288 if (local_err) { 1289 error_propagate(errp, local_err); 1290 return; 1291 } 1292 1293 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1294 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1295 } 1296 1297 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1298 DeviceState *dev, Error **errp) 1299 { 1300 Error *local_err = NULL; 1301 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1302 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1303 MachineState *ms = MACHINE(hotplug_dev); 1304 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1305 1306 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 1307 if (local_err) { 1308 goto out; 1309 } 1310 1311 if (is_nvdimm) { 1312 nvdimm_plug(ms->nvdimms_state); 1313 } 1314 1315 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1316 out: 1317 error_propagate(errp, local_err); 1318 } 1319 1320 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1321 DeviceState *dev, Error **errp) 1322 { 1323 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1324 1325 /* 1326 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1327 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1328 * addition to cover this case. 1329 */ 1330 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1331 error_setg(errp, 1332 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1333 return; 1334 } 1335 1336 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1337 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1338 return; 1339 } 1340 1341 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1342 errp); 1343 } 1344 1345 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1346 DeviceState *dev, Error **errp) 1347 { 1348 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1349 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1350 Error *local_err = NULL; 1351 1352 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1353 if (local_err) { 1354 goto out; 1355 } 1356 1357 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1358 qdev_unrealize(dev); 1359 out: 1360 error_propagate(errp, local_err); 1361 } 1362 1363 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1364 DeviceState *dev, Error **errp) 1365 { 1366 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1367 Error *local_err = NULL; 1368 1369 if (!hotplug_dev2 && dev->hotplugged) { 1370 /* 1371 * Without a bus hotplug handler, we cannot control the plug/unplug 1372 * order. We should never reach this point when hotplugging on x86, 1373 * however, better add a safety net. 1374 */ 1375 error_setg(errp, "hotplug of virtio based memory devices not supported" 1376 " on this bus."); 1377 return; 1378 } 1379 /* 1380 * First, see if we can plug this memory device at all. If that 1381 * succeeds, branch of to the actual hotplug handler. 1382 */ 1383 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1384 &local_err); 1385 if (!local_err && hotplug_dev2) { 1386 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1387 } 1388 error_propagate(errp, local_err); 1389 } 1390 1391 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1392 DeviceState *dev, Error **errp) 1393 { 1394 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1395 Error *local_err = NULL; 1396 1397 /* 1398 * Plug the memory device first and then branch off to the actual 1399 * hotplug handler. If that one fails, we can easily undo the memory 1400 * device bits. 1401 */ 1402 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1403 if (hotplug_dev2) { 1404 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1405 if (local_err) { 1406 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1407 } 1408 } 1409 error_propagate(errp, local_err); 1410 } 1411 1412 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1413 DeviceState *dev, Error **errp) 1414 { 1415 /* We don't support hot unplug of virtio based memory devices */ 1416 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1417 } 1418 1419 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1420 DeviceState *dev, Error **errp) 1421 { 1422 /* We don't support hot unplug of virtio based memory devices */ 1423 } 1424 1425 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1426 DeviceState *dev, Error **errp) 1427 { 1428 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1429 pc_memory_pre_plug(hotplug_dev, dev, errp); 1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1431 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1433 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1434 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1435 } 1436 } 1437 1438 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1439 DeviceState *dev, Error **errp) 1440 { 1441 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1442 pc_memory_plug(hotplug_dev, dev, errp); 1443 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1444 x86_cpu_plug(hotplug_dev, dev, errp); 1445 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1446 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1447 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1448 } 1449 } 1450 1451 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1452 DeviceState *dev, Error **errp) 1453 { 1454 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1455 pc_memory_unplug_request(hotplug_dev, dev, errp); 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1457 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1458 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1459 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1460 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1461 } else { 1462 error_setg(errp, "acpi: device unplug request for not supported device" 1463 " type: %s", object_get_typename(OBJECT(dev))); 1464 } 1465 } 1466 1467 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1468 DeviceState *dev, Error **errp) 1469 { 1470 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1471 pc_memory_unplug(hotplug_dev, dev, errp); 1472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1473 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1474 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1475 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1476 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1477 } else { 1478 error_setg(errp, "acpi: device unplug for not supported device" 1479 " type: %s", object_get_typename(OBJECT(dev))); 1480 } 1481 } 1482 1483 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1484 DeviceState *dev) 1485 { 1486 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1487 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1488 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1489 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1490 return HOTPLUG_HANDLER(machine); 1491 } 1492 1493 return NULL; 1494 } 1495 1496 static void 1497 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1498 const char *name, void *opaque, 1499 Error **errp) 1500 { 1501 MachineState *ms = MACHINE(obj); 1502 int64_t value = 0; 1503 1504 if (ms->device_memory) { 1505 value = memory_region_size(&ms->device_memory->mr); 1506 } 1507 1508 visit_type_int(v, name, &value, errp); 1509 } 1510 1511 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1512 void *opaque, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 OnOffAuto vmport = pcms->vmport; 1516 1517 visit_type_OnOffAuto(v, name, &vmport, errp); 1518 } 1519 1520 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1521 void *opaque, Error **errp) 1522 { 1523 PCMachineState *pcms = PC_MACHINE(obj); 1524 1525 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1526 } 1527 1528 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1529 { 1530 PCMachineState *pcms = PC_MACHINE(obj); 1531 1532 return pcms->smbus_enabled; 1533 } 1534 1535 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1536 { 1537 PCMachineState *pcms = PC_MACHINE(obj); 1538 1539 pcms->smbus_enabled = value; 1540 } 1541 1542 static bool pc_machine_get_sata(Object *obj, Error **errp) 1543 { 1544 PCMachineState *pcms = PC_MACHINE(obj); 1545 1546 return pcms->sata_enabled; 1547 } 1548 1549 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1550 { 1551 PCMachineState *pcms = PC_MACHINE(obj); 1552 1553 pcms->sata_enabled = value; 1554 } 1555 1556 static bool pc_machine_get_pit(Object *obj, Error **errp) 1557 { 1558 PCMachineState *pcms = PC_MACHINE(obj); 1559 1560 return pcms->pit_enabled; 1561 } 1562 1563 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1564 { 1565 PCMachineState *pcms = PC_MACHINE(obj); 1566 1567 pcms->pit_enabled = value; 1568 } 1569 1570 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1571 const char *name, void *opaque, 1572 Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 uint64_t value = pcms->max_ram_below_4g; 1576 1577 visit_type_size(v, name, &value, errp); 1578 } 1579 1580 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1581 const char *name, void *opaque, 1582 Error **errp) 1583 { 1584 PCMachineState *pcms = PC_MACHINE(obj); 1585 uint64_t value; 1586 1587 if (!visit_type_size(v, name, &value, errp)) { 1588 return; 1589 } 1590 if (value > 4 * GiB) { 1591 error_setg(errp, 1592 "Machine option 'max-ram-below-4g=%"PRIu64 1593 "' expects size less than or equal to 4G", value); 1594 return; 1595 } 1596 1597 if (value < 1 * MiB) { 1598 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1599 "BIOS may not work with less than 1MiB", value); 1600 } 1601 1602 pcms->max_ram_below_4g = value; 1603 } 1604 1605 static void pc_machine_initfn(Object *obj) 1606 { 1607 PCMachineState *pcms = PC_MACHINE(obj); 1608 1609 #ifdef CONFIG_VMPORT 1610 pcms->vmport = ON_OFF_AUTO_AUTO; 1611 #else 1612 pcms->vmport = ON_OFF_AUTO_OFF; 1613 #endif /* CONFIG_VMPORT */ 1614 pcms->max_ram_below_4g = 0; /* use default */ 1615 /* acpi build is enabled by default if machine supports it */ 1616 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1617 pcms->smbus_enabled = true; 1618 pcms->sata_enabled = true; 1619 pcms->pit_enabled = true; 1620 1621 pc_system_flash_create(pcms); 1622 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1623 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1624 OBJECT(pcms->pcspk), "audiodev"); 1625 } 1626 1627 static void pc_machine_reset(MachineState *machine) 1628 { 1629 CPUState *cs; 1630 X86CPU *cpu; 1631 1632 qemu_devices_reset(); 1633 1634 /* Reset APIC after devices have been reset to cancel 1635 * any changes that qemu_devices_reset() might have done. 1636 */ 1637 CPU_FOREACH(cs) { 1638 cpu = X86_CPU(cs); 1639 1640 if (cpu->apic_state) { 1641 device_legacy_reset(cpu->apic_state); 1642 } 1643 } 1644 } 1645 1646 static void pc_machine_wakeup(MachineState *machine) 1647 { 1648 cpu_synchronize_all_states(); 1649 pc_machine_reset(machine); 1650 cpu_synchronize_all_post_reset(); 1651 } 1652 1653 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1654 { 1655 X86IOMMUState *iommu = x86_iommu_get_default(); 1656 IntelIOMMUState *intel_iommu; 1657 1658 if (iommu && 1659 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1660 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1661 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1662 if (!intel_iommu->caching_mode) { 1663 error_setg(errp, "Device assignment is not allowed without " 1664 "enabling caching-mode=on for Intel IOMMU."); 1665 return false; 1666 } 1667 } 1668 1669 return true; 1670 } 1671 1672 static void pc_machine_class_init(ObjectClass *oc, void *data) 1673 { 1674 MachineClass *mc = MACHINE_CLASS(oc); 1675 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1676 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1677 1678 pcmc->pci_enabled = true; 1679 pcmc->has_acpi_build = true; 1680 pcmc->rsdp_in_ram = true; 1681 pcmc->smbios_defaults = true; 1682 pcmc->smbios_uuid_encoded = true; 1683 pcmc->gigabyte_align = true; 1684 pcmc->has_reserved_memory = true; 1685 pcmc->kvmclock_enabled = true; 1686 pcmc->enforce_aligned_dimm = true; 1687 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1688 * to be used at the moment, 32K should be enough for a while. */ 1689 pcmc->acpi_data_size = 0x20000 + 0x8000; 1690 pcmc->linuxboot_dma_enabled = true; 1691 pcmc->pvh_enabled = true; 1692 assert(!mc->get_hotplug_handler); 1693 mc->get_hotplug_handler = pc_get_hotplug_handler; 1694 mc->hotplug_allowed = pc_hotplug_allowed; 1695 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1696 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1697 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1698 mc->auto_enable_numa_with_memhp = true; 1699 mc->auto_enable_numa_with_memdev = true; 1700 mc->has_hotpluggable_cpus = true; 1701 mc->default_boot_order = "cad"; 1702 mc->hot_add_cpu = pc_hot_add_cpu; 1703 mc->smp_parse = pc_smp_parse; 1704 mc->block_default_type = IF_IDE; 1705 mc->max_cpus = 255; 1706 mc->reset = pc_machine_reset; 1707 mc->wakeup = pc_machine_wakeup; 1708 hc->pre_plug = pc_machine_device_pre_plug_cb; 1709 hc->plug = pc_machine_device_plug_cb; 1710 hc->unplug_request = pc_machine_device_unplug_request_cb; 1711 hc->unplug = pc_machine_device_unplug_cb; 1712 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1713 mc->nvdimm_supported = true; 1714 mc->default_ram_id = "pc.ram"; 1715 1716 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1717 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1718 NULL, NULL); 1719 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1720 "Maximum ram below the 4G boundary (32bit boundary)"); 1721 1722 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1723 pc_machine_get_device_memory_region_size, NULL, 1724 NULL, NULL); 1725 1726 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1727 pc_machine_get_vmport, pc_machine_set_vmport, 1728 NULL, NULL); 1729 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1730 "Enable vmport (pc & q35)"); 1731 1732 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1733 pc_machine_get_smbus, pc_machine_set_smbus); 1734 1735 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1736 pc_machine_get_sata, pc_machine_set_sata); 1737 1738 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1739 pc_machine_get_pit, pc_machine_set_pit); 1740 } 1741 1742 static const TypeInfo pc_machine_info = { 1743 .name = TYPE_PC_MACHINE, 1744 .parent = TYPE_X86_MACHINE, 1745 .abstract = true, 1746 .instance_size = sizeof(PCMachineState), 1747 .instance_init = pc_machine_initfn, 1748 .class_size = sizeof(PCMachineClass), 1749 .class_init = pc_machine_class_init, 1750 .interfaces = (InterfaceInfo[]) { 1751 { TYPE_HOTPLUG_HANDLER }, 1752 { } 1753 }, 1754 }; 1755 1756 static void pc_machine_register_types(void) 1757 { 1758 type_register_static(&pc_machine_info); 1759 } 1760 1761 type_init(pc_machine_register_types) 1762