1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_8_2[] = {}; 82 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 83 84 GlobalProperty pc_compat_8_1[] = {}; 85 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 86 87 GlobalProperty pc_compat_8_0[] = { 88 { "virtio-mem", "unplugged-inaccessible", "auto" }, 89 }; 90 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 91 92 GlobalProperty pc_compat_7_2[] = { 93 { "ICH9-LPC", "noreboot", "true" }, 94 }; 95 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 96 97 GlobalProperty pc_compat_7_1[] = {}; 98 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 99 100 GlobalProperty pc_compat_7_0[] = {}; 101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 102 103 GlobalProperty pc_compat_6_2[] = { 104 { "virtio-mem", "unplugged-inaccessible", "off" }, 105 }; 106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 107 108 GlobalProperty pc_compat_6_1[] = { 109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 113 }; 114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 115 116 GlobalProperty pc_compat_6_0[] = { 117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 123 }; 124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 125 126 GlobalProperty pc_compat_5_2[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 128 }; 129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 130 131 GlobalProperty pc_compat_5_1[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 134 }; 135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 136 137 GlobalProperty pc_compat_5_0[] = { 138 }; 139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 140 141 GlobalProperty pc_compat_4_2[] = { 142 { "mch", "smbase-smram", "off" }, 143 }; 144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 145 146 GlobalProperty pc_compat_4_1[] = {}; 147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 148 149 GlobalProperty pc_compat_4_0[] = {}; 150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 151 152 GlobalProperty pc_compat_3_1[] = { 153 { "intel-iommu", "dma-drain", "off" }, 154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 174 }; 175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 176 177 GlobalProperty pc_compat_3_0[] = { 178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 181 }; 182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 183 184 GlobalProperty pc_compat_2_12[] = { 185 { TYPE_X86_CPU, "legacy-cache", "on" }, 186 { TYPE_X86_CPU, "topoext", "off" }, 187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 }; 190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 191 192 GlobalProperty pc_compat_2_11[] = { 193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 195 }; 196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 197 198 GlobalProperty pc_compat_2_10[] = { 199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 201 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 202 }; 203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 204 205 GlobalProperty pc_compat_2_9[] = { 206 { "mch", "extended-tseg-mbytes", "0" }, 207 }; 208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 209 210 GlobalProperty pc_compat_2_8[] = { 211 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 213 { "ICH9-LPC", "x-smi-broadcast", "off" }, 214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 216 }; 217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 218 219 GlobalProperty pc_compat_2_7[] = { 220 { TYPE_X86_CPU, "l3-cache", "off" }, 221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 225 { "isa-pcspk", "migrate", "off" }, 226 }; 227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 228 229 GlobalProperty pc_compat_2_6[] = { 230 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 231 { "vmxnet3", "romfile", "" }, 232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 233 { "apic-common", "legacy-instance-id", "on", } 234 }; 235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 236 237 GlobalProperty pc_compat_2_5[] = {}; 238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 239 240 GlobalProperty pc_compat_2_4[] = { 241 PC_CPU_MODEL_IDS("2.4.0") 242 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 247 { TYPE_X86_CPU, "check", "off" }, 248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 256 }; 257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 258 259 GlobalProperty pc_compat_2_3[] = { 260 PC_CPU_MODEL_IDS("2.3.0") 261 { TYPE_X86_CPU, "arat", "off" }, 262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 281 }; 282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 283 284 GlobalProperty pc_compat_2_2[] = { 285 PC_CPU_MODEL_IDS("2.2.0") 286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 304 }; 305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 306 307 GlobalProperty pc_compat_2_1[] = { 308 PC_CPU_MODEL_IDS("2.1.0") 309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 }; 312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 313 314 GlobalProperty pc_compat_2_0[] = { 315 PC_CPU_MODEL_IDS("2.0.0") 316 { "virtio-scsi-pci", "any_layout", "off" }, 317 { "PIIX4_PM", "memory-hotplug-support", "off" }, 318 { "apic", "version", "0x11" }, 319 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 320 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 321 { "pci-serial", "prog_if", "0" }, 322 { "pci-serial-2x", "prog_if", "0" }, 323 { "pci-serial-4x", "prog_if", "0" }, 324 { "virtio-net-pci", "guest_announce", "off" }, 325 { "ICH9-LPC", "memory-hotplug-support", "off" }, 326 }; 327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 328 329 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 330 { 331 GSIState *s; 332 333 s = g_new0(GSIState, 1); 334 if (kvm_ioapic_in_kernel()) { 335 kvm_pc_setup_irq_routing(pci_enabled); 336 } 337 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 338 339 return s; 340 } 341 342 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 343 unsigned size) 344 { 345 } 346 347 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 348 { 349 return 0xffffffffffffffffULL; 350 } 351 352 /* MS-DOS compatibility mode FPU exception support */ 353 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 354 unsigned size) 355 { 356 if (tcg_enabled()) { 357 cpu_set_ignne(); 358 } 359 } 360 361 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 362 { 363 return 0xffffffffffffffffULL; 364 } 365 366 /* PC cmos mappings */ 367 368 #define REG_EQUIPMENT_BYTE 0x14 369 370 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 371 int16_t cylinders, int8_t heads, int8_t sectors) 372 { 373 mc146818rtc_set_cmos_data(s, type_ofs, 47); 374 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 375 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 376 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 377 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 378 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 379 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 380 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 381 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 382 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 383 } 384 385 /* convert boot_device letter to something recognizable by the bios */ 386 static int boot_device2nibble(char boot_device) 387 { 388 switch(boot_device) { 389 case 'a': 390 case 'b': 391 return 0x01; /* floppy boot */ 392 case 'c': 393 return 0x02; /* hard drive boot */ 394 case 'd': 395 return 0x03; /* CD-ROM boot */ 396 case 'n': 397 return 0x04; /* Network boot */ 398 } 399 return 0; 400 } 401 402 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 403 Error **errp) 404 { 405 #define PC_MAX_BOOT_DEVICES 3 406 int nbds, bds[3] = { 0, }; 407 int i; 408 409 nbds = strlen(boot_device); 410 if (nbds > PC_MAX_BOOT_DEVICES) { 411 error_setg(errp, "Too many boot devices for PC"); 412 return; 413 } 414 for (i = 0; i < nbds; i++) { 415 bds[i] = boot_device2nibble(boot_device[i]); 416 if (bds[i] == 0) { 417 error_setg(errp, "Invalid boot device for PC: '%c'", 418 boot_device[i]); 419 return; 420 } 421 } 422 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 423 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 424 } 425 426 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 427 { 428 set_boot_dev(opaque, boot_device, errp); 429 } 430 431 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 432 { 433 int val, nb, i; 434 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 435 FLOPPY_DRIVE_TYPE_NONE }; 436 437 /* floppy type */ 438 if (floppy) { 439 for (i = 0; i < 2; i++) { 440 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 441 } 442 } 443 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 444 cmos_get_fd_drive_type(fd_type[1]); 445 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 446 447 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 448 nb = 0; 449 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 450 nb++; 451 } 452 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 453 nb++; 454 } 455 switch (nb) { 456 case 0: 457 break; 458 case 1: 459 val |= 0x01; /* 1 drive, ready for boot */ 460 break; 461 case 2: 462 val |= 0x41; /* 2 drives, ready for boot */ 463 break; 464 } 465 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 466 } 467 468 typedef struct check_fdc_state { 469 ISADevice *floppy; 470 bool multiple; 471 } CheckFdcState; 472 473 static int check_fdc(Object *obj, void *opaque) 474 { 475 CheckFdcState *state = opaque; 476 Object *fdc; 477 uint32_t iobase; 478 Error *local_err = NULL; 479 480 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 481 if (!fdc) { 482 return 0; 483 } 484 485 iobase = object_property_get_uint(obj, "iobase", &local_err); 486 if (local_err || iobase != 0x3f0) { 487 error_free(local_err); 488 return 0; 489 } 490 491 if (state->floppy) { 492 state->multiple = true; 493 } else { 494 state->floppy = ISA_DEVICE(obj); 495 } 496 return 0; 497 } 498 499 static const char * const fdc_container_path[] = { 500 "/unattached", "/peripheral", "/peripheral-anon" 501 }; 502 503 /* 504 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 505 * and ACPI objects. 506 */ 507 static ISADevice *pc_find_fdc0(void) 508 { 509 int i; 510 Object *container; 511 CheckFdcState state = { 0 }; 512 513 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 514 container = container_get(qdev_get_machine(), fdc_container_path[i]); 515 object_child_foreach(container, check_fdc, &state); 516 } 517 518 if (state.multiple) { 519 warn_report("multiple floppy disk controllers with " 520 "iobase=0x3f0 have been found"); 521 error_printf("the one being picked for CMOS setup might not reflect " 522 "your intent"); 523 } 524 525 return state.floppy; 526 } 527 528 static void pc_cmos_init_late(PCMachineState *pcms) 529 { 530 X86MachineState *x86ms = X86_MACHINE(pcms); 531 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 532 int16_t cylinders; 533 int8_t heads, sectors; 534 int val; 535 int i, trans; 536 537 val = 0; 538 if (pcms->idebus[0] && 539 ide_get_geometry(pcms->idebus[0], 0, 540 &cylinders, &heads, §ors) >= 0) { 541 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 542 val |= 0xf0; 543 } 544 if (pcms->idebus[0] && 545 ide_get_geometry(pcms->idebus[0], 1, 546 &cylinders, &heads, §ors) >= 0) { 547 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 548 val |= 0x0f; 549 } 550 mc146818rtc_set_cmos_data(s, 0x12, val); 551 552 val = 0; 553 for (i = 0; i < 4; i++) { 554 /* NOTE: ide_get_geometry() returns the physical 555 geometry. It is always such that: 1 <= sects <= 63, 1 556 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 557 geometry can be different if a translation is done. */ 558 BusState *idebus = pcms->idebus[i / 2]; 559 if (idebus && 560 ide_get_geometry(idebus, i % 2, 561 &cylinders, &heads, §ors) >= 0) { 562 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 563 assert((trans & ~3) == 0); 564 val |= trans << (i * 2); 565 } 566 } 567 mc146818rtc_set_cmos_data(s, 0x39, val); 568 569 pc_cmos_init_floppy(s, pc_find_fdc0()); 570 } 571 572 void pc_cmos_init(PCMachineState *pcms, 573 ISADevice *rtc) 574 { 575 int val; 576 X86MachineState *x86ms = X86_MACHINE(pcms); 577 MC146818RtcState *s = MC146818_RTC(rtc); 578 579 /* various important CMOS locations needed by PC/Bochs bios */ 580 581 /* memory size */ 582 /* base memory (first MiB) */ 583 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 584 mc146818rtc_set_cmos_data(s, 0x15, val); 585 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 586 /* extended memory (next 64MiB) */ 587 if (x86ms->below_4g_mem_size > 1 * MiB) { 588 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 589 } else { 590 val = 0; 591 } 592 if (val > 65535) 593 val = 65535; 594 mc146818rtc_set_cmos_data(s, 0x17, val); 595 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 596 mc146818rtc_set_cmos_data(s, 0x30, val); 597 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 598 /* memory between 16MiB and 4GiB */ 599 if (x86ms->below_4g_mem_size > 16 * MiB) { 600 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 601 } else { 602 val = 0; 603 } 604 if (val > 65535) 605 val = 65535; 606 mc146818rtc_set_cmos_data(s, 0x34, val); 607 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 608 /* memory above 4GiB */ 609 val = x86ms->above_4g_mem_size / 65536; 610 mc146818rtc_set_cmos_data(s, 0x5b, val); 611 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 612 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 613 614 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 615 616 val = 0; 617 val |= 0x02; /* FPU is there */ 618 val |= 0x04; /* PS/2 mouse installed */ 619 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 620 621 /* hard drives and FDC are handled by pc_cmos_init_late() */ 622 } 623 624 static void handle_a20_line_change(void *opaque, int irq, int level) 625 { 626 X86CPU *cpu = opaque; 627 628 /* XXX: send to all CPUs ? */ 629 /* XXX: add logic to handle multiple A20 line sources */ 630 x86_cpu_set_a20(cpu, level); 631 } 632 633 #define NE2000_NB_MAX 6 634 635 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 636 0x280, 0x380 }; 637 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 638 639 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 640 { 641 static int nb_ne2k = 0; 642 643 if (nb_ne2k == NE2000_NB_MAX) { 644 error_setg(errp, 645 "maximum number of ISA NE2000 devices exceeded"); 646 return false; 647 } 648 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 649 ne2000_irq[nb_ne2k], nd); 650 nb_ne2k++; 651 return true; 652 } 653 654 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 655 { 656 X86CPU *cpu = opaque; 657 658 if (level) { 659 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 660 } 661 } 662 663 static 664 void pc_machine_done(Notifier *notifier, void *data) 665 { 666 PCMachineState *pcms = container_of(notifier, 667 PCMachineState, machine_done); 668 X86MachineState *x86ms = X86_MACHINE(pcms); 669 670 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 671 &error_fatal); 672 673 if (pcms->cxl_devices_state.is_enabled) { 674 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 675 } 676 677 /* set the number of CPUs */ 678 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 679 680 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 681 682 acpi_setup(); 683 if (x86ms->fw_cfg) { 684 fw_cfg_build_smbios(pcms, x86ms->fw_cfg); 685 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 686 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 687 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 688 } 689 690 pc_cmos_init_late(pcms); 691 } 692 693 /* setup pci memory address space mapping into system address space */ 694 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 695 MemoryRegion *pci_address_space) 696 { 697 /* Set to lower priority than RAM */ 698 memory_region_add_subregion_overlap(system_memory, 0x0, 699 pci_address_space, -1); 700 } 701 702 void xen_load_linux(PCMachineState *pcms) 703 { 704 int i; 705 FWCfgState *fw_cfg; 706 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 707 X86MachineState *x86ms = X86_MACHINE(pcms); 708 709 assert(MACHINE(pcms)->kernel_filename != NULL); 710 711 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 712 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 713 rom_set_fw(fw_cfg); 714 715 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 716 pcmc->pvh_enabled); 717 for (i = 0; i < nb_option_roms; i++) { 718 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 719 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 720 !strcmp(option_rom[i].name, "pvh.bin") || 721 !strcmp(option_rom[i].name, "multiboot.bin") || 722 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 723 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 724 } 725 x86ms->fw_cfg = fw_cfg; 726 } 727 728 #define PC_ROM_MIN_VGA 0xc0000 729 #define PC_ROM_MIN_OPTION 0xc8000 730 #define PC_ROM_MAX 0xe0000 731 #define PC_ROM_ALIGN 0x800 732 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 733 734 static hwaddr pc_above_4g_end(PCMachineState *pcms) 735 { 736 X86MachineState *x86ms = X86_MACHINE(pcms); 737 738 if (pcms->sgx_epc.size != 0) { 739 return sgx_epc_above_4g_end(&pcms->sgx_epc); 740 } 741 742 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 743 } 744 745 static void pc_get_device_memory_range(PCMachineState *pcms, 746 hwaddr *base, 747 ram_addr_t *device_mem_size) 748 { 749 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 750 MachineState *machine = MACHINE(pcms); 751 ram_addr_t size; 752 hwaddr addr; 753 754 size = machine->maxram_size - machine->ram_size; 755 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 756 757 if (pcmc->enforce_aligned_dimm) { 758 /* size device region assuming 1G page max alignment per slot */ 759 size += (1 * GiB) * machine->ram_slots; 760 } 761 762 *base = addr; 763 *device_mem_size = size; 764 } 765 766 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 767 { 768 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 769 MachineState *ms = MACHINE(pcms); 770 hwaddr cxl_base; 771 ram_addr_t size; 772 773 if (pcmc->has_reserved_memory && 774 (ms->ram_size < ms->maxram_size)) { 775 pc_get_device_memory_range(pcms, &cxl_base, &size); 776 cxl_base += size; 777 } else { 778 cxl_base = pc_above_4g_end(pcms); 779 } 780 781 return cxl_base; 782 } 783 784 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 785 { 786 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 787 788 if (pcms->cxl_devices_state.fixed_windows) { 789 GList *it; 790 791 start = ROUND_UP(start, 256 * MiB); 792 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 793 CXLFixedWindow *fw = it->data; 794 start += fw->size; 795 } 796 } 797 798 return start; 799 } 800 801 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 802 { 803 X86CPU *cpu = X86_CPU(first_cpu); 804 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 805 MachineState *ms = MACHINE(pcms); 806 807 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 808 /* 64-bit systems */ 809 return pc_pci_hole64_start() + pci_hole64_size - 1; 810 } 811 812 /* 32-bit systems */ 813 if (pcmc->broken_32bit_mem_addr_check) { 814 /* old value for compatibility reasons */ 815 return ((hwaddr)1 << cpu->phys_bits) - 1; 816 } 817 818 /* 819 * 32-bit systems don't have hole64 but they might have a region for 820 * memory devices. Even if additional hotplugged memory devices might 821 * not be usable by most guest OSes, we need to still consider them for 822 * calculating the highest possible GPA so that we can properly report 823 * if someone configures them on a CPU that cannot possibly address them. 824 */ 825 if (pcmc->has_reserved_memory && 826 (ms->ram_size < ms->maxram_size)) { 827 hwaddr devmem_start; 828 ram_addr_t devmem_size; 829 830 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 831 devmem_start += devmem_size; 832 return devmem_start - 1; 833 } 834 835 /* configuration without any memory hotplug */ 836 return pc_above_4g_end(pcms) - 1; 837 } 838 839 /* 840 * AMD systems with an IOMMU have an additional hole close to the 841 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 842 * on kernel version, VFIO may or may not let you DMA map those ranges. 843 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 844 * with certain memory sizes. It's also wrong to use those IOVA ranges 845 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 846 * The ranges reserved for Hyper-Transport are: 847 * 848 * FD_0000_0000h - FF_FFFF_FFFFh 849 * 850 * The ranges represent the following: 851 * 852 * Base Address Top Address Use 853 * 854 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 855 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 856 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 857 * FD_F910_0000h FD_F91F_FFFFh System Management 858 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 859 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 860 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 861 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 862 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 863 * FE_2000_0000h FF_FFFF_FFFFh Reserved 864 * 865 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 866 * Table 3: Special Address Controls (GPA) for more information. 867 */ 868 #define AMD_HT_START 0xfd00000000UL 869 #define AMD_HT_END 0xffffffffffUL 870 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 871 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 872 873 void pc_memory_init(PCMachineState *pcms, 874 MemoryRegion *system_memory, 875 MemoryRegion *rom_memory, 876 uint64_t pci_hole64_size) 877 { 878 int linux_boot, i; 879 MemoryRegion *option_rom_mr; 880 MemoryRegion *ram_below_4g, *ram_above_4g; 881 FWCfgState *fw_cfg; 882 MachineState *machine = MACHINE(pcms); 883 MachineClass *mc = MACHINE_GET_CLASS(machine); 884 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 885 X86MachineState *x86ms = X86_MACHINE(pcms); 886 hwaddr maxphysaddr, maxusedaddr; 887 hwaddr cxl_base, cxl_resv_end = 0; 888 X86CPU *cpu = X86_CPU(first_cpu); 889 890 assert(machine->ram_size == x86ms->below_4g_mem_size + 891 x86ms->above_4g_mem_size); 892 893 linux_boot = (machine->kernel_filename != NULL); 894 895 /* 896 * The HyperTransport range close to the 1T boundary is unique to AMD 897 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 898 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 899 * older machine types (<= 7.0) for compatibility purposes. 900 */ 901 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 902 /* Bail out if max possible address does not cross HT range */ 903 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 904 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 905 } 906 907 /* 908 * Advertise the HT region if address space covers the reserved 909 * region or if we relocate. 910 */ 911 if (cpu->phys_bits >= 40) { 912 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 913 } 914 } 915 916 /* 917 * phys-bits is required to be appropriately configured 918 * to make sure max used GPA is reachable. 919 */ 920 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 921 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 922 if (maxphysaddr < maxusedaddr) { 923 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 924 " phys-bits too low (%u)", 925 maxphysaddr, maxusedaddr, cpu->phys_bits); 926 exit(EXIT_FAILURE); 927 } 928 929 /* 930 * Split single memory region and use aliases to address portions of it, 931 * done for backwards compatibility with older qemus. 932 */ 933 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 934 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 935 0, x86ms->below_4g_mem_size); 936 memory_region_add_subregion(system_memory, 0, ram_below_4g); 937 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 938 if (x86ms->above_4g_mem_size > 0) { 939 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 940 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 941 machine->ram, 942 x86ms->below_4g_mem_size, 943 x86ms->above_4g_mem_size); 944 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 945 ram_above_4g); 946 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 947 E820_RAM); 948 } 949 950 if (pcms->sgx_epc.size != 0) { 951 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 952 } 953 954 if (!pcmc->has_reserved_memory && 955 (machine->ram_slots || 956 (machine->maxram_size > machine->ram_size))) { 957 958 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 959 mc->name); 960 exit(EXIT_FAILURE); 961 } 962 963 /* initialize device memory address space */ 964 if (pcmc->has_reserved_memory && 965 (machine->ram_size < machine->maxram_size)) { 966 ram_addr_t device_mem_size; 967 hwaddr device_mem_base; 968 969 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 970 error_report("unsupported amount of memory slots: %"PRIu64, 971 machine->ram_slots); 972 exit(EXIT_FAILURE); 973 } 974 975 if (QEMU_ALIGN_UP(machine->maxram_size, 976 TARGET_PAGE_SIZE) != machine->maxram_size) { 977 error_report("maximum memory size must by aligned to multiple of " 978 "%d bytes", TARGET_PAGE_SIZE); 979 exit(EXIT_FAILURE); 980 } 981 982 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 983 984 if (device_mem_base + device_mem_size < device_mem_size) { 985 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 986 machine->maxram_size); 987 exit(EXIT_FAILURE); 988 } 989 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 990 } 991 992 if (pcms->cxl_devices_state.is_enabled) { 993 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 994 hwaddr cxl_size = MiB; 995 996 cxl_base = pc_get_cxl_range_start(pcms); 997 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 998 memory_region_add_subregion(system_memory, cxl_base, mr); 999 cxl_resv_end = cxl_base + cxl_size; 1000 if (pcms->cxl_devices_state.fixed_windows) { 1001 hwaddr cxl_fmw_base; 1002 GList *it; 1003 1004 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1005 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1006 CXLFixedWindow *fw = it->data; 1007 1008 fw->base = cxl_fmw_base; 1009 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1010 "cxl-fixed-memory-region", fw->size); 1011 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1012 cxl_fmw_base += fw->size; 1013 cxl_resv_end = cxl_fmw_base; 1014 } 1015 } 1016 } 1017 1018 /* Initialize PC system firmware */ 1019 pc_system_firmware_init(pcms, rom_memory); 1020 1021 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1022 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1023 &error_fatal); 1024 if (pcmc->pci_enabled) { 1025 memory_region_set_readonly(option_rom_mr, true); 1026 } 1027 memory_region_add_subregion_overlap(rom_memory, 1028 PC_ROM_MIN_VGA, 1029 option_rom_mr, 1030 1); 1031 1032 fw_cfg = fw_cfg_arch_create(machine, 1033 x86ms->boot_cpus, x86ms->apic_id_limit); 1034 1035 rom_set_fw(fw_cfg); 1036 1037 if (machine->device_memory) { 1038 uint64_t *val = g_malloc(sizeof(*val)); 1039 uint64_t res_mem_end = machine->device_memory->base; 1040 1041 if (!pcmc->broken_reserved_end) { 1042 res_mem_end += memory_region_size(&machine->device_memory->mr); 1043 } 1044 1045 if (pcms->cxl_devices_state.is_enabled) { 1046 res_mem_end = cxl_resv_end; 1047 } 1048 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1049 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1050 } 1051 1052 if (linux_boot) { 1053 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1054 pcmc->pvh_enabled); 1055 } 1056 1057 for (i = 0; i < nb_option_roms; i++) { 1058 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1059 } 1060 x86ms->fw_cfg = fw_cfg; 1061 1062 /* Init default IOAPIC address space */ 1063 x86ms->ioapic_as = &address_space_memory; 1064 1065 /* Init ACPI memory hotplug IO base address */ 1066 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1067 } 1068 1069 /* 1070 * The 64bit pci hole starts after "above 4G RAM" and 1071 * potentially the space reserved for memory hotplug. 1072 */ 1073 uint64_t pc_pci_hole64_start(void) 1074 { 1075 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1076 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1077 MachineState *ms = MACHINE(pcms); 1078 uint64_t hole64_start = 0; 1079 ram_addr_t size = 0; 1080 1081 if (pcms->cxl_devices_state.is_enabled) { 1082 hole64_start = pc_get_cxl_range_end(pcms); 1083 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1084 pc_get_device_memory_range(pcms, &hole64_start, &size); 1085 if (!pcmc->broken_reserved_end) { 1086 hole64_start += size; 1087 } 1088 } else { 1089 hole64_start = pc_above_4g_end(pcms); 1090 } 1091 1092 return ROUND_UP(hole64_start, 1 * GiB); 1093 } 1094 1095 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1096 { 1097 DeviceState *dev = NULL; 1098 1099 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1100 if (pci_bus) { 1101 PCIDevice *pcidev = pci_vga_init(pci_bus); 1102 dev = pcidev ? &pcidev->qdev : NULL; 1103 } else if (isa_bus) { 1104 ISADevice *isadev = isa_vga_init(isa_bus); 1105 dev = isadev ? DEVICE(isadev) : NULL; 1106 } 1107 rom_reset_order_override(); 1108 return dev; 1109 } 1110 1111 static const MemoryRegionOps ioport80_io_ops = { 1112 .write = ioport80_write, 1113 .read = ioport80_read, 1114 .endianness = DEVICE_NATIVE_ENDIAN, 1115 .impl = { 1116 .min_access_size = 1, 1117 .max_access_size = 1, 1118 }, 1119 }; 1120 1121 static const MemoryRegionOps ioportF0_io_ops = { 1122 .write = ioportF0_write, 1123 .read = ioportF0_read, 1124 .endianness = DEVICE_NATIVE_ENDIAN, 1125 .impl = { 1126 .min_access_size = 1, 1127 .max_access_size = 1, 1128 }, 1129 }; 1130 1131 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1132 bool create_i8042, bool no_vmport) 1133 { 1134 int i; 1135 DriveInfo *fd[MAX_FD]; 1136 qemu_irq *a20_line; 1137 ISADevice *fdc, *i8042, *port92, *vmmouse; 1138 1139 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1140 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1141 1142 for (i = 0; i < MAX_FD; i++) { 1143 fd[i] = drive_get(IF_FLOPPY, 0, i); 1144 create_fdctrl |= !!fd[i]; 1145 } 1146 if (create_fdctrl) { 1147 fdc = isa_new(TYPE_ISA_FDC); 1148 if (fdc) { 1149 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1150 isa_fdc_init_drives(fdc, fd); 1151 } 1152 } 1153 1154 if (!create_i8042) { 1155 return; 1156 } 1157 1158 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1159 if (!no_vmport) { 1160 isa_create_simple(isa_bus, TYPE_VMPORT); 1161 vmmouse = isa_try_new("vmmouse"); 1162 } else { 1163 vmmouse = NULL; 1164 } 1165 if (vmmouse) { 1166 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1167 &error_abort); 1168 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1169 } 1170 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1171 1172 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1173 qdev_connect_gpio_out_named(DEVICE(i8042), 1174 I8042_A20_LINE, 0, a20_line[0]); 1175 qdev_connect_gpio_out_named(DEVICE(port92), 1176 PORT92_A20_LINE, 0, a20_line[1]); 1177 g_free(a20_line); 1178 } 1179 1180 void pc_basic_device_init(struct PCMachineState *pcms, 1181 ISABus *isa_bus, qemu_irq *gsi, 1182 ISADevice *rtc_state, 1183 bool create_fdctrl, 1184 uint32_t hpet_irqs) 1185 { 1186 int i; 1187 DeviceState *hpet = NULL; 1188 int pit_isa_irq = 0; 1189 qemu_irq pit_alt_irq = NULL; 1190 ISADevice *pit = NULL; 1191 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1192 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1193 X86MachineState *x86ms = X86_MACHINE(pcms); 1194 1195 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1196 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1197 1198 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1199 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1200 1201 /* 1202 * Check if an HPET shall be created. 1203 */ 1204 if (pcms->hpet_enabled) { 1205 qemu_irq rtc_irq; 1206 1207 hpet = qdev_try_new(TYPE_HPET); 1208 if (!hpet) { 1209 error_report("couldn't create HPET device"); 1210 exit(1); 1211 } 1212 /* 1213 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1214 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1215 * the property, use whatever mask they specified. 1216 */ 1217 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1218 HPET_INTCAP, NULL); 1219 if (!compat) { 1220 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1221 } 1222 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1223 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1224 1225 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1226 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1227 } 1228 pit_isa_irq = -1; 1229 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1230 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1231 1232 /* overwrite connection created by south bridge */ 1233 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1234 } 1235 1236 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1237 "date"); 1238 1239 #ifdef CONFIG_XEN_EMU 1240 if (xen_mode == XEN_EMULATE) { 1241 xen_overlay_create(); 1242 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1243 xen_gnttab_create(); 1244 xen_xenstore_create(); 1245 if (pcms->pcibus) { 1246 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1247 } 1248 xen_bus_init(); 1249 xen_be_init(); 1250 } 1251 #endif 1252 1253 qemu_register_boot_set(pc_boot_set, rtc_state); 1254 1255 if (!xen_enabled() && 1256 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1257 if (kvm_pit_in_kernel()) { 1258 pit = kvm_pit_init(isa_bus, 0x40); 1259 } else { 1260 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1261 } 1262 if (hpet) { 1263 /* connect PIT to output control line of the HPET */ 1264 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1265 } 1266 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1267 OBJECT(pit), &error_fatal); 1268 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1269 } 1270 1271 /* Super I/O */ 1272 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1273 pcms->vmport != ON_OFF_AUTO_ON); 1274 } 1275 1276 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(pcmc); 1279 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1280 NICInfo *nd; 1281 1282 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1283 1284 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1285 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1286 } 1287 1288 /* Anything remaining should be a PCI NIC */ 1289 pci_init_nic_devices(pci_bus, mc->default_nic); 1290 1291 rom_reset_order_override(); 1292 } 1293 1294 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1295 { 1296 qemu_irq *i8259; 1297 1298 if (kvm_pic_in_kernel()) { 1299 i8259 = kvm_i8259_init(isa_bus); 1300 } else if (xen_enabled()) { 1301 i8259 = xen_interrupt_controller_init(); 1302 } else { 1303 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1304 } 1305 1306 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1307 i8259_irqs[i] = i8259[i]; 1308 } 1309 1310 g_free(i8259); 1311 } 1312 1313 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1314 Error **errp) 1315 { 1316 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1317 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1318 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1319 const MachineState *ms = MACHINE(hotplug_dev); 1320 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1321 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1322 Error *local_err = NULL; 1323 1324 /* 1325 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1326 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1327 * addition to cover this case. 1328 */ 1329 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1330 error_setg(errp, 1331 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1332 return; 1333 } 1334 1335 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1336 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1337 return; 1338 } 1339 1340 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1341 if (local_err) { 1342 error_propagate(errp, local_err); 1343 return; 1344 } 1345 1346 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1347 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1348 } 1349 1350 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1351 DeviceState *dev, Error **errp) 1352 { 1353 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1354 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1355 MachineState *ms = MACHINE(hotplug_dev); 1356 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1357 1358 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1359 1360 if (is_nvdimm) { 1361 nvdimm_plug(ms->nvdimms_state); 1362 } 1363 1364 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1365 } 1366 1367 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1371 1372 /* 1373 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1374 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1375 * addition to cover this case. 1376 */ 1377 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1378 error_setg(errp, 1379 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1380 return; 1381 } 1382 1383 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1384 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1385 return; 1386 } 1387 1388 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1389 errp); 1390 } 1391 1392 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1393 DeviceState *dev, Error **errp) 1394 { 1395 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1396 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1397 Error *local_err = NULL; 1398 1399 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1400 if (local_err) { 1401 goto out; 1402 } 1403 1404 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1405 qdev_unrealize(dev); 1406 out: 1407 error_propagate(errp, local_err); 1408 } 1409 1410 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1411 DeviceState *dev, Error **errp) 1412 { 1413 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1414 g_assert(!dev->hotplugged); 1415 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1416 errp); 1417 } 1418 1419 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1420 DeviceState *dev, Error **errp) 1421 { 1422 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1423 } 1424 1425 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1426 DeviceState *dev, Error **errp) 1427 { 1428 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1429 pc_memory_pre_plug(hotplug_dev, dev, errp); 1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1431 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1433 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1435 /* Declare the APIC range as the reserved MSI region */ 1436 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1437 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1438 QList *reserved_regions = qlist_new(); 1439 1440 qlist_append_str(reserved_regions, resv_prop_str); 1441 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1442 1443 g_free(resv_prop_str); 1444 } 1445 1446 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1447 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1448 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1449 1450 if (pcms->iommu) { 1451 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1452 "for x86 yet."); 1453 return; 1454 } 1455 pcms->iommu = dev; 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1457 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1458 } 1459 } 1460 1461 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1462 DeviceState *dev, Error **errp) 1463 { 1464 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1465 pc_memory_plug(hotplug_dev, dev, errp); 1466 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1467 x86_cpu_plug(hotplug_dev, dev, errp); 1468 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1469 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1470 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1471 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1472 } 1473 } 1474 1475 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1476 DeviceState *dev, Error **errp) 1477 { 1478 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1479 pc_memory_unplug_request(hotplug_dev, dev, errp); 1480 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1481 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1482 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1483 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1484 errp); 1485 } else { 1486 error_setg(errp, "acpi: device unplug request for not supported device" 1487 " type: %s", object_get_typename(OBJECT(dev))); 1488 } 1489 } 1490 1491 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1492 DeviceState *dev, Error **errp) 1493 { 1494 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1495 pc_memory_unplug(hotplug_dev, dev, errp); 1496 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1497 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1498 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1499 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1500 } else { 1501 error_setg(errp, "acpi: device unplug for not supported device" 1502 " type: %s", object_get_typename(OBJECT(dev))); 1503 } 1504 } 1505 1506 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1507 DeviceState *dev) 1508 { 1509 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1510 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1511 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1512 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1513 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1514 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1515 return HOTPLUG_HANDLER(machine); 1516 } 1517 1518 return NULL; 1519 } 1520 1521 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1522 void *opaque, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 OnOffAuto vmport = pcms->vmport; 1526 1527 visit_type_OnOffAuto(v, name, &vmport, errp); 1528 } 1529 1530 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1531 void *opaque, Error **errp) 1532 { 1533 PCMachineState *pcms = PC_MACHINE(obj); 1534 1535 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1536 } 1537 1538 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1539 { 1540 PCMachineState *pcms = PC_MACHINE(obj); 1541 1542 return pcms->smbus_enabled; 1543 } 1544 1545 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1546 { 1547 PCMachineState *pcms = PC_MACHINE(obj); 1548 1549 pcms->smbus_enabled = value; 1550 } 1551 1552 static bool pc_machine_get_sata(Object *obj, Error **errp) 1553 { 1554 PCMachineState *pcms = PC_MACHINE(obj); 1555 1556 return pcms->sata_enabled; 1557 } 1558 1559 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1560 { 1561 PCMachineState *pcms = PC_MACHINE(obj); 1562 1563 pcms->sata_enabled = value; 1564 } 1565 1566 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1567 { 1568 PCMachineState *pcms = PC_MACHINE(obj); 1569 1570 return pcms->hpet_enabled; 1571 } 1572 1573 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1574 { 1575 PCMachineState *pcms = PC_MACHINE(obj); 1576 1577 pcms->hpet_enabled = value; 1578 } 1579 1580 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1581 { 1582 PCMachineState *pcms = PC_MACHINE(obj); 1583 1584 return pcms->i8042_enabled; 1585 } 1586 1587 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1588 { 1589 PCMachineState *pcms = PC_MACHINE(obj); 1590 1591 pcms->i8042_enabled = value; 1592 } 1593 1594 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1595 { 1596 PCMachineState *pcms = PC_MACHINE(obj); 1597 1598 return pcms->default_bus_bypass_iommu; 1599 } 1600 1601 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1602 Error **errp) 1603 { 1604 PCMachineState *pcms = PC_MACHINE(obj); 1605 1606 pcms->default_bus_bypass_iommu = value; 1607 } 1608 1609 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1610 void *opaque, Error **errp) 1611 { 1612 PCMachineState *pcms = PC_MACHINE(obj); 1613 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1614 1615 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1616 } 1617 1618 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1619 void *opaque, Error **errp) 1620 { 1621 PCMachineState *pcms = PC_MACHINE(obj); 1622 1623 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1624 } 1625 1626 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1627 const char *name, void *opaque, 1628 Error **errp) 1629 { 1630 PCMachineState *pcms = PC_MACHINE(obj); 1631 uint64_t value = pcms->max_ram_below_4g; 1632 1633 visit_type_size(v, name, &value, errp); 1634 } 1635 1636 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1637 const char *name, void *opaque, 1638 Error **errp) 1639 { 1640 PCMachineState *pcms = PC_MACHINE(obj); 1641 uint64_t value; 1642 1643 if (!visit_type_size(v, name, &value, errp)) { 1644 return; 1645 } 1646 if (value > 4 * GiB) { 1647 error_setg(errp, 1648 "Machine option 'max-ram-below-4g=%"PRIu64 1649 "' expects size less than or equal to 4G", value); 1650 return; 1651 } 1652 1653 if (value < 1 * MiB) { 1654 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1655 "BIOS may not work with less than 1MiB", value); 1656 } 1657 1658 pcms->max_ram_below_4g = value; 1659 } 1660 1661 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1662 const char *name, void *opaque, 1663 Error **errp) 1664 { 1665 PCMachineState *pcms = PC_MACHINE(obj); 1666 uint64_t value = pcms->max_fw_size; 1667 1668 visit_type_size(v, name, &value, errp); 1669 } 1670 1671 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1672 const char *name, void *opaque, 1673 Error **errp) 1674 { 1675 PCMachineState *pcms = PC_MACHINE(obj); 1676 uint64_t value; 1677 1678 if (!visit_type_size(v, name, &value, errp)) { 1679 return; 1680 } 1681 1682 /* 1683 * We don't have a theoretically justifiable exact lower bound on the base 1684 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1685 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1686 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1687 * 16MiB in size. 1688 */ 1689 if (value > 16 * MiB) { 1690 error_setg(errp, 1691 "User specified max allowed firmware size %" PRIu64 " is " 1692 "greater than 16MiB. If combined firmware size exceeds " 1693 "16MiB the system may not boot, or experience intermittent" 1694 "stability issues.", 1695 value); 1696 return; 1697 } 1698 1699 pcms->max_fw_size = value; 1700 } 1701 1702 1703 static void pc_machine_initfn(Object *obj) 1704 { 1705 PCMachineState *pcms = PC_MACHINE(obj); 1706 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1707 1708 #ifdef CONFIG_VMPORT 1709 pcms->vmport = ON_OFF_AUTO_AUTO; 1710 #else 1711 pcms->vmport = ON_OFF_AUTO_OFF; 1712 #endif /* CONFIG_VMPORT */ 1713 pcms->max_ram_below_4g = 0; /* use default */ 1714 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1715 pcms->south_bridge = pcmc->default_south_bridge; 1716 1717 /* acpi build is enabled by default if machine supports it */ 1718 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1719 pcms->smbus_enabled = true; 1720 pcms->sata_enabled = true; 1721 pcms->i8042_enabled = true; 1722 pcms->max_fw_size = 8 * MiB; 1723 #ifdef CONFIG_HPET 1724 pcms->hpet_enabled = true; 1725 #endif 1726 pcms->default_bus_bypass_iommu = false; 1727 1728 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1729 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1730 OBJECT(pcms->pcspk), "audiodev"); 1731 cxl_machine_init(obj, &pcms->cxl_devices_state); 1732 1733 pcms->machine_done.notify = pc_machine_done; 1734 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1735 } 1736 1737 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1738 { 1739 CPUState *cs; 1740 X86CPU *cpu; 1741 1742 qemu_devices_reset(reason); 1743 1744 /* Reset APIC after devices have been reset to cancel 1745 * any changes that qemu_devices_reset() might have done. 1746 */ 1747 CPU_FOREACH(cs) { 1748 cpu = X86_CPU(cs); 1749 1750 x86_cpu_after_reset(cpu); 1751 } 1752 } 1753 1754 static void pc_machine_wakeup(MachineState *machine) 1755 { 1756 cpu_synchronize_all_states(); 1757 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1758 cpu_synchronize_all_post_reset(); 1759 } 1760 1761 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1762 { 1763 X86IOMMUState *iommu = x86_iommu_get_default(); 1764 IntelIOMMUState *intel_iommu; 1765 1766 if (iommu && 1767 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1768 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1769 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1770 if (!intel_iommu->caching_mode) { 1771 error_setg(errp, "Device assignment is not allowed without " 1772 "enabling caching-mode=on for Intel IOMMU."); 1773 return false; 1774 } 1775 } 1776 1777 return true; 1778 } 1779 1780 static void pc_machine_class_init(ObjectClass *oc, void *data) 1781 { 1782 MachineClass *mc = MACHINE_CLASS(oc); 1783 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1784 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1785 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1786 1787 pcmc->pci_enabled = true; 1788 pcmc->has_acpi_build = true; 1789 pcmc->rsdp_in_ram = true; 1790 pcmc->smbios_defaults = true; 1791 pcmc->smbios_uuid_encoded = true; 1792 pcmc->gigabyte_align = true; 1793 pcmc->has_reserved_memory = true; 1794 pcmc->enforce_aligned_dimm = true; 1795 pcmc->enforce_amd_1tb_hole = true; 1796 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1797 * to be used at the moment, 32K should be enough for a while. */ 1798 pcmc->acpi_data_size = 0x20000 + 0x8000; 1799 pcmc->pvh_enabled = true; 1800 pcmc->kvmclock_create_always = true; 1801 pcmc->resizable_acpi_blob = true; 1802 x86mc->apic_xrupt_override = true; 1803 assert(!mc->get_hotplug_handler); 1804 mc->get_hotplug_handler = pc_get_hotplug_handler; 1805 mc->hotplug_allowed = pc_hotplug_allowed; 1806 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1807 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1808 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1809 mc->auto_enable_numa_with_memhp = true; 1810 mc->auto_enable_numa_with_memdev = true; 1811 mc->has_hotpluggable_cpus = true; 1812 mc->default_boot_order = "cad"; 1813 mc->block_default_type = IF_IDE; 1814 mc->max_cpus = 255; 1815 mc->reset = pc_machine_reset; 1816 mc->wakeup = pc_machine_wakeup; 1817 hc->pre_plug = pc_machine_device_pre_plug_cb; 1818 hc->plug = pc_machine_device_plug_cb; 1819 hc->unplug_request = pc_machine_device_unplug_request_cb; 1820 hc->unplug = pc_machine_device_unplug_cb; 1821 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1822 mc->nvdimm_supported = true; 1823 mc->smp_props.dies_supported = true; 1824 mc->default_ram_id = "pc.ram"; 1825 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 1826 1827 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1828 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1829 NULL, NULL); 1830 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1831 "Maximum ram below the 4G boundary (32bit boundary)"); 1832 1833 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1834 pc_machine_get_vmport, pc_machine_set_vmport, 1835 NULL, NULL); 1836 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1837 "Enable vmport (pc & q35)"); 1838 1839 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1840 pc_machine_get_smbus, pc_machine_set_smbus); 1841 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1842 "Enable/disable system management bus"); 1843 1844 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1845 pc_machine_get_sata, pc_machine_set_sata); 1846 object_class_property_set_description(oc, PC_MACHINE_SATA, 1847 "Enable/disable Serial ATA bus"); 1848 1849 object_class_property_add_bool(oc, "hpet", 1850 pc_machine_get_hpet, pc_machine_set_hpet); 1851 object_class_property_set_description(oc, "hpet", 1852 "Enable/disable high precision event timer emulation"); 1853 1854 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1855 pc_machine_get_i8042, pc_machine_set_i8042); 1856 1857 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1858 pc_machine_get_default_bus_bypass_iommu, 1859 pc_machine_set_default_bus_bypass_iommu); 1860 1861 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1862 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1863 NULL, NULL); 1864 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1865 "Maximum combined firmware size"); 1866 1867 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1868 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1869 NULL, NULL); 1870 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1871 "SMBIOS Entry Point type [32, 64]"); 1872 } 1873 1874 static const TypeInfo pc_machine_info = { 1875 .name = TYPE_PC_MACHINE, 1876 .parent = TYPE_X86_MACHINE, 1877 .abstract = true, 1878 .instance_size = sizeof(PCMachineState), 1879 .instance_init = pc_machine_initfn, 1880 .class_size = sizeof(PCMachineClass), 1881 .class_init = pc_machine_class_init, 1882 .interfaces = (InterfaceInfo[]) { 1883 { TYPE_HOTPLUG_HANDLER }, 1884 { } 1885 }, 1886 }; 1887 1888 static void pc_machine_register_types(void) 1889 { 1890 type_register_static(&pc_machine_info); 1891 } 1892 1893 type_init(pc_machine_register_types) 1894