1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/acpi/cpu_hotplug.h" 57 #include "hw/cpu/icc_bus.h" 58 #include "hw/boards.h" 59 #include "hw/pci/pci_host.h" 60 #include "acpi-build.h" 61 62 /* debug PC/ISA interrupts */ 63 //#define DEBUG_IRQ 64 65 #ifdef DEBUG_IRQ 66 #define DPRINTF(fmt, ...) \ 67 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 68 #else 69 #define DPRINTF(fmt, ...) 70 #endif 71 72 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 73 #define ACPI_DATA_SIZE 0x10000 74 #define BIOS_CFG_IOPORT 0x510 75 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 76 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 77 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 78 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 79 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 80 81 #define E820_NR_ENTRIES 16 82 83 struct e820_entry { 84 uint64_t address; 85 uint64_t length; 86 uint32_t type; 87 } QEMU_PACKED __attribute((__aligned__(4))); 88 89 struct e820_table { 90 uint32_t count; 91 struct e820_entry entry[E820_NR_ENTRIES]; 92 } QEMU_PACKED __attribute((__aligned__(4))); 93 94 static struct e820_table e820_reserve; 95 static struct e820_entry *e820_table; 96 static unsigned e820_entries; 97 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 98 99 void gsi_handler(void *opaque, int n, int level) 100 { 101 GSIState *s = opaque; 102 103 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 104 if (n < ISA_NUM_IRQS) { 105 qemu_set_irq(s->i8259_irq[n], level); 106 } 107 qemu_set_irq(s->ioapic_irq[n], level); 108 } 109 110 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 111 unsigned size) 112 { 113 } 114 115 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 116 { 117 return 0xffffffffffffffffULL; 118 } 119 120 /* MSDOS compatibility mode FPU exception support */ 121 static qemu_irq ferr_irq; 122 123 void pc_register_ferr_irq(qemu_irq irq) 124 { 125 ferr_irq = irq; 126 } 127 128 /* XXX: add IGNNE support */ 129 void cpu_set_ferr(CPUX86State *s) 130 { 131 qemu_irq_raise(ferr_irq); 132 } 133 134 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 135 unsigned size) 136 { 137 qemu_irq_lower(ferr_irq); 138 } 139 140 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 141 { 142 return 0xffffffffffffffffULL; 143 } 144 145 /* TSC handling */ 146 uint64_t cpu_get_tsc(CPUX86State *env) 147 { 148 return cpu_get_ticks(); 149 } 150 151 /* SMM support */ 152 153 static cpu_set_smm_t smm_set; 154 static void *smm_arg; 155 156 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 157 { 158 assert(smm_set == NULL); 159 assert(smm_arg == NULL); 160 smm_set = callback; 161 smm_arg = arg; 162 } 163 164 void cpu_smm_update(CPUX86State *env) 165 { 166 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 167 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 168 } 169 } 170 171 172 /* IRQ handling */ 173 int cpu_get_pic_interrupt(CPUX86State *env) 174 { 175 X86CPU *cpu = x86_env_get_cpu(env); 176 int intno; 177 178 intno = apic_get_interrupt(cpu->apic_state); 179 if (intno >= 0) { 180 return intno; 181 } 182 /* read the irq from the PIC */ 183 if (!apic_accept_pic_intr(cpu->apic_state)) { 184 return -1; 185 } 186 187 intno = pic_read_irq(isa_pic); 188 return intno; 189 } 190 191 static void pic_irq_request(void *opaque, int irq, int level) 192 { 193 CPUState *cs = first_cpu; 194 X86CPU *cpu = X86_CPU(cs); 195 196 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 197 if (cpu->apic_state) { 198 CPU_FOREACH(cs) { 199 cpu = X86_CPU(cs); 200 if (apic_accept_pic_intr(cpu->apic_state)) { 201 apic_deliver_pic_intr(cpu->apic_state, level); 202 } 203 } 204 } else { 205 if (level) { 206 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 207 } else { 208 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 209 } 210 } 211 } 212 213 /* PC cmos mappings */ 214 215 #define REG_EQUIPMENT_BYTE 0x14 216 217 static int cmos_get_fd_drive_type(FDriveType fd0) 218 { 219 int val; 220 221 switch (fd0) { 222 case FDRIVE_DRV_144: 223 /* 1.44 Mb 3"5 drive */ 224 val = 4; 225 break; 226 case FDRIVE_DRV_288: 227 /* 2.88 Mb 3"5 drive */ 228 val = 5; 229 break; 230 case FDRIVE_DRV_120: 231 /* 1.2 Mb 5"5 drive */ 232 val = 2; 233 break; 234 case FDRIVE_DRV_NONE: 235 default: 236 val = 0; 237 break; 238 } 239 return val; 240 } 241 242 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 243 int16_t cylinders, int8_t heads, int8_t sectors) 244 { 245 rtc_set_memory(s, type_ofs, 47); 246 rtc_set_memory(s, info_ofs, cylinders); 247 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 2, heads); 249 rtc_set_memory(s, info_ofs + 3, 0xff); 250 rtc_set_memory(s, info_ofs + 4, 0xff); 251 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 252 rtc_set_memory(s, info_ofs + 6, cylinders); 253 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 254 rtc_set_memory(s, info_ofs + 8, sectors); 255 } 256 257 /* convert boot_device letter to something recognizable by the bios */ 258 static int boot_device2nibble(char boot_device) 259 { 260 switch(boot_device) { 261 case 'a': 262 case 'b': 263 return 0x01; /* floppy boot */ 264 case 'c': 265 return 0x02; /* hard drive boot */ 266 case 'd': 267 return 0x03; /* CD-ROM boot */ 268 case 'n': 269 return 0x04; /* Network boot */ 270 } 271 return 0; 272 } 273 274 static int set_boot_dev(ISADevice *s, const char *boot_device) 275 { 276 #define PC_MAX_BOOT_DEVICES 3 277 int nbds, bds[3] = { 0, }; 278 int i; 279 280 nbds = strlen(boot_device); 281 if (nbds > PC_MAX_BOOT_DEVICES) { 282 error_report("Too many boot devices for PC"); 283 return(1); 284 } 285 for (i = 0; i < nbds; i++) { 286 bds[i] = boot_device2nibble(boot_device[i]); 287 if (bds[i] == 0) { 288 error_report("Invalid boot device for PC: '%c'", 289 boot_device[i]); 290 return(1); 291 } 292 } 293 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 294 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 295 return(0); 296 } 297 298 static int pc_boot_set(void *opaque, const char *boot_device) 299 { 300 return set_boot_dev(opaque, boot_device); 301 } 302 303 typedef struct pc_cmos_init_late_arg { 304 ISADevice *rtc_state; 305 BusState *idebus[2]; 306 } pc_cmos_init_late_arg; 307 308 static void pc_cmos_init_late(void *opaque) 309 { 310 pc_cmos_init_late_arg *arg = opaque; 311 ISADevice *s = arg->rtc_state; 312 int16_t cylinders; 313 int8_t heads, sectors; 314 int val; 315 int i, trans; 316 317 val = 0; 318 if (ide_get_geometry(arg->idebus[0], 0, 319 &cylinders, &heads, §ors) >= 0) { 320 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 321 val |= 0xf0; 322 } 323 if (ide_get_geometry(arg->idebus[0], 1, 324 &cylinders, &heads, §ors) >= 0) { 325 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 326 val |= 0x0f; 327 } 328 rtc_set_memory(s, 0x12, val); 329 330 val = 0; 331 for (i = 0; i < 4; i++) { 332 /* NOTE: ide_get_geometry() returns the physical 333 geometry. It is always such that: 1 <= sects <= 63, 1 334 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 335 geometry can be different if a translation is done. */ 336 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 337 &cylinders, &heads, §ors) >= 0) { 338 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 339 assert((trans & ~3) == 0); 340 val |= trans << (i * 2); 341 } 342 } 343 rtc_set_memory(s, 0x39, val); 344 345 qemu_unregister_reset(pc_cmos_init_late, opaque); 346 } 347 348 typedef struct RTCCPUHotplugArg { 349 Notifier cpu_added_notifier; 350 ISADevice *rtc_state; 351 } RTCCPUHotplugArg; 352 353 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 354 { 355 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 356 cpu_added_notifier); 357 ISADevice *s = arg->rtc_state; 358 359 /* increment the number of CPUs */ 360 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 361 } 362 363 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 364 const char *boot_device, 365 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 366 ISADevice *s) 367 { 368 int val, nb, i; 369 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 370 static pc_cmos_init_late_arg arg; 371 static RTCCPUHotplugArg cpu_hotplug_cb; 372 373 /* various important CMOS locations needed by PC/Bochs bios */ 374 375 /* memory size */ 376 /* base memory (first MiB) */ 377 val = MIN(ram_size / 1024, 640); 378 rtc_set_memory(s, 0x15, val); 379 rtc_set_memory(s, 0x16, val >> 8); 380 /* extended memory (next 64MiB) */ 381 if (ram_size > 1024 * 1024) { 382 val = (ram_size - 1024 * 1024) / 1024; 383 } else { 384 val = 0; 385 } 386 if (val > 65535) 387 val = 65535; 388 rtc_set_memory(s, 0x17, val); 389 rtc_set_memory(s, 0x18, val >> 8); 390 rtc_set_memory(s, 0x30, val); 391 rtc_set_memory(s, 0x31, val >> 8); 392 /* memory between 16MiB and 4GiB */ 393 if (ram_size > 16 * 1024 * 1024) { 394 val = (ram_size - 16 * 1024 * 1024) / 65536; 395 } else { 396 val = 0; 397 } 398 if (val > 65535) 399 val = 65535; 400 rtc_set_memory(s, 0x34, val); 401 rtc_set_memory(s, 0x35, val >> 8); 402 /* memory above 4GiB */ 403 val = above_4g_mem_size / 65536; 404 rtc_set_memory(s, 0x5b, val); 405 rtc_set_memory(s, 0x5c, val >> 8); 406 rtc_set_memory(s, 0x5d, val >> 16); 407 408 /* set the number of CPU */ 409 rtc_set_memory(s, 0x5f, smp_cpus - 1); 410 /* init CPU hotplug notifier */ 411 cpu_hotplug_cb.rtc_state = s; 412 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 413 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 414 415 if (set_boot_dev(s, boot_device)) { 416 exit(1); 417 } 418 419 /* floppy type */ 420 if (floppy) { 421 for (i = 0; i < 2; i++) { 422 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 423 } 424 } 425 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 426 cmos_get_fd_drive_type(fd_type[1]); 427 rtc_set_memory(s, 0x10, val); 428 429 val = 0; 430 nb = 0; 431 if (fd_type[0] < FDRIVE_DRV_NONE) { 432 nb++; 433 } 434 if (fd_type[1] < FDRIVE_DRV_NONE) { 435 nb++; 436 } 437 switch (nb) { 438 case 0: 439 break; 440 case 1: 441 val |= 0x01; /* 1 drive, ready for boot */ 442 break; 443 case 2: 444 val |= 0x41; /* 2 drives, ready for boot */ 445 break; 446 } 447 val |= 0x02; /* FPU is there */ 448 val |= 0x04; /* PS/2 mouse installed */ 449 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 450 451 /* hard drives */ 452 arg.rtc_state = s; 453 arg.idebus[0] = idebus0; 454 arg.idebus[1] = idebus1; 455 qemu_register_reset(pc_cmos_init_late, &arg); 456 } 457 458 #define TYPE_PORT92 "port92" 459 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 460 461 /* port 92 stuff: could be split off */ 462 typedef struct Port92State { 463 ISADevice parent_obj; 464 465 MemoryRegion io; 466 uint8_t outport; 467 qemu_irq *a20_out; 468 } Port92State; 469 470 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 471 unsigned size) 472 { 473 Port92State *s = opaque; 474 int oldval = s->outport; 475 476 DPRINTF("port92: write 0x%02x\n", val); 477 s->outport = val; 478 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 479 if ((val & 1) && !(oldval & 1)) { 480 qemu_system_reset_request(); 481 } 482 } 483 484 static uint64_t port92_read(void *opaque, hwaddr addr, 485 unsigned size) 486 { 487 Port92State *s = opaque; 488 uint32_t ret; 489 490 ret = s->outport; 491 DPRINTF("port92: read 0x%02x\n", ret); 492 return ret; 493 } 494 495 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 496 { 497 Port92State *s = PORT92(dev); 498 499 s->a20_out = a20_out; 500 } 501 502 static const VMStateDescription vmstate_port92_isa = { 503 .name = "port92", 504 .version_id = 1, 505 .minimum_version_id = 1, 506 .minimum_version_id_old = 1, 507 .fields = (VMStateField []) { 508 VMSTATE_UINT8(outport, Port92State), 509 VMSTATE_END_OF_LIST() 510 } 511 }; 512 513 static void port92_reset(DeviceState *d) 514 { 515 Port92State *s = PORT92(d); 516 517 s->outport &= ~1; 518 } 519 520 static const MemoryRegionOps port92_ops = { 521 .read = port92_read, 522 .write = port92_write, 523 .impl = { 524 .min_access_size = 1, 525 .max_access_size = 1, 526 }, 527 .endianness = DEVICE_LITTLE_ENDIAN, 528 }; 529 530 static void port92_initfn(Object *obj) 531 { 532 Port92State *s = PORT92(obj); 533 534 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 535 536 s->outport = 0; 537 } 538 539 static void port92_realizefn(DeviceState *dev, Error **errp) 540 { 541 ISADevice *isadev = ISA_DEVICE(dev); 542 Port92State *s = PORT92(dev); 543 544 isa_register_ioport(isadev, &s->io, 0x92); 545 } 546 547 static void port92_class_initfn(ObjectClass *klass, void *data) 548 { 549 DeviceClass *dc = DEVICE_CLASS(klass); 550 551 dc->realize = port92_realizefn; 552 dc->reset = port92_reset; 553 dc->vmsd = &vmstate_port92_isa; 554 /* 555 * Reason: unlike ordinary ISA devices, this one needs additional 556 * wiring: its A20 output line needs to be wired up by 557 * port92_init(). 558 */ 559 dc->cannot_instantiate_with_device_add_yet = true; 560 } 561 562 static const TypeInfo port92_info = { 563 .name = TYPE_PORT92, 564 .parent = TYPE_ISA_DEVICE, 565 .instance_size = sizeof(Port92State), 566 .instance_init = port92_initfn, 567 .class_init = port92_class_initfn, 568 }; 569 570 static void port92_register_types(void) 571 { 572 type_register_static(&port92_info); 573 } 574 575 type_init(port92_register_types) 576 577 static void handle_a20_line_change(void *opaque, int irq, int level) 578 { 579 X86CPU *cpu = opaque; 580 581 /* XXX: send to all CPUs ? */ 582 /* XXX: add logic to handle multiple A20 line sources */ 583 x86_cpu_set_a20(cpu, level); 584 } 585 586 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 587 { 588 int index = le32_to_cpu(e820_reserve.count); 589 struct e820_entry *entry; 590 591 if (type != E820_RAM) { 592 /* old FW_CFG_E820_TABLE entry -- reservations only */ 593 if (index >= E820_NR_ENTRIES) { 594 return -EBUSY; 595 } 596 entry = &e820_reserve.entry[index++]; 597 598 entry->address = cpu_to_le64(address); 599 entry->length = cpu_to_le64(length); 600 entry->type = cpu_to_le32(type); 601 602 e820_reserve.count = cpu_to_le32(index); 603 } 604 605 /* new "etc/e820" file -- include ram too */ 606 e820_table = g_realloc(e820_table, 607 sizeof(struct e820_entry) * (e820_entries+1)); 608 e820_table[e820_entries].address = cpu_to_le64(address); 609 e820_table[e820_entries].length = cpu_to_le64(length); 610 e820_table[e820_entries].type = cpu_to_le32(type); 611 e820_entries++; 612 613 return e820_entries; 614 } 615 616 int e820_get_num_entries(void) 617 { 618 return e820_entries; 619 } 620 621 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 622 { 623 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 624 *address = le64_to_cpu(e820_table[idx].address); 625 *length = le64_to_cpu(e820_table[idx].length); 626 return true; 627 } 628 return false; 629 } 630 631 /* Calculates the limit to CPU APIC ID values 632 * 633 * This function returns the limit for the APIC ID value, so that all 634 * CPU APIC IDs are < pc_apic_id_limit(). 635 * 636 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 637 */ 638 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 639 { 640 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 641 } 642 643 static FWCfgState *bochs_bios_init(void) 644 { 645 FWCfgState *fw_cfg; 646 uint8_t *smbios_tables, *smbios_anchor; 647 size_t smbios_tables_len, smbios_anchor_len; 648 uint64_t *numa_fw_cfg; 649 int i, j; 650 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 651 652 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 653 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 654 * 655 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 656 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 657 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 658 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 659 * may see". 660 * 661 * So, this means we must not use max_cpus, here, but the maximum possible 662 * APIC ID value, plus one. 663 * 664 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 665 * the APIC ID, not the "CPU index" 666 */ 667 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 668 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 669 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 670 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 671 acpi_tables, acpi_tables_len); 672 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 673 674 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 675 if (smbios_tables) { 676 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 677 smbios_tables, smbios_tables_len); 678 } 679 680 smbios_get_tables(&smbios_tables, &smbios_tables_len, 681 &smbios_anchor, &smbios_anchor_len); 682 if (smbios_anchor) { 683 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 684 smbios_tables, smbios_tables_len); 685 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 686 smbios_anchor, smbios_anchor_len); 687 } 688 689 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 690 &e820_reserve, sizeof(e820_reserve)); 691 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 692 sizeof(struct e820_entry) * e820_entries); 693 694 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 695 /* allocate memory for the NUMA channel: one (64bit) word for the number 696 * of nodes, one word for each VCPU->node and one word for each node to 697 * hold the amount of memory. 698 */ 699 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 700 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 701 for (i = 0; i < max_cpus; i++) { 702 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 703 assert(apic_id < apic_id_limit); 704 for (j = 0; j < nb_numa_nodes; j++) { 705 if (test_bit(i, node_cpumask[j])) { 706 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 707 break; 708 } 709 } 710 } 711 for (i = 0; i < nb_numa_nodes; i++) { 712 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); 713 } 714 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 715 (1 + apic_id_limit + nb_numa_nodes) * 716 sizeof(*numa_fw_cfg)); 717 718 return fw_cfg; 719 } 720 721 static long get_file_size(FILE *f) 722 { 723 long where, size; 724 725 /* XXX: on Unix systems, using fstat() probably makes more sense */ 726 727 where = ftell(f); 728 fseek(f, 0, SEEK_END); 729 size = ftell(f); 730 fseek(f, where, SEEK_SET); 731 732 return size; 733 } 734 735 static void load_linux(FWCfgState *fw_cfg, 736 const char *kernel_filename, 737 const char *initrd_filename, 738 const char *kernel_cmdline, 739 hwaddr max_ram_size) 740 { 741 uint16_t protocol; 742 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 743 uint32_t initrd_max; 744 uint8_t header[8192], *setup, *kernel, *initrd_data; 745 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 746 FILE *f; 747 char *vmode; 748 749 /* Align to 16 bytes as a paranoia measure */ 750 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 751 752 /* load the kernel header */ 753 f = fopen(kernel_filename, "rb"); 754 if (!f || !(kernel_size = get_file_size(f)) || 755 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 756 MIN(ARRAY_SIZE(header), kernel_size)) { 757 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 758 kernel_filename, strerror(errno)); 759 exit(1); 760 } 761 762 /* kernel protocol version */ 763 #if 0 764 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 765 #endif 766 if (ldl_p(header+0x202) == 0x53726448) { 767 protocol = lduw_p(header+0x206); 768 } else { 769 /* This looks like a multiboot kernel. If it is, let's stop 770 treating it like a Linux kernel. */ 771 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 772 kernel_cmdline, kernel_size, header)) { 773 return; 774 } 775 protocol = 0; 776 } 777 778 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 779 /* Low kernel */ 780 real_addr = 0x90000; 781 cmdline_addr = 0x9a000 - cmdline_size; 782 prot_addr = 0x10000; 783 } else if (protocol < 0x202) { 784 /* High but ancient kernel */ 785 real_addr = 0x90000; 786 cmdline_addr = 0x9a000 - cmdline_size; 787 prot_addr = 0x100000; 788 } else { 789 /* High and recent kernel */ 790 real_addr = 0x10000; 791 cmdline_addr = 0x20000; 792 prot_addr = 0x100000; 793 } 794 795 #if 0 796 fprintf(stderr, 797 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 798 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 799 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 800 real_addr, 801 cmdline_addr, 802 prot_addr); 803 #endif 804 805 /* highest address for loading the initrd */ 806 if (protocol >= 0x203) { 807 initrd_max = ldl_p(header+0x22c); 808 } else { 809 initrd_max = 0x37ffffff; 810 } 811 812 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 813 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 814 815 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 816 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 817 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 818 819 if (protocol >= 0x202) { 820 stl_p(header+0x228, cmdline_addr); 821 } else { 822 stw_p(header+0x20, 0xA33F); 823 stw_p(header+0x22, cmdline_addr-real_addr); 824 } 825 826 /* handle vga= parameter */ 827 vmode = strstr(kernel_cmdline, "vga="); 828 if (vmode) { 829 unsigned int video_mode; 830 /* skip "vga=" */ 831 vmode += 4; 832 if (!strncmp(vmode, "normal", 6)) { 833 video_mode = 0xffff; 834 } else if (!strncmp(vmode, "ext", 3)) { 835 video_mode = 0xfffe; 836 } else if (!strncmp(vmode, "ask", 3)) { 837 video_mode = 0xfffd; 838 } else { 839 video_mode = strtol(vmode, NULL, 0); 840 } 841 stw_p(header+0x1fa, video_mode); 842 } 843 844 /* loader type */ 845 /* High nybble = B reserved for QEMU; low nybble is revision number. 846 If this code is substantially changed, you may want to consider 847 incrementing the revision. */ 848 if (protocol >= 0x200) { 849 header[0x210] = 0xB0; 850 } 851 /* heap */ 852 if (protocol >= 0x201) { 853 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 854 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 855 } 856 857 /* load initrd */ 858 if (initrd_filename) { 859 if (protocol < 0x200) { 860 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 861 exit(1); 862 } 863 864 initrd_size = get_image_size(initrd_filename); 865 if (initrd_size < 0) { 866 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 867 initrd_filename, strerror(errno)); 868 exit(1); 869 } 870 871 initrd_addr = (initrd_max-initrd_size) & ~4095; 872 873 initrd_data = g_malloc(initrd_size); 874 load_image(initrd_filename, initrd_data); 875 876 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 877 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 878 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 879 880 stl_p(header+0x218, initrd_addr); 881 stl_p(header+0x21c, initrd_size); 882 } 883 884 /* load kernel and setup */ 885 setup_size = header[0x1f1]; 886 if (setup_size == 0) { 887 setup_size = 4; 888 } 889 setup_size = (setup_size+1)*512; 890 kernel_size -= setup_size; 891 892 setup = g_malloc(setup_size); 893 kernel = g_malloc(kernel_size); 894 fseek(f, 0, SEEK_SET); 895 if (fread(setup, 1, setup_size, f) != setup_size) { 896 fprintf(stderr, "fread() failed\n"); 897 exit(1); 898 } 899 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 900 fprintf(stderr, "fread() failed\n"); 901 exit(1); 902 } 903 fclose(f); 904 memcpy(setup, header, MIN(sizeof(header), setup_size)); 905 906 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 907 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 908 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 909 910 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 911 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 912 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 913 914 option_rom[nb_option_roms].name = "linuxboot.bin"; 915 option_rom[nb_option_roms].bootindex = 0; 916 nb_option_roms++; 917 } 918 919 #define NE2000_NB_MAX 6 920 921 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 922 0x280, 0x380 }; 923 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 924 925 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 926 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; 927 928 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 929 { 930 static int nb_ne2k = 0; 931 932 if (nb_ne2k == NE2000_NB_MAX) 933 return; 934 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 935 ne2000_irq[nb_ne2k], nd); 936 nb_ne2k++; 937 } 938 939 DeviceState *cpu_get_current_apic(void) 940 { 941 if (current_cpu) { 942 X86CPU *cpu = X86_CPU(current_cpu); 943 return cpu->apic_state; 944 } else { 945 return NULL; 946 } 947 } 948 949 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 950 { 951 X86CPU *cpu = opaque; 952 953 if (level) { 954 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 955 } 956 } 957 958 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 959 DeviceState *icc_bridge, Error **errp) 960 { 961 X86CPU *cpu; 962 Error *local_err = NULL; 963 964 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 965 if (local_err != NULL) { 966 error_propagate(errp, local_err); 967 return NULL; 968 } 969 970 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 971 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 972 973 if (local_err) { 974 error_propagate(errp, local_err); 975 object_unref(OBJECT(cpu)); 976 cpu = NULL; 977 } 978 return cpu; 979 } 980 981 static const char *current_cpu_model; 982 983 void pc_hot_add_cpu(const int64_t id, Error **errp) 984 { 985 DeviceState *icc_bridge; 986 int64_t apic_id = x86_cpu_apic_id_from_index(id); 987 988 if (id < 0) { 989 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 990 return; 991 } 992 993 if (cpu_exists(apic_id)) { 994 error_setg(errp, "Unable to add CPU: %" PRIi64 995 ", it already exists", id); 996 return; 997 } 998 999 if (id >= max_cpus) { 1000 error_setg(errp, "Unable to add CPU: %" PRIi64 1001 ", max allowed: %d", id, max_cpus - 1); 1002 return; 1003 } 1004 1005 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1006 error_setg(errp, "Unable to add CPU: %" PRIi64 1007 ", resulting APIC ID (%" PRIi64 ") is too large", 1008 id, apic_id); 1009 return; 1010 } 1011 1012 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1013 TYPE_ICC_BRIDGE, NULL)); 1014 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1015 } 1016 1017 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1018 { 1019 int i; 1020 X86CPU *cpu = NULL; 1021 Error *error = NULL; 1022 unsigned long apic_id_limit; 1023 1024 /* init CPUs */ 1025 if (cpu_model == NULL) { 1026 #ifdef TARGET_X86_64 1027 cpu_model = "qemu64"; 1028 #else 1029 cpu_model = "qemu32"; 1030 #endif 1031 } 1032 current_cpu_model = cpu_model; 1033 1034 apic_id_limit = pc_apic_id_limit(max_cpus); 1035 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1036 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1037 apic_id_limit - 1); 1038 exit(1); 1039 } 1040 1041 for (i = 0; i < smp_cpus; i++) { 1042 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1043 icc_bridge, &error); 1044 if (error) { 1045 error_report("%s", error_get_pretty(error)); 1046 error_free(error); 1047 exit(1); 1048 } 1049 } 1050 1051 /* map APIC MMIO area if CPU has APIC */ 1052 if (cpu && cpu->apic_state) { 1053 /* XXX: what if the base changes? */ 1054 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1055 APIC_DEFAULT_ADDRESS, 0x1000); 1056 } 1057 1058 /* tell smbios about cpuid version and features */ 1059 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1060 } 1061 1062 /* pci-info ROM file. Little endian format */ 1063 typedef struct PcRomPciInfo { 1064 uint64_t w32_min; 1065 uint64_t w32_max; 1066 uint64_t w64_min; 1067 uint64_t w64_max; 1068 } PcRomPciInfo; 1069 1070 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info) 1071 { 1072 PcRomPciInfo *info; 1073 Object *pci_info; 1074 bool ambiguous = false; 1075 1076 if (!guest_info->has_pci_info || !guest_info->fw_cfg) { 1077 return; 1078 } 1079 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1080 g_assert(!ambiguous); 1081 if (!pci_info) { 1082 return; 1083 } 1084 1085 info = g_malloc(sizeof *info); 1086 info->w32_min = cpu_to_le64(object_property_get_int(pci_info, 1087 PCI_HOST_PROP_PCI_HOLE_START, NULL)); 1088 info->w32_max = cpu_to_le64(object_property_get_int(pci_info, 1089 PCI_HOST_PROP_PCI_HOLE_END, NULL)); 1090 info->w64_min = cpu_to_le64(object_property_get_int(pci_info, 1091 PCI_HOST_PROP_PCI_HOLE64_START, NULL)); 1092 info->w64_max = cpu_to_le64(object_property_get_int(pci_info, 1093 PCI_HOST_PROP_PCI_HOLE64_END, NULL)); 1094 /* Pass PCI hole info to guest via a side channel. 1095 * Required so guest PCI enumeration does the right thing. */ 1096 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info); 1097 } 1098 1099 typedef struct PcGuestInfoState { 1100 PcGuestInfo info; 1101 Notifier machine_done; 1102 } PcGuestInfoState; 1103 1104 static 1105 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1106 { 1107 PcGuestInfoState *guest_info_state = container_of(notifier, 1108 PcGuestInfoState, 1109 machine_done); 1110 pc_fw_cfg_guest_info(&guest_info_state->info); 1111 acpi_setup(&guest_info_state->info); 1112 } 1113 1114 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1115 ram_addr_t above_4g_mem_size) 1116 { 1117 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1118 PcGuestInfo *guest_info = &guest_info_state->info; 1119 int i, j; 1120 1121 guest_info->ram_size_below_4g = below_4g_mem_size; 1122 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1123 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1124 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1125 guest_info->numa_nodes = nb_numa_nodes; 1126 guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes * 1127 sizeof *guest_info->node_mem); 1128 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1129 sizeof *guest_info->node_cpu); 1130 1131 for (i = 0; i < max_cpus; i++) { 1132 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1133 assert(apic_id < guest_info->apic_id_limit); 1134 for (j = 0; j < nb_numa_nodes; j++) { 1135 if (test_bit(i, node_cpumask[j])) { 1136 guest_info->node_cpu[apic_id] = j; 1137 break; 1138 } 1139 } 1140 } 1141 1142 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1143 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1144 return guest_info; 1145 } 1146 1147 /* setup pci memory address space mapping into system address space */ 1148 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1149 MemoryRegion *pci_address_space) 1150 { 1151 /* Set to lower priority than RAM */ 1152 memory_region_add_subregion_overlap(system_memory, 0x0, 1153 pci_address_space, -1); 1154 } 1155 1156 void pc_acpi_init(const char *default_dsdt) 1157 { 1158 char *filename; 1159 1160 if (acpi_tables != NULL) { 1161 /* manually set via -acpitable, leave it alone */ 1162 return; 1163 } 1164 1165 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1166 if (filename == NULL) { 1167 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1168 } else { 1169 char *arg; 1170 QemuOpts *opts; 1171 Error *err = NULL; 1172 1173 arg = g_strdup_printf("file=%s", filename); 1174 1175 /* creates a deep copy of "arg" */ 1176 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1177 g_assert(opts != NULL); 1178 1179 acpi_table_add_builtin(opts, &err); 1180 if (err) { 1181 error_report("WARNING: failed to load %s: %s", filename, 1182 error_get_pretty(err)); 1183 error_free(err); 1184 } 1185 g_free(arg); 1186 g_free(filename); 1187 } 1188 } 1189 1190 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 1191 const char *kernel_filename, 1192 const char *kernel_cmdline, 1193 const char *initrd_filename, 1194 ram_addr_t below_4g_mem_size, 1195 ram_addr_t above_4g_mem_size, 1196 MemoryRegion *rom_memory, 1197 MemoryRegion **ram_memory, 1198 PcGuestInfo *guest_info) 1199 { 1200 int linux_boot, i; 1201 MemoryRegion *ram, *option_rom_mr; 1202 MemoryRegion *ram_below_4g, *ram_above_4g; 1203 FWCfgState *fw_cfg; 1204 1205 linux_boot = (kernel_filename != NULL); 1206 1207 /* Allocate RAM. We allocate it as a single memory region and use 1208 * aliases to address portions of it, mostly for backwards compatibility 1209 * with older qemus that used qemu_ram_alloc(). 1210 */ 1211 ram = g_malloc(sizeof(*ram)); 1212 memory_region_init_ram(ram, NULL, "pc.ram", 1213 below_4g_mem_size + above_4g_mem_size); 1214 vmstate_register_ram_global(ram); 1215 *ram_memory = ram; 1216 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1217 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1218 0, below_4g_mem_size); 1219 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1220 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1221 if (above_4g_mem_size > 0) { 1222 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1223 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1224 below_4g_mem_size, above_4g_mem_size); 1225 memory_region_add_subregion(system_memory, 0x100000000ULL, 1226 ram_above_4g); 1227 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1228 } 1229 1230 1231 /* Initialize PC system firmware */ 1232 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1233 1234 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1235 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); 1236 vmstate_register_ram_global(option_rom_mr); 1237 memory_region_add_subregion_overlap(rom_memory, 1238 PC_ROM_MIN_VGA, 1239 option_rom_mr, 1240 1); 1241 1242 fw_cfg = bochs_bios_init(); 1243 rom_set_fw(fw_cfg); 1244 1245 if (linux_boot) { 1246 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 1247 } 1248 1249 for (i = 0; i < nb_option_roms; i++) { 1250 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1251 } 1252 guest_info->fw_cfg = fw_cfg; 1253 return fw_cfg; 1254 } 1255 1256 qemu_irq *pc_allocate_cpu_irq(void) 1257 { 1258 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1259 } 1260 1261 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1262 { 1263 DeviceState *dev = NULL; 1264 1265 if (pci_bus) { 1266 PCIDevice *pcidev = pci_vga_init(pci_bus); 1267 dev = pcidev ? &pcidev->qdev : NULL; 1268 } else if (isa_bus) { 1269 ISADevice *isadev = isa_vga_init(isa_bus); 1270 dev = isadev ? DEVICE(isadev) : NULL; 1271 } 1272 return dev; 1273 } 1274 1275 static void cpu_request_exit(void *opaque, int irq, int level) 1276 { 1277 CPUState *cpu = current_cpu; 1278 1279 if (cpu && level) { 1280 cpu_exit(cpu); 1281 } 1282 } 1283 1284 static const MemoryRegionOps ioport80_io_ops = { 1285 .write = ioport80_write, 1286 .read = ioport80_read, 1287 .endianness = DEVICE_NATIVE_ENDIAN, 1288 .impl = { 1289 .min_access_size = 1, 1290 .max_access_size = 1, 1291 }, 1292 }; 1293 1294 static const MemoryRegionOps ioportF0_io_ops = { 1295 .write = ioportF0_write, 1296 .read = ioportF0_read, 1297 .endianness = DEVICE_NATIVE_ENDIAN, 1298 .impl = { 1299 .min_access_size = 1, 1300 .max_access_size = 1, 1301 }, 1302 }; 1303 1304 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1305 ISADevice **rtc_state, 1306 ISADevice **floppy, 1307 bool no_vmport, 1308 uint32 hpet_irqs) 1309 { 1310 int i; 1311 DriveInfo *fd[MAX_FD]; 1312 DeviceState *hpet = NULL; 1313 int pit_isa_irq = 0; 1314 qemu_irq pit_alt_irq = NULL; 1315 qemu_irq rtc_irq = NULL; 1316 qemu_irq *a20_line; 1317 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1318 qemu_irq *cpu_exit_irq; 1319 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1320 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1321 1322 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1323 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1324 1325 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1326 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1327 1328 /* 1329 * Check if an HPET shall be created. 1330 * 1331 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1332 * when the HPET wants to take over. Thus we have to disable the latter. 1333 */ 1334 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1335 /* In order to set property, here not using sysbus_try_create_simple */ 1336 hpet = qdev_try_create(NULL, TYPE_HPET); 1337 if (hpet) { 1338 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1339 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1340 * IRQ8 and IRQ2. 1341 */ 1342 uint8_t compat = object_property_get_int(OBJECT(hpet), 1343 HPET_INTCAP, NULL); 1344 if (!compat) { 1345 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1346 } 1347 qdev_init_nofail(hpet); 1348 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1349 1350 for (i = 0; i < GSI_NUM_PINS; i++) { 1351 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1352 } 1353 pit_isa_irq = -1; 1354 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1355 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1356 } 1357 } 1358 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1359 1360 qemu_register_boot_set(pc_boot_set, *rtc_state); 1361 1362 if (!xen_enabled()) { 1363 if (kvm_irqchip_in_kernel()) { 1364 pit = kvm_pit_init(isa_bus, 0x40); 1365 } else { 1366 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1367 } 1368 if (hpet) { 1369 /* connect PIT to output control line of the HPET */ 1370 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1371 } 1372 pcspk_init(isa_bus, pit); 1373 } 1374 1375 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1376 if (serial_hds[i]) { 1377 serial_isa_init(isa_bus, i, serial_hds[i]); 1378 } 1379 } 1380 1381 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1382 if (parallel_hds[i]) { 1383 parallel_init(isa_bus, i, parallel_hds[i]); 1384 } 1385 } 1386 1387 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1388 i8042 = isa_create_simple(isa_bus, "i8042"); 1389 i8042_setup_a20_line(i8042, &a20_line[0]); 1390 if (!no_vmport) { 1391 vmport_init(isa_bus); 1392 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1393 } else { 1394 vmmouse = NULL; 1395 } 1396 if (vmmouse) { 1397 DeviceState *dev = DEVICE(vmmouse); 1398 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1399 qdev_init_nofail(dev); 1400 } 1401 port92 = isa_create_simple(isa_bus, "port92"); 1402 port92_init(port92, &a20_line[1]); 1403 1404 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1405 DMA_init(0, cpu_exit_irq); 1406 1407 for(i = 0; i < MAX_FD; i++) { 1408 fd[i] = drive_get(IF_FLOPPY, 0, i); 1409 } 1410 *floppy = fdctrl_init_isa(isa_bus, fd); 1411 } 1412 1413 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1414 { 1415 int i; 1416 1417 for (i = 0; i < nb_nics; i++) { 1418 NICInfo *nd = &nd_table[i]; 1419 1420 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1421 pc_init_ne2k_isa(isa_bus, nd); 1422 } else { 1423 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1424 } 1425 } 1426 } 1427 1428 void pc_pci_device_init(PCIBus *pci_bus) 1429 { 1430 int max_bus; 1431 int bus; 1432 1433 max_bus = drive_get_max_bus(IF_SCSI); 1434 for (bus = 0; bus <= max_bus; bus++) { 1435 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1436 } 1437 } 1438 1439 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1440 { 1441 DeviceState *dev; 1442 SysBusDevice *d; 1443 unsigned int i; 1444 1445 if (kvm_irqchip_in_kernel()) { 1446 dev = qdev_create(NULL, "kvm-ioapic"); 1447 } else { 1448 dev = qdev_create(NULL, "ioapic"); 1449 } 1450 if (parent_name) { 1451 object_property_add_child(object_resolve_path(parent_name, NULL), 1452 "ioapic", OBJECT(dev), NULL); 1453 } 1454 qdev_init_nofail(dev); 1455 d = SYS_BUS_DEVICE(dev); 1456 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1457 1458 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1459 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1460 } 1461 } 1462