xref: /openbmc/qemu/hw/i386/pc.c (revision 2daea9c16ffe61377b6e5426d9c52014bf538df3)
1 /*
2  * QEMU PC System Emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 #include "hw/hw.h"
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/i386/topology.h"
29 #include "sysemu/cpus.h"
30 #include "hw/block/fdc.h"
31 #include "hw/ide.h"
32 #include "hw/pci/pci.h"
33 #include "monitor/monitor.h"
34 #include "hw/nvram/fw_cfg.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/smbios.h"
37 #include "hw/loader.h"
38 #include "elf.h"
39 #include "multiboot.h"
40 #include "hw/timer/mc146818rtc.h"
41 #include "hw/timer/i8254.h"
42 #include "hw/audio/pcspk.h"
43 #include "hw/pci/msi.h"
44 #include "hw/sysbus.h"
45 #include "sysemu/sysemu.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/kvm.h"
48 #include "sysemu/qtest.h"
49 #include "kvm_i386.h"
50 #include "hw/xen/xen.h"
51 #include "sysemu/block-backend.h"
52 #include "hw/block/block.h"
53 #include "ui/qemu-spice.h"
54 #include "exec/memory.h"
55 #include "exec/address-spaces.h"
56 #include "sysemu/arch_init.h"
57 #include "qemu/bitmap.h"
58 #include "qemu/config-file.h"
59 #include "hw/acpi/acpi.h"
60 #include "hw/acpi/cpu_hotplug.h"
61 #include "hw/cpu/icc_bus.h"
62 #include "hw/boards.h"
63 #include "hw/pci/pci_host.h"
64 #include "acpi-build.h"
65 #include "hw/mem/pc-dimm.h"
66 #include "trace.h"
67 #include "qapi/visitor.h"
68 #include "qapi-visit.h"
69 
70 /* debug PC/ISA interrupts */
71 //#define DEBUG_IRQ
72 
73 #ifdef DEBUG_IRQ
74 #define DPRINTF(fmt, ...)                                       \
75     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
76 #else
77 #define DPRINTF(fmt, ...)
78 #endif
79 
80 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables
81  * (128K) and other BIOS datastructures (less than 4K reported to be used at
82  * the moment, 32K should be enough for a while).  */
83 static unsigned acpi_data_size = 0x20000 + 0x8000;
84 void pc_set_legacy_acpi_data_size(void)
85 {
86     acpi_data_size = 0x10000;
87 }
88 
89 #define BIOS_CFG_IOPORT 0x510
90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
95 
96 #define E820_NR_ENTRIES		16
97 
98 struct e820_entry {
99     uint64_t address;
100     uint64_t length;
101     uint32_t type;
102 } QEMU_PACKED __attribute((__aligned__(4)));
103 
104 struct e820_table {
105     uint32_t count;
106     struct e820_entry entry[E820_NR_ENTRIES];
107 } QEMU_PACKED __attribute((__aligned__(4)));
108 
109 static struct e820_table e820_reserve;
110 static struct e820_entry *e820_table;
111 static unsigned e820_entries;
112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
113 
114 void gsi_handler(void *opaque, int n, int level)
115 {
116     GSIState *s = opaque;
117 
118     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
119     if (n < ISA_NUM_IRQS) {
120         qemu_set_irq(s->i8259_irq[n], level);
121     }
122     qemu_set_irq(s->ioapic_irq[n], level);
123 }
124 
125 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
126                            unsigned size)
127 {
128 }
129 
130 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
131 {
132     return 0xffffffffffffffffULL;
133 }
134 
135 /* MSDOS compatibility mode FPU exception support */
136 static qemu_irq ferr_irq;
137 
138 void pc_register_ferr_irq(qemu_irq irq)
139 {
140     ferr_irq = irq;
141 }
142 
143 /* XXX: add IGNNE support */
144 void cpu_set_ferr(CPUX86State *s)
145 {
146     qemu_irq_raise(ferr_irq);
147 }
148 
149 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
150                            unsigned size)
151 {
152     qemu_irq_lower(ferr_irq);
153 }
154 
155 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
156 {
157     return 0xffffffffffffffffULL;
158 }
159 
160 /* TSC handling */
161 uint64_t cpu_get_tsc(CPUX86State *env)
162 {
163     return cpu_get_ticks();
164 }
165 
166 /* SMM support */
167 
168 static cpu_set_smm_t smm_set;
169 static void *smm_arg;
170 
171 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
172 {
173     assert(smm_set == NULL);
174     assert(smm_arg == NULL);
175     smm_set = callback;
176     smm_arg = arg;
177 }
178 
179 void cpu_smm_update(CPUX86State *env)
180 {
181     if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
182         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
183     }
184 }
185 
186 
187 /* IRQ handling */
188 int cpu_get_pic_interrupt(CPUX86State *env)
189 {
190     X86CPU *cpu = x86_env_get_cpu(env);
191     int intno;
192 
193     intno = apic_get_interrupt(cpu->apic_state);
194     if (intno >= 0) {
195         return intno;
196     }
197     /* read the irq from the PIC */
198     if (!apic_accept_pic_intr(cpu->apic_state)) {
199         return -1;
200     }
201 
202     intno = pic_read_irq(isa_pic);
203     return intno;
204 }
205 
206 static void pic_irq_request(void *opaque, int irq, int level)
207 {
208     CPUState *cs = first_cpu;
209     X86CPU *cpu = X86_CPU(cs);
210 
211     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
212     if (cpu->apic_state) {
213         CPU_FOREACH(cs) {
214             cpu = X86_CPU(cs);
215             if (apic_accept_pic_intr(cpu->apic_state)) {
216                 apic_deliver_pic_intr(cpu->apic_state, level);
217             }
218         }
219     } else {
220         if (level) {
221             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
222         } else {
223             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
224         }
225     }
226 }
227 
228 /* PC cmos mappings */
229 
230 #define REG_EQUIPMENT_BYTE          0x14
231 
232 static int cmos_get_fd_drive_type(FDriveType fd0)
233 {
234     int val;
235 
236     switch (fd0) {
237     case FDRIVE_DRV_144:
238         /* 1.44 Mb 3"5 drive */
239         val = 4;
240         break;
241     case FDRIVE_DRV_288:
242         /* 2.88 Mb 3"5 drive */
243         val = 5;
244         break;
245     case FDRIVE_DRV_120:
246         /* 1.2 Mb 5"5 drive */
247         val = 2;
248         break;
249     case FDRIVE_DRV_NONE:
250     default:
251         val = 0;
252         break;
253     }
254     return val;
255 }
256 
257 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
258                          int16_t cylinders, int8_t heads, int8_t sectors)
259 {
260     rtc_set_memory(s, type_ofs, 47);
261     rtc_set_memory(s, info_ofs, cylinders);
262     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
263     rtc_set_memory(s, info_ofs + 2, heads);
264     rtc_set_memory(s, info_ofs + 3, 0xff);
265     rtc_set_memory(s, info_ofs + 4, 0xff);
266     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
267     rtc_set_memory(s, info_ofs + 6, cylinders);
268     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
269     rtc_set_memory(s, info_ofs + 8, sectors);
270 }
271 
272 /* convert boot_device letter to something recognizable by the bios */
273 static int boot_device2nibble(char boot_device)
274 {
275     switch(boot_device) {
276     case 'a':
277     case 'b':
278         return 0x01; /* floppy boot */
279     case 'c':
280         return 0x02; /* hard drive boot */
281     case 'd':
282         return 0x03; /* CD-ROM boot */
283     case 'n':
284         return 0x04; /* Network boot */
285     }
286     return 0;
287 }
288 
289 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
290 {
291 #define PC_MAX_BOOT_DEVICES 3
292     int nbds, bds[3] = { 0, };
293     int i;
294 
295     nbds = strlen(boot_device);
296     if (nbds > PC_MAX_BOOT_DEVICES) {
297         error_setg(errp, "Too many boot devices for PC");
298         return;
299     }
300     for (i = 0; i < nbds; i++) {
301         bds[i] = boot_device2nibble(boot_device[i]);
302         if (bds[i] == 0) {
303             error_setg(errp, "Invalid boot device for PC: '%c'",
304                        boot_device[i]);
305             return;
306         }
307     }
308     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
309     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
310 }
311 
312 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
313 {
314     set_boot_dev(opaque, boot_device, errp);
315 }
316 
317 typedef struct pc_cmos_init_late_arg {
318     ISADevice *rtc_state;
319     BusState *idebus[2];
320 } pc_cmos_init_late_arg;
321 
322 static void pc_cmos_init_late(void *opaque)
323 {
324     pc_cmos_init_late_arg *arg = opaque;
325     ISADevice *s = arg->rtc_state;
326     int16_t cylinders;
327     int8_t heads, sectors;
328     int val;
329     int i, trans;
330 
331     val = 0;
332     if (ide_get_geometry(arg->idebus[0], 0,
333                          &cylinders, &heads, &sectors) >= 0) {
334         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
335         val |= 0xf0;
336     }
337     if (ide_get_geometry(arg->idebus[0], 1,
338                          &cylinders, &heads, &sectors) >= 0) {
339         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
340         val |= 0x0f;
341     }
342     rtc_set_memory(s, 0x12, val);
343 
344     val = 0;
345     for (i = 0; i < 4; i++) {
346         /* NOTE: ide_get_geometry() returns the physical
347            geometry.  It is always such that: 1 <= sects <= 63, 1
348            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
349            geometry can be different if a translation is done. */
350         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
351                              &cylinders, &heads, &sectors) >= 0) {
352             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
353             assert((trans & ~3) == 0);
354             val |= trans << (i * 2);
355         }
356     }
357     rtc_set_memory(s, 0x39, val);
358 
359     qemu_unregister_reset(pc_cmos_init_late, opaque);
360 }
361 
362 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
363                   const char *boot_device, MachineState *machine,
364                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
365                   ISADevice *s)
366 {
367     int val, nb, i;
368     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
369     static pc_cmos_init_late_arg arg;
370     PCMachineState *pc_machine = PC_MACHINE(machine);
371     Error *local_err = NULL;
372 
373     /* various important CMOS locations needed by PC/Bochs bios */
374 
375     /* memory size */
376     /* base memory (first MiB) */
377     val = MIN(ram_size / 1024, 640);
378     rtc_set_memory(s, 0x15, val);
379     rtc_set_memory(s, 0x16, val >> 8);
380     /* extended memory (next 64MiB) */
381     if (ram_size > 1024 * 1024) {
382         val = (ram_size - 1024 * 1024) / 1024;
383     } else {
384         val = 0;
385     }
386     if (val > 65535)
387         val = 65535;
388     rtc_set_memory(s, 0x17, val);
389     rtc_set_memory(s, 0x18, val >> 8);
390     rtc_set_memory(s, 0x30, val);
391     rtc_set_memory(s, 0x31, val >> 8);
392     /* memory between 16MiB and 4GiB */
393     if (ram_size > 16 * 1024 * 1024) {
394         val = (ram_size - 16 * 1024 * 1024) / 65536;
395     } else {
396         val = 0;
397     }
398     if (val > 65535)
399         val = 65535;
400     rtc_set_memory(s, 0x34, val);
401     rtc_set_memory(s, 0x35, val >> 8);
402     /* memory above 4GiB */
403     val = above_4g_mem_size / 65536;
404     rtc_set_memory(s, 0x5b, val);
405     rtc_set_memory(s, 0x5c, val >> 8);
406     rtc_set_memory(s, 0x5d, val >> 16);
407 
408     /* set the number of CPU */
409     rtc_set_memory(s, 0x5f, smp_cpus - 1);
410 
411     object_property_add_link(OBJECT(machine), "rtc_state",
412                              TYPE_ISA_DEVICE,
413                              (Object **)&pc_machine->rtc,
414                              object_property_allow_set_link,
415                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
416     object_property_set_link(OBJECT(machine), OBJECT(s),
417                              "rtc_state", &error_abort);
418 
419     set_boot_dev(s, boot_device, &local_err);
420     if (local_err) {
421         error_report_err(local_err);
422         exit(1);
423     }
424 
425     /* floppy type */
426     if (floppy) {
427         for (i = 0; i < 2; i++) {
428             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
429         }
430     }
431     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
432         cmos_get_fd_drive_type(fd_type[1]);
433     rtc_set_memory(s, 0x10, val);
434 
435     val = 0;
436     nb = 0;
437     if (fd_type[0] < FDRIVE_DRV_NONE) {
438         nb++;
439     }
440     if (fd_type[1] < FDRIVE_DRV_NONE) {
441         nb++;
442     }
443     switch (nb) {
444     case 0:
445         break;
446     case 1:
447         val |= 0x01; /* 1 drive, ready for boot */
448         break;
449     case 2:
450         val |= 0x41; /* 2 drives, ready for boot */
451         break;
452     }
453     val |= 0x02; /* FPU is there */
454     val |= 0x04; /* PS/2 mouse installed */
455     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
456 
457     /* hard drives */
458     arg.rtc_state = s;
459     arg.idebus[0] = idebus0;
460     arg.idebus[1] = idebus1;
461     qemu_register_reset(pc_cmos_init_late, &arg);
462 }
463 
464 #define TYPE_PORT92 "port92"
465 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
466 
467 /* port 92 stuff: could be split off */
468 typedef struct Port92State {
469     ISADevice parent_obj;
470 
471     MemoryRegion io;
472     uint8_t outport;
473     qemu_irq *a20_out;
474 } Port92State;
475 
476 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
477                          unsigned size)
478 {
479     Port92State *s = opaque;
480     int oldval = s->outport;
481 
482     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
483     s->outport = val;
484     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
485     if ((val & 1) && !(oldval & 1)) {
486         qemu_system_reset_request();
487     }
488 }
489 
490 static uint64_t port92_read(void *opaque, hwaddr addr,
491                             unsigned size)
492 {
493     Port92State *s = opaque;
494     uint32_t ret;
495 
496     ret = s->outport;
497     DPRINTF("port92: read 0x%02x\n", ret);
498     return ret;
499 }
500 
501 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
502 {
503     Port92State *s = PORT92(dev);
504 
505     s->a20_out = a20_out;
506 }
507 
508 static const VMStateDescription vmstate_port92_isa = {
509     .name = "port92",
510     .version_id = 1,
511     .minimum_version_id = 1,
512     .fields = (VMStateField[]) {
513         VMSTATE_UINT8(outport, Port92State),
514         VMSTATE_END_OF_LIST()
515     }
516 };
517 
518 static void port92_reset(DeviceState *d)
519 {
520     Port92State *s = PORT92(d);
521 
522     s->outport &= ~1;
523 }
524 
525 static const MemoryRegionOps port92_ops = {
526     .read = port92_read,
527     .write = port92_write,
528     .impl = {
529         .min_access_size = 1,
530         .max_access_size = 1,
531     },
532     .endianness = DEVICE_LITTLE_ENDIAN,
533 };
534 
535 static void port92_initfn(Object *obj)
536 {
537     Port92State *s = PORT92(obj);
538 
539     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
540 
541     s->outport = 0;
542 }
543 
544 static void port92_realizefn(DeviceState *dev, Error **errp)
545 {
546     ISADevice *isadev = ISA_DEVICE(dev);
547     Port92State *s = PORT92(dev);
548 
549     isa_register_ioport(isadev, &s->io, 0x92);
550 }
551 
552 static void port92_class_initfn(ObjectClass *klass, void *data)
553 {
554     DeviceClass *dc = DEVICE_CLASS(klass);
555 
556     dc->realize = port92_realizefn;
557     dc->reset = port92_reset;
558     dc->vmsd = &vmstate_port92_isa;
559     /*
560      * Reason: unlike ordinary ISA devices, this one needs additional
561      * wiring: its A20 output line needs to be wired up by
562      * port92_init().
563      */
564     dc->cannot_instantiate_with_device_add_yet = true;
565 }
566 
567 static const TypeInfo port92_info = {
568     .name          = TYPE_PORT92,
569     .parent        = TYPE_ISA_DEVICE,
570     .instance_size = sizeof(Port92State),
571     .instance_init = port92_initfn,
572     .class_init    = port92_class_initfn,
573 };
574 
575 static void port92_register_types(void)
576 {
577     type_register_static(&port92_info);
578 }
579 
580 type_init(port92_register_types)
581 
582 static void handle_a20_line_change(void *opaque, int irq, int level)
583 {
584     X86CPU *cpu = opaque;
585 
586     /* XXX: send to all CPUs ? */
587     /* XXX: add logic to handle multiple A20 line sources */
588     x86_cpu_set_a20(cpu, level);
589 }
590 
591 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
592 {
593     int index = le32_to_cpu(e820_reserve.count);
594     struct e820_entry *entry;
595 
596     if (type != E820_RAM) {
597         /* old FW_CFG_E820_TABLE entry -- reservations only */
598         if (index >= E820_NR_ENTRIES) {
599             return -EBUSY;
600         }
601         entry = &e820_reserve.entry[index++];
602 
603         entry->address = cpu_to_le64(address);
604         entry->length = cpu_to_le64(length);
605         entry->type = cpu_to_le32(type);
606 
607         e820_reserve.count = cpu_to_le32(index);
608     }
609 
610     /* new "etc/e820" file -- include ram too */
611     e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
612     e820_table[e820_entries].address = cpu_to_le64(address);
613     e820_table[e820_entries].length = cpu_to_le64(length);
614     e820_table[e820_entries].type = cpu_to_le32(type);
615     e820_entries++;
616 
617     return e820_entries;
618 }
619 
620 int e820_get_num_entries(void)
621 {
622     return e820_entries;
623 }
624 
625 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
626 {
627     if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
628         *address = le64_to_cpu(e820_table[idx].address);
629         *length = le64_to_cpu(e820_table[idx].length);
630         return true;
631     }
632     return false;
633 }
634 
635 /* Enables contiguous-apic-ID mode, for compatibility */
636 static bool compat_apic_id_mode;
637 
638 void enable_compat_apic_id_mode(void)
639 {
640     compat_apic_id_mode = true;
641 }
642 
643 /* Calculates initial APIC ID for a specific CPU index
644  *
645  * Currently we need to be able to calculate the APIC ID from the CPU index
646  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
647  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
648  * all CPUs up to max_cpus.
649  */
650 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
651 {
652     uint32_t correct_id;
653     static bool warned;
654 
655     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
656     if (compat_apic_id_mode) {
657         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
658             error_report("APIC IDs set in compatibility mode, "
659                          "CPU topology won't match the configuration");
660             warned = true;
661         }
662         return cpu_index;
663     } else {
664         return correct_id;
665     }
666 }
667 
668 /* Calculates the limit to CPU APIC ID values
669  *
670  * This function returns the limit for the APIC ID value, so that all
671  * CPU APIC IDs are < pc_apic_id_limit().
672  *
673  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
674  */
675 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
676 {
677     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
678 }
679 
680 static FWCfgState *bochs_bios_init(void)
681 {
682     FWCfgState *fw_cfg;
683     uint8_t *smbios_tables, *smbios_anchor;
684     size_t smbios_tables_len, smbios_anchor_len;
685     uint64_t *numa_fw_cfg;
686     int i, j;
687     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
688 
689     fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
690     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
691      *
692      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
693      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
694      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
695      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
696      * may see".
697      *
698      * So, this means we must not use max_cpus, here, but the maximum possible
699      * APIC ID value, plus one.
700      *
701      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
702      *     the APIC ID, not the "CPU index"
703      */
704     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
705     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
706     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
707                      acpi_tables, acpi_tables_len);
708     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
709 
710     smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
711     if (smbios_tables) {
712         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
713                          smbios_tables, smbios_tables_len);
714     }
715 
716     smbios_get_tables(&smbios_tables, &smbios_tables_len,
717                       &smbios_anchor, &smbios_anchor_len);
718     if (smbios_anchor) {
719         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
720                         smbios_tables, smbios_tables_len);
721         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
722                         smbios_anchor, smbios_anchor_len);
723     }
724 
725     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
726                      &e820_reserve, sizeof(e820_reserve));
727     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
728                     sizeof(struct e820_entry) * e820_entries);
729 
730     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
731     /* allocate memory for the NUMA channel: one (64bit) word for the number
732      * of nodes, one word for each VCPU->node and one word for each node to
733      * hold the amount of memory.
734      */
735     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
736     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
737     for (i = 0; i < max_cpus; i++) {
738         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
739         assert(apic_id < apic_id_limit);
740         for (j = 0; j < nb_numa_nodes; j++) {
741             if (test_bit(i, numa_info[j].node_cpu)) {
742                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
743                 break;
744             }
745         }
746     }
747     for (i = 0; i < nb_numa_nodes; i++) {
748         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem);
749     }
750     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
751                      (1 + apic_id_limit + nb_numa_nodes) *
752                      sizeof(*numa_fw_cfg));
753 
754     return fw_cfg;
755 }
756 
757 static long get_file_size(FILE *f)
758 {
759     long where, size;
760 
761     /* XXX: on Unix systems, using fstat() probably makes more sense */
762 
763     where = ftell(f);
764     fseek(f, 0, SEEK_END);
765     size = ftell(f);
766     fseek(f, where, SEEK_SET);
767 
768     return size;
769 }
770 
771 static void load_linux(FWCfgState *fw_cfg,
772                        const char *kernel_filename,
773                        const char *initrd_filename,
774                        const char *kernel_cmdline,
775                        hwaddr max_ram_size)
776 {
777     uint16_t protocol;
778     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
779     uint32_t initrd_max;
780     uint8_t header[8192], *setup, *kernel, *initrd_data;
781     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
782     FILE *f;
783     char *vmode;
784 
785     /* Align to 16 bytes as a paranoia measure */
786     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
787 
788     /* load the kernel header */
789     f = fopen(kernel_filename, "rb");
790     if (!f || !(kernel_size = get_file_size(f)) ||
791         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
792         MIN(ARRAY_SIZE(header), kernel_size)) {
793         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
794                 kernel_filename, strerror(errno));
795         exit(1);
796     }
797 
798     /* kernel protocol version */
799 #if 0
800     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
801 #endif
802     if (ldl_p(header+0x202) == 0x53726448) {
803         protocol = lduw_p(header+0x206);
804     } else {
805         /* This looks like a multiboot kernel. If it is, let's stop
806            treating it like a Linux kernel. */
807         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
808                            kernel_cmdline, kernel_size, header)) {
809             return;
810         }
811         protocol = 0;
812     }
813 
814     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
815         /* Low kernel */
816         real_addr    = 0x90000;
817         cmdline_addr = 0x9a000 - cmdline_size;
818         prot_addr    = 0x10000;
819     } else if (protocol < 0x202) {
820         /* High but ancient kernel */
821         real_addr    = 0x90000;
822         cmdline_addr = 0x9a000 - cmdline_size;
823         prot_addr    = 0x100000;
824     } else {
825         /* High and recent kernel */
826         real_addr    = 0x10000;
827         cmdline_addr = 0x20000;
828         prot_addr    = 0x100000;
829     }
830 
831 #if 0
832     fprintf(stderr,
833             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
834             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
835             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
836             real_addr,
837             cmdline_addr,
838             prot_addr);
839 #endif
840 
841     /* highest address for loading the initrd */
842     if (protocol >= 0x203) {
843         initrd_max = ldl_p(header+0x22c);
844     } else {
845         initrd_max = 0x37ffffff;
846     }
847 
848     if (initrd_max >= max_ram_size - acpi_data_size) {
849         initrd_max = max_ram_size - acpi_data_size - 1;
850     }
851 
852     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
853     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
854     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
855 
856     if (protocol >= 0x202) {
857         stl_p(header+0x228, cmdline_addr);
858     } else {
859         stw_p(header+0x20, 0xA33F);
860         stw_p(header+0x22, cmdline_addr-real_addr);
861     }
862 
863     /* handle vga= parameter */
864     vmode = strstr(kernel_cmdline, "vga=");
865     if (vmode) {
866         unsigned int video_mode;
867         /* skip "vga=" */
868         vmode += 4;
869         if (!strncmp(vmode, "normal", 6)) {
870             video_mode = 0xffff;
871         } else if (!strncmp(vmode, "ext", 3)) {
872             video_mode = 0xfffe;
873         } else if (!strncmp(vmode, "ask", 3)) {
874             video_mode = 0xfffd;
875         } else {
876             video_mode = strtol(vmode, NULL, 0);
877         }
878         stw_p(header+0x1fa, video_mode);
879     }
880 
881     /* loader type */
882     /* High nybble = B reserved for QEMU; low nybble is revision number.
883        If this code is substantially changed, you may want to consider
884        incrementing the revision. */
885     if (protocol >= 0x200) {
886         header[0x210] = 0xB0;
887     }
888     /* heap */
889     if (protocol >= 0x201) {
890         header[0x211] |= 0x80;	/* CAN_USE_HEAP */
891         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
892     }
893 
894     /* load initrd */
895     if (initrd_filename) {
896         if (protocol < 0x200) {
897             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
898             exit(1);
899         }
900 
901         initrd_size = get_image_size(initrd_filename);
902         if (initrd_size < 0) {
903             fprintf(stderr, "qemu: error reading initrd %s: %s\n",
904                     initrd_filename, strerror(errno));
905             exit(1);
906         }
907 
908         initrd_addr = (initrd_max-initrd_size) & ~4095;
909 
910         initrd_data = g_malloc(initrd_size);
911         load_image(initrd_filename, initrd_data);
912 
913         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
914         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
915         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
916 
917         stl_p(header+0x218, initrd_addr);
918         stl_p(header+0x21c, initrd_size);
919     }
920 
921     /* load kernel and setup */
922     setup_size = header[0x1f1];
923     if (setup_size == 0) {
924         setup_size = 4;
925     }
926     setup_size = (setup_size+1)*512;
927     kernel_size -= setup_size;
928 
929     setup  = g_malloc(setup_size);
930     kernel = g_malloc(kernel_size);
931     fseek(f, 0, SEEK_SET);
932     if (fread(setup, 1, setup_size, f) != setup_size) {
933         fprintf(stderr, "fread() failed\n");
934         exit(1);
935     }
936     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
937         fprintf(stderr, "fread() failed\n");
938         exit(1);
939     }
940     fclose(f);
941     memcpy(setup, header, MIN(sizeof(header), setup_size));
942 
943     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
944     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
945     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
946 
947     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
948     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
949     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
950 
951     option_rom[nb_option_roms].name = "linuxboot.bin";
952     option_rom[nb_option_roms].bootindex = 0;
953     nb_option_roms++;
954 }
955 
956 #define NE2000_NB_MAX 6
957 
958 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
959                                               0x280, 0x380 };
960 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
961 
962 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
963 {
964     static int nb_ne2k = 0;
965 
966     if (nb_ne2k == NE2000_NB_MAX)
967         return;
968     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
969                     ne2000_irq[nb_ne2k], nd);
970     nb_ne2k++;
971 }
972 
973 DeviceState *cpu_get_current_apic(void)
974 {
975     if (current_cpu) {
976         X86CPU *cpu = X86_CPU(current_cpu);
977         return cpu->apic_state;
978     } else {
979         return NULL;
980     }
981 }
982 
983 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
984 {
985     X86CPU *cpu = opaque;
986 
987     if (level) {
988         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
989     }
990 }
991 
992 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
993                           DeviceState *icc_bridge, Error **errp)
994 {
995     X86CPU *cpu = NULL;
996     Error *local_err = NULL;
997 
998     if (icc_bridge == NULL) {
999         error_setg(&local_err, "Invalid icc-bridge value");
1000         goto out;
1001     }
1002 
1003     cpu = cpu_x86_create(cpu_model, &local_err);
1004     if (local_err != NULL) {
1005         goto out;
1006     }
1007 
1008     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1009 
1010     object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
1011     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
1012 
1013 out:
1014     if (local_err) {
1015         error_propagate(errp, local_err);
1016         object_unref(OBJECT(cpu));
1017         cpu = NULL;
1018     }
1019     return cpu;
1020 }
1021 
1022 static const char *current_cpu_model;
1023 
1024 void pc_hot_add_cpu(const int64_t id, Error **errp)
1025 {
1026     DeviceState *icc_bridge;
1027     X86CPU *cpu;
1028     int64_t apic_id = x86_cpu_apic_id_from_index(id);
1029     Error *local_err = NULL;
1030 
1031     if (id < 0) {
1032         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1033         return;
1034     }
1035 
1036     if (cpu_exists(apic_id)) {
1037         error_setg(errp, "Unable to add CPU: %" PRIi64
1038                    ", it already exists", id);
1039         return;
1040     }
1041 
1042     if (id >= max_cpus) {
1043         error_setg(errp, "Unable to add CPU: %" PRIi64
1044                    ", max allowed: %d", id, max_cpus - 1);
1045         return;
1046     }
1047 
1048     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1049         error_setg(errp, "Unable to add CPU: %" PRIi64
1050                    ", resulting APIC ID (%" PRIi64 ") is too large",
1051                    id, apic_id);
1052         return;
1053     }
1054 
1055     icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
1056                                                  TYPE_ICC_BRIDGE, NULL));
1057     cpu = pc_new_cpu(current_cpu_model, apic_id, icc_bridge, &local_err);
1058     if (local_err) {
1059         error_propagate(errp, local_err);
1060         return;
1061     }
1062     object_unref(OBJECT(cpu));
1063 }
1064 
1065 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
1066 {
1067     int i;
1068     X86CPU *cpu = NULL;
1069     Error *error = NULL;
1070     unsigned long apic_id_limit;
1071 
1072     /* init CPUs */
1073     if (cpu_model == NULL) {
1074 #ifdef TARGET_X86_64
1075         cpu_model = "qemu64";
1076 #else
1077         cpu_model = "qemu32";
1078 #endif
1079     }
1080     current_cpu_model = cpu_model;
1081 
1082     apic_id_limit = pc_apic_id_limit(max_cpus);
1083     if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1084         error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1085                      apic_id_limit - 1);
1086         exit(1);
1087     }
1088 
1089     for (i = 0; i < smp_cpus; i++) {
1090         cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
1091                          icc_bridge, &error);
1092         if (error) {
1093             error_report_err(error);
1094             exit(1);
1095         }
1096         object_unref(OBJECT(cpu));
1097     }
1098 
1099     /* map APIC MMIO area if CPU has APIC */
1100     if (cpu && cpu->apic_state) {
1101         /* XXX: what if the base changes? */
1102         sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1103                                 APIC_DEFAULT_ADDRESS, 0x1000);
1104     }
1105 
1106     /* tell smbios about cpuid version and features */
1107     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
1108 }
1109 
1110 /* pci-info ROM file. Little endian format */
1111 typedef struct PcRomPciInfo {
1112     uint64_t w32_min;
1113     uint64_t w32_max;
1114     uint64_t w64_min;
1115     uint64_t w64_max;
1116 } PcRomPciInfo;
1117 
1118 typedef struct PcGuestInfoState {
1119     PcGuestInfo info;
1120     Notifier machine_done;
1121 } PcGuestInfoState;
1122 
1123 static
1124 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1125 {
1126     PcGuestInfoState *guest_info_state = container_of(notifier,
1127                                                       PcGuestInfoState,
1128                                                       machine_done);
1129     acpi_setup(&guest_info_state->info);
1130 }
1131 
1132 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1133                                 ram_addr_t above_4g_mem_size)
1134 {
1135     PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1136     PcGuestInfo *guest_info = &guest_info_state->info;
1137     int i, j;
1138 
1139     guest_info->ram_size_below_4g = below_4g_mem_size;
1140     guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
1141     guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
1142     guest_info->apic_xrupt_override = kvm_allows_irq0_override();
1143     guest_info->numa_nodes = nb_numa_nodes;
1144     guest_info->node_mem = g_malloc0(guest_info->numa_nodes *
1145                                     sizeof *guest_info->node_mem);
1146     for (i = 0; i < nb_numa_nodes; i++) {
1147         guest_info->node_mem[i] = numa_info[i].node_mem;
1148     }
1149 
1150     guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
1151                                      sizeof *guest_info->node_cpu);
1152 
1153     for (i = 0; i < max_cpus; i++) {
1154         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1155         assert(apic_id < guest_info->apic_id_limit);
1156         for (j = 0; j < nb_numa_nodes; j++) {
1157             if (test_bit(i, numa_info[j].node_cpu)) {
1158                 guest_info->node_cpu[apic_id] = j;
1159                 break;
1160             }
1161         }
1162     }
1163 
1164     guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1165     qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1166     return guest_info;
1167 }
1168 
1169 /* setup pci memory address space mapping into system address space */
1170 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1171                             MemoryRegion *pci_address_space)
1172 {
1173     /* Set to lower priority than RAM */
1174     memory_region_add_subregion_overlap(system_memory, 0x0,
1175                                         pci_address_space, -1);
1176 }
1177 
1178 void pc_acpi_init(const char *default_dsdt)
1179 {
1180     char *filename;
1181 
1182     if (acpi_tables != NULL) {
1183         /* manually set via -acpitable, leave it alone */
1184         return;
1185     }
1186 
1187     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1188     if (filename == NULL) {
1189         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1190     } else {
1191         QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1192                                           &error_abort);
1193         Error *err = NULL;
1194 
1195         qemu_opt_set(opts, "file", filename, &error_abort);
1196 
1197         acpi_table_add_builtin(opts, &err);
1198         if (err) {
1199             error_report("WARNING: failed to load %s: %s", filename,
1200                          error_get_pretty(err));
1201             error_free(err);
1202         }
1203         g_free(filename);
1204     }
1205 }
1206 
1207 FWCfgState *xen_load_linux(const char *kernel_filename,
1208                            const char *kernel_cmdline,
1209                            const char *initrd_filename,
1210                            ram_addr_t below_4g_mem_size,
1211                            PcGuestInfo *guest_info)
1212 {
1213     int i;
1214     FWCfgState *fw_cfg;
1215 
1216     assert(kernel_filename != NULL);
1217 
1218     fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
1219     rom_set_fw(fw_cfg);
1220 
1221     load_linux(fw_cfg, kernel_filename, initrd_filename,
1222                kernel_cmdline, below_4g_mem_size);
1223     for (i = 0; i < nb_option_roms; i++) {
1224         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1225                !strcmp(option_rom[i].name, "multiboot.bin"));
1226         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1227     }
1228     guest_info->fw_cfg = fw_cfg;
1229     return fw_cfg;
1230 }
1231 
1232 FWCfgState *pc_memory_init(MachineState *machine,
1233                            MemoryRegion *system_memory,
1234                            ram_addr_t below_4g_mem_size,
1235                            ram_addr_t above_4g_mem_size,
1236                            MemoryRegion *rom_memory,
1237                            MemoryRegion **ram_memory,
1238                            PcGuestInfo *guest_info)
1239 {
1240     int linux_boot, i;
1241     MemoryRegion *ram, *option_rom_mr;
1242     MemoryRegion *ram_below_4g, *ram_above_4g;
1243     FWCfgState *fw_cfg;
1244     PCMachineState *pcms = PC_MACHINE(machine);
1245 
1246     assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size);
1247 
1248     linux_boot = (machine->kernel_filename != NULL);
1249 
1250     /* Allocate RAM.  We allocate it as a single memory region and use
1251      * aliases to address portions of it, mostly for backwards compatibility
1252      * with older qemus that used qemu_ram_alloc().
1253      */
1254     ram = g_malloc(sizeof(*ram));
1255     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1256                                          machine->ram_size);
1257     *ram_memory = ram;
1258     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1259     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1260                              0, below_4g_mem_size);
1261     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1262     e820_add_entry(0, below_4g_mem_size, E820_RAM);
1263     if (above_4g_mem_size > 0) {
1264         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1265         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1266                                  below_4g_mem_size, above_4g_mem_size);
1267         memory_region_add_subregion(system_memory, 0x100000000ULL,
1268                                     ram_above_4g);
1269         e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM);
1270     }
1271 
1272     if (!guest_info->has_reserved_memory &&
1273         (machine->ram_slots ||
1274          (machine->maxram_size > machine->ram_size))) {
1275         MachineClass *mc = MACHINE_GET_CLASS(machine);
1276 
1277         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1278                      mc->name);
1279         exit(EXIT_FAILURE);
1280     }
1281 
1282     /* initialize hotplug memory address space */
1283     if (guest_info->has_reserved_memory &&
1284         (machine->ram_size < machine->maxram_size)) {
1285         ram_addr_t hotplug_mem_size =
1286             machine->maxram_size - machine->ram_size;
1287 
1288         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1289             error_report("unsupported amount of memory slots: %"PRIu64,
1290                          machine->ram_slots);
1291             exit(EXIT_FAILURE);
1292         }
1293 
1294         if (QEMU_ALIGN_UP(machine->maxram_size,
1295                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1296             error_report("maximum memory size must by aligned to multiple of "
1297                          "%d bytes", TARGET_PAGE_SIZE);
1298             exit(EXIT_FAILURE);
1299         }
1300 
1301         pcms->hotplug_memory_base =
1302             ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30);
1303 
1304         if (pcms->enforce_aligned_dimm) {
1305             /* size hotplug region assuming 1G page max alignment per slot */
1306             hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
1307         }
1308 
1309         if ((pcms->hotplug_memory_base + hotplug_mem_size) <
1310             hotplug_mem_size) {
1311             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1312                          machine->maxram_size);
1313             exit(EXIT_FAILURE);
1314         }
1315 
1316         memory_region_init(&pcms->hotplug_memory, OBJECT(pcms),
1317                            "hotplug-memory", hotplug_mem_size);
1318         memory_region_add_subregion(system_memory, pcms->hotplug_memory_base,
1319                                     &pcms->hotplug_memory);
1320     }
1321 
1322     /* Initialize PC system firmware */
1323     pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1324 
1325     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1326     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1327                            &error_abort);
1328     vmstate_register_ram_global(option_rom_mr);
1329     memory_region_add_subregion_overlap(rom_memory,
1330                                         PC_ROM_MIN_VGA,
1331                                         option_rom_mr,
1332                                         1);
1333 
1334     fw_cfg = bochs_bios_init();
1335     rom_set_fw(fw_cfg);
1336 
1337     if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) {
1338         uint64_t *val = g_malloc(sizeof(*val));
1339         *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30));
1340         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1341     }
1342 
1343     if (linux_boot) {
1344         load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename,
1345                    machine->kernel_cmdline, below_4g_mem_size);
1346     }
1347 
1348     for (i = 0; i < nb_option_roms; i++) {
1349         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1350     }
1351     guest_info->fw_cfg = fw_cfg;
1352     return fw_cfg;
1353 }
1354 
1355 qemu_irq pc_allocate_cpu_irq(void)
1356 {
1357     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1358 }
1359 
1360 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1361 {
1362     DeviceState *dev = NULL;
1363 
1364     if (pci_bus) {
1365         PCIDevice *pcidev = pci_vga_init(pci_bus);
1366         dev = pcidev ? &pcidev->qdev : NULL;
1367     } else if (isa_bus) {
1368         ISADevice *isadev = isa_vga_init(isa_bus);
1369         dev = isadev ? DEVICE(isadev) : NULL;
1370     }
1371     return dev;
1372 }
1373 
1374 static void cpu_request_exit(void *opaque, int irq, int level)
1375 {
1376     CPUState *cpu = current_cpu;
1377 
1378     if (cpu && level) {
1379         cpu_exit(cpu);
1380     }
1381 }
1382 
1383 static const MemoryRegionOps ioport80_io_ops = {
1384     .write = ioport80_write,
1385     .read = ioport80_read,
1386     .endianness = DEVICE_NATIVE_ENDIAN,
1387     .impl = {
1388         .min_access_size = 1,
1389         .max_access_size = 1,
1390     },
1391 };
1392 
1393 static const MemoryRegionOps ioportF0_io_ops = {
1394     .write = ioportF0_write,
1395     .read = ioportF0_read,
1396     .endianness = DEVICE_NATIVE_ENDIAN,
1397     .impl = {
1398         .min_access_size = 1,
1399         .max_access_size = 1,
1400     },
1401 };
1402 
1403 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1404                           ISADevice **rtc_state,
1405                           bool create_fdctrl,
1406                           ISADevice **floppy,
1407                           bool no_vmport,
1408                           uint32 hpet_irqs)
1409 {
1410     int i;
1411     DriveInfo *fd[MAX_FD];
1412     DeviceState *hpet = NULL;
1413     int pit_isa_irq = 0;
1414     qemu_irq pit_alt_irq = NULL;
1415     qemu_irq rtc_irq = NULL;
1416     qemu_irq *a20_line;
1417     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1418     qemu_irq *cpu_exit_irq;
1419     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1420     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1421 
1422     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1423     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1424 
1425     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1426     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1427 
1428     /*
1429      * Check if an HPET shall be created.
1430      *
1431      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1432      * when the HPET wants to take over. Thus we have to disable the latter.
1433      */
1434     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1435         /* In order to set property, here not using sysbus_try_create_simple */
1436         hpet = qdev_try_create(NULL, TYPE_HPET);
1437         if (hpet) {
1438             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1439              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1440              * IRQ8 and IRQ2.
1441              */
1442             uint8_t compat = object_property_get_int(OBJECT(hpet),
1443                     HPET_INTCAP, NULL);
1444             if (!compat) {
1445                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1446             }
1447             qdev_init_nofail(hpet);
1448             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1449 
1450             for (i = 0; i < GSI_NUM_PINS; i++) {
1451                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1452             }
1453             pit_isa_irq = -1;
1454             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1455             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1456         }
1457     }
1458     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1459 
1460     qemu_register_boot_set(pc_boot_set, *rtc_state);
1461 
1462     if (!xen_enabled()) {
1463         if (kvm_irqchip_in_kernel()) {
1464             pit = kvm_pit_init(isa_bus, 0x40);
1465         } else {
1466             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1467         }
1468         if (hpet) {
1469             /* connect PIT to output control line of the HPET */
1470             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1471         }
1472         pcspk_init(isa_bus, pit);
1473     }
1474 
1475     serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
1476     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1477 
1478     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1479     i8042 = isa_create_simple(isa_bus, "i8042");
1480     i8042_setup_a20_line(i8042, &a20_line[0]);
1481     if (!no_vmport) {
1482         vmport_init(isa_bus);
1483         vmmouse = isa_try_create(isa_bus, "vmmouse");
1484     } else {
1485         vmmouse = NULL;
1486     }
1487     if (vmmouse) {
1488         DeviceState *dev = DEVICE(vmmouse);
1489         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1490         qdev_init_nofail(dev);
1491     }
1492     port92 = isa_create_simple(isa_bus, "port92");
1493     port92_init(port92, &a20_line[1]);
1494 
1495     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1496     DMA_init(0, cpu_exit_irq);
1497 
1498     for(i = 0; i < MAX_FD; i++) {
1499         fd[i] = drive_get(IF_FLOPPY, 0, i);
1500         create_fdctrl |= !!fd[i];
1501     }
1502     *floppy = create_fdctrl ? fdctrl_init_isa(isa_bus, fd) : NULL;
1503 }
1504 
1505 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1506 {
1507     int i;
1508 
1509     for (i = 0; i < nb_nics; i++) {
1510         NICInfo *nd = &nd_table[i];
1511 
1512         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1513             pc_init_ne2k_isa(isa_bus, nd);
1514         } else {
1515             pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1516         }
1517     }
1518 }
1519 
1520 void pc_pci_device_init(PCIBus *pci_bus)
1521 {
1522     int max_bus;
1523     int bus;
1524 
1525     max_bus = drive_get_max_bus(IF_SCSI);
1526     for (bus = 0; bus <= max_bus; bus++) {
1527         pci_create_simple(pci_bus, -1, "lsi53c895a");
1528     }
1529 }
1530 
1531 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1532 {
1533     DeviceState *dev;
1534     SysBusDevice *d;
1535     unsigned int i;
1536 
1537     if (kvm_irqchip_in_kernel()) {
1538         dev = qdev_create(NULL, "kvm-ioapic");
1539     } else {
1540         dev = qdev_create(NULL, "ioapic");
1541     }
1542     if (parent_name) {
1543         object_property_add_child(object_resolve_path(parent_name, NULL),
1544                                   "ioapic", OBJECT(dev), NULL);
1545     }
1546     qdev_init_nofail(dev);
1547     d = SYS_BUS_DEVICE(dev);
1548     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1549 
1550     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1551         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1552     }
1553 }
1554 
1555 static void pc_dimm_plug(HotplugHandler *hotplug_dev,
1556                          DeviceState *dev, Error **errp)
1557 {
1558     int slot;
1559     HotplugHandlerClass *hhc;
1560     Error *local_err = NULL;
1561     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1562     MachineState *machine = MACHINE(hotplug_dev);
1563     PCDIMMDevice *dimm = PC_DIMM(dev);
1564     PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1565     MemoryRegion *mr = ddc->get_memory_region(dimm);
1566     uint64_t existing_dimms_capacity = 0;
1567     uint64_t align = TARGET_PAGE_SIZE;
1568     uint64_t addr;
1569 
1570     addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
1571     if (local_err) {
1572         goto out;
1573     }
1574 
1575     if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) {
1576         align = memory_region_get_alignment(mr);
1577     }
1578 
1579     addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base,
1580                                  memory_region_size(&pcms->hotplug_memory),
1581                                  !addr ? NULL : &addr, align,
1582                                  memory_region_size(mr), &local_err);
1583     if (local_err) {
1584         goto out;
1585     }
1586 
1587     existing_dimms_capacity = pc_existing_dimms_capacity(&local_err);
1588     if (local_err) {
1589         goto out;
1590     }
1591 
1592     if (existing_dimms_capacity + memory_region_size(mr) >
1593         machine->maxram_size - machine->ram_size) {
1594         error_setg(&local_err, "not enough space, currently 0x%" PRIx64
1595                    " in use of total hot pluggable 0x" RAM_ADDR_FMT,
1596                    existing_dimms_capacity,
1597                    machine->maxram_size - machine->ram_size);
1598         goto out;
1599     }
1600 
1601     object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err);
1602     if (local_err) {
1603         goto out;
1604     }
1605     trace_mhp_pc_dimm_assigned_address(addr);
1606 
1607     slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err);
1608     if (local_err) {
1609         goto out;
1610     }
1611 
1612     slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot,
1613                                  machine->ram_slots, &local_err);
1614     if (local_err) {
1615         goto out;
1616     }
1617     object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err);
1618     if (local_err) {
1619         goto out;
1620     }
1621     trace_mhp_pc_dimm_assigned_slot(slot);
1622 
1623     if (!pcms->acpi_dev) {
1624         error_setg(&local_err,
1625                    "memory hotplug is not enabled: missing acpi device");
1626         goto out;
1627     }
1628 
1629     if (kvm_enabled() && !kvm_has_free_slot(machine)) {
1630         error_setg(&local_err, "hypervisor has no free memory slots left");
1631         goto out;
1632     }
1633 
1634     memory_region_add_subregion(&pcms->hotplug_memory,
1635                                 addr - pcms->hotplug_memory_base, mr);
1636     vmstate_register_ram(mr, dev);
1637 
1638     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1639     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1640 out:
1641     error_propagate(errp, local_err);
1642 }
1643 
1644 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev,
1645                                    DeviceState *dev, Error **errp)
1646 {
1647     HotplugHandlerClass *hhc;
1648     Error *local_err = NULL;
1649     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1650 
1651     if (!pcms->acpi_dev) {
1652         error_setg(&local_err,
1653                    "memory hotplug is not enabled: missing acpi device");
1654         goto out;
1655     }
1656 
1657     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1658     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1659 
1660 out:
1661     error_propagate(errp, local_err);
1662 }
1663 
1664 static void pc_dimm_unplug(HotplugHandler *hotplug_dev,
1665                            DeviceState *dev, Error **errp)
1666 {
1667     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1668     PCDIMMDevice *dimm = PC_DIMM(dev);
1669     PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
1670     MemoryRegion *mr = ddc->get_memory_region(dimm);
1671     HotplugHandlerClass *hhc;
1672     Error *local_err = NULL;
1673 
1674     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1675     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1676 
1677     if (local_err) {
1678         goto out;
1679     }
1680 
1681     memory_region_del_subregion(&pcms->hotplug_memory, mr);
1682     vmstate_unregister_ram(mr, dev);
1683 
1684     object_unparent(OBJECT(dev));
1685 
1686  out:
1687     error_propagate(errp, local_err);
1688 }
1689 
1690 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1691                         DeviceState *dev, Error **errp)
1692 {
1693     HotplugHandlerClass *hhc;
1694     Error *local_err = NULL;
1695     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1696 
1697     if (!dev->hotplugged) {
1698         goto out;
1699     }
1700 
1701     if (!pcms->acpi_dev) {
1702         error_setg(&local_err,
1703                    "cpu hotplug is not enabled: missing acpi device");
1704         goto out;
1705     }
1706 
1707     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1708     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1709     if (local_err) {
1710         goto out;
1711     }
1712 
1713     /* increment the number of CPUs */
1714     rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1);
1715 out:
1716     error_propagate(errp, local_err);
1717 }
1718 
1719 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1720                                       DeviceState *dev, Error **errp)
1721 {
1722     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1723         pc_dimm_plug(hotplug_dev, dev, errp);
1724     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1725         pc_cpu_plug(hotplug_dev, dev, errp);
1726     }
1727 }
1728 
1729 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1730                                                 DeviceState *dev, Error **errp)
1731 {
1732     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1733         pc_dimm_unplug_request(hotplug_dev, dev, errp);
1734     } else {
1735         error_setg(errp, "acpi: device unplug request for not supported device"
1736                    " type: %s", object_get_typename(OBJECT(dev)));
1737     }
1738 }
1739 
1740 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1741                                         DeviceState *dev, Error **errp)
1742 {
1743     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1744         pc_dimm_unplug(hotplug_dev, dev, errp);
1745     } else {
1746         error_setg(errp, "acpi: device unplug for not supported device"
1747                    " type: %s", object_get_typename(OBJECT(dev)));
1748     }
1749 }
1750 
1751 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
1752                                              DeviceState *dev)
1753 {
1754     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1755 
1756     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1757         object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1758         return HOTPLUG_HANDLER(machine);
1759     }
1760 
1761     return pcmc->get_hotplug_handler ?
1762         pcmc->get_hotplug_handler(machine, dev) : NULL;
1763 }
1764 
1765 static void
1766 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque,
1767                                           const char *name, Error **errp)
1768 {
1769     PCMachineState *pcms = PC_MACHINE(obj);
1770     int64_t value = memory_region_size(&pcms->hotplug_memory);
1771 
1772     visit_type_int(v, &value, name, errp);
1773 }
1774 
1775 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1776                                          void *opaque, const char *name,
1777                                          Error **errp)
1778 {
1779     PCMachineState *pcms = PC_MACHINE(obj);
1780     uint64_t value = pcms->max_ram_below_4g;
1781 
1782     visit_type_size(v, &value, name, errp);
1783 }
1784 
1785 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1786                                          void *opaque, const char *name,
1787                                          Error **errp)
1788 {
1789     PCMachineState *pcms = PC_MACHINE(obj);
1790     Error *error = NULL;
1791     uint64_t value;
1792 
1793     visit_type_size(v, &value, name, &error);
1794     if (error) {
1795         error_propagate(errp, error);
1796         return;
1797     }
1798     if (value > (1ULL << 32)) {
1799         error_set(&error, ERROR_CLASS_GENERIC_ERROR,
1800                   "Machine option 'max-ram-below-4g=%"PRIu64
1801                   "' expects size less than or equal to 4G", value);
1802         error_propagate(errp, error);
1803         return;
1804     }
1805 
1806     if (value < (1ULL << 20)) {
1807         error_report("Warning: small max_ram_below_4g(%"PRIu64
1808                      ") less than 1M.  BIOS may not work..",
1809                      value);
1810     }
1811 
1812     pcms->max_ram_below_4g = value;
1813 }
1814 
1815 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque,
1816                                   const char *name, Error **errp)
1817 {
1818     PCMachineState *pcms = PC_MACHINE(obj);
1819     OnOffAuto vmport = pcms->vmport;
1820 
1821     visit_type_OnOffAuto(v, &vmport, name, errp);
1822 }
1823 
1824 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque,
1825                                   const char *name, Error **errp)
1826 {
1827     PCMachineState *pcms = PC_MACHINE(obj);
1828 
1829     visit_type_OnOffAuto(v, &pcms->vmport, name, errp);
1830 }
1831 
1832 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp)
1833 {
1834     PCMachineState *pcms = PC_MACHINE(obj);
1835 
1836     return pcms->enforce_aligned_dimm;
1837 }
1838 
1839 static void pc_machine_initfn(Object *obj)
1840 {
1841     PCMachineState *pcms = PC_MACHINE(obj);
1842 
1843     object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int",
1844                         pc_machine_get_hotplug_memory_region_size,
1845                         NULL, NULL, NULL, NULL);
1846 
1847     pcms->max_ram_below_4g = 1ULL << 32; /* 4G */
1848     object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1849                         pc_machine_get_max_ram_below_4g,
1850                         pc_machine_set_max_ram_below_4g,
1851                         NULL, NULL, NULL);
1852     object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G,
1853                                     "Maximum ram below the 4G boundary (32bit boundary)",
1854                                     NULL);
1855 
1856     pcms->vmport = ON_OFF_AUTO_AUTO;
1857     object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto",
1858                         pc_machine_get_vmport,
1859                         pc_machine_set_vmport,
1860                         NULL, NULL, NULL);
1861     object_property_set_description(obj, PC_MACHINE_VMPORT,
1862                                     "Enable vmport (pc & q35)",
1863                                     NULL);
1864 
1865     pcms->enforce_aligned_dimm = true;
1866     object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM,
1867                              pc_machine_get_aligned_dimm,
1868                              NULL, NULL);
1869 }
1870 
1871 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index)
1872 {
1873     unsigned pkg_id, core_id, smt_id;
1874     x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index,
1875                           &pkg_id, &core_id, &smt_id);
1876     return pkg_id;
1877 }
1878 
1879 static void pc_machine_class_init(ObjectClass *oc, void *data)
1880 {
1881     MachineClass *mc = MACHINE_CLASS(oc);
1882     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1883     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1884 
1885     pcmc->get_hotplug_handler = mc->get_hotplug_handler;
1886     mc->get_hotplug_handler = pc_get_hotpug_handler;
1887     mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
1888     hc->plug = pc_machine_device_plug_cb;
1889     hc->unplug_request = pc_machine_device_unplug_request_cb;
1890     hc->unplug = pc_machine_device_unplug_cb;
1891 }
1892 
1893 static const TypeInfo pc_machine_info = {
1894     .name = TYPE_PC_MACHINE,
1895     .parent = TYPE_MACHINE,
1896     .abstract = true,
1897     .instance_size = sizeof(PCMachineState),
1898     .instance_init = pc_machine_initfn,
1899     .class_size = sizeof(PCMachineClass),
1900     .class_init = pc_machine_class_init,
1901     .interfaces = (InterfaceInfo[]) {
1902          { TYPE_HOTPLUG_HANDLER },
1903          { }
1904     },
1905 };
1906 
1907 static void pc_machine_register_types(void)
1908 {
1909     type_register_static(&pc_machine_info);
1910 }
1911 
1912 type_init(pc_machine_register_types)
1913