1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "exec/target_page.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial-isa.h" 30 #include "hw/char/parallel.h" 31 #include "hw/hyperv/hv-balloon.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "system/cpus.h" 35 #include "hw/ide/ide-bus.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/loader.h" 38 #include "hw/rtc/mc146818rtc.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/input/i8042.h" 42 #include "hw/audio/pcspk.h" 43 #include "system/system.h" 44 #include "system/xen.h" 45 #include "system/reset.h" 46 #include "kvm/kvm_i386.h" 47 #include "kvm/tdx.h" 48 #include "hw/xen/xen.h" 49 #include "qobject/qlist.h" 50 #include "qemu/error-report.h" 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "acpi-build.h" 53 #include "hw/mem/nvdimm.h" 54 #include "hw/cxl/cxl_host.h" 55 #include "hw/usb.h" 56 #include "hw/i386/intel_iommu.h" 57 #include "hw/net/ne2000-isa.h" 58 #include "hw/virtio/virtio-iommu.h" 59 #include "hw/virtio/virtio-md-pci.h" 60 #include "hw/i386/kvm/xen_overlay.h" 61 #include "hw/i386/kvm/xen_evtchn.h" 62 #include "hw/i386/kvm/xen_gnttab.h" 63 #include "hw/i386/kvm/xen_xenstore.h" 64 #include "hw/mem/memory-device.h" 65 #include "e820_memory_layout.h" 66 #include "trace.h" 67 #include "sev.h" 68 #include CONFIG_DEVICES 69 70 #ifdef CONFIG_XEN_EMU 71 #include "hw/xen/xen-legacy-backend.h" 72 #include "hw/xen/xen-bus.h" 73 #endif 74 75 /* 76 * Helper for setting model-id for CPU models that changed model-id 77 * depending on QEMU versions up to QEMU 2.4. 78 */ 79 #define PC_CPU_MODEL_IDS(v) \ 80 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 81 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 82 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 83 84 GlobalProperty pc_compat_10_0[] = { 85 { TYPE_X86_CPU, "x-consistent-cache", "false" }, 86 { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, 87 { TYPE_X86_CPU, "x-arch-cap-always-on", "true" }, 88 { TYPE_X86_CPU, "x-pdcm-on-even-without-pmu", "true" }, 89 }; 90 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 91 92 GlobalProperty pc_compat_9_2[] = {}; 93 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 94 95 GlobalProperty pc_compat_9_1[] = { 96 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 97 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 98 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 99 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 100 }; 101 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 102 103 GlobalProperty pc_compat_9_0[] = { 104 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 105 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 106 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 107 { "sev-guest", "legacy-vm-type", "on" }, 108 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 109 }; 110 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 111 112 GlobalProperty pc_compat_8_2[] = {}; 113 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 114 115 GlobalProperty pc_compat_8_1[] = {}; 116 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 117 118 GlobalProperty pc_compat_8_0[] = { 119 { "virtio-mem", "unplugged-inaccessible", "auto" }, 120 }; 121 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 122 123 GlobalProperty pc_compat_7_2[] = { 124 { "ICH9-LPC", "noreboot", "true" }, 125 }; 126 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 127 128 GlobalProperty pc_compat_7_1[] = {}; 129 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 130 131 GlobalProperty pc_compat_7_0[] = {}; 132 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 133 134 GlobalProperty pc_compat_6_2[] = { 135 { "virtio-mem", "unplugged-inaccessible", "off" }, 136 }; 137 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 138 139 GlobalProperty pc_compat_6_1[] = { 140 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 141 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 142 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 143 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 144 }; 145 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 146 147 GlobalProperty pc_compat_6_0[] = { 148 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 149 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 150 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 151 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 152 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 153 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 154 }; 155 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 156 157 GlobalProperty pc_compat_5_2[] = { 158 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 159 }; 160 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 161 162 GlobalProperty pc_compat_5_1[] = { 163 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 164 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 165 }; 166 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 167 168 GlobalProperty pc_compat_5_0[] = { 169 }; 170 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 171 172 GlobalProperty pc_compat_4_2[] = { 173 { "mch", "smbase-smram", "off" }, 174 }; 175 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 176 177 GlobalProperty pc_compat_4_1[] = {}; 178 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 179 180 GlobalProperty pc_compat_4_0[] = {}; 181 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 182 183 GlobalProperty pc_compat_3_1[] = { 184 { "intel-iommu", "dma-drain", "off" }, 185 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 186 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 187 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 188 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 189 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 190 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 191 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 192 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 193 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 194 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 195 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 196 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 197 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 198 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 199 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 200 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 201 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 202 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 203 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 204 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 205 }; 206 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 207 208 GlobalProperty pc_compat_3_0[] = { 209 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 210 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 211 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 212 }; 213 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 214 215 GlobalProperty pc_compat_2_12[] = { 216 { TYPE_X86_CPU, "legacy-cache", "on" }, 217 { TYPE_X86_CPU, "topoext", "off" }, 218 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 219 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 220 }; 221 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 222 223 GlobalProperty pc_compat_2_11[] = { 224 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 225 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 226 }; 227 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 228 229 GlobalProperty pc_compat_2_10[] = { 230 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 231 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 232 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 233 }; 234 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 235 236 GlobalProperty pc_compat_2_9[] = { 237 { "mch", "extended-tseg-mbytes", "0" }, 238 }; 239 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 240 241 GlobalProperty pc_compat_2_8[] = { 242 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 243 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 244 { "ICH9-LPC", "x-smi-broadcast", "off" }, 245 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 246 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 247 }; 248 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 249 250 GlobalProperty pc_compat_2_7[] = { 251 { TYPE_X86_CPU, "l3-cache", "off" }, 252 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 254 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 255 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 256 { "isa-pcspk", "migrate", "off" }, 257 }; 258 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 259 260 GlobalProperty pc_compat_2_6[] = { 261 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 262 { "vmxnet3", "romfile", "" }, 263 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 264 { "apic-common", "legacy-instance-id", "on", } 265 }; 266 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 267 268 /* 269 * @PC_FW_DATA: 270 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 271 * and other BIOS datastructures. 272 * 273 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 274 * reported to be used at the moment, 32K should be enough for a while. 275 */ 276 #define PC_FW_DATA (0x20000 + 0x8000) 277 278 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 279 { 280 GSIState *s; 281 282 s = g_new0(GSIState, 1); 283 if (kvm_ioapic_in_kernel()) { 284 kvm_pc_setup_irq_routing(pci_enabled); 285 } 286 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 287 288 return s; 289 } 290 291 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 292 unsigned size) 293 { 294 } 295 296 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 297 { 298 return 0xffffffffffffffffULL; 299 } 300 301 /* MS-DOS compatibility mode FPU exception support */ 302 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 303 unsigned size) 304 { 305 if (tcg_enabled()) { 306 cpu_set_ignne(); 307 } 308 } 309 310 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 311 { 312 return 0xffffffffffffffffULL; 313 } 314 315 /* PC cmos mappings */ 316 317 #define REG_EQUIPMENT_BYTE 0x14 318 319 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 320 int16_t cylinders, int8_t heads, int8_t sectors) 321 { 322 mc146818rtc_set_cmos_data(s, type_ofs, 47); 323 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 324 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 325 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 326 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 327 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 328 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 329 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 330 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 331 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 332 } 333 334 /* convert boot_device letter to something recognizable by the bios */ 335 static int boot_device2nibble(char boot_device) 336 { 337 switch(boot_device) { 338 case 'a': 339 case 'b': 340 return 0x01; /* floppy boot */ 341 case 'c': 342 return 0x02; /* hard drive boot */ 343 case 'd': 344 return 0x03; /* CD-ROM boot */ 345 case 'n': 346 return 0x04; /* Network boot */ 347 } 348 return 0; 349 } 350 351 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 352 const char *boot_device, Error **errp) 353 { 354 #define PC_MAX_BOOT_DEVICES 3 355 int nbds, bds[3] = { 0, }; 356 int i; 357 358 nbds = strlen(boot_device); 359 if (nbds > PC_MAX_BOOT_DEVICES) { 360 error_setg(errp, "Too many boot devices for PC"); 361 return; 362 } 363 for (i = 0; i < nbds; i++) { 364 bds[i] = boot_device2nibble(boot_device[i]); 365 if (bds[i] == 0) { 366 error_setg(errp, "Invalid boot device for PC: '%c'", 367 boot_device[i]); 368 return; 369 } 370 } 371 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 372 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 373 } 374 375 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 376 { 377 PCMachineState *pcms = opaque; 378 X86MachineState *x86ms = X86_MACHINE(pcms); 379 380 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 381 } 382 383 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 384 { 385 int val, nb; 386 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 387 FLOPPY_DRIVE_TYPE_NONE }; 388 389 #ifdef CONFIG_FDC_ISA 390 /* floppy type */ 391 if (floppy) { 392 for (int i = 0; i < 2; i++) { 393 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 394 } 395 } 396 #endif 397 398 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 399 cmos_get_fd_drive_type(fd_type[1]); 400 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 401 402 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 403 nb = 0; 404 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 405 nb++; 406 } 407 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 408 nb++; 409 } 410 switch (nb) { 411 case 0: 412 break; 413 case 1: 414 val |= 0x01; /* 1 drive, ready for boot */ 415 break; 416 case 2: 417 val |= 0x41; /* 2 drives, ready for boot */ 418 break; 419 } 420 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 421 } 422 423 typedef struct check_fdc_state { 424 ISADevice *floppy; 425 bool multiple; 426 } CheckFdcState; 427 428 static int check_fdc(Object *obj, void *opaque) 429 { 430 CheckFdcState *state = opaque; 431 Object *fdc; 432 uint32_t iobase; 433 Error *local_err = NULL; 434 435 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 436 if (!fdc) { 437 return 0; 438 } 439 440 iobase = object_property_get_uint(obj, "iobase", &local_err); 441 if (local_err || iobase != 0x3f0) { 442 error_free(local_err); 443 return 0; 444 } 445 446 if (state->floppy) { 447 state->multiple = true; 448 } else { 449 state->floppy = ISA_DEVICE(obj); 450 } 451 return 0; 452 } 453 454 static const char * const fdc_container_path[] = { 455 "unattached", "peripheral", "peripheral-anon" 456 }; 457 458 /* 459 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 460 * and ACPI objects. 461 */ 462 static ISADevice *pc_find_fdc0(void) 463 { 464 int i; 465 Object *container; 466 CheckFdcState state = { 0 }; 467 468 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 469 container = machine_get_container(fdc_container_path[i]); 470 object_child_foreach(container, check_fdc, &state); 471 } 472 473 if (state.multiple) { 474 warn_report("multiple floppy disk controllers with " 475 "iobase=0x3f0 have been found"); 476 error_printf("the one being picked for CMOS setup might not reflect " 477 "your intent"); 478 } 479 480 return state.floppy; 481 } 482 483 static void pc_cmos_init_late(PCMachineState *pcms) 484 { 485 X86MachineState *x86ms = X86_MACHINE(pcms); 486 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 487 int16_t cylinders; 488 int8_t heads, sectors; 489 int val; 490 int i, trans; 491 492 val = 0; 493 if (pcms->idebus[0] && 494 ide_get_geometry(pcms->idebus[0], 0, 495 &cylinders, &heads, §ors) >= 0) { 496 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 497 val |= 0xf0; 498 } 499 if (pcms->idebus[0] && 500 ide_get_geometry(pcms->idebus[0], 1, 501 &cylinders, &heads, §ors) >= 0) { 502 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 503 val |= 0x0f; 504 } 505 mc146818rtc_set_cmos_data(s, 0x12, val); 506 507 val = 0; 508 for (i = 0; i < 4; i++) { 509 /* NOTE: ide_get_geometry() returns the physical 510 geometry. It is always such that: 1 <= sects <= 63, 1 511 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 512 geometry can be different if a translation is done. */ 513 BusState *idebus = pcms->idebus[i / 2]; 514 if (idebus && 515 ide_get_geometry(idebus, i % 2, 516 &cylinders, &heads, §ors) >= 0) { 517 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 518 assert((trans & ~3) == 0); 519 val |= trans << (i * 2); 520 } 521 } 522 mc146818rtc_set_cmos_data(s, 0x39, val); 523 524 pc_cmos_init_floppy(s, pc_find_fdc0()); 525 526 /* various important CMOS locations needed by PC/Bochs bios */ 527 528 /* memory size */ 529 /* base memory (first MiB) */ 530 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 531 mc146818rtc_set_cmos_data(s, 0x15, val); 532 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 533 /* extended memory (next 64MiB) */ 534 if (x86ms->below_4g_mem_size > 1 * MiB) { 535 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 536 } else { 537 val = 0; 538 } 539 if (val > 65535) 540 val = 65535; 541 mc146818rtc_set_cmos_data(s, 0x17, val); 542 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 543 mc146818rtc_set_cmos_data(s, 0x30, val); 544 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 545 /* memory between 16MiB and 4GiB */ 546 if (x86ms->below_4g_mem_size > 16 * MiB) { 547 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 548 } else { 549 val = 0; 550 } 551 if (val > 65535) 552 val = 65535; 553 mc146818rtc_set_cmos_data(s, 0x34, val); 554 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 555 /* memory above 4GiB */ 556 val = x86ms->above_4g_mem_size / 65536; 557 mc146818rtc_set_cmos_data(s, 0x5b, val); 558 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 559 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 560 561 val = 0; 562 val |= 0x02; /* FPU is there */ 563 val |= 0x04; /* PS/2 mouse installed */ 564 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 565 } 566 567 static void handle_a20_line_change(void *opaque, int irq, int level) 568 { 569 X86CPU *cpu = opaque; 570 571 /* XXX: send to all CPUs ? */ 572 /* XXX: add logic to handle multiple A20 line sources */ 573 x86_cpu_set_a20(cpu, level); 574 } 575 576 #define NE2000_NB_MAX 6 577 578 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 579 0x280, 0x380 }; 580 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 581 582 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 583 { 584 static int nb_ne2k = 0; 585 586 if (nb_ne2k == NE2000_NB_MAX) { 587 error_setg(errp, 588 "maximum number of ISA NE2000 devices exceeded"); 589 return false; 590 } 591 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 592 ne2000_irq[nb_ne2k], nd); 593 nb_ne2k++; 594 return true; 595 } 596 597 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 598 { 599 X86CPU *cpu = opaque; 600 601 if (level) { 602 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 603 } 604 } 605 606 static 607 void pc_machine_done(Notifier *notifier, void *data) 608 { 609 PCMachineState *pcms = container_of(notifier, 610 PCMachineState, machine_done); 611 X86MachineState *x86ms = X86_MACHINE(pcms); 612 613 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 614 &error_fatal); 615 616 if (pcms->cxl_devices_state.is_enabled) { 617 cxl_fmws_link_targets(&error_fatal); 618 } 619 620 /* set the number of CPUs */ 621 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 622 623 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 624 &error_abort); 625 626 acpi_setup(); 627 if (x86ms->fw_cfg) { 628 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 629 fw_cfg_add_e820(x86ms->fw_cfg); 630 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 631 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 632 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 633 } 634 635 pc_cmos_init_late(pcms); 636 } 637 638 /* setup pci memory address space mapping into system address space */ 639 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 640 MemoryRegion *pci_address_space) 641 { 642 /* Set to lower priority than RAM */ 643 memory_region_add_subregion_overlap(system_memory, 0x0, 644 pci_address_space, -1); 645 } 646 647 void xen_load_linux(PCMachineState *pcms) 648 { 649 int i; 650 FWCfgState *fw_cfg; 651 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 652 X86MachineState *x86ms = X86_MACHINE(pcms); 653 654 assert(MACHINE(pcms)->kernel_filename != NULL); 655 656 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 657 &address_space_memory); 658 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 659 rom_set_fw(fw_cfg); 660 661 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 662 for (i = 0; i < nb_option_roms; i++) { 663 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 664 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 665 !strcmp(option_rom[i].name, "pvh.bin") || 666 !strcmp(option_rom[i].name, "multiboot.bin") || 667 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 668 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 669 } 670 x86ms->fw_cfg = fw_cfg; 671 } 672 673 #define PC_ROM_MIN_VGA 0xc0000 674 #define PC_ROM_MIN_OPTION 0xc8000 675 #define PC_ROM_MAX 0xe0000 676 #define PC_ROM_ALIGN 0x800 677 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 678 679 static hwaddr pc_above_4g_end(PCMachineState *pcms) 680 { 681 X86MachineState *x86ms = X86_MACHINE(pcms); 682 683 if (pcms->sgx_epc.size != 0) { 684 return sgx_epc_above_4g_end(&pcms->sgx_epc); 685 } 686 687 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 688 } 689 690 static void pc_get_device_memory_range(PCMachineState *pcms, 691 hwaddr *base, 692 ram_addr_t *device_mem_size) 693 { 694 MachineState *machine = MACHINE(pcms); 695 ram_addr_t size; 696 hwaddr addr; 697 698 size = machine->maxram_size - machine->ram_size; 699 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 700 701 /* size device region assuming 1G page max alignment per slot */ 702 size += (1 * GiB) * machine->ram_slots; 703 704 *base = addr; 705 *device_mem_size = size; 706 } 707 708 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 709 { 710 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 711 MachineState *ms = MACHINE(pcms); 712 hwaddr cxl_base; 713 ram_addr_t size; 714 715 if (pcmc->has_reserved_memory && 716 (ms->ram_size < ms->maxram_size)) { 717 pc_get_device_memory_range(pcms, &cxl_base, &size); 718 cxl_base += size; 719 } else { 720 cxl_base = pc_above_4g_end(pcms); 721 } 722 723 return cxl_base; 724 } 725 726 static int cxl_get_fmw_end(Object *obj, void *opaque) 727 { 728 struct CXLFixedWindow *fw; 729 uint64_t *start = opaque; 730 731 if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { 732 return 0; 733 } 734 fw = CXL_FMW(obj); 735 736 *start += fw->size; 737 738 return 0; 739 } 740 741 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 742 { 743 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 744 745 /* Ordering doesn't matter so no need to build a sorted list */ 746 object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end, 747 &start); 748 return start; 749 } 750 751 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 752 { 753 X86CPU *cpu = X86_CPU(first_cpu); 754 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 755 MachineState *ms = MACHINE(pcms); 756 757 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 758 /* 64-bit systems */ 759 return pc_pci_hole64_start() + pci_hole64_size - 1; 760 } 761 762 /* 32-bit systems */ 763 if (pcmc->broken_32bit_mem_addr_check) { 764 /* old value for compatibility reasons */ 765 return ((hwaddr)1 << cpu->phys_bits) - 1; 766 } 767 768 /* 769 * 32-bit systems don't have hole64 but they might have a region for 770 * memory devices. Even if additional hotplugged memory devices might 771 * not be usable by most guest OSes, we need to still consider them for 772 * calculating the highest possible GPA so that we can properly report 773 * if someone configures them on a CPU that cannot possibly address them. 774 */ 775 if (pcmc->has_reserved_memory && 776 (ms->ram_size < ms->maxram_size)) { 777 hwaddr devmem_start; 778 ram_addr_t devmem_size; 779 780 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 781 devmem_start += devmem_size; 782 return devmem_start - 1; 783 } 784 785 /* configuration without any memory hotplug */ 786 return pc_above_4g_end(pcms) - 1; 787 } 788 789 /* 790 * AMD systems with an IOMMU have an additional hole close to the 791 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 792 * on kernel version, VFIO may or may not let you DMA map those ranges. 793 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 794 * with certain memory sizes. It's also wrong to use those IOVA ranges 795 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 796 * The ranges reserved for Hyper-Transport are: 797 * 798 * FD_0000_0000h - FF_FFFF_FFFFh 799 * 800 * The ranges represent the following: 801 * 802 * Base Address Top Address Use 803 * 804 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 805 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 806 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 807 * FD_F910_0000h FD_F91F_FFFFh System Management 808 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 809 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 810 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 811 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 812 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 813 * FE_2000_0000h FF_FFFF_FFFFh Reserved 814 * 815 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 816 * Table 3: Special Address Controls (GPA) for more information. 817 */ 818 #define AMD_HT_START 0xfd00000000UL 819 #define AMD_HT_END 0xffffffffffUL 820 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 821 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 822 823 void pc_memory_init(PCMachineState *pcms, 824 MemoryRegion *system_memory, 825 MemoryRegion *rom_memory, 826 uint64_t pci_hole64_size) 827 { 828 int linux_boot, i; 829 MemoryRegion *option_rom_mr; 830 MemoryRegion *ram_below_4g, *ram_above_4g; 831 FWCfgState *fw_cfg; 832 MachineState *machine = MACHINE(pcms); 833 MachineClass *mc = MACHINE_GET_CLASS(machine); 834 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 835 X86MachineState *x86ms = X86_MACHINE(pcms); 836 hwaddr maxphysaddr, maxusedaddr; 837 hwaddr cxl_base, cxl_resv_end = 0; 838 X86CPU *cpu = X86_CPU(first_cpu); 839 840 assert(machine->ram_size == x86ms->below_4g_mem_size + 841 x86ms->above_4g_mem_size); 842 843 linux_boot = (machine->kernel_filename != NULL); 844 845 /* 846 * The HyperTransport range close to the 1T boundary is unique to AMD 847 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 848 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 849 * older machine types (<= 7.0) for compatibility purposes. 850 */ 851 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 852 /* Bail out if max possible address does not cross HT range */ 853 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 854 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 855 } 856 857 /* 858 * Advertise the HT region if address space covers the reserved 859 * region or if we relocate. 860 */ 861 if (cpu->phys_bits >= 40) { 862 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 863 } 864 } 865 866 /* 867 * phys-bits is required to be appropriately configured 868 * to make sure max used GPA is reachable. 869 */ 870 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 871 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 872 if (maxphysaddr < maxusedaddr) { 873 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 874 " phys-bits too low (%u)", 875 maxphysaddr, maxusedaddr, cpu->phys_bits); 876 exit(EXIT_FAILURE); 877 } 878 879 /* 880 * Split single memory region and use aliases to address portions of it, 881 * done for backwards compatibility with older qemus. 882 */ 883 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 884 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 885 0, x86ms->below_4g_mem_size); 886 memory_region_add_subregion(system_memory, 0, ram_below_4g); 887 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 888 if (x86ms->above_4g_mem_size > 0) { 889 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 890 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 891 machine->ram, 892 x86ms->below_4g_mem_size, 893 x86ms->above_4g_mem_size); 894 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 895 ram_above_4g); 896 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 897 E820_RAM); 898 } 899 900 if (pcms->sgx_epc.size != 0) { 901 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 902 } 903 904 if (!pcmc->has_reserved_memory && 905 (machine->ram_slots || 906 (machine->maxram_size > machine->ram_size))) { 907 908 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 909 mc->name); 910 exit(EXIT_FAILURE); 911 } 912 913 /* initialize device memory address space */ 914 if (pcmc->has_reserved_memory && 915 (machine->ram_size < machine->maxram_size)) { 916 ram_addr_t device_mem_size; 917 hwaddr device_mem_base; 918 919 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 920 error_report("unsupported amount of memory slots: %"PRIu64, 921 machine->ram_slots); 922 exit(EXIT_FAILURE); 923 } 924 925 if (QEMU_ALIGN_UP(machine->maxram_size, 926 TARGET_PAGE_SIZE) != machine->maxram_size) { 927 error_report("maximum memory size must by aligned to multiple of " 928 "%d bytes", TARGET_PAGE_SIZE); 929 exit(EXIT_FAILURE); 930 } 931 932 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 933 934 if (device_mem_base + device_mem_size < device_mem_size) { 935 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 936 machine->maxram_size); 937 exit(EXIT_FAILURE); 938 } 939 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 940 } 941 942 if (pcms->cxl_devices_state.is_enabled) { 943 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 944 hwaddr cxl_size = MiB; 945 946 cxl_base = pc_get_cxl_range_start(pcms); 947 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 948 memory_region_add_subregion(system_memory, cxl_base, mr); 949 cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 950 cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr); 951 cxl_fmws_update_mmio(); 952 } 953 954 /* Initialize PC system firmware */ 955 pc_system_firmware_init(pcms, rom_memory); 956 957 if (!is_tdx_vm()) { 958 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 959 if (machine_require_guest_memfd(machine)) { 960 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 961 PC_ROM_SIZE, &error_fatal); 962 } else { 963 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 964 &error_fatal); 965 if (pcmc->pci_enabled) { 966 memory_region_set_readonly(option_rom_mr, true); 967 } 968 } 969 memory_region_add_subregion_overlap(rom_memory, 970 PC_ROM_MIN_VGA, 971 option_rom_mr, 972 1); 973 } 974 975 fw_cfg = fw_cfg_arch_create(machine, 976 x86ms->boot_cpus, x86ms->apic_id_limit); 977 978 rom_set_fw(fw_cfg); 979 980 if (machine->device_memory) { 981 uint64_t *val = g_malloc(sizeof(*val)); 982 uint64_t res_mem_end; 983 984 if (pcms->cxl_devices_state.is_enabled) { 985 res_mem_end = cxl_resv_end; 986 } else { 987 res_mem_end = machine->device_memory->base 988 + memory_region_size(&machine->device_memory->mr); 989 } 990 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 991 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 992 } 993 994 if (linux_boot) { 995 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 996 } 997 998 for (i = 0; i < nb_option_roms; i++) { 999 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1000 } 1001 x86ms->fw_cfg = fw_cfg; 1002 1003 /* Init default IOAPIC address space */ 1004 x86ms->ioapic_as = &address_space_memory; 1005 1006 /* Init ACPI memory hotplug IO base address */ 1007 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1008 } 1009 1010 /* 1011 * The 64bit pci hole starts after "above 4G RAM" and 1012 * potentially the space reserved for memory hotplug. 1013 */ 1014 uint64_t pc_pci_hole64_start(void) 1015 { 1016 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1017 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1018 MachineState *ms = MACHINE(pcms); 1019 uint64_t hole64_start = 0; 1020 ram_addr_t size = 0; 1021 1022 if (pcms->cxl_devices_state.is_enabled) { 1023 hole64_start = pc_get_cxl_range_end(pcms); 1024 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1025 pc_get_device_memory_range(pcms, &hole64_start, &size); 1026 hole64_start += size; 1027 } else { 1028 hole64_start = pc_above_4g_end(pcms); 1029 } 1030 1031 return ROUND_UP(hole64_start, 1 * GiB); 1032 } 1033 1034 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1035 { 1036 DeviceState *dev = NULL; 1037 1038 if (pci_bus) { 1039 PCIDevice *pcidev = pci_vga_init(pci_bus); 1040 dev = pcidev ? &pcidev->qdev : NULL; 1041 } else if (isa_bus) { 1042 ISADevice *isadev = isa_vga_init(isa_bus); 1043 dev = isadev ? DEVICE(isadev) : NULL; 1044 } 1045 1046 return dev; 1047 } 1048 1049 static const MemoryRegionOps ioport80_io_ops = { 1050 .write = ioport80_write, 1051 .read = ioport80_read, 1052 .endianness = DEVICE_LITTLE_ENDIAN, 1053 .impl = { 1054 .min_access_size = 1, 1055 .max_access_size = 1, 1056 }, 1057 }; 1058 1059 static const MemoryRegionOps ioportF0_io_ops = { 1060 .write = ioportF0_write, 1061 .read = ioportF0_read, 1062 .endianness = DEVICE_LITTLE_ENDIAN, 1063 .impl = { 1064 .min_access_size = 1, 1065 .max_access_size = 1, 1066 }, 1067 }; 1068 1069 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1070 bool create_i8042, bool no_vmport, Error **errp) 1071 { 1072 int i; 1073 DriveInfo *fd[MAX_FD]; 1074 qemu_irq *a20_line; 1075 ISADevice *i8042, *port92, *vmmouse; 1076 1077 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1078 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1079 1080 for (i = 0; i < MAX_FD; i++) { 1081 fd[i] = drive_get(IF_FLOPPY, 0, i); 1082 create_fdctrl |= !!fd[i]; 1083 } 1084 if (create_fdctrl) { 1085 #ifdef CONFIG_FDC_ISA 1086 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1087 if (fdc) { 1088 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1089 isa_fdc_init_drives(fdc, fd); 1090 } 1091 #endif 1092 } 1093 1094 if (!create_i8042) { 1095 if (!no_vmport) { 1096 error_setg(errp, 1097 "vmport requires the i8042 controller to be enabled"); 1098 } 1099 return; 1100 } 1101 1102 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1103 if (!no_vmport) { 1104 isa_create_simple(isa_bus, TYPE_VMPORT); 1105 vmmouse = isa_try_new("vmmouse"); 1106 } else { 1107 vmmouse = NULL; 1108 } 1109 if (vmmouse) { 1110 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1111 &error_abort); 1112 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1113 } 1114 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1115 1116 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1117 qdev_connect_gpio_out_named(DEVICE(i8042), 1118 I8042_A20_LINE, 0, a20_line[0]); 1119 qdev_connect_gpio_out_named(DEVICE(port92), 1120 PORT92_A20_LINE, 0, a20_line[1]); 1121 g_free(a20_line); 1122 } 1123 1124 void pc_basic_device_init(struct PCMachineState *pcms, 1125 ISABus *isa_bus, qemu_irq *gsi, 1126 ISADevice *rtc_state, 1127 bool create_fdctrl, 1128 uint32_t hpet_irqs) 1129 { 1130 int i; 1131 DeviceState *hpet = NULL; 1132 int pit_isa_irq = 0; 1133 qemu_irq pit_alt_irq = NULL; 1134 ISADevice *pit = NULL; 1135 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1136 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1137 X86MachineState *x86ms = X86_MACHINE(pcms); 1138 1139 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1140 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1141 1142 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1143 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1144 1145 /* 1146 * Check if an HPET shall be created. 1147 */ 1148 if (pcms->hpet_enabled) { 1149 qemu_irq rtc_irq; 1150 1151 hpet = qdev_try_new(TYPE_HPET); 1152 if (!hpet) { 1153 error_report("couldn't create HPET device"); 1154 exit(1); 1155 } 1156 /* 1157 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1158 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1159 * the property, use whatever mask they specified. 1160 */ 1161 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1162 HPET_INTCAP, NULL); 1163 if (!compat) { 1164 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1165 } 1166 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1167 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1168 1169 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1170 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1171 } 1172 pit_isa_irq = -1; 1173 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1174 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1175 1176 /* overwrite connection created by south bridge */ 1177 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1178 } 1179 1180 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1181 "date"); 1182 1183 #ifdef CONFIG_XEN_EMU 1184 if (xen_mode == XEN_EMULATE) { 1185 xen_overlay_create(); 1186 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1187 xen_gnttab_create(); 1188 xen_xenstore_create(); 1189 if (pcms->pcibus) { 1190 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1191 } 1192 xen_bus_init(); 1193 } 1194 #endif 1195 1196 qemu_register_boot_set(pc_boot_set, pcms); 1197 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1198 MACHINE(pcms)->boot_config.order, &error_fatal); 1199 1200 if (!xen_enabled() && 1201 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1202 if (kvm_pit_in_kernel()) { 1203 pit = kvm_pit_init(isa_bus, 0x40); 1204 } else { 1205 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1206 } 1207 if (hpet) { 1208 /* connect PIT to output control line of the HPET */ 1209 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1210 } 1211 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1212 OBJECT(pit), &error_fatal); 1213 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1214 } 1215 1216 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1217 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1218 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1219 } 1220 1221 /* Super I/O */ 1222 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1223 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1224 1225 pcms->machine_done.notify = pc_machine_done; 1226 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1227 } 1228 1229 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1230 { 1231 MachineClass *mc = MACHINE_CLASS(pcmc); 1232 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1233 NICInfo *nd; 1234 1235 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1236 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1237 } 1238 1239 /* Anything remaining should be a PCI NIC */ 1240 if (pci_bus) { 1241 pci_init_nic_devices(pci_bus, mc->default_nic); 1242 } 1243 } 1244 1245 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1246 { 1247 qemu_irq *i8259; 1248 1249 if (kvm_pic_in_kernel()) { 1250 i8259 = kvm_i8259_init(isa_bus); 1251 } else if (xen_enabled()) { 1252 i8259 = xen_interrupt_controller_init(); 1253 } else { 1254 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1255 } 1256 1257 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1258 i8259_irqs[i] = i8259[i]; 1259 } 1260 1261 g_free(i8259); 1262 } 1263 1264 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1265 Error **errp) 1266 { 1267 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1268 const MachineState *ms = MACHINE(hotplug_dev); 1269 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1270 Error *local_err = NULL; 1271 1272 /* 1273 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1274 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1275 * addition to cover this case. 1276 */ 1277 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1278 error_setg(errp, 1279 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1280 return; 1281 } 1282 1283 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1284 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1285 return; 1286 } 1287 1288 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1289 if (local_err) { 1290 error_propagate(errp, local_err); 1291 return; 1292 } 1293 1294 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1295 } 1296 1297 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1298 DeviceState *dev, Error **errp) 1299 { 1300 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1301 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1302 MachineState *ms = MACHINE(hotplug_dev); 1303 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1304 1305 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1306 1307 if (is_nvdimm) { 1308 nvdimm_plug(ms->nvdimms_state); 1309 } 1310 1311 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1312 } 1313 1314 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1315 DeviceState *dev, Error **errp) 1316 { 1317 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1318 1319 /* 1320 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1321 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1322 * addition to cover this case. 1323 */ 1324 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1325 error_setg(errp, 1326 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1327 return; 1328 } 1329 1330 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1331 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1332 return; 1333 } 1334 1335 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1336 errp); 1337 } 1338 1339 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1340 DeviceState *dev, Error **errp) 1341 { 1342 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1343 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1344 Error *local_err = NULL; 1345 1346 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1347 if (local_err) { 1348 goto out; 1349 } 1350 1351 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1352 qdev_unrealize(dev); 1353 out: 1354 error_propagate(errp, local_err); 1355 } 1356 1357 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1358 DeviceState *dev, Error **errp) 1359 { 1360 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1361 g_assert(!dev->hotplugged); 1362 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1363 } 1364 1365 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1366 DeviceState *dev, Error **errp) 1367 { 1368 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1369 } 1370 1371 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1372 DeviceState *dev, Error **errp) 1373 { 1374 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1375 pc_memory_pre_plug(hotplug_dev, dev, errp); 1376 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1377 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1379 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1380 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1381 /* Declare the APIC range as the reserved MSI region */ 1382 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1383 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1384 QList *reserved_regions = qlist_new(); 1385 1386 qlist_append_str(reserved_regions, resv_prop_str); 1387 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1388 1389 g_free(resv_prop_str); 1390 } 1391 1392 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1393 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1394 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1395 1396 if (pcms->iommu) { 1397 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1398 "for x86 yet."); 1399 return; 1400 } 1401 pcms->iommu = dev; 1402 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1403 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1404 } 1405 } 1406 1407 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1408 DeviceState *dev, Error **errp) 1409 { 1410 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1411 pc_memory_plug(hotplug_dev, dev, errp); 1412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1413 x86_cpu_plug(hotplug_dev, dev, errp); 1414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1415 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1416 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1417 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1418 } 1419 } 1420 1421 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1422 DeviceState *dev, Error **errp) 1423 { 1424 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1425 pc_memory_unplug_request(hotplug_dev, dev, errp); 1426 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1427 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1428 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1429 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1430 errp); 1431 } else { 1432 error_setg(errp, "acpi: device unplug request for not supported device" 1433 " type: %s", object_get_typename(OBJECT(dev))); 1434 } 1435 } 1436 1437 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1438 DeviceState *dev, Error **errp) 1439 { 1440 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1441 pc_memory_unplug(hotplug_dev, dev, errp); 1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1443 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1444 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1445 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1446 } else { 1447 error_setg(errp, "acpi: device unplug for not supported device" 1448 " type: %s", object_get_typename(OBJECT(dev))); 1449 } 1450 } 1451 1452 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1453 DeviceState *dev) 1454 { 1455 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1456 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1457 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1458 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1459 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1460 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1461 return HOTPLUG_HANDLER(machine); 1462 } 1463 1464 return NULL; 1465 } 1466 1467 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1468 void *opaque, Error **errp) 1469 { 1470 PCMachineState *pcms = PC_MACHINE(obj); 1471 OnOffAuto vmport = pcms->vmport; 1472 1473 visit_type_OnOffAuto(v, name, &vmport, errp); 1474 } 1475 1476 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1477 void *opaque, Error **errp) 1478 { 1479 PCMachineState *pcms = PC_MACHINE(obj); 1480 1481 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1482 } 1483 1484 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1485 { 1486 PCMachineState *pcms = PC_MACHINE(obj); 1487 1488 return pcms->fd_bootchk; 1489 } 1490 1491 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1492 { 1493 PCMachineState *pcms = PC_MACHINE(obj); 1494 1495 pcms->fd_bootchk = value; 1496 } 1497 1498 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1499 { 1500 PCMachineState *pcms = PC_MACHINE(obj); 1501 1502 return pcms->smbus_enabled; 1503 } 1504 1505 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 pcms->smbus_enabled = value; 1510 } 1511 1512 static bool pc_machine_get_sata(Object *obj, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 return pcms->sata_enabled; 1517 } 1518 1519 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 pcms->sata_enabled = value; 1524 } 1525 1526 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 1530 return pcms->hpet_enabled; 1531 } 1532 1533 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1534 { 1535 PCMachineState *pcms = PC_MACHINE(obj); 1536 1537 pcms->hpet_enabled = value; 1538 } 1539 1540 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1541 { 1542 PCMachineState *pcms = PC_MACHINE(obj); 1543 1544 return pcms->i8042_enabled; 1545 } 1546 1547 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1548 { 1549 PCMachineState *pcms = PC_MACHINE(obj); 1550 1551 pcms->i8042_enabled = value; 1552 } 1553 1554 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(obj); 1557 1558 return pcms->default_bus_bypass_iommu; 1559 } 1560 1561 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1562 Error **errp) 1563 { 1564 PCMachineState *pcms = PC_MACHINE(obj); 1565 1566 pcms->default_bus_bypass_iommu = value; 1567 } 1568 1569 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1570 void *opaque, Error **errp) 1571 { 1572 PCMachineState *pcms = PC_MACHINE(obj); 1573 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1574 1575 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1576 } 1577 1578 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1579 void *opaque, Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 1583 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1584 } 1585 1586 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1587 const char *name, void *opaque, 1588 Error **errp) 1589 { 1590 PCMachineState *pcms = PC_MACHINE(obj); 1591 uint64_t value = pcms->max_ram_below_4g; 1592 1593 visit_type_size(v, name, &value, errp); 1594 } 1595 1596 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1597 const char *name, void *opaque, 1598 Error **errp) 1599 { 1600 PCMachineState *pcms = PC_MACHINE(obj); 1601 uint64_t value; 1602 1603 if (!visit_type_size(v, name, &value, errp)) { 1604 return; 1605 } 1606 if (value > 4 * GiB) { 1607 error_setg(errp, 1608 "Machine option 'max-ram-below-4g=%"PRIu64 1609 "' expects size less than or equal to 4G", value); 1610 return; 1611 } 1612 1613 if (value < 1 * MiB) { 1614 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1615 "BIOS may not work with less than 1MiB", value); 1616 } 1617 1618 pcms->max_ram_below_4g = value; 1619 } 1620 1621 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1622 const char *name, void *opaque, 1623 Error **errp) 1624 { 1625 PCMachineState *pcms = PC_MACHINE(obj); 1626 uint64_t value = pcms->max_fw_size; 1627 1628 visit_type_size(v, name, &value, errp); 1629 } 1630 1631 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1632 const char *name, void *opaque, 1633 Error **errp) 1634 { 1635 PCMachineState *pcms = PC_MACHINE(obj); 1636 uint64_t value; 1637 1638 if (!visit_type_size(v, name, &value, errp)) { 1639 return; 1640 } 1641 1642 /* 1643 * We don't have a theoretically justifiable exact lower bound on the base 1644 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1645 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1646 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1647 * 16MiB in size. 1648 */ 1649 if (value > 16 * MiB) { 1650 error_setg(errp, 1651 "User specified max allowed firmware size %" PRIu64 " is " 1652 "greater than 16MiB. If combined firmware size exceeds " 1653 "16MiB the system may not boot, or experience intermittent" 1654 "stability issues.", 1655 value); 1656 return; 1657 } 1658 1659 pcms->max_fw_size = value; 1660 } 1661 1662 1663 static void pc_machine_initfn(Object *obj) 1664 { 1665 PCMachineState *pcms = PC_MACHINE(obj); 1666 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1667 1668 #ifdef CONFIG_VMPORT 1669 pcms->vmport = ON_OFF_AUTO_AUTO; 1670 #else 1671 pcms->vmport = ON_OFF_AUTO_OFF; 1672 #endif /* CONFIG_VMPORT */ 1673 pcms->max_ram_below_4g = 0; /* use default */ 1674 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1675 pcms->south_bridge = pcmc->default_south_bridge; 1676 1677 /* acpi build is enabled by default if machine supports it */ 1678 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1679 pcms->smbus_enabled = true; 1680 pcms->sata_enabled = true; 1681 pcms->i8042_enabled = true; 1682 pcms->max_fw_size = 8 * MiB; 1683 #if defined(CONFIG_HPET) 1684 pcms->hpet_enabled = true; 1685 #endif 1686 pcms->fd_bootchk = true; 1687 pcms->default_bus_bypass_iommu = false; 1688 1689 pc_system_flash_create(pcms); 1690 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1691 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1692 OBJECT(pcms->pcspk), "audiodev"); 1693 if (pcmc->pci_enabled) { 1694 cxl_machine_init(obj, &pcms->cxl_devices_state); 1695 } 1696 } 1697 1698 static void pc_machine_reset(MachineState *machine, ResetType type) 1699 { 1700 CPUState *cs; 1701 X86CPU *cpu; 1702 1703 qemu_devices_reset(type); 1704 1705 /* Reset APIC after devices have been reset to cancel 1706 * any changes that qemu_devices_reset() might have done. 1707 */ 1708 CPU_FOREACH(cs) { 1709 cpu = X86_CPU(cs); 1710 1711 x86_cpu_after_reset(cpu); 1712 } 1713 } 1714 1715 static void pc_machine_wakeup(MachineState *machine) 1716 { 1717 cpu_synchronize_all_states(); 1718 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1719 cpu_synchronize_all_post_reset(); 1720 } 1721 1722 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1723 { 1724 X86IOMMUState *iommu = x86_iommu_get_default(); 1725 IntelIOMMUState *intel_iommu; 1726 1727 if (iommu && 1728 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1729 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1730 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1731 if (!intel_iommu->caching_mode) { 1732 error_setg(errp, "Device assignment is not allowed without " 1733 "enabling caching-mode=on for Intel IOMMU."); 1734 return false; 1735 } 1736 } 1737 1738 return true; 1739 } 1740 1741 static void pc_machine_class_init(ObjectClass *oc, const void *data) 1742 { 1743 MachineClass *mc = MACHINE_CLASS(oc); 1744 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1745 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1746 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1747 1748 pcmc->pci_enabled = true; 1749 pcmc->has_acpi_build = true; 1750 pcmc->smbios_defaults = true; 1751 pcmc->gigabyte_align = true; 1752 pcmc->has_reserved_memory = true; 1753 pcmc->enforce_amd_1tb_hole = true; 1754 pcmc->isa_bios_alias = true; 1755 pcmc->pvh_enabled = true; 1756 pcmc->kvmclock_create_always = true; 1757 x86mc->apic_xrupt_override = true; 1758 assert(!mc->get_hotplug_handler); 1759 mc->get_hotplug_handler = pc_get_hotplug_handler; 1760 mc->hotplug_allowed = pc_hotplug_allowed; 1761 mc->auto_enable_numa_with_memhp = true; 1762 mc->auto_enable_numa_with_memdev = true; 1763 mc->has_hotpluggable_cpus = true; 1764 mc->default_boot_order = "cad"; 1765 mc->block_default_type = IF_IDE; 1766 mc->max_cpus = 255; 1767 mc->reset = pc_machine_reset; 1768 mc->wakeup = pc_machine_wakeup; 1769 hc->pre_plug = pc_machine_device_pre_plug_cb; 1770 hc->plug = pc_machine_device_plug_cb; 1771 hc->unplug_request = pc_machine_device_unplug_request_cb; 1772 hc->unplug = pc_machine_device_unplug_cb; 1773 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1774 mc->nvdimm_supported = true; 1775 mc->smp_props.dies_supported = true; 1776 mc->smp_props.modules_supported = true; 1777 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1778 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1779 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1780 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1781 mc->default_ram_id = "pc.ram"; 1782 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1783 1784 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1785 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1786 NULL, NULL); 1787 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1788 "Maximum ram below the 4G boundary (32bit boundary)"); 1789 1790 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1791 pc_machine_get_vmport, pc_machine_set_vmport, 1792 NULL, NULL); 1793 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1794 "Enable vmport (pc & q35)"); 1795 1796 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1797 pc_machine_get_smbus, pc_machine_set_smbus); 1798 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1799 "Enable/disable system management bus"); 1800 1801 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1802 pc_machine_get_sata, pc_machine_set_sata); 1803 object_class_property_set_description(oc, PC_MACHINE_SATA, 1804 "Enable/disable Serial ATA bus"); 1805 1806 object_class_property_add_bool(oc, "hpet", 1807 pc_machine_get_hpet, pc_machine_set_hpet); 1808 object_class_property_set_description(oc, "hpet", 1809 "Enable/disable high precision event timer emulation"); 1810 1811 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1812 pc_machine_get_i8042, pc_machine_set_i8042); 1813 object_class_property_set_description(oc, PC_MACHINE_I8042, 1814 "Enable/disable Intel 8042 PS/2 controller emulation"); 1815 1816 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1817 pc_machine_get_default_bus_bypass_iommu, 1818 pc_machine_set_default_bus_bypass_iommu); 1819 1820 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1821 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1822 NULL, NULL); 1823 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1824 "Maximum combined firmware size"); 1825 1826 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1827 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1828 NULL, NULL); 1829 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1830 "SMBIOS Entry Point type [32, 64]"); 1831 1832 object_class_property_add_bool(oc, "fd-bootchk", 1833 pc_machine_get_fd_bootchk, 1834 pc_machine_set_fd_bootchk); 1835 1836 #if defined(CONFIG_IGVM) 1837 object_class_property_add_link(oc, "igvm-cfg", 1838 TYPE_IGVM_CFG, 1839 offsetof(X86MachineState, igvm), 1840 object_property_allow_set_link, 1841 OBJ_PROP_LINK_STRONG); 1842 object_class_property_set_description(oc, "igvm-cfg", 1843 "Set IGVM configuration"); 1844 #endif 1845 1846 1847 } 1848 1849 static const TypeInfo pc_machine_info = { 1850 .name = TYPE_PC_MACHINE, 1851 .parent = TYPE_X86_MACHINE, 1852 .abstract = true, 1853 .instance_size = sizeof(PCMachineState), 1854 .instance_init = pc_machine_initfn, 1855 .class_size = sizeof(PCMachineClass), 1856 .class_init = pc_machine_class_init, 1857 .interfaces = (const InterfaceInfo[]) { 1858 { TYPE_HOTPLUG_HANDLER }, 1859 { } 1860 }, 1861 }; 1862 1863 static void pc_machine_register_types(void) 1864 { 1865 type_register_static(&pc_machine_info); 1866 } 1867 1868 type_init(pc_machine_register_types) 1869