1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/dma/i8257.h" 51 #include "hw/timer/i8254.h" 52 #include "hw/input/i8042.h" 53 #include "hw/irq.h" 54 #include "hw/audio/pcspk.h" 55 #include "hw/pci/msi.h" 56 #include "hw/sysbus.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/tcg.h" 59 #include "sysemu/numa.h" 60 #include "sysemu/kvm.h" 61 #include "sysemu/xen.h" 62 #include "sysemu/reset.h" 63 #include "sysemu/runstate.h" 64 #include "kvm/kvm_i386.h" 65 #include "hw/xen/xen.h" 66 #include "hw/xen/start_info.h" 67 #include "ui/qemu-spice.h" 68 #include "exec/memory.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/cxl/cxl.h" 80 #include "hw/cxl/cxl_host.h" 81 #include "qapi/error.h" 82 #include "qapi/qapi-visit-common.h" 83 #include "qapi/qapi-visit-machine.h" 84 #include "qapi/visitor.h" 85 #include "hw/core/cpu.h" 86 #include "hw/usb.h" 87 #include "hw/i386/intel_iommu.h" 88 #include "hw/net/ne2000-isa.h" 89 #include "standard-headers/asm-x86/bootparam.h" 90 #include "hw/virtio/virtio-iommu.h" 91 #include "hw/virtio/virtio-pmem-pci.h" 92 #include "hw/virtio/virtio-mem-pci.h" 93 #include "hw/mem/memory-device.h" 94 #include "sysemu/replay.h" 95 #include "qapi/qmp/qerror.h" 96 #include "e820_memory_layout.h" 97 #include "fw_cfg.h" 98 #include "trace.h" 99 #include CONFIG_DEVICES 100 101 GlobalProperty pc_compat_7_0[] = {}; 102 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 103 104 GlobalProperty pc_compat_6_2[] = { 105 { "virtio-mem", "unplugged-inaccessible", "off" }, 106 }; 107 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 108 109 GlobalProperty pc_compat_6_1[] = { 110 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 111 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 112 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 113 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 114 }; 115 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 116 117 GlobalProperty pc_compat_6_0[] = { 118 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 120 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 121 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 122 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 123 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 124 }; 125 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 126 127 GlobalProperty pc_compat_5_2[] = { 128 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 129 }; 130 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 131 132 GlobalProperty pc_compat_5_1[] = { 133 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 134 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 135 }; 136 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 137 138 GlobalProperty pc_compat_5_0[] = { 139 }; 140 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 141 142 GlobalProperty pc_compat_4_2[] = { 143 { "mch", "smbase-smram", "off" }, 144 }; 145 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 146 147 GlobalProperty pc_compat_4_1[] = {}; 148 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 149 150 GlobalProperty pc_compat_4_0[] = {}; 151 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 152 153 GlobalProperty pc_compat_3_1[] = { 154 { "intel-iommu", "dma-drain", "off" }, 155 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 158 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 161 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 163 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 165 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 166 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 173 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 174 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 175 }; 176 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 177 178 GlobalProperty pc_compat_3_0[] = { 179 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 180 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 181 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 182 }; 183 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 184 185 GlobalProperty pc_compat_2_12[] = { 186 { TYPE_X86_CPU, "legacy-cache", "on" }, 187 { TYPE_X86_CPU, "topoext", "off" }, 188 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 190 }; 191 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 192 193 GlobalProperty pc_compat_2_11[] = { 194 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 195 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 196 }; 197 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 198 199 GlobalProperty pc_compat_2_10[] = { 200 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 201 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 202 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 203 }; 204 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 205 206 GlobalProperty pc_compat_2_9[] = { 207 { "mch", "extended-tseg-mbytes", "0" }, 208 }; 209 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 210 211 GlobalProperty pc_compat_2_8[] = { 212 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 213 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 214 { "ICH9-LPC", "x-smi-broadcast", "off" }, 215 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 216 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 217 }; 218 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 219 220 GlobalProperty pc_compat_2_7[] = { 221 { TYPE_X86_CPU, "l3-cache", "off" }, 222 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 225 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 226 { "isa-pcspk", "migrate", "off" }, 227 }; 228 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 229 230 GlobalProperty pc_compat_2_6[] = { 231 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 232 { "vmxnet3", "romfile", "" }, 233 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 234 { "apic-common", "legacy-instance-id", "on", } 235 }; 236 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 237 238 GlobalProperty pc_compat_2_5[] = {}; 239 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 240 241 GlobalProperty pc_compat_2_4[] = { 242 PC_CPU_MODEL_IDS("2.4.0") 243 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 244 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 246 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 247 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 248 { TYPE_X86_CPU, "check", "off" }, 249 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 251 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 253 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 256 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 257 }; 258 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 259 260 GlobalProperty pc_compat_2_3[] = { 261 PC_CPU_MODEL_IDS("2.3.0") 262 { TYPE_X86_CPU, "arat", "off" }, 263 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 264 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 265 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 266 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 267 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 270 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 281 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 282 }; 283 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 284 285 GlobalProperty pc_compat_2_2[] = { 286 PC_CPU_MODEL_IDS("2.2.0") 287 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 302 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 304 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 305 }; 306 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 307 308 GlobalProperty pc_compat_2_1[] = { 309 PC_CPU_MODEL_IDS("2.1.0") 310 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 312 }; 313 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 314 315 GlobalProperty pc_compat_2_0[] = { 316 PC_CPU_MODEL_IDS("2.0.0") 317 { "virtio-scsi-pci", "any_layout", "off" }, 318 { "PIIX4_PM", "memory-hotplug-support", "off" }, 319 { "apic", "version", "0x11" }, 320 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 321 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 322 { "pci-serial", "prog_if", "0" }, 323 { "pci-serial-2x", "prog_if", "0" }, 324 { "pci-serial-4x", "prog_if", "0" }, 325 { "virtio-net-pci", "guest_announce", "off" }, 326 { "ICH9-LPC", "memory-hotplug-support", "off" }, 327 }; 328 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 329 330 GlobalProperty pc_compat_1_7[] = { 331 PC_CPU_MODEL_IDS("1.7.0") 332 { TYPE_USB_DEVICE, "msos-desc", "no" }, 333 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 334 { "hpet", HPET_INTCAP, "4" }, 335 }; 336 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 337 338 GlobalProperty pc_compat_1_6[] = { 339 PC_CPU_MODEL_IDS("1.6.0") 340 { "e1000", "mitigation", "off" }, 341 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 342 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 343 { "i440FX-pcihost", "short_root_bus", "1" }, 344 { "q35-pcihost", "short_root_bus", "1" }, 345 }; 346 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 347 348 GlobalProperty pc_compat_1_5[] = { 349 PC_CPU_MODEL_IDS("1.5.0") 350 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 351 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 352 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 353 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 354 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 355 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 356 { "virtio-net-pci", "any_layout", "off" }, 357 { TYPE_X86_CPU, "pmu", "on" }, 358 { "i440FX-pcihost", "short_root_bus", "0" }, 359 { "q35-pcihost", "short_root_bus", "0" }, 360 }; 361 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 362 363 GlobalProperty pc_compat_1_4[] = { 364 PC_CPU_MODEL_IDS("1.4.0") 365 { "scsi-hd", "discard_granularity", "0" }, 366 { "scsi-cd", "discard_granularity", "0" }, 367 { "ide-hd", "discard_granularity", "0" }, 368 { "ide-cd", "discard_granularity", "0" }, 369 { "virtio-blk-pci", "discard_granularity", "0" }, 370 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 371 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 372 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 373 { "e1000", "romfile", "pxe-e1000.rom" }, 374 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 375 { "pcnet", "romfile", "pxe-pcnet.rom" }, 376 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 377 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 378 { "486-" TYPE_X86_CPU, "model", "0" }, 379 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 380 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 381 }; 382 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 383 384 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 385 { 386 GSIState *s; 387 388 s = g_new0(GSIState, 1); 389 if (kvm_ioapic_in_kernel()) { 390 kvm_pc_setup_irq_routing(pci_enabled); 391 } 392 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 393 394 return s; 395 } 396 397 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 398 unsigned size) 399 { 400 } 401 402 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 403 { 404 return 0xffffffffffffffffULL; 405 } 406 407 /* MSDOS compatibility mode FPU exception support */ 408 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 409 unsigned size) 410 { 411 if (tcg_enabled()) { 412 cpu_set_ignne(); 413 } 414 } 415 416 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 417 { 418 return 0xffffffffffffffffULL; 419 } 420 421 /* PC cmos mappings */ 422 423 #define REG_EQUIPMENT_BYTE 0x14 424 425 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 426 int16_t cylinders, int8_t heads, int8_t sectors) 427 { 428 rtc_set_memory(s, type_ofs, 47); 429 rtc_set_memory(s, info_ofs, cylinders); 430 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 431 rtc_set_memory(s, info_ofs + 2, heads); 432 rtc_set_memory(s, info_ofs + 3, 0xff); 433 rtc_set_memory(s, info_ofs + 4, 0xff); 434 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 435 rtc_set_memory(s, info_ofs + 6, cylinders); 436 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 437 rtc_set_memory(s, info_ofs + 8, sectors); 438 } 439 440 /* convert boot_device letter to something recognizable by the bios */ 441 static int boot_device2nibble(char boot_device) 442 { 443 switch(boot_device) { 444 case 'a': 445 case 'b': 446 return 0x01; /* floppy boot */ 447 case 'c': 448 return 0x02; /* hard drive boot */ 449 case 'd': 450 return 0x03; /* CD-ROM boot */ 451 case 'n': 452 return 0x04; /* Network boot */ 453 } 454 return 0; 455 } 456 457 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 458 { 459 #define PC_MAX_BOOT_DEVICES 3 460 int nbds, bds[3] = { 0, }; 461 int i; 462 463 nbds = strlen(boot_device); 464 if (nbds > PC_MAX_BOOT_DEVICES) { 465 error_setg(errp, "Too many boot devices for PC"); 466 return; 467 } 468 for (i = 0; i < nbds; i++) { 469 bds[i] = boot_device2nibble(boot_device[i]); 470 if (bds[i] == 0) { 471 error_setg(errp, "Invalid boot device for PC: '%c'", 472 boot_device[i]); 473 return; 474 } 475 } 476 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 477 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 478 } 479 480 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 481 { 482 set_boot_dev(opaque, boot_device, errp); 483 } 484 485 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 486 { 487 int val, nb, i; 488 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 489 FLOPPY_DRIVE_TYPE_NONE }; 490 491 /* floppy type */ 492 if (floppy) { 493 for (i = 0; i < 2; i++) { 494 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 495 } 496 } 497 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 498 cmos_get_fd_drive_type(fd_type[1]); 499 rtc_set_memory(rtc_state, 0x10, val); 500 501 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 502 nb = 0; 503 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 504 nb++; 505 } 506 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 507 nb++; 508 } 509 switch (nb) { 510 case 0: 511 break; 512 case 1: 513 val |= 0x01; /* 1 drive, ready for boot */ 514 break; 515 case 2: 516 val |= 0x41; /* 2 drives, ready for boot */ 517 break; 518 } 519 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 520 } 521 522 typedef struct pc_cmos_init_late_arg { 523 ISADevice *rtc_state; 524 BusState *idebus[2]; 525 } pc_cmos_init_late_arg; 526 527 typedef struct check_fdc_state { 528 ISADevice *floppy; 529 bool multiple; 530 } CheckFdcState; 531 532 static int check_fdc(Object *obj, void *opaque) 533 { 534 CheckFdcState *state = opaque; 535 Object *fdc; 536 uint32_t iobase; 537 Error *local_err = NULL; 538 539 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 540 if (!fdc) { 541 return 0; 542 } 543 544 iobase = object_property_get_uint(obj, "iobase", &local_err); 545 if (local_err || iobase != 0x3f0) { 546 error_free(local_err); 547 return 0; 548 } 549 550 if (state->floppy) { 551 state->multiple = true; 552 } else { 553 state->floppy = ISA_DEVICE(obj); 554 } 555 return 0; 556 } 557 558 static const char * const fdc_container_path[] = { 559 "/unattached", "/peripheral", "/peripheral-anon" 560 }; 561 562 /* 563 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 564 * and ACPI objects. 565 */ 566 ISADevice *pc_find_fdc0(void) 567 { 568 int i; 569 Object *container; 570 CheckFdcState state = { 0 }; 571 572 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 573 container = container_get(qdev_get_machine(), fdc_container_path[i]); 574 object_child_foreach(container, check_fdc, &state); 575 } 576 577 if (state.multiple) { 578 warn_report("multiple floppy disk controllers with " 579 "iobase=0x3f0 have been found"); 580 error_printf("the one being picked for CMOS setup might not reflect " 581 "your intent"); 582 } 583 584 return state.floppy; 585 } 586 587 static void pc_cmos_init_late(void *opaque) 588 { 589 pc_cmos_init_late_arg *arg = opaque; 590 ISADevice *s = arg->rtc_state; 591 int16_t cylinders; 592 int8_t heads, sectors; 593 int val; 594 int i, trans; 595 596 val = 0; 597 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 598 &cylinders, &heads, §ors) >= 0) { 599 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 600 val |= 0xf0; 601 } 602 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 603 &cylinders, &heads, §ors) >= 0) { 604 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 605 val |= 0x0f; 606 } 607 rtc_set_memory(s, 0x12, val); 608 609 val = 0; 610 for (i = 0; i < 4; i++) { 611 /* NOTE: ide_get_geometry() returns the physical 612 geometry. It is always such that: 1 <= sects <= 63, 1 613 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 614 geometry can be different if a translation is done. */ 615 if (arg->idebus[i / 2] && 616 ide_get_geometry(arg->idebus[i / 2], i % 2, 617 &cylinders, &heads, §ors) >= 0) { 618 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 619 assert((trans & ~3) == 0); 620 val |= trans << (i * 2); 621 } 622 } 623 rtc_set_memory(s, 0x39, val); 624 625 pc_cmos_init_floppy(s, pc_find_fdc0()); 626 627 qemu_unregister_reset(pc_cmos_init_late, opaque); 628 } 629 630 void pc_cmos_init(PCMachineState *pcms, 631 BusState *idebus0, BusState *idebus1, 632 ISADevice *s) 633 { 634 int val; 635 static pc_cmos_init_late_arg arg; 636 X86MachineState *x86ms = X86_MACHINE(pcms); 637 638 /* various important CMOS locations needed by PC/Bochs bios */ 639 640 /* memory size */ 641 /* base memory (first MiB) */ 642 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 643 rtc_set_memory(s, 0x15, val); 644 rtc_set_memory(s, 0x16, val >> 8); 645 /* extended memory (next 64MiB) */ 646 if (x86ms->below_4g_mem_size > 1 * MiB) { 647 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 648 } else { 649 val = 0; 650 } 651 if (val > 65535) 652 val = 65535; 653 rtc_set_memory(s, 0x17, val); 654 rtc_set_memory(s, 0x18, val >> 8); 655 rtc_set_memory(s, 0x30, val); 656 rtc_set_memory(s, 0x31, val >> 8); 657 /* memory between 16MiB and 4GiB */ 658 if (x86ms->below_4g_mem_size > 16 * MiB) { 659 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 660 } else { 661 val = 0; 662 } 663 if (val > 65535) 664 val = 65535; 665 rtc_set_memory(s, 0x34, val); 666 rtc_set_memory(s, 0x35, val >> 8); 667 /* memory above 4GiB */ 668 val = x86ms->above_4g_mem_size / 65536; 669 rtc_set_memory(s, 0x5b, val); 670 rtc_set_memory(s, 0x5c, val >> 8); 671 rtc_set_memory(s, 0x5d, val >> 16); 672 673 object_property_add_link(OBJECT(pcms), "rtc_state", 674 TYPE_ISA_DEVICE, 675 (Object **)&x86ms->rtc, 676 object_property_allow_set_link, 677 OBJ_PROP_LINK_STRONG); 678 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 679 &error_abort); 680 681 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 682 683 val = 0; 684 val |= 0x02; /* FPU is there */ 685 val |= 0x04; /* PS/2 mouse installed */ 686 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 687 688 /* hard drives and FDC */ 689 arg.rtc_state = s; 690 arg.idebus[0] = idebus0; 691 arg.idebus[1] = idebus1; 692 qemu_register_reset(pc_cmos_init_late, &arg); 693 } 694 695 static void handle_a20_line_change(void *opaque, int irq, int level) 696 { 697 X86CPU *cpu = opaque; 698 699 /* XXX: send to all CPUs ? */ 700 /* XXX: add logic to handle multiple A20 line sources */ 701 x86_cpu_set_a20(cpu, level); 702 } 703 704 #define NE2000_NB_MAX 6 705 706 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 707 0x280, 0x380 }; 708 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 709 710 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 711 { 712 static int nb_ne2k = 0; 713 714 if (nb_ne2k == NE2000_NB_MAX) 715 return; 716 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 717 ne2000_irq[nb_ne2k], nd); 718 nb_ne2k++; 719 } 720 721 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 722 { 723 X86CPU *cpu = opaque; 724 725 if (level) { 726 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 727 } 728 } 729 730 static 731 void pc_machine_done(Notifier *notifier, void *data) 732 { 733 PCMachineState *pcms = container_of(notifier, 734 PCMachineState, machine_done); 735 X86MachineState *x86ms = X86_MACHINE(pcms); 736 737 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 738 &error_fatal); 739 740 if (pcms->cxl_devices_state.is_enabled) { 741 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 742 } 743 744 /* set the number of CPUs */ 745 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 746 747 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 748 749 acpi_setup(); 750 if (x86ms->fw_cfg) { 751 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 752 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 753 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 754 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 755 } 756 } 757 758 void pc_guest_info_init(PCMachineState *pcms) 759 { 760 X86MachineState *x86ms = X86_MACHINE(pcms); 761 762 x86ms->apic_xrupt_override = true; 763 pcms->machine_done.notify = pc_machine_done; 764 qemu_add_machine_init_done_notifier(&pcms->machine_done); 765 } 766 767 /* setup pci memory address space mapping into system address space */ 768 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 769 MemoryRegion *pci_address_space) 770 { 771 /* Set to lower priority than RAM */ 772 memory_region_add_subregion_overlap(system_memory, 0x0, 773 pci_address_space, -1); 774 } 775 776 void xen_load_linux(PCMachineState *pcms) 777 { 778 int i; 779 FWCfgState *fw_cfg; 780 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 781 X86MachineState *x86ms = X86_MACHINE(pcms); 782 783 assert(MACHINE(pcms)->kernel_filename != NULL); 784 785 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 786 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 787 rom_set_fw(fw_cfg); 788 789 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 790 pcmc->pvh_enabled); 791 for (i = 0; i < nb_option_roms; i++) { 792 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 793 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 794 !strcmp(option_rom[i].name, "pvh.bin") || 795 !strcmp(option_rom[i].name, "multiboot.bin") || 796 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 797 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 798 } 799 x86ms->fw_cfg = fw_cfg; 800 } 801 802 #define PC_ROM_MIN_VGA 0xc0000 803 #define PC_ROM_MIN_OPTION 0xc8000 804 #define PC_ROM_MAX 0xe0000 805 #define PC_ROM_ALIGN 0x800 806 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 807 808 void pc_memory_init(PCMachineState *pcms, 809 MemoryRegion *system_memory, 810 MemoryRegion *rom_memory, 811 MemoryRegion **ram_memory) 812 { 813 int linux_boot, i; 814 MemoryRegion *option_rom_mr; 815 MemoryRegion *ram_below_4g, *ram_above_4g; 816 FWCfgState *fw_cfg; 817 MachineState *machine = MACHINE(pcms); 818 MachineClass *mc = MACHINE_GET_CLASS(machine); 819 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 820 X86MachineState *x86ms = X86_MACHINE(pcms); 821 hwaddr cxl_base, cxl_resv_end = 0; 822 823 assert(machine->ram_size == x86ms->below_4g_mem_size + 824 x86ms->above_4g_mem_size); 825 826 linux_boot = (machine->kernel_filename != NULL); 827 828 /* 829 * Split single memory region and use aliases to address portions of it, 830 * done for backwards compatibility with older qemus. 831 */ 832 *ram_memory = machine->ram; 833 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 834 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 835 0, x86ms->below_4g_mem_size); 836 memory_region_add_subregion(system_memory, 0, ram_below_4g); 837 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 838 if (x86ms->above_4g_mem_size > 0) { 839 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 840 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 841 machine->ram, 842 x86ms->below_4g_mem_size, 843 x86ms->above_4g_mem_size); 844 memory_region_add_subregion(system_memory, 0x100000000ULL, 845 ram_above_4g); 846 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 847 } 848 849 if (pcms->sgx_epc.size != 0) { 850 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 851 } 852 853 if (!pcmc->has_reserved_memory && 854 (machine->ram_slots || 855 (machine->maxram_size > machine->ram_size))) { 856 857 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 858 mc->name); 859 exit(EXIT_FAILURE); 860 } 861 862 /* always allocate the device memory information */ 863 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 864 865 /* initialize device memory address space */ 866 if (pcmc->has_reserved_memory && 867 (machine->ram_size < machine->maxram_size)) { 868 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 869 870 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 871 error_report("unsupported amount of memory slots: %"PRIu64, 872 machine->ram_slots); 873 exit(EXIT_FAILURE); 874 } 875 876 if (QEMU_ALIGN_UP(machine->maxram_size, 877 TARGET_PAGE_SIZE) != machine->maxram_size) { 878 error_report("maximum memory size must by aligned to multiple of " 879 "%d bytes", TARGET_PAGE_SIZE); 880 exit(EXIT_FAILURE); 881 } 882 883 if (pcms->sgx_epc.size != 0) { 884 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 885 } else { 886 machine->device_memory->base = 887 0x100000000ULL + x86ms->above_4g_mem_size; 888 } 889 890 machine->device_memory->base = 891 ROUND_UP(machine->device_memory->base, 1 * GiB); 892 893 if (pcmc->enforce_aligned_dimm) { 894 /* size device region assuming 1G page max alignment per slot */ 895 device_mem_size += (1 * GiB) * machine->ram_slots; 896 } 897 898 if ((machine->device_memory->base + device_mem_size) < 899 device_mem_size) { 900 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 901 machine->maxram_size); 902 exit(EXIT_FAILURE); 903 } 904 905 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 906 "device-memory", device_mem_size); 907 memory_region_add_subregion(system_memory, machine->device_memory->base, 908 &machine->device_memory->mr); 909 } 910 911 if (pcms->cxl_devices_state.is_enabled) { 912 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 913 hwaddr cxl_size = MiB; 914 915 if (pcmc->has_reserved_memory && machine->device_memory->base) { 916 cxl_base = machine->device_memory->base; 917 if (!pcmc->broken_reserved_end) { 918 cxl_base += memory_region_size(&machine->device_memory->mr); 919 } 920 } else if (pcms->sgx_epc.size != 0) { 921 cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc); 922 } else { 923 cxl_base = 0x100000000ULL + x86ms->above_4g_mem_size; 924 } 925 926 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); 927 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 928 memory_region_add_subregion(system_memory, cxl_base, mr); 929 cxl_resv_end = cxl_base + cxl_size; 930 if (pcms->cxl_devices_state.fixed_windows) { 931 hwaddr cxl_fmw_base; 932 GList *it; 933 934 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 935 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 936 CXLFixedWindow *fw = it->data; 937 938 fw->base = cxl_fmw_base; 939 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 940 "cxl-fixed-memory-region", fw->size); 941 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 942 e820_add_entry(fw->base, fw->size, E820_RESERVED); 943 cxl_fmw_base += fw->size; 944 cxl_resv_end = cxl_fmw_base; 945 } 946 } 947 } 948 949 /* Initialize PC system firmware */ 950 pc_system_firmware_init(pcms, rom_memory); 951 952 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 953 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 954 &error_fatal); 955 if (pcmc->pci_enabled) { 956 memory_region_set_readonly(option_rom_mr, true); 957 } 958 memory_region_add_subregion_overlap(rom_memory, 959 PC_ROM_MIN_VGA, 960 option_rom_mr, 961 1); 962 963 fw_cfg = fw_cfg_arch_create(machine, 964 x86ms->boot_cpus, x86ms->apic_id_limit); 965 966 rom_set_fw(fw_cfg); 967 968 if (pcmc->has_reserved_memory && machine->device_memory->base) { 969 uint64_t *val = g_malloc(sizeof(*val)); 970 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 971 uint64_t res_mem_end = machine->device_memory->base; 972 973 if (!pcmc->broken_reserved_end) { 974 res_mem_end += memory_region_size(&machine->device_memory->mr); 975 } 976 977 if (pcms->cxl_devices_state.is_enabled) { 978 res_mem_end = cxl_resv_end; 979 } 980 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 981 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 982 } 983 984 if (linux_boot) { 985 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 986 pcmc->pvh_enabled); 987 } 988 989 for (i = 0; i < nb_option_roms; i++) { 990 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 991 } 992 x86ms->fw_cfg = fw_cfg; 993 994 /* Init default IOAPIC address space */ 995 x86ms->ioapic_as = &address_space_memory; 996 997 /* Init ACPI memory hotplug IO base address */ 998 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 999 } 1000 1001 /* 1002 * The 64bit pci hole starts after "above 4G RAM" and 1003 * potentially the space reserved for memory hotplug. 1004 */ 1005 uint64_t pc_pci_hole64_start(void) 1006 { 1007 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1008 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1009 MachineState *ms = MACHINE(pcms); 1010 X86MachineState *x86ms = X86_MACHINE(pcms); 1011 uint64_t hole64_start = 0; 1012 1013 if (pcms->cxl_devices_state.host_mr.addr) { 1014 hole64_start = pcms->cxl_devices_state.host_mr.addr + 1015 memory_region_size(&pcms->cxl_devices_state.host_mr); 1016 if (pcms->cxl_devices_state.fixed_windows) { 1017 GList *it; 1018 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1019 CXLFixedWindow *fw = it->data; 1020 hole64_start = fw->mr.addr + memory_region_size(&fw->mr); 1021 } 1022 } 1023 } else if (pcmc->has_reserved_memory && ms->device_memory->base) { 1024 hole64_start = ms->device_memory->base; 1025 if (!pcmc->broken_reserved_end) { 1026 hole64_start += memory_region_size(&ms->device_memory->mr); 1027 } 1028 } else if (pcms->sgx_epc.size != 0) { 1029 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 1030 } else { 1031 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1032 } 1033 1034 return ROUND_UP(hole64_start, 1 * GiB); 1035 } 1036 1037 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1038 { 1039 DeviceState *dev = NULL; 1040 1041 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1042 if (pci_bus) { 1043 PCIDevice *pcidev = pci_vga_init(pci_bus); 1044 dev = pcidev ? &pcidev->qdev : NULL; 1045 } else if (isa_bus) { 1046 ISADevice *isadev = isa_vga_init(isa_bus); 1047 dev = isadev ? DEVICE(isadev) : NULL; 1048 } 1049 rom_reset_order_override(); 1050 return dev; 1051 } 1052 1053 static const MemoryRegionOps ioport80_io_ops = { 1054 .write = ioport80_write, 1055 .read = ioport80_read, 1056 .endianness = DEVICE_NATIVE_ENDIAN, 1057 .impl = { 1058 .min_access_size = 1, 1059 .max_access_size = 1, 1060 }, 1061 }; 1062 1063 static const MemoryRegionOps ioportF0_io_ops = { 1064 .write = ioportF0_write, 1065 .read = ioportF0_read, 1066 .endianness = DEVICE_NATIVE_ENDIAN, 1067 .impl = { 1068 .min_access_size = 1, 1069 .max_access_size = 1, 1070 }, 1071 }; 1072 1073 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1074 bool create_i8042, bool no_vmport) 1075 { 1076 int i; 1077 DriveInfo *fd[MAX_FD]; 1078 qemu_irq *a20_line; 1079 ISADevice *fdc, *i8042, *port92, *vmmouse; 1080 1081 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1082 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1083 1084 for (i = 0; i < MAX_FD; i++) { 1085 fd[i] = drive_get(IF_FLOPPY, 0, i); 1086 create_fdctrl |= !!fd[i]; 1087 } 1088 if (create_fdctrl) { 1089 fdc = isa_new(TYPE_ISA_FDC); 1090 if (fdc) { 1091 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1092 isa_fdc_init_drives(fdc, fd); 1093 } 1094 } 1095 1096 if (!create_i8042) { 1097 return; 1098 } 1099 1100 i8042 = isa_create_simple(isa_bus, "i8042"); 1101 if (!no_vmport) { 1102 isa_create_simple(isa_bus, TYPE_VMPORT); 1103 vmmouse = isa_try_new("vmmouse"); 1104 } else { 1105 vmmouse = NULL; 1106 } 1107 if (vmmouse) { 1108 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1109 &error_abort); 1110 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1111 } 1112 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1113 1114 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1115 i8042_setup_a20_line(i8042, a20_line[0]); 1116 qdev_connect_gpio_out_named(DEVICE(port92), 1117 PORT92_A20_LINE, 0, a20_line[1]); 1118 g_free(a20_line); 1119 } 1120 1121 void pc_basic_device_init(struct PCMachineState *pcms, 1122 ISABus *isa_bus, qemu_irq *gsi, 1123 ISADevice **rtc_state, 1124 bool create_fdctrl, 1125 uint32_t hpet_irqs) 1126 { 1127 int i; 1128 DeviceState *hpet = NULL; 1129 int pit_isa_irq = 0; 1130 qemu_irq pit_alt_irq = NULL; 1131 qemu_irq rtc_irq = NULL; 1132 ISADevice *pit = NULL; 1133 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1134 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1135 X86MachineState *x86ms = X86_MACHINE(pcms); 1136 1137 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1138 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1139 1140 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1141 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1142 1143 /* 1144 * Check if an HPET shall be created. 1145 * 1146 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1147 * when the HPET wants to take over. Thus we have to disable the latter. 1148 */ 1149 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1150 kvm_has_pit_state2())) { 1151 hpet = qdev_try_new(TYPE_HPET); 1152 if (!hpet) { 1153 error_report("couldn't create HPET device"); 1154 exit(1); 1155 } 1156 /* 1157 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1158 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1159 * IRQ2. 1160 */ 1161 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1162 HPET_INTCAP, NULL); 1163 if (!compat) { 1164 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1165 } 1166 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1167 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1168 1169 for (i = 0; i < GSI_NUM_PINS; i++) { 1170 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1171 } 1172 pit_isa_irq = -1; 1173 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1174 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1175 } 1176 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1177 1178 qemu_register_boot_set(pc_boot_set, *rtc_state); 1179 1180 if (!xen_enabled() && 1181 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1182 if (kvm_pit_in_kernel()) { 1183 pit = kvm_pit_init(isa_bus, 0x40); 1184 } else { 1185 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1186 } 1187 if (hpet) { 1188 /* connect PIT to output control line of the HPET */ 1189 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1190 } 1191 pcspk_init(pcms->pcspk, isa_bus, pit); 1192 } 1193 1194 i8257_dma_init(isa_bus, 0); 1195 1196 /* Super I/O */ 1197 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1198 pcms->vmport != ON_OFF_AUTO_ON); 1199 } 1200 1201 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1202 { 1203 int i; 1204 1205 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1206 for (i = 0; i < nb_nics; i++) { 1207 NICInfo *nd = &nd_table[i]; 1208 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1209 1210 if (g_str_equal(model, "ne2k_isa")) { 1211 pc_init_ne2k_isa(isa_bus, nd); 1212 } else { 1213 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1214 } 1215 } 1216 rom_reset_order_override(); 1217 } 1218 1219 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1220 { 1221 qemu_irq *i8259; 1222 1223 if (kvm_pic_in_kernel()) { 1224 i8259 = kvm_i8259_init(isa_bus); 1225 } else if (xen_enabled()) { 1226 i8259 = xen_interrupt_controller_init(); 1227 } else { 1228 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1229 } 1230 1231 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1232 i8259_irqs[i] = i8259[i]; 1233 } 1234 1235 g_free(i8259); 1236 } 1237 1238 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1239 Error **errp) 1240 { 1241 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1242 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1243 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1244 const MachineState *ms = MACHINE(hotplug_dev); 1245 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1246 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1247 Error *local_err = NULL; 1248 1249 /* 1250 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1251 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1252 * addition to cover this case. 1253 */ 1254 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1255 error_setg(errp, 1256 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1257 return; 1258 } 1259 1260 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1261 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1262 return; 1263 } 1264 1265 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1266 if (local_err) { 1267 error_propagate(errp, local_err); 1268 return; 1269 } 1270 1271 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1272 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1273 } 1274 1275 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1276 DeviceState *dev, Error **errp) 1277 { 1278 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1279 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1280 MachineState *ms = MACHINE(hotplug_dev); 1281 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1282 1283 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1284 1285 if (is_nvdimm) { 1286 nvdimm_plug(ms->nvdimms_state); 1287 } 1288 1289 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1290 } 1291 1292 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1293 DeviceState *dev, Error **errp) 1294 { 1295 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1296 1297 /* 1298 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1299 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1300 * addition to cover this case. 1301 */ 1302 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1303 error_setg(errp, 1304 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1305 return; 1306 } 1307 1308 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1309 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1310 return; 1311 } 1312 1313 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1314 errp); 1315 } 1316 1317 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1318 DeviceState *dev, Error **errp) 1319 { 1320 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1321 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1322 Error *local_err = NULL; 1323 1324 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1325 if (local_err) { 1326 goto out; 1327 } 1328 1329 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1330 qdev_unrealize(dev); 1331 out: 1332 error_propagate(errp, local_err); 1333 } 1334 1335 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1336 DeviceState *dev, Error **errp) 1337 { 1338 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1339 Error *local_err = NULL; 1340 1341 if (!hotplug_dev2 && dev->hotplugged) { 1342 /* 1343 * Without a bus hotplug handler, we cannot control the plug/unplug 1344 * order. We should never reach this point when hotplugging on x86, 1345 * however, better add a safety net. 1346 */ 1347 error_setg(errp, "hotplug of virtio based memory devices not supported" 1348 " on this bus."); 1349 return; 1350 } 1351 /* 1352 * First, see if we can plug this memory device at all. If that 1353 * succeeds, branch of to the actual hotplug handler. 1354 */ 1355 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1356 &local_err); 1357 if (!local_err && hotplug_dev2) { 1358 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1359 } 1360 error_propagate(errp, local_err); 1361 } 1362 1363 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1364 DeviceState *dev, Error **errp) 1365 { 1366 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1367 Error *local_err = NULL; 1368 1369 /* 1370 * Plug the memory device first and then branch off to the actual 1371 * hotplug handler. If that one fails, we can easily undo the memory 1372 * device bits. 1373 */ 1374 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1375 if (hotplug_dev2) { 1376 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1377 if (local_err) { 1378 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1379 } 1380 } 1381 error_propagate(errp, local_err); 1382 } 1383 1384 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1385 DeviceState *dev, Error **errp) 1386 { 1387 /* We don't support hot unplug of virtio based memory devices */ 1388 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1389 } 1390 1391 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1392 DeviceState *dev, Error **errp) 1393 { 1394 /* We don't support hot unplug of virtio based memory devices */ 1395 } 1396 1397 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1398 DeviceState *dev, Error **errp) 1399 { 1400 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1401 pc_memory_pre_plug(hotplug_dev, dev, errp); 1402 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1403 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1404 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1405 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1406 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1408 /* Declare the APIC range as the reserved MSI region */ 1409 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1410 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1411 1412 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1413 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1414 resv_prop_str, errp); 1415 g_free(resv_prop_str); 1416 } 1417 1418 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1419 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1420 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1421 1422 if (pcms->iommu) { 1423 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1424 "for x86 yet."); 1425 return; 1426 } 1427 pcms->iommu = dev; 1428 } 1429 } 1430 1431 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1432 DeviceState *dev, Error **errp) 1433 { 1434 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1435 pc_memory_plug(hotplug_dev, dev, errp); 1436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1437 x86_cpu_plug(hotplug_dev, dev, errp); 1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1439 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1440 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1441 } 1442 } 1443 1444 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1445 DeviceState *dev, Error **errp) 1446 { 1447 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1448 pc_memory_unplug_request(hotplug_dev, dev, errp); 1449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1450 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1452 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1453 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1454 } else { 1455 error_setg(errp, "acpi: device unplug request for not supported device" 1456 " type: %s", object_get_typename(OBJECT(dev))); 1457 } 1458 } 1459 1460 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1461 DeviceState *dev, Error **errp) 1462 { 1463 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1464 pc_memory_unplug(hotplug_dev, dev, errp); 1465 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1466 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1467 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1468 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1469 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1470 } else { 1471 error_setg(errp, "acpi: device unplug for not supported device" 1472 " type: %s", object_get_typename(OBJECT(dev))); 1473 } 1474 } 1475 1476 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1477 DeviceState *dev) 1478 { 1479 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1480 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1481 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1482 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1483 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1484 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1485 return HOTPLUG_HANDLER(machine); 1486 } 1487 1488 return NULL; 1489 } 1490 1491 static void 1492 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1493 const char *name, void *opaque, 1494 Error **errp) 1495 { 1496 MachineState *ms = MACHINE(obj); 1497 int64_t value = 0; 1498 1499 if (ms->device_memory) { 1500 value = memory_region_size(&ms->device_memory->mr); 1501 } 1502 1503 visit_type_int(v, name, &value, errp); 1504 } 1505 1506 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1507 void *opaque, Error **errp) 1508 { 1509 PCMachineState *pcms = PC_MACHINE(obj); 1510 OnOffAuto vmport = pcms->vmport; 1511 1512 visit_type_OnOffAuto(v, name, &vmport, errp); 1513 } 1514 1515 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1516 void *opaque, Error **errp) 1517 { 1518 PCMachineState *pcms = PC_MACHINE(obj); 1519 1520 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1521 } 1522 1523 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1524 { 1525 PCMachineState *pcms = PC_MACHINE(obj); 1526 1527 return pcms->smbus_enabled; 1528 } 1529 1530 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1531 { 1532 PCMachineState *pcms = PC_MACHINE(obj); 1533 1534 pcms->smbus_enabled = value; 1535 } 1536 1537 static bool pc_machine_get_sata(Object *obj, Error **errp) 1538 { 1539 PCMachineState *pcms = PC_MACHINE(obj); 1540 1541 return pcms->sata_enabled; 1542 } 1543 1544 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 1548 pcms->sata_enabled = value; 1549 } 1550 1551 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1552 { 1553 PCMachineState *pcms = PC_MACHINE(obj); 1554 1555 return pcms->hpet_enabled; 1556 } 1557 1558 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1559 { 1560 PCMachineState *pcms = PC_MACHINE(obj); 1561 1562 pcms->hpet_enabled = value; 1563 } 1564 1565 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1566 { 1567 PCMachineState *pcms = PC_MACHINE(obj); 1568 1569 return pcms->i8042_enabled; 1570 } 1571 1572 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 1576 pcms->i8042_enabled = value; 1577 } 1578 1579 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 1583 return pcms->default_bus_bypass_iommu; 1584 } 1585 1586 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1587 Error **errp) 1588 { 1589 PCMachineState *pcms = PC_MACHINE(obj); 1590 1591 pcms->default_bus_bypass_iommu = value; 1592 } 1593 1594 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1595 void *opaque, Error **errp) 1596 { 1597 PCMachineState *pcms = PC_MACHINE(obj); 1598 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1599 1600 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1601 } 1602 1603 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1604 void *opaque, Error **errp) 1605 { 1606 PCMachineState *pcms = PC_MACHINE(obj); 1607 1608 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1609 } 1610 1611 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1612 const char *name, void *opaque, 1613 Error **errp) 1614 { 1615 PCMachineState *pcms = PC_MACHINE(obj); 1616 uint64_t value = pcms->max_ram_below_4g; 1617 1618 visit_type_size(v, name, &value, errp); 1619 } 1620 1621 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1622 const char *name, void *opaque, 1623 Error **errp) 1624 { 1625 PCMachineState *pcms = PC_MACHINE(obj); 1626 uint64_t value; 1627 1628 if (!visit_type_size(v, name, &value, errp)) { 1629 return; 1630 } 1631 if (value > 4 * GiB) { 1632 error_setg(errp, 1633 "Machine option 'max-ram-below-4g=%"PRIu64 1634 "' expects size less than or equal to 4G", value); 1635 return; 1636 } 1637 1638 if (value < 1 * MiB) { 1639 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1640 "BIOS may not work with less than 1MiB", value); 1641 } 1642 1643 pcms->max_ram_below_4g = value; 1644 } 1645 1646 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1647 const char *name, void *opaque, 1648 Error **errp) 1649 { 1650 PCMachineState *pcms = PC_MACHINE(obj); 1651 uint64_t value = pcms->max_fw_size; 1652 1653 visit_type_size(v, name, &value, errp); 1654 } 1655 1656 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1657 const char *name, void *opaque, 1658 Error **errp) 1659 { 1660 PCMachineState *pcms = PC_MACHINE(obj); 1661 Error *error = NULL; 1662 uint64_t value; 1663 1664 visit_type_size(v, name, &value, &error); 1665 if (error) { 1666 error_propagate(errp, error); 1667 return; 1668 } 1669 1670 /* 1671 * We don't have a theoretically justifiable exact lower bound on the base 1672 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1673 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1674 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1675 * size. 1676 */ 1677 if (value > 16 * MiB) { 1678 error_setg(errp, 1679 "User specified max allowed firmware size %" PRIu64 " is " 1680 "greater than 16MiB. If combined firwmare size exceeds " 1681 "16MiB the system may not boot, or experience intermittent" 1682 "stability issues.", 1683 value); 1684 return; 1685 } 1686 1687 pcms->max_fw_size = value; 1688 } 1689 1690 1691 static void pc_machine_initfn(Object *obj) 1692 { 1693 PCMachineState *pcms = PC_MACHINE(obj); 1694 1695 #ifdef CONFIG_VMPORT 1696 pcms->vmport = ON_OFF_AUTO_AUTO; 1697 #else 1698 pcms->vmport = ON_OFF_AUTO_OFF; 1699 #endif /* CONFIG_VMPORT */ 1700 pcms->max_ram_below_4g = 0; /* use default */ 1701 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1702 1703 /* acpi build is enabled by default if machine supports it */ 1704 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1705 pcms->smbus_enabled = true; 1706 pcms->sata_enabled = true; 1707 pcms->i8042_enabled = true; 1708 pcms->max_fw_size = 8 * MiB; 1709 #ifdef CONFIG_HPET 1710 pcms->hpet_enabled = true; 1711 #endif 1712 pcms->default_bus_bypass_iommu = false; 1713 1714 pc_system_flash_create(pcms); 1715 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1716 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1717 OBJECT(pcms->pcspk), "audiodev"); 1718 cxl_machine_init(obj, &pcms->cxl_devices_state); 1719 } 1720 1721 static void pc_machine_reset(MachineState *machine) 1722 { 1723 CPUState *cs; 1724 X86CPU *cpu; 1725 1726 qemu_devices_reset(); 1727 1728 /* Reset APIC after devices have been reset to cancel 1729 * any changes that qemu_devices_reset() might have done. 1730 */ 1731 CPU_FOREACH(cs) { 1732 cpu = X86_CPU(cs); 1733 1734 if (cpu->apic_state) { 1735 device_legacy_reset(cpu->apic_state); 1736 } 1737 } 1738 } 1739 1740 static void pc_machine_wakeup(MachineState *machine) 1741 { 1742 cpu_synchronize_all_states(); 1743 pc_machine_reset(machine); 1744 cpu_synchronize_all_post_reset(); 1745 } 1746 1747 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1748 { 1749 X86IOMMUState *iommu = x86_iommu_get_default(); 1750 IntelIOMMUState *intel_iommu; 1751 1752 if (iommu && 1753 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1754 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1755 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1756 if (!intel_iommu->caching_mode) { 1757 error_setg(errp, "Device assignment is not allowed without " 1758 "enabling caching-mode=on for Intel IOMMU."); 1759 return false; 1760 } 1761 } 1762 1763 return true; 1764 } 1765 1766 static void pc_machine_class_init(ObjectClass *oc, void *data) 1767 { 1768 MachineClass *mc = MACHINE_CLASS(oc); 1769 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1770 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1771 1772 pcmc->pci_enabled = true; 1773 pcmc->has_acpi_build = true; 1774 pcmc->rsdp_in_ram = true; 1775 pcmc->smbios_defaults = true; 1776 pcmc->smbios_uuid_encoded = true; 1777 pcmc->gigabyte_align = true; 1778 pcmc->has_reserved_memory = true; 1779 pcmc->kvmclock_enabled = true; 1780 pcmc->enforce_aligned_dimm = true; 1781 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1782 * to be used at the moment, 32K should be enough for a while. */ 1783 pcmc->acpi_data_size = 0x20000 + 0x8000; 1784 pcmc->pvh_enabled = true; 1785 pcmc->kvmclock_create_always = true; 1786 assert(!mc->get_hotplug_handler); 1787 mc->get_hotplug_handler = pc_get_hotplug_handler; 1788 mc->hotplug_allowed = pc_hotplug_allowed; 1789 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1790 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1791 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1792 mc->auto_enable_numa_with_memhp = true; 1793 mc->auto_enable_numa_with_memdev = true; 1794 mc->has_hotpluggable_cpus = true; 1795 mc->default_boot_order = "cad"; 1796 mc->block_default_type = IF_IDE; 1797 mc->max_cpus = 255; 1798 mc->reset = pc_machine_reset; 1799 mc->wakeup = pc_machine_wakeup; 1800 hc->pre_plug = pc_machine_device_pre_plug_cb; 1801 hc->plug = pc_machine_device_plug_cb; 1802 hc->unplug_request = pc_machine_device_unplug_request_cb; 1803 hc->unplug = pc_machine_device_unplug_cb; 1804 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1805 mc->nvdimm_supported = true; 1806 mc->smp_props.dies_supported = true; 1807 mc->cxl_supported = true; 1808 mc->default_ram_id = "pc.ram"; 1809 1810 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1811 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1812 NULL, NULL); 1813 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1814 "Maximum ram below the 4G boundary (32bit boundary)"); 1815 1816 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1817 pc_machine_get_device_memory_region_size, NULL, 1818 NULL, NULL); 1819 1820 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1821 pc_machine_get_vmport, pc_machine_set_vmport, 1822 NULL, NULL); 1823 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1824 "Enable vmport (pc & q35)"); 1825 1826 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1827 pc_machine_get_smbus, pc_machine_set_smbus); 1828 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1829 "Enable/disable system management bus"); 1830 1831 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1832 pc_machine_get_sata, pc_machine_set_sata); 1833 object_class_property_set_description(oc, PC_MACHINE_SATA, 1834 "Enable/disable Serial ATA bus"); 1835 1836 object_class_property_add_bool(oc, "hpet", 1837 pc_machine_get_hpet, pc_machine_set_hpet); 1838 object_class_property_set_description(oc, "hpet", 1839 "Enable/disable high precision event timer emulation"); 1840 1841 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1842 pc_machine_get_i8042, pc_machine_set_i8042); 1843 1844 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1845 pc_machine_get_default_bus_bypass_iommu, 1846 pc_machine_set_default_bus_bypass_iommu); 1847 1848 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1849 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1850 NULL, NULL); 1851 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1852 "Maximum combined firmware size"); 1853 1854 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1855 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1856 NULL, NULL); 1857 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1858 "SMBIOS Entry Point type [32, 64]"); 1859 } 1860 1861 static const TypeInfo pc_machine_info = { 1862 .name = TYPE_PC_MACHINE, 1863 .parent = TYPE_X86_MACHINE, 1864 .abstract = true, 1865 .instance_size = sizeof(PCMachineState), 1866 .instance_init = pc_machine_initfn, 1867 .class_size = sizeof(PCMachineClass), 1868 .class_init = pc_machine_class_init, 1869 .interfaces = (InterfaceInfo[]) { 1870 { TYPE_HOTPLUG_HANDLER }, 1871 { } 1872 }, 1873 }; 1874 1875 static void pc_machine_register_types(void) 1876 { 1877 type_register_static(&pc_machine_info); 1878 } 1879 1880 type_init(pc_machine_register_types) 1881