1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/acpi/cpu_hotplug.h" 57 #include "hw/cpu/icc_bus.h" 58 #include "hw/boards.h" 59 #include "hw/pci/pci_host.h" 60 #include "acpi-build.h" 61 #include "hw/mem/pc-dimm.h" 62 #include "trace.h" 63 #include "qapi/visitor.h" 64 65 /* debug PC/ISA interrupts */ 66 //#define DEBUG_IRQ 67 68 #ifdef DEBUG_IRQ 69 #define DPRINTF(fmt, ...) \ 70 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 71 #else 72 #define DPRINTF(fmt, ...) 73 #endif 74 75 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 76 * (128K) and other BIOS datastructures (less than 4K reported to be used at 77 * the moment, 32K should be enough for a while). */ 78 static unsigned acpi_data_size = 0x20000 + 0x8000; 79 void pc_set_legacy_acpi_data_size(void) 80 { 81 acpi_data_size = 0x10000; 82 } 83 84 #define BIOS_CFG_IOPORT 0x510 85 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 86 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 87 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 88 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 89 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 90 91 #define E820_NR_ENTRIES 16 92 93 struct e820_entry { 94 uint64_t address; 95 uint64_t length; 96 uint32_t type; 97 } QEMU_PACKED __attribute((__aligned__(4))); 98 99 struct e820_table { 100 uint32_t count; 101 struct e820_entry entry[E820_NR_ENTRIES]; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 static struct e820_table e820_reserve; 105 static struct e820_entry *e820_table; 106 static unsigned e820_entries; 107 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 108 109 void gsi_handler(void *opaque, int n, int level) 110 { 111 GSIState *s = opaque; 112 113 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 114 if (n < ISA_NUM_IRQS) { 115 qemu_set_irq(s->i8259_irq[n], level); 116 } 117 qemu_set_irq(s->ioapic_irq[n], level); 118 } 119 120 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 121 unsigned size) 122 { 123 } 124 125 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 126 { 127 return 0xffffffffffffffffULL; 128 } 129 130 /* MSDOS compatibility mode FPU exception support */ 131 static qemu_irq ferr_irq; 132 133 void pc_register_ferr_irq(qemu_irq irq) 134 { 135 ferr_irq = irq; 136 } 137 138 /* XXX: add IGNNE support */ 139 void cpu_set_ferr(CPUX86State *s) 140 { 141 qemu_irq_raise(ferr_irq); 142 } 143 144 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 145 unsigned size) 146 { 147 qemu_irq_lower(ferr_irq); 148 } 149 150 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 151 { 152 return 0xffffffffffffffffULL; 153 } 154 155 /* TSC handling */ 156 uint64_t cpu_get_tsc(CPUX86State *env) 157 { 158 return cpu_get_ticks(); 159 } 160 161 /* SMM support */ 162 163 static cpu_set_smm_t smm_set; 164 static void *smm_arg; 165 166 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 167 { 168 assert(smm_set == NULL); 169 assert(smm_arg == NULL); 170 smm_set = callback; 171 smm_arg = arg; 172 } 173 174 void cpu_smm_update(CPUX86State *env) 175 { 176 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 177 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 178 } 179 } 180 181 182 /* IRQ handling */ 183 int cpu_get_pic_interrupt(CPUX86State *env) 184 { 185 X86CPU *cpu = x86_env_get_cpu(env); 186 int intno; 187 188 intno = apic_get_interrupt(cpu->apic_state); 189 if (intno >= 0) { 190 return intno; 191 } 192 /* read the irq from the PIC */ 193 if (!apic_accept_pic_intr(cpu->apic_state)) { 194 return -1; 195 } 196 197 intno = pic_read_irq(isa_pic); 198 return intno; 199 } 200 201 static void pic_irq_request(void *opaque, int irq, int level) 202 { 203 CPUState *cs = first_cpu; 204 X86CPU *cpu = X86_CPU(cs); 205 206 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 207 if (cpu->apic_state) { 208 CPU_FOREACH(cs) { 209 cpu = X86_CPU(cs); 210 if (apic_accept_pic_intr(cpu->apic_state)) { 211 apic_deliver_pic_intr(cpu->apic_state, level); 212 } 213 } 214 } else { 215 if (level) { 216 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 217 } else { 218 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 219 } 220 } 221 } 222 223 /* PC cmos mappings */ 224 225 #define REG_EQUIPMENT_BYTE 0x14 226 227 static int cmos_get_fd_drive_type(FDriveType fd0) 228 { 229 int val; 230 231 switch (fd0) { 232 case FDRIVE_DRV_144: 233 /* 1.44 Mb 3"5 drive */ 234 val = 4; 235 break; 236 case FDRIVE_DRV_288: 237 /* 2.88 Mb 3"5 drive */ 238 val = 5; 239 break; 240 case FDRIVE_DRV_120: 241 /* 1.2 Mb 5"5 drive */ 242 val = 2; 243 break; 244 case FDRIVE_DRV_NONE: 245 default: 246 val = 0; 247 break; 248 } 249 return val; 250 } 251 252 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 253 int16_t cylinders, int8_t heads, int8_t sectors) 254 { 255 rtc_set_memory(s, type_ofs, 47); 256 rtc_set_memory(s, info_ofs, cylinders); 257 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 258 rtc_set_memory(s, info_ofs + 2, heads); 259 rtc_set_memory(s, info_ofs + 3, 0xff); 260 rtc_set_memory(s, info_ofs + 4, 0xff); 261 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 262 rtc_set_memory(s, info_ofs + 6, cylinders); 263 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 264 rtc_set_memory(s, info_ofs + 8, sectors); 265 } 266 267 /* convert boot_device letter to something recognizable by the bios */ 268 static int boot_device2nibble(char boot_device) 269 { 270 switch(boot_device) { 271 case 'a': 272 case 'b': 273 return 0x01; /* floppy boot */ 274 case 'c': 275 return 0x02; /* hard drive boot */ 276 case 'd': 277 return 0x03; /* CD-ROM boot */ 278 case 'n': 279 return 0x04; /* Network boot */ 280 } 281 return 0; 282 } 283 284 static int set_boot_dev(ISADevice *s, const char *boot_device) 285 { 286 #define PC_MAX_BOOT_DEVICES 3 287 int nbds, bds[3] = { 0, }; 288 int i; 289 290 nbds = strlen(boot_device); 291 if (nbds > PC_MAX_BOOT_DEVICES) { 292 error_report("Too many boot devices for PC"); 293 return(1); 294 } 295 for (i = 0; i < nbds; i++) { 296 bds[i] = boot_device2nibble(boot_device[i]); 297 if (bds[i] == 0) { 298 error_report("Invalid boot device for PC: '%c'", 299 boot_device[i]); 300 return(1); 301 } 302 } 303 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 304 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 305 return(0); 306 } 307 308 static int pc_boot_set(void *opaque, const char *boot_device) 309 { 310 return set_boot_dev(opaque, boot_device); 311 } 312 313 typedef struct pc_cmos_init_late_arg { 314 ISADevice *rtc_state; 315 BusState *idebus[2]; 316 } pc_cmos_init_late_arg; 317 318 static void pc_cmos_init_late(void *opaque) 319 { 320 pc_cmos_init_late_arg *arg = opaque; 321 ISADevice *s = arg->rtc_state; 322 int16_t cylinders; 323 int8_t heads, sectors; 324 int val; 325 int i, trans; 326 327 val = 0; 328 if (ide_get_geometry(arg->idebus[0], 0, 329 &cylinders, &heads, §ors) >= 0) { 330 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 331 val |= 0xf0; 332 } 333 if (ide_get_geometry(arg->idebus[0], 1, 334 &cylinders, &heads, §ors) >= 0) { 335 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 336 val |= 0x0f; 337 } 338 rtc_set_memory(s, 0x12, val); 339 340 val = 0; 341 for (i = 0; i < 4; i++) { 342 /* NOTE: ide_get_geometry() returns the physical 343 geometry. It is always such that: 1 <= sects <= 63, 1 344 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 345 geometry can be different if a translation is done. */ 346 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 347 &cylinders, &heads, §ors) >= 0) { 348 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 349 assert((trans & ~3) == 0); 350 val |= trans << (i * 2); 351 } 352 } 353 rtc_set_memory(s, 0x39, val); 354 355 qemu_unregister_reset(pc_cmos_init_late, opaque); 356 } 357 358 typedef struct RTCCPUHotplugArg { 359 Notifier cpu_added_notifier; 360 ISADevice *rtc_state; 361 } RTCCPUHotplugArg; 362 363 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 364 { 365 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 366 cpu_added_notifier); 367 ISADevice *s = arg->rtc_state; 368 369 /* increment the number of CPUs */ 370 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 371 } 372 373 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 374 const char *boot_device, 375 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 376 ISADevice *s) 377 { 378 int val, nb, i; 379 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 380 static pc_cmos_init_late_arg arg; 381 static RTCCPUHotplugArg cpu_hotplug_cb; 382 383 /* various important CMOS locations needed by PC/Bochs bios */ 384 385 /* memory size */ 386 /* base memory (first MiB) */ 387 val = MIN(ram_size / 1024, 640); 388 rtc_set_memory(s, 0x15, val); 389 rtc_set_memory(s, 0x16, val >> 8); 390 /* extended memory (next 64MiB) */ 391 if (ram_size > 1024 * 1024) { 392 val = (ram_size - 1024 * 1024) / 1024; 393 } else { 394 val = 0; 395 } 396 if (val > 65535) 397 val = 65535; 398 rtc_set_memory(s, 0x17, val); 399 rtc_set_memory(s, 0x18, val >> 8); 400 rtc_set_memory(s, 0x30, val); 401 rtc_set_memory(s, 0x31, val >> 8); 402 /* memory between 16MiB and 4GiB */ 403 if (ram_size > 16 * 1024 * 1024) { 404 val = (ram_size - 16 * 1024 * 1024) / 65536; 405 } else { 406 val = 0; 407 } 408 if (val > 65535) 409 val = 65535; 410 rtc_set_memory(s, 0x34, val); 411 rtc_set_memory(s, 0x35, val >> 8); 412 /* memory above 4GiB */ 413 val = above_4g_mem_size / 65536; 414 rtc_set_memory(s, 0x5b, val); 415 rtc_set_memory(s, 0x5c, val >> 8); 416 rtc_set_memory(s, 0x5d, val >> 16); 417 418 /* set the number of CPU */ 419 rtc_set_memory(s, 0x5f, smp_cpus - 1); 420 /* init CPU hotplug notifier */ 421 cpu_hotplug_cb.rtc_state = s; 422 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 423 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 424 425 if (set_boot_dev(s, boot_device)) { 426 exit(1); 427 } 428 429 /* floppy type */ 430 if (floppy) { 431 for (i = 0; i < 2; i++) { 432 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 433 } 434 } 435 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 436 cmos_get_fd_drive_type(fd_type[1]); 437 rtc_set_memory(s, 0x10, val); 438 439 val = 0; 440 nb = 0; 441 if (fd_type[0] < FDRIVE_DRV_NONE) { 442 nb++; 443 } 444 if (fd_type[1] < FDRIVE_DRV_NONE) { 445 nb++; 446 } 447 switch (nb) { 448 case 0: 449 break; 450 case 1: 451 val |= 0x01; /* 1 drive, ready for boot */ 452 break; 453 case 2: 454 val |= 0x41; /* 2 drives, ready for boot */ 455 break; 456 } 457 val |= 0x02; /* FPU is there */ 458 val |= 0x04; /* PS/2 mouse installed */ 459 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 460 461 /* hard drives */ 462 arg.rtc_state = s; 463 arg.idebus[0] = idebus0; 464 arg.idebus[1] = idebus1; 465 qemu_register_reset(pc_cmos_init_late, &arg); 466 } 467 468 #define TYPE_PORT92 "port92" 469 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 470 471 /* port 92 stuff: could be split off */ 472 typedef struct Port92State { 473 ISADevice parent_obj; 474 475 MemoryRegion io; 476 uint8_t outport; 477 qemu_irq *a20_out; 478 } Port92State; 479 480 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 481 unsigned size) 482 { 483 Port92State *s = opaque; 484 int oldval = s->outport; 485 486 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 487 s->outport = val; 488 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 489 if ((val & 1) && !(oldval & 1)) { 490 qemu_system_reset_request(); 491 } 492 } 493 494 static uint64_t port92_read(void *opaque, hwaddr addr, 495 unsigned size) 496 { 497 Port92State *s = opaque; 498 uint32_t ret; 499 500 ret = s->outport; 501 DPRINTF("port92: read 0x%02x\n", ret); 502 return ret; 503 } 504 505 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 506 { 507 Port92State *s = PORT92(dev); 508 509 s->a20_out = a20_out; 510 } 511 512 static const VMStateDescription vmstate_port92_isa = { 513 .name = "port92", 514 .version_id = 1, 515 .minimum_version_id = 1, 516 .fields = (VMStateField[]) { 517 VMSTATE_UINT8(outport, Port92State), 518 VMSTATE_END_OF_LIST() 519 } 520 }; 521 522 static void port92_reset(DeviceState *d) 523 { 524 Port92State *s = PORT92(d); 525 526 s->outport &= ~1; 527 } 528 529 static const MemoryRegionOps port92_ops = { 530 .read = port92_read, 531 .write = port92_write, 532 .impl = { 533 .min_access_size = 1, 534 .max_access_size = 1, 535 }, 536 .endianness = DEVICE_LITTLE_ENDIAN, 537 }; 538 539 static void port92_initfn(Object *obj) 540 { 541 Port92State *s = PORT92(obj); 542 543 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 544 545 s->outport = 0; 546 } 547 548 static void port92_realizefn(DeviceState *dev, Error **errp) 549 { 550 ISADevice *isadev = ISA_DEVICE(dev); 551 Port92State *s = PORT92(dev); 552 553 isa_register_ioport(isadev, &s->io, 0x92); 554 } 555 556 static void port92_class_initfn(ObjectClass *klass, void *data) 557 { 558 DeviceClass *dc = DEVICE_CLASS(klass); 559 560 dc->realize = port92_realizefn; 561 dc->reset = port92_reset; 562 dc->vmsd = &vmstate_port92_isa; 563 /* 564 * Reason: unlike ordinary ISA devices, this one needs additional 565 * wiring: its A20 output line needs to be wired up by 566 * port92_init(). 567 */ 568 dc->cannot_instantiate_with_device_add_yet = true; 569 } 570 571 static const TypeInfo port92_info = { 572 .name = TYPE_PORT92, 573 .parent = TYPE_ISA_DEVICE, 574 .instance_size = sizeof(Port92State), 575 .instance_init = port92_initfn, 576 .class_init = port92_class_initfn, 577 }; 578 579 static void port92_register_types(void) 580 { 581 type_register_static(&port92_info); 582 } 583 584 type_init(port92_register_types) 585 586 static void handle_a20_line_change(void *opaque, int irq, int level) 587 { 588 X86CPU *cpu = opaque; 589 590 /* XXX: send to all CPUs ? */ 591 /* XXX: add logic to handle multiple A20 line sources */ 592 x86_cpu_set_a20(cpu, level); 593 } 594 595 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 596 { 597 int index = le32_to_cpu(e820_reserve.count); 598 struct e820_entry *entry; 599 600 if (type != E820_RAM) { 601 /* old FW_CFG_E820_TABLE entry -- reservations only */ 602 if (index >= E820_NR_ENTRIES) { 603 return -EBUSY; 604 } 605 entry = &e820_reserve.entry[index++]; 606 607 entry->address = cpu_to_le64(address); 608 entry->length = cpu_to_le64(length); 609 entry->type = cpu_to_le32(type); 610 611 e820_reserve.count = cpu_to_le32(index); 612 } 613 614 /* new "etc/e820" file -- include ram too */ 615 e820_table = g_realloc(e820_table, 616 sizeof(struct e820_entry) * (e820_entries+1)); 617 e820_table[e820_entries].address = cpu_to_le64(address); 618 e820_table[e820_entries].length = cpu_to_le64(length); 619 e820_table[e820_entries].type = cpu_to_le32(type); 620 e820_entries++; 621 622 return e820_entries; 623 } 624 625 int e820_get_num_entries(void) 626 { 627 return e820_entries; 628 } 629 630 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 631 { 632 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 633 *address = le64_to_cpu(e820_table[idx].address); 634 *length = le64_to_cpu(e820_table[idx].length); 635 return true; 636 } 637 return false; 638 } 639 640 /* Calculates the limit to CPU APIC ID values 641 * 642 * This function returns the limit for the APIC ID value, so that all 643 * CPU APIC IDs are < pc_apic_id_limit(). 644 * 645 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 646 */ 647 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 648 { 649 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 650 } 651 652 static FWCfgState *bochs_bios_init(void) 653 { 654 FWCfgState *fw_cfg; 655 uint8_t *smbios_tables, *smbios_anchor; 656 size_t smbios_tables_len, smbios_anchor_len; 657 uint64_t *numa_fw_cfg; 658 int i, j; 659 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 660 661 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 662 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 663 * 664 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 665 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 666 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 667 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 668 * may see". 669 * 670 * So, this means we must not use max_cpus, here, but the maximum possible 671 * APIC ID value, plus one. 672 * 673 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 674 * the APIC ID, not the "CPU index" 675 */ 676 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 677 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 678 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 679 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 680 acpi_tables, acpi_tables_len); 681 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 682 683 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 684 if (smbios_tables) { 685 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 686 smbios_tables, smbios_tables_len); 687 } 688 689 smbios_get_tables(&smbios_tables, &smbios_tables_len, 690 &smbios_anchor, &smbios_anchor_len); 691 if (smbios_anchor) { 692 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 693 smbios_tables, smbios_tables_len); 694 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 695 smbios_anchor, smbios_anchor_len); 696 } 697 698 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 699 &e820_reserve, sizeof(e820_reserve)); 700 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 701 sizeof(struct e820_entry) * e820_entries); 702 703 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 704 /* allocate memory for the NUMA channel: one (64bit) word for the number 705 * of nodes, one word for each VCPU->node and one word for each node to 706 * hold the amount of memory. 707 */ 708 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 709 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 710 for (i = 0; i < max_cpus; i++) { 711 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 712 assert(apic_id < apic_id_limit); 713 for (j = 0; j < nb_numa_nodes; j++) { 714 if (test_bit(i, numa_info[j].node_cpu)) { 715 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 716 break; 717 } 718 } 719 } 720 for (i = 0; i < nb_numa_nodes; i++) { 721 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 722 } 723 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 724 (1 + apic_id_limit + nb_numa_nodes) * 725 sizeof(*numa_fw_cfg)); 726 727 return fw_cfg; 728 } 729 730 static long get_file_size(FILE *f) 731 { 732 long where, size; 733 734 /* XXX: on Unix systems, using fstat() probably makes more sense */ 735 736 where = ftell(f); 737 fseek(f, 0, SEEK_END); 738 size = ftell(f); 739 fseek(f, where, SEEK_SET); 740 741 return size; 742 } 743 744 static void load_linux(FWCfgState *fw_cfg, 745 const char *kernel_filename, 746 const char *initrd_filename, 747 const char *kernel_cmdline, 748 hwaddr max_ram_size) 749 { 750 uint16_t protocol; 751 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 752 uint32_t initrd_max; 753 uint8_t header[8192], *setup, *kernel, *initrd_data; 754 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 755 FILE *f; 756 char *vmode; 757 758 /* Align to 16 bytes as a paranoia measure */ 759 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 760 761 /* load the kernel header */ 762 f = fopen(kernel_filename, "rb"); 763 if (!f || !(kernel_size = get_file_size(f)) || 764 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 765 MIN(ARRAY_SIZE(header), kernel_size)) { 766 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 767 kernel_filename, strerror(errno)); 768 exit(1); 769 } 770 771 /* kernel protocol version */ 772 #if 0 773 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 774 #endif 775 if (ldl_p(header+0x202) == 0x53726448) { 776 protocol = lduw_p(header+0x206); 777 } else { 778 /* This looks like a multiboot kernel. If it is, let's stop 779 treating it like a Linux kernel. */ 780 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 781 kernel_cmdline, kernel_size, header)) { 782 return; 783 } 784 protocol = 0; 785 } 786 787 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 788 /* Low kernel */ 789 real_addr = 0x90000; 790 cmdline_addr = 0x9a000 - cmdline_size; 791 prot_addr = 0x10000; 792 } else if (protocol < 0x202) { 793 /* High but ancient kernel */ 794 real_addr = 0x90000; 795 cmdline_addr = 0x9a000 - cmdline_size; 796 prot_addr = 0x100000; 797 } else { 798 /* High and recent kernel */ 799 real_addr = 0x10000; 800 cmdline_addr = 0x20000; 801 prot_addr = 0x100000; 802 } 803 804 #if 0 805 fprintf(stderr, 806 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 807 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 808 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 809 real_addr, 810 cmdline_addr, 811 prot_addr); 812 #endif 813 814 /* highest address for loading the initrd */ 815 if (protocol >= 0x203) { 816 initrd_max = ldl_p(header+0x22c); 817 } else { 818 initrd_max = 0x37ffffff; 819 } 820 821 if (initrd_max >= max_ram_size - acpi_data_size) { 822 initrd_max = max_ram_size - acpi_data_size - 1; 823 } 824 825 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 826 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 827 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 828 829 if (protocol >= 0x202) { 830 stl_p(header+0x228, cmdline_addr); 831 } else { 832 stw_p(header+0x20, 0xA33F); 833 stw_p(header+0x22, cmdline_addr-real_addr); 834 } 835 836 /* handle vga= parameter */ 837 vmode = strstr(kernel_cmdline, "vga="); 838 if (vmode) { 839 unsigned int video_mode; 840 /* skip "vga=" */ 841 vmode += 4; 842 if (!strncmp(vmode, "normal", 6)) { 843 video_mode = 0xffff; 844 } else if (!strncmp(vmode, "ext", 3)) { 845 video_mode = 0xfffe; 846 } else if (!strncmp(vmode, "ask", 3)) { 847 video_mode = 0xfffd; 848 } else { 849 video_mode = strtol(vmode, NULL, 0); 850 } 851 stw_p(header+0x1fa, video_mode); 852 } 853 854 /* loader type */ 855 /* High nybble = B reserved for QEMU; low nybble is revision number. 856 If this code is substantially changed, you may want to consider 857 incrementing the revision. */ 858 if (protocol >= 0x200) { 859 header[0x210] = 0xB0; 860 } 861 /* heap */ 862 if (protocol >= 0x201) { 863 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 864 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 865 } 866 867 /* load initrd */ 868 if (initrd_filename) { 869 if (protocol < 0x200) { 870 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 871 exit(1); 872 } 873 874 initrd_size = get_image_size(initrd_filename); 875 if (initrd_size < 0) { 876 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 877 initrd_filename, strerror(errno)); 878 exit(1); 879 } 880 881 initrd_addr = (initrd_max-initrd_size) & ~4095; 882 883 initrd_data = g_malloc(initrd_size); 884 load_image(initrd_filename, initrd_data); 885 886 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 887 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 888 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 889 890 stl_p(header+0x218, initrd_addr); 891 stl_p(header+0x21c, initrd_size); 892 } 893 894 /* load kernel and setup */ 895 setup_size = header[0x1f1]; 896 if (setup_size == 0) { 897 setup_size = 4; 898 } 899 setup_size = (setup_size+1)*512; 900 kernel_size -= setup_size; 901 902 setup = g_malloc(setup_size); 903 kernel = g_malloc(kernel_size); 904 fseek(f, 0, SEEK_SET); 905 if (fread(setup, 1, setup_size, f) != setup_size) { 906 fprintf(stderr, "fread() failed\n"); 907 exit(1); 908 } 909 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 910 fprintf(stderr, "fread() failed\n"); 911 exit(1); 912 } 913 fclose(f); 914 memcpy(setup, header, MIN(sizeof(header), setup_size)); 915 916 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 917 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 918 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 919 920 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 921 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 922 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 923 924 option_rom[nb_option_roms].name = "linuxboot.bin"; 925 option_rom[nb_option_roms].bootindex = 0; 926 nb_option_roms++; 927 } 928 929 #define NE2000_NB_MAX 6 930 931 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 932 0x280, 0x380 }; 933 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 934 935 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 936 { 937 static int nb_ne2k = 0; 938 939 if (nb_ne2k == NE2000_NB_MAX) 940 return; 941 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 942 ne2000_irq[nb_ne2k], nd); 943 nb_ne2k++; 944 } 945 946 DeviceState *cpu_get_current_apic(void) 947 { 948 if (current_cpu) { 949 X86CPU *cpu = X86_CPU(current_cpu); 950 return cpu->apic_state; 951 } else { 952 return NULL; 953 } 954 } 955 956 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 957 { 958 X86CPU *cpu = opaque; 959 960 if (level) { 961 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 962 } 963 } 964 965 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 966 DeviceState *icc_bridge, Error **errp) 967 { 968 X86CPU *cpu; 969 Error *local_err = NULL; 970 971 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 972 if (local_err != NULL) { 973 error_propagate(errp, local_err); 974 return NULL; 975 } 976 977 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 978 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 979 980 if (local_err) { 981 error_propagate(errp, local_err); 982 object_unref(OBJECT(cpu)); 983 cpu = NULL; 984 } 985 return cpu; 986 } 987 988 static const char *current_cpu_model; 989 990 void pc_hot_add_cpu(const int64_t id, Error **errp) 991 { 992 DeviceState *icc_bridge; 993 int64_t apic_id = x86_cpu_apic_id_from_index(id); 994 995 if (id < 0) { 996 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 997 return; 998 } 999 1000 if (cpu_exists(apic_id)) { 1001 error_setg(errp, "Unable to add CPU: %" PRIi64 1002 ", it already exists", id); 1003 return; 1004 } 1005 1006 if (id >= max_cpus) { 1007 error_setg(errp, "Unable to add CPU: %" PRIi64 1008 ", max allowed: %d", id, max_cpus - 1); 1009 return; 1010 } 1011 1012 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1013 error_setg(errp, "Unable to add CPU: %" PRIi64 1014 ", resulting APIC ID (%" PRIi64 ") is too large", 1015 id, apic_id); 1016 return; 1017 } 1018 1019 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1020 TYPE_ICC_BRIDGE, NULL)); 1021 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1022 } 1023 1024 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1025 { 1026 int i; 1027 X86CPU *cpu = NULL; 1028 Error *error = NULL; 1029 unsigned long apic_id_limit; 1030 1031 /* init CPUs */ 1032 if (cpu_model == NULL) { 1033 #ifdef TARGET_X86_64 1034 cpu_model = "qemu64"; 1035 #else 1036 cpu_model = "qemu32"; 1037 #endif 1038 } 1039 current_cpu_model = cpu_model; 1040 1041 apic_id_limit = pc_apic_id_limit(max_cpus); 1042 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1043 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1044 apic_id_limit - 1); 1045 exit(1); 1046 } 1047 1048 for (i = 0; i < smp_cpus; i++) { 1049 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1050 icc_bridge, &error); 1051 if (error) { 1052 error_report("%s", error_get_pretty(error)); 1053 error_free(error); 1054 exit(1); 1055 } 1056 } 1057 1058 /* map APIC MMIO area if CPU has APIC */ 1059 if (cpu && cpu->apic_state) { 1060 /* XXX: what if the base changes? */ 1061 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1062 APIC_DEFAULT_ADDRESS, 0x1000); 1063 } 1064 1065 /* tell smbios about cpuid version and features */ 1066 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1067 } 1068 1069 /* pci-info ROM file. Little endian format */ 1070 typedef struct PcRomPciInfo { 1071 uint64_t w32_min; 1072 uint64_t w32_max; 1073 uint64_t w64_min; 1074 uint64_t w64_max; 1075 } PcRomPciInfo; 1076 1077 typedef struct PcGuestInfoState { 1078 PcGuestInfo info; 1079 Notifier machine_done; 1080 } PcGuestInfoState; 1081 1082 static 1083 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1084 { 1085 PcGuestInfoState *guest_info_state = container_of(notifier, 1086 PcGuestInfoState, 1087 machine_done); 1088 acpi_setup(&guest_info_state->info); 1089 } 1090 1091 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1092 ram_addr_t above_4g_mem_size) 1093 { 1094 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1095 PcGuestInfo *guest_info = &guest_info_state->info; 1096 int i, j; 1097 1098 guest_info->ram_size_below_4g = below_4g_mem_size; 1099 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1100 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1101 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1102 guest_info->numa_nodes = nb_numa_nodes; 1103 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1104 sizeof *guest_info->node_mem); 1105 for (i = 0; i < nb_numa_nodes; i++) { 1106 guest_info->node_mem[i] = numa_info[i].node_mem; 1107 } 1108 1109 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1110 sizeof *guest_info->node_cpu); 1111 1112 for (i = 0; i < max_cpus; i++) { 1113 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1114 assert(apic_id < guest_info->apic_id_limit); 1115 for (j = 0; j < nb_numa_nodes; j++) { 1116 if (test_bit(i, numa_info[j].node_cpu)) { 1117 guest_info->node_cpu[apic_id] = j; 1118 break; 1119 } 1120 } 1121 } 1122 1123 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1124 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1125 return guest_info; 1126 } 1127 1128 /* setup pci memory address space mapping into system address space */ 1129 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1130 MemoryRegion *pci_address_space) 1131 { 1132 /* Set to lower priority than RAM */ 1133 memory_region_add_subregion_overlap(system_memory, 0x0, 1134 pci_address_space, -1); 1135 } 1136 1137 void pc_acpi_init(const char *default_dsdt) 1138 { 1139 char *filename; 1140 1141 if (acpi_tables != NULL) { 1142 /* manually set via -acpitable, leave it alone */ 1143 return; 1144 } 1145 1146 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1147 if (filename == NULL) { 1148 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1149 } else { 1150 char *arg; 1151 QemuOpts *opts; 1152 Error *err = NULL; 1153 1154 arg = g_strdup_printf("file=%s", filename); 1155 1156 /* creates a deep copy of "arg" */ 1157 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1158 g_assert(opts != NULL); 1159 1160 acpi_table_add_builtin(opts, &err); 1161 if (err) { 1162 error_report("WARNING: failed to load %s: %s", filename, 1163 error_get_pretty(err)); 1164 error_free(err); 1165 } 1166 g_free(arg); 1167 g_free(filename); 1168 } 1169 } 1170 1171 FWCfgState *xen_load_linux(const char *kernel_filename, 1172 const char *kernel_cmdline, 1173 const char *initrd_filename, 1174 ram_addr_t below_4g_mem_size, 1175 PcGuestInfo *guest_info) 1176 { 1177 int i; 1178 FWCfgState *fw_cfg; 1179 1180 assert(kernel_filename != NULL); 1181 1182 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 1183 rom_set_fw(fw_cfg); 1184 1185 load_linux(fw_cfg, kernel_filename, initrd_filename, 1186 kernel_cmdline, below_4g_mem_size); 1187 for (i = 0; i < nb_option_roms; i++) { 1188 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1189 !strcmp(option_rom[i].name, "multiboot.bin")); 1190 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1191 } 1192 guest_info->fw_cfg = fw_cfg; 1193 return fw_cfg; 1194 } 1195 1196 FWCfgState *pc_memory_init(MachineState *machine, 1197 MemoryRegion *system_memory, 1198 ram_addr_t below_4g_mem_size, 1199 ram_addr_t above_4g_mem_size, 1200 MemoryRegion *rom_memory, 1201 MemoryRegion **ram_memory, 1202 PcGuestInfo *guest_info) 1203 { 1204 int linux_boot, i; 1205 MemoryRegion *ram, *option_rom_mr; 1206 MemoryRegion *ram_below_4g, *ram_above_4g; 1207 FWCfgState *fw_cfg; 1208 PCMachineState *pcms = PC_MACHINE(machine); 1209 1210 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1211 1212 linux_boot = (machine->kernel_filename != NULL); 1213 1214 /* Allocate RAM. We allocate it as a single memory region and use 1215 * aliases to address portions of it, mostly for backwards compatibility 1216 * with older qemus that used qemu_ram_alloc(). 1217 */ 1218 ram = g_malloc(sizeof(*ram)); 1219 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1220 machine->ram_size); 1221 *ram_memory = ram; 1222 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1223 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1224 0, below_4g_mem_size); 1225 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1226 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1227 if (above_4g_mem_size > 0) { 1228 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1229 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1230 below_4g_mem_size, above_4g_mem_size); 1231 memory_region_add_subregion(system_memory, 0x100000000ULL, 1232 ram_above_4g); 1233 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1234 } 1235 1236 if (!guest_info->has_reserved_memory && 1237 (machine->ram_slots || 1238 (machine->maxram_size > machine->ram_size))) { 1239 MachineClass *mc = MACHINE_GET_CLASS(machine); 1240 1241 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1242 mc->name); 1243 exit(EXIT_FAILURE); 1244 } 1245 1246 /* initialize hotplug memory address space */ 1247 if (guest_info->has_reserved_memory && 1248 (machine->ram_size < machine->maxram_size)) { 1249 ram_addr_t hotplug_mem_size = 1250 machine->maxram_size - machine->ram_size; 1251 1252 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1253 error_report("unsupported amount of memory slots: %"PRIu64, 1254 machine->ram_slots); 1255 exit(EXIT_FAILURE); 1256 } 1257 1258 pcms->hotplug_memory_base = 1259 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1260 1261 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1262 hotplug_mem_size) { 1263 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1264 machine->maxram_size); 1265 exit(EXIT_FAILURE); 1266 } 1267 1268 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1269 "hotplug-memory", hotplug_mem_size); 1270 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1271 &pcms->hotplug_memory); 1272 } 1273 1274 /* Initialize PC system firmware */ 1275 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1276 1277 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1278 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1279 &error_abort); 1280 vmstate_register_ram_global(option_rom_mr); 1281 memory_region_add_subregion_overlap(rom_memory, 1282 PC_ROM_MIN_VGA, 1283 option_rom_mr, 1284 1); 1285 1286 fw_cfg = bochs_bios_init(); 1287 rom_set_fw(fw_cfg); 1288 1289 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1290 uint64_t *val = g_malloc(sizeof(*val)); 1291 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1292 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1293 } 1294 1295 if (linux_boot) { 1296 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1297 machine->kernel_cmdline, below_4g_mem_size); 1298 } 1299 1300 for (i = 0; i < nb_option_roms; i++) { 1301 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1302 } 1303 guest_info->fw_cfg = fw_cfg; 1304 return fw_cfg; 1305 } 1306 1307 qemu_irq *pc_allocate_cpu_irq(void) 1308 { 1309 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1310 } 1311 1312 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1313 { 1314 DeviceState *dev = NULL; 1315 1316 if (pci_bus) { 1317 PCIDevice *pcidev = pci_vga_init(pci_bus); 1318 dev = pcidev ? &pcidev->qdev : NULL; 1319 } else if (isa_bus) { 1320 ISADevice *isadev = isa_vga_init(isa_bus); 1321 dev = isadev ? DEVICE(isadev) : NULL; 1322 } 1323 return dev; 1324 } 1325 1326 static void cpu_request_exit(void *opaque, int irq, int level) 1327 { 1328 CPUState *cpu = current_cpu; 1329 1330 if (cpu && level) { 1331 cpu_exit(cpu); 1332 } 1333 } 1334 1335 static const MemoryRegionOps ioport80_io_ops = { 1336 .write = ioport80_write, 1337 .read = ioport80_read, 1338 .endianness = DEVICE_NATIVE_ENDIAN, 1339 .impl = { 1340 .min_access_size = 1, 1341 .max_access_size = 1, 1342 }, 1343 }; 1344 1345 static const MemoryRegionOps ioportF0_io_ops = { 1346 .write = ioportF0_write, 1347 .read = ioportF0_read, 1348 .endianness = DEVICE_NATIVE_ENDIAN, 1349 .impl = { 1350 .min_access_size = 1, 1351 .max_access_size = 1, 1352 }, 1353 }; 1354 1355 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1356 ISADevice **rtc_state, 1357 ISADevice **floppy, 1358 bool no_vmport, 1359 uint32 hpet_irqs) 1360 { 1361 int i; 1362 DriveInfo *fd[MAX_FD]; 1363 DeviceState *hpet = NULL; 1364 int pit_isa_irq = 0; 1365 qemu_irq pit_alt_irq = NULL; 1366 qemu_irq rtc_irq = NULL; 1367 qemu_irq *a20_line; 1368 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1369 qemu_irq *cpu_exit_irq; 1370 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1371 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1372 1373 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1374 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1375 1376 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1377 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1378 1379 /* 1380 * Check if an HPET shall be created. 1381 * 1382 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1383 * when the HPET wants to take over. Thus we have to disable the latter. 1384 */ 1385 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1386 /* In order to set property, here not using sysbus_try_create_simple */ 1387 hpet = qdev_try_create(NULL, TYPE_HPET); 1388 if (hpet) { 1389 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1390 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1391 * IRQ8 and IRQ2. 1392 */ 1393 uint8_t compat = object_property_get_int(OBJECT(hpet), 1394 HPET_INTCAP, NULL); 1395 if (!compat) { 1396 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1397 } 1398 qdev_init_nofail(hpet); 1399 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1400 1401 for (i = 0; i < GSI_NUM_PINS; i++) { 1402 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1403 } 1404 pit_isa_irq = -1; 1405 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1406 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1407 } 1408 } 1409 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1410 1411 qemu_register_boot_set(pc_boot_set, *rtc_state); 1412 1413 if (!xen_enabled()) { 1414 if (kvm_irqchip_in_kernel()) { 1415 pit = kvm_pit_init(isa_bus, 0x40); 1416 } else { 1417 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1418 } 1419 if (hpet) { 1420 /* connect PIT to output control line of the HPET */ 1421 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1422 } 1423 pcspk_init(isa_bus, pit); 1424 } 1425 1426 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1427 if (serial_hds[i]) { 1428 serial_isa_init(isa_bus, i, serial_hds[i]); 1429 } 1430 } 1431 1432 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1433 if (parallel_hds[i]) { 1434 parallel_init(isa_bus, i, parallel_hds[i]); 1435 } 1436 } 1437 1438 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1439 i8042 = isa_create_simple(isa_bus, "i8042"); 1440 i8042_setup_a20_line(i8042, &a20_line[0]); 1441 if (!no_vmport) { 1442 vmport_init(isa_bus); 1443 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1444 } else { 1445 vmmouse = NULL; 1446 } 1447 if (vmmouse) { 1448 DeviceState *dev = DEVICE(vmmouse); 1449 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1450 qdev_init_nofail(dev); 1451 } 1452 port92 = isa_create_simple(isa_bus, "port92"); 1453 port92_init(port92, &a20_line[1]); 1454 1455 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1456 DMA_init(0, cpu_exit_irq); 1457 1458 for(i = 0; i < MAX_FD; i++) { 1459 fd[i] = drive_get(IF_FLOPPY, 0, i); 1460 } 1461 *floppy = fdctrl_init_isa(isa_bus, fd); 1462 } 1463 1464 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1465 { 1466 int i; 1467 1468 for (i = 0; i < nb_nics; i++) { 1469 NICInfo *nd = &nd_table[i]; 1470 1471 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1472 pc_init_ne2k_isa(isa_bus, nd); 1473 } else { 1474 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1475 } 1476 } 1477 } 1478 1479 void pc_pci_device_init(PCIBus *pci_bus) 1480 { 1481 int max_bus; 1482 int bus; 1483 1484 max_bus = drive_get_max_bus(IF_SCSI); 1485 for (bus = 0; bus <= max_bus; bus++) { 1486 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1487 } 1488 } 1489 1490 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1491 { 1492 DeviceState *dev; 1493 SysBusDevice *d; 1494 unsigned int i; 1495 1496 if (kvm_irqchip_in_kernel()) { 1497 dev = qdev_create(NULL, "kvm-ioapic"); 1498 } else { 1499 dev = qdev_create(NULL, "ioapic"); 1500 } 1501 if (parent_name) { 1502 object_property_add_child(object_resolve_path(parent_name, NULL), 1503 "ioapic", OBJECT(dev), NULL); 1504 } 1505 qdev_init_nofail(dev); 1506 d = SYS_BUS_DEVICE(dev); 1507 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1508 1509 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1510 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1511 } 1512 } 1513 1514 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1515 { 1516 MachineClass *mc = MACHINE_CLASS(oc); 1517 QEMUMachine *qm = data; 1518 1519 mc->name = qm->name; 1520 mc->alias = qm->alias; 1521 mc->desc = qm->desc; 1522 mc->init = qm->init; 1523 mc->reset = qm->reset; 1524 mc->hot_add_cpu = qm->hot_add_cpu; 1525 mc->kvm_type = qm->kvm_type; 1526 mc->block_default_type = qm->block_default_type; 1527 mc->max_cpus = qm->max_cpus; 1528 mc->no_serial = qm->no_serial; 1529 mc->no_parallel = qm->no_parallel; 1530 mc->use_virtcon = qm->use_virtcon; 1531 mc->use_sclp = qm->use_sclp; 1532 mc->no_floppy = qm->no_floppy; 1533 mc->no_cdrom = qm->no_cdrom; 1534 mc->no_sdcard = qm->no_sdcard; 1535 mc->is_default = qm->is_default; 1536 mc->default_machine_opts = qm->default_machine_opts; 1537 mc->default_boot_order = qm->default_boot_order; 1538 mc->compat_props = qm->compat_props; 1539 mc->hw_version = qm->hw_version; 1540 } 1541 1542 void qemu_register_pc_machine(QEMUMachine *m) 1543 { 1544 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1545 TypeInfo ti = { 1546 .name = name, 1547 .parent = TYPE_PC_MACHINE, 1548 .class_init = pc_generic_machine_class_init, 1549 .class_data = (void *)m, 1550 }; 1551 1552 type_register(&ti); 1553 g_free(name); 1554 } 1555 1556 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1557 DeviceState *dev, Error **errp) 1558 { 1559 int slot; 1560 HotplugHandlerClass *hhc; 1561 Error *local_err = NULL; 1562 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1563 MachineState *machine = MACHINE(hotplug_dev); 1564 PCDIMMDevice *dimm = PC_DIMM(dev); 1565 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1566 MemoryRegion *mr = ddc->get_memory_region(dimm); 1567 uint64_t addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 1568 &local_err); 1569 if (local_err) { 1570 goto out; 1571 } 1572 1573 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1574 memory_region_size(&pcms->hotplug_memory), 1575 !addr ? NULL : &addr, 1576 memory_region_size(mr), &local_err); 1577 if (local_err) { 1578 goto out; 1579 } 1580 1581 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1582 if (local_err) { 1583 goto out; 1584 } 1585 trace_mhp_pc_dimm_assigned_address(addr); 1586 1587 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1588 if (local_err) { 1589 goto out; 1590 } 1591 1592 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1593 machine->ram_slots, &local_err); 1594 if (local_err) { 1595 goto out; 1596 } 1597 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1598 if (local_err) { 1599 goto out; 1600 } 1601 trace_mhp_pc_dimm_assigned_slot(slot); 1602 1603 if (!pcms->acpi_dev) { 1604 error_setg(&local_err, 1605 "memory hotplug is not enabled: missing acpi device"); 1606 goto out; 1607 } 1608 1609 memory_region_add_subregion(&pcms->hotplug_memory, 1610 addr - pcms->hotplug_memory_base, mr); 1611 vmstate_register_ram(mr, dev); 1612 1613 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1614 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1615 out: 1616 error_propagate(errp, local_err); 1617 } 1618 1619 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1620 DeviceState *dev, Error **errp) 1621 { 1622 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1623 pc_dimm_plug(hotplug_dev, dev, errp); 1624 } 1625 } 1626 1627 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1628 DeviceState *dev) 1629 { 1630 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1631 1632 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1633 return HOTPLUG_HANDLER(machine); 1634 } 1635 1636 return pcmc->get_hotplug_handler ? 1637 pcmc->get_hotplug_handler(machine, dev) : NULL; 1638 } 1639 1640 static void 1641 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1642 const char *name, Error **errp) 1643 { 1644 PCMachineState *pcms = PC_MACHINE(obj); 1645 int64_t value = memory_region_size(&pcms->hotplug_memory); 1646 1647 visit_type_int(v, &value, name, errp); 1648 } 1649 1650 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1651 void *opaque, const char *name, 1652 Error **errp) 1653 { 1654 PCMachineState *pcms = PC_MACHINE(obj); 1655 uint64_t value = pcms->max_ram_below_4g; 1656 1657 visit_type_size(v, &value, name, errp); 1658 } 1659 1660 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1661 void *opaque, const char *name, 1662 Error **errp) 1663 { 1664 PCMachineState *pcms = PC_MACHINE(obj); 1665 Error *error = NULL; 1666 uint64_t value; 1667 1668 visit_type_size(v, &value, name, &error); 1669 if (error) { 1670 error_propagate(errp, error); 1671 return; 1672 } 1673 if (value > (1ULL << 32)) { 1674 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1675 "Machine option 'max-ram-below-4g=%"PRIu64 1676 "' expects size less than or equal to 4G", value); 1677 error_propagate(errp, error); 1678 return; 1679 } 1680 1681 if (value < (1ULL << 20)) { 1682 error_report("Warning: small max_ram_below_4g(%"PRIu64 1683 ") less than 1M. BIOS may not work..", 1684 value); 1685 } 1686 1687 pcms->max_ram_below_4g = value; 1688 } 1689 1690 static void pc_machine_initfn(Object *obj) 1691 { 1692 PCMachineState *pcms = PC_MACHINE(obj); 1693 1694 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1695 pc_machine_get_hotplug_memory_region_size, 1696 NULL, NULL, NULL, NULL); 1697 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1698 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1699 pc_machine_get_max_ram_below_4g, 1700 pc_machine_set_max_ram_below_4g, 1701 NULL, NULL, NULL); 1702 } 1703 1704 static void pc_machine_class_init(ObjectClass *oc, void *data) 1705 { 1706 MachineClass *mc = MACHINE_CLASS(oc); 1707 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1708 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1709 1710 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1711 mc->get_hotplug_handler = pc_get_hotpug_handler; 1712 hc->plug = pc_machine_device_plug_cb; 1713 } 1714 1715 static const TypeInfo pc_machine_info = { 1716 .name = TYPE_PC_MACHINE, 1717 .parent = TYPE_MACHINE, 1718 .abstract = true, 1719 .instance_size = sizeof(PCMachineState), 1720 .instance_init = pc_machine_initfn, 1721 .class_size = sizeof(PCMachineClass), 1722 .class_init = pc_machine_class_init, 1723 .interfaces = (InterfaceInfo[]) { 1724 { TYPE_HOTPLUG_HANDLER }, 1725 { } 1726 }, 1727 }; 1728 1729 static void pc_machine_register_types(void) 1730 { 1731 type_register_static(&pc_machine_info); 1732 } 1733 1734 type_init(pc_machine_register_types) 1735