1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "exec/target_page.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial-isa.h" 30 #include "hw/char/parallel.h" 31 #include "hw/hyperv/hv-balloon.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "system/cpus.h" 35 #include "hw/ide/ide-bus.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/loader.h" 38 #include "hw/rtc/mc146818rtc.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/input/i8042.h" 42 #include "hw/audio/pcspk.h" 43 #include "system/system.h" 44 #include "system/xen.h" 45 #include "system/reset.h" 46 #include "kvm/kvm_i386.h" 47 #include "hw/xen/xen.h" 48 #include "qobject/qlist.h" 49 #include "qemu/error-report.h" 50 #include "hw/acpi/cpu_hotplug.h" 51 #include "acpi-build.h" 52 #include "hw/mem/nvdimm.h" 53 #include "hw/cxl/cxl_host.h" 54 #include "hw/usb.h" 55 #include "hw/i386/intel_iommu.h" 56 #include "hw/net/ne2000-isa.h" 57 #include "hw/virtio/virtio-iommu.h" 58 #include "hw/virtio/virtio-md-pci.h" 59 #include "hw/i386/kvm/xen_overlay.h" 60 #include "hw/i386/kvm/xen_evtchn.h" 61 #include "hw/i386/kvm/xen_gnttab.h" 62 #include "hw/i386/kvm/xen_xenstore.h" 63 #include "hw/mem/memory-device.h" 64 #include "e820_memory_layout.h" 65 #include "trace.h" 66 #include "sev.h" 67 #include CONFIG_DEVICES 68 69 #ifdef CONFIG_XEN_EMU 70 #include "hw/xen/xen-legacy-backend.h" 71 #include "hw/xen/xen-bus.h" 72 #endif 73 74 /* 75 * Helper for setting model-id for CPU models that changed model-id 76 * depending on QEMU versions up to QEMU 2.4. 77 */ 78 #define PC_CPU_MODEL_IDS(v) \ 79 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 81 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 82 83 GlobalProperty pc_compat_10_0[] = {}; 84 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 85 86 GlobalProperty pc_compat_9_2[] = {}; 87 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 88 89 GlobalProperty pc_compat_9_1[] = { 90 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 91 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 92 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 93 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 94 }; 95 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 96 97 GlobalProperty pc_compat_9_0[] = { 98 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 99 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 100 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 101 { "sev-guest", "legacy-vm-type", "on" }, 102 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 103 }; 104 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 105 106 GlobalProperty pc_compat_8_2[] = {}; 107 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 108 109 GlobalProperty pc_compat_8_1[] = {}; 110 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 111 112 GlobalProperty pc_compat_8_0[] = { 113 { "virtio-mem", "unplugged-inaccessible", "auto" }, 114 }; 115 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 116 117 GlobalProperty pc_compat_7_2[] = { 118 { "ICH9-LPC", "noreboot", "true" }, 119 }; 120 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 121 122 GlobalProperty pc_compat_7_1[] = {}; 123 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 124 125 GlobalProperty pc_compat_7_0[] = {}; 126 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 127 128 GlobalProperty pc_compat_6_2[] = { 129 { "virtio-mem", "unplugged-inaccessible", "off" }, 130 }; 131 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 132 133 GlobalProperty pc_compat_6_1[] = { 134 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 135 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 136 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 137 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 138 }; 139 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 140 141 GlobalProperty pc_compat_6_0[] = { 142 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 143 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 144 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 145 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 146 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 147 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 148 }; 149 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 150 151 GlobalProperty pc_compat_5_2[] = { 152 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 153 }; 154 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 155 156 GlobalProperty pc_compat_5_1[] = { 157 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 158 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 159 }; 160 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 161 162 GlobalProperty pc_compat_5_0[] = { 163 }; 164 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 165 166 GlobalProperty pc_compat_4_2[] = { 167 { "mch", "smbase-smram", "off" }, 168 }; 169 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 170 171 GlobalProperty pc_compat_4_1[] = {}; 172 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 173 174 GlobalProperty pc_compat_4_0[] = {}; 175 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 176 177 GlobalProperty pc_compat_3_1[] = { 178 { "intel-iommu", "dma-drain", "off" }, 179 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 180 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 181 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 182 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 183 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 184 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 185 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 186 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 187 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 188 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 189 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 190 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 191 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 194 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 195 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 196 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 197 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 198 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 199 }; 200 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 201 202 GlobalProperty pc_compat_3_0[] = { 203 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 204 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 205 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 206 }; 207 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 208 209 GlobalProperty pc_compat_2_12[] = { 210 { TYPE_X86_CPU, "legacy-cache", "on" }, 211 { TYPE_X86_CPU, "topoext", "off" }, 212 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 213 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 214 }; 215 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 216 217 GlobalProperty pc_compat_2_11[] = { 218 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 219 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 220 }; 221 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 222 223 GlobalProperty pc_compat_2_10[] = { 224 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 225 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 226 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 227 }; 228 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 229 230 GlobalProperty pc_compat_2_9[] = { 231 { "mch", "extended-tseg-mbytes", "0" }, 232 }; 233 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 234 235 GlobalProperty pc_compat_2_8[] = { 236 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 237 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 238 { "ICH9-LPC", "x-smi-broadcast", "off" }, 239 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 240 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 241 }; 242 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 243 244 GlobalProperty pc_compat_2_7[] = { 245 { TYPE_X86_CPU, "l3-cache", "off" }, 246 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 247 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 248 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 249 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 250 { "isa-pcspk", "migrate", "off" }, 251 }; 252 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 253 254 GlobalProperty pc_compat_2_6[] = { 255 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 256 { "vmxnet3", "romfile", "" }, 257 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 258 { "apic-common", "legacy-instance-id", "on", } 259 }; 260 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 261 262 /* 263 * @PC_FW_DATA: 264 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 265 * and other BIOS datastructures. 266 * 267 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 268 * reported to be used at the moment, 32K should be enough for a while. 269 */ 270 #define PC_FW_DATA (0x20000 + 0x8000) 271 272 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 273 { 274 GSIState *s; 275 276 s = g_new0(GSIState, 1); 277 if (kvm_ioapic_in_kernel()) { 278 kvm_pc_setup_irq_routing(pci_enabled); 279 } 280 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 281 282 return s; 283 } 284 285 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 286 unsigned size) 287 { 288 } 289 290 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 291 { 292 return 0xffffffffffffffffULL; 293 } 294 295 /* MS-DOS compatibility mode FPU exception support */ 296 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 297 unsigned size) 298 { 299 if (tcg_enabled()) { 300 cpu_set_ignne(); 301 } 302 } 303 304 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 305 { 306 return 0xffffffffffffffffULL; 307 } 308 309 /* PC cmos mappings */ 310 311 #define REG_EQUIPMENT_BYTE 0x14 312 313 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 314 int16_t cylinders, int8_t heads, int8_t sectors) 315 { 316 mc146818rtc_set_cmos_data(s, type_ofs, 47); 317 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 318 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 319 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 320 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 321 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 322 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 323 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 324 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 325 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 326 } 327 328 /* convert boot_device letter to something recognizable by the bios */ 329 static int boot_device2nibble(char boot_device) 330 { 331 switch(boot_device) { 332 case 'a': 333 case 'b': 334 return 0x01; /* floppy boot */ 335 case 'c': 336 return 0x02; /* hard drive boot */ 337 case 'd': 338 return 0x03; /* CD-ROM boot */ 339 case 'n': 340 return 0x04; /* Network boot */ 341 } 342 return 0; 343 } 344 345 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 346 const char *boot_device, Error **errp) 347 { 348 #define PC_MAX_BOOT_DEVICES 3 349 int nbds, bds[3] = { 0, }; 350 int i; 351 352 nbds = strlen(boot_device); 353 if (nbds > PC_MAX_BOOT_DEVICES) { 354 error_setg(errp, "Too many boot devices for PC"); 355 return; 356 } 357 for (i = 0; i < nbds; i++) { 358 bds[i] = boot_device2nibble(boot_device[i]); 359 if (bds[i] == 0) { 360 error_setg(errp, "Invalid boot device for PC: '%c'", 361 boot_device[i]); 362 return; 363 } 364 } 365 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 366 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 367 } 368 369 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 370 { 371 PCMachineState *pcms = opaque; 372 X86MachineState *x86ms = X86_MACHINE(pcms); 373 374 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 375 } 376 377 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 378 { 379 int val, nb; 380 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 381 FLOPPY_DRIVE_TYPE_NONE }; 382 383 #ifdef CONFIG_FDC_ISA 384 /* floppy type */ 385 if (floppy) { 386 for (int i = 0; i < 2; i++) { 387 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 388 } 389 } 390 #endif 391 392 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 393 cmos_get_fd_drive_type(fd_type[1]); 394 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 395 396 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 397 nb = 0; 398 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 399 nb++; 400 } 401 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 402 nb++; 403 } 404 switch (nb) { 405 case 0: 406 break; 407 case 1: 408 val |= 0x01; /* 1 drive, ready for boot */ 409 break; 410 case 2: 411 val |= 0x41; /* 2 drives, ready for boot */ 412 break; 413 } 414 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 415 } 416 417 typedef struct check_fdc_state { 418 ISADevice *floppy; 419 bool multiple; 420 } CheckFdcState; 421 422 static int check_fdc(Object *obj, void *opaque) 423 { 424 CheckFdcState *state = opaque; 425 Object *fdc; 426 uint32_t iobase; 427 Error *local_err = NULL; 428 429 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 430 if (!fdc) { 431 return 0; 432 } 433 434 iobase = object_property_get_uint(obj, "iobase", &local_err); 435 if (local_err || iobase != 0x3f0) { 436 error_free(local_err); 437 return 0; 438 } 439 440 if (state->floppy) { 441 state->multiple = true; 442 } else { 443 state->floppy = ISA_DEVICE(obj); 444 } 445 return 0; 446 } 447 448 static const char * const fdc_container_path[] = { 449 "unattached", "peripheral", "peripheral-anon" 450 }; 451 452 /* 453 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 454 * and ACPI objects. 455 */ 456 static ISADevice *pc_find_fdc0(void) 457 { 458 int i; 459 Object *container; 460 CheckFdcState state = { 0 }; 461 462 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 463 container = machine_get_container(fdc_container_path[i]); 464 object_child_foreach(container, check_fdc, &state); 465 } 466 467 if (state.multiple) { 468 warn_report("multiple floppy disk controllers with " 469 "iobase=0x3f0 have been found"); 470 error_printf("the one being picked for CMOS setup might not reflect " 471 "your intent"); 472 } 473 474 return state.floppy; 475 } 476 477 static void pc_cmos_init_late(PCMachineState *pcms) 478 { 479 X86MachineState *x86ms = X86_MACHINE(pcms); 480 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 481 int16_t cylinders; 482 int8_t heads, sectors; 483 int val; 484 int i, trans; 485 486 val = 0; 487 if (pcms->idebus[0] && 488 ide_get_geometry(pcms->idebus[0], 0, 489 &cylinders, &heads, §ors) >= 0) { 490 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 491 val |= 0xf0; 492 } 493 if (pcms->idebus[0] && 494 ide_get_geometry(pcms->idebus[0], 1, 495 &cylinders, &heads, §ors) >= 0) { 496 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 497 val |= 0x0f; 498 } 499 mc146818rtc_set_cmos_data(s, 0x12, val); 500 501 val = 0; 502 for (i = 0; i < 4; i++) { 503 /* NOTE: ide_get_geometry() returns the physical 504 geometry. It is always such that: 1 <= sects <= 63, 1 505 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 506 geometry can be different if a translation is done. */ 507 BusState *idebus = pcms->idebus[i / 2]; 508 if (idebus && 509 ide_get_geometry(idebus, i % 2, 510 &cylinders, &heads, §ors) >= 0) { 511 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 512 assert((trans & ~3) == 0); 513 val |= trans << (i * 2); 514 } 515 } 516 mc146818rtc_set_cmos_data(s, 0x39, val); 517 518 pc_cmos_init_floppy(s, pc_find_fdc0()); 519 520 /* various important CMOS locations needed by PC/Bochs bios */ 521 522 /* memory size */ 523 /* base memory (first MiB) */ 524 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 525 mc146818rtc_set_cmos_data(s, 0x15, val); 526 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 527 /* extended memory (next 64MiB) */ 528 if (x86ms->below_4g_mem_size > 1 * MiB) { 529 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 530 } else { 531 val = 0; 532 } 533 if (val > 65535) 534 val = 65535; 535 mc146818rtc_set_cmos_data(s, 0x17, val); 536 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 537 mc146818rtc_set_cmos_data(s, 0x30, val); 538 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 539 /* memory between 16MiB and 4GiB */ 540 if (x86ms->below_4g_mem_size > 16 * MiB) { 541 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 542 } else { 543 val = 0; 544 } 545 if (val > 65535) 546 val = 65535; 547 mc146818rtc_set_cmos_data(s, 0x34, val); 548 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 549 /* memory above 4GiB */ 550 val = x86ms->above_4g_mem_size / 65536; 551 mc146818rtc_set_cmos_data(s, 0x5b, val); 552 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 553 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 554 555 val = 0; 556 val |= 0x02; /* FPU is there */ 557 val |= 0x04; /* PS/2 mouse installed */ 558 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 559 } 560 561 static void handle_a20_line_change(void *opaque, int irq, int level) 562 { 563 X86CPU *cpu = opaque; 564 565 /* XXX: send to all CPUs ? */ 566 /* XXX: add logic to handle multiple A20 line sources */ 567 x86_cpu_set_a20(cpu, level); 568 } 569 570 #define NE2000_NB_MAX 6 571 572 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 573 0x280, 0x380 }; 574 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 575 576 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 577 { 578 static int nb_ne2k = 0; 579 580 if (nb_ne2k == NE2000_NB_MAX) { 581 error_setg(errp, 582 "maximum number of ISA NE2000 devices exceeded"); 583 return false; 584 } 585 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 586 ne2000_irq[nb_ne2k], nd); 587 nb_ne2k++; 588 return true; 589 } 590 591 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 592 { 593 X86CPU *cpu = opaque; 594 595 if (level) { 596 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 597 } 598 } 599 600 static 601 void pc_machine_done(Notifier *notifier, void *data) 602 { 603 PCMachineState *pcms = container_of(notifier, 604 PCMachineState, machine_done); 605 X86MachineState *x86ms = X86_MACHINE(pcms); 606 607 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 608 &error_fatal); 609 610 if (pcms->cxl_devices_state.is_enabled) { 611 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 612 } 613 614 /* set the number of CPUs */ 615 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 616 617 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 618 &error_abort); 619 620 acpi_setup(); 621 if (x86ms->fw_cfg) { 622 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 623 fw_cfg_add_e820(x86ms->fw_cfg); 624 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 625 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 626 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 627 } 628 629 pc_cmos_init_late(pcms); 630 } 631 632 /* setup pci memory address space mapping into system address space */ 633 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 634 MemoryRegion *pci_address_space) 635 { 636 /* Set to lower priority than RAM */ 637 memory_region_add_subregion_overlap(system_memory, 0x0, 638 pci_address_space, -1); 639 } 640 641 void xen_load_linux(PCMachineState *pcms) 642 { 643 int i; 644 FWCfgState *fw_cfg; 645 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 646 X86MachineState *x86ms = X86_MACHINE(pcms); 647 648 assert(MACHINE(pcms)->kernel_filename != NULL); 649 650 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 651 &address_space_memory); 652 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 653 rom_set_fw(fw_cfg); 654 655 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 656 for (i = 0; i < nb_option_roms; i++) { 657 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 658 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 659 !strcmp(option_rom[i].name, "pvh.bin") || 660 !strcmp(option_rom[i].name, "multiboot.bin") || 661 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 662 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 663 } 664 x86ms->fw_cfg = fw_cfg; 665 } 666 667 #define PC_ROM_MIN_VGA 0xc0000 668 #define PC_ROM_MIN_OPTION 0xc8000 669 #define PC_ROM_MAX 0xe0000 670 #define PC_ROM_ALIGN 0x800 671 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 672 673 static hwaddr pc_above_4g_end(PCMachineState *pcms) 674 { 675 X86MachineState *x86ms = X86_MACHINE(pcms); 676 677 if (pcms->sgx_epc.size != 0) { 678 return sgx_epc_above_4g_end(&pcms->sgx_epc); 679 } 680 681 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 682 } 683 684 static void pc_get_device_memory_range(PCMachineState *pcms, 685 hwaddr *base, 686 ram_addr_t *device_mem_size) 687 { 688 MachineState *machine = MACHINE(pcms); 689 ram_addr_t size; 690 hwaddr addr; 691 692 size = machine->maxram_size - machine->ram_size; 693 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 694 695 /* size device region assuming 1G page max alignment per slot */ 696 size += (1 * GiB) * machine->ram_slots; 697 698 *base = addr; 699 *device_mem_size = size; 700 } 701 702 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 703 { 704 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 705 MachineState *ms = MACHINE(pcms); 706 hwaddr cxl_base; 707 ram_addr_t size; 708 709 if (pcmc->has_reserved_memory && 710 (ms->ram_size < ms->maxram_size)) { 711 pc_get_device_memory_range(pcms, &cxl_base, &size); 712 cxl_base += size; 713 } else { 714 cxl_base = pc_above_4g_end(pcms); 715 } 716 717 return cxl_base; 718 } 719 720 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 721 { 722 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 723 724 if (pcms->cxl_devices_state.fixed_windows) { 725 GList *it; 726 727 start = ROUND_UP(start, 256 * MiB); 728 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 729 CXLFixedWindow *fw = it->data; 730 start += fw->size; 731 } 732 } 733 734 return start; 735 } 736 737 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 738 { 739 X86CPU *cpu = X86_CPU(first_cpu); 740 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 741 MachineState *ms = MACHINE(pcms); 742 743 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 744 /* 64-bit systems */ 745 return pc_pci_hole64_start() + pci_hole64_size - 1; 746 } 747 748 /* 32-bit systems */ 749 if (pcmc->broken_32bit_mem_addr_check) { 750 /* old value for compatibility reasons */ 751 return ((hwaddr)1 << cpu->phys_bits) - 1; 752 } 753 754 /* 755 * 32-bit systems don't have hole64 but they might have a region for 756 * memory devices. Even if additional hotplugged memory devices might 757 * not be usable by most guest OSes, we need to still consider them for 758 * calculating the highest possible GPA so that we can properly report 759 * if someone configures them on a CPU that cannot possibly address them. 760 */ 761 if (pcmc->has_reserved_memory && 762 (ms->ram_size < ms->maxram_size)) { 763 hwaddr devmem_start; 764 ram_addr_t devmem_size; 765 766 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 767 devmem_start += devmem_size; 768 return devmem_start - 1; 769 } 770 771 /* configuration without any memory hotplug */ 772 return pc_above_4g_end(pcms) - 1; 773 } 774 775 /* 776 * AMD systems with an IOMMU have an additional hole close to the 777 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 778 * on kernel version, VFIO may or may not let you DMA map those ranges. 779 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 780 * with certain memory sizes. It's also wrong to use those IOVA ranges 781 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 782 * The ranges reserved for Hyper-Transport are: 783 * 784 * FD_0000_0000h - FF_FFFF_FFFFh 785 * 786 * The ranges represent the following: 787 * 788 * Base Address Top Address Use 789 * 790 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 791 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 792 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 793 * FD_F910_0000h FD_F91F_FFFFh System Management 794 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 795 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 796 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 797 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 798 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 799 * FE_2000_0000h FF_FFFF_FFFFh Reserved 800 * 801 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 802 * Table 3: Special Address Controls (GPA) for more information. 803 */ 804 #define AMD_HT_START 0xfd00000000UL 805 #define AMD_HT_END 0xffffffffffUL 806 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 807 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 808 809 void pc_memory_init(PCMachineState *pcms, 810 MemoryRegion *system_memory, 811 MemoryRegion *rom_memory, 812 uint64_t pci_hole64_size) 813 { 814 int linux_boot, i; 815 MemoryRegion *option_rom_mr; 816 MemoryRegion *ram_below_4g, *ram_above_4g; 817 FWCfgState *fw_cfg; 818 MachineState *machine = MACHINE(pcms); 819 MachineClass *mc = MACHINE_GET_CLASS(machine); 820 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 821 X86MachineState *x86ms = X86_MACHINE(pcms); 822 hwaddr maxphysaddr, maxusedaddr; 823 hwaddr cxl_base, cxl_resv_end = 0; 824 X86CPU *cpu = X86_CPU(first_cpu); 825 826 assert(machine->ram_size == x86ms->below_4g_mem_size + 827 x86ms->above_4g_mem_size); 828 829 linux_boot = (machine->kernel_filename != NULL); 830 831 /* 832 * The HyperTransport range close to the 1T boundary is unique to AMD 833 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 834 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 835 * older machine types (<= 7.0) for compatibility purposes. 836 */ 837 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 838 /* Bail out if max possible address does not cross HT range */ 839 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 840 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 841 } 842 843 /* 844 * Advertise the HT region if address space covers the reserved 845 * region or if we relocate. 846 */ 847 if (cpu->phys_bits >= 40) { 848 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 849 } 850 } 851 852 /* 853 * phys-bits is required to be appropriately configured 854 * to make sure max used GPA is reachable. 855 */ 856 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 857 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 858 if (maxphysaddr < maxusedaddr) { 859 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 860 " phys-bits too low (%u)", 861 maxphysaddr, maxusedaddr, cpu->phys_bits); 862 exit(EXIT_FAILURE); 863 } 864 865 /* 866 * Split single memory region and use aliases to address portions of it, 867 * done for backwards compatibility with older qemus. 868 */ 869 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 870 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 871 0, x86ms->below_4g_mem_size); 872 memory_region_add_subregion(system_memory, 0, ram_below_4g); 873 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 874 if (x86ms->above_4g_mem_size > 0) { 875 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 876 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 877 machine->ram, 878 x86ms->below_4g_mem_size, 879 x86ms->above_4g_mem_size); 880 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 881 ram_above_4g); 882 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 883 E820_RAM); 884 } 885 886 if (pcms->sgx_epc.size != 0) { 887 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 888 } 889 890 if (!pcmc->has_reserved_memory && 891 (machine->ram_slots || 892 (machine->maxram_size > machine->ram_size))) { 893 894 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 895 mc->name); 896 exit(EXIT_FAILURE); 897 } 898 899 /* initialize device memory address space */ 900 if (pcmc->has_reserved_memory && 901 (machine->ram_size < machine->maxram_size)) { 902 ram_addr_t device_mem_size; 903 hwaddr device_mem_base; 904 905 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 906 error_report("unsupported amount of memory slots: %"PRIu64, 907 machine->ram_slots); 908 exit(EXIT_FAILURE); 909 } 910 911 if (QEMU_ALIGN_UP(machine->maxram_size, 912 TARGET_PAGE_SIZE) != machine->maxram_size) { 913 error_report("maximum memory size must by aligned to multiple of " 914 "%d bytes", TARGET_PAGE_SIZE); 915 exit(EXIT_FAILURE); 916 } 917 918 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 919 920 if (device_mem_base + device_mem_size < device_mem_size) { 921 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 922 machine->maxram_size); 923 exit(EXIT_FAILURE); 924 } 925 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 926 } 927 928 if (pcms->cxl_devices_state.is_enabled) { 929 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 930 hwaddr cxl_size = MiB; 931 932 cxl_base = pc_get_cxl_range_start(pcms); 933 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 934 memory_region_add_subregion(system_memory, cxl_base, mr); 935 cxl_resv_end = cxl_base + cxl_size; 936 if (pcms->cxl_devices_state.fixed_windows) { 937 hwaddr cxl_fmw_base; 938 GList *it; 939 940 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 941 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 942 CXLFixedWindow *fw = it->data; 943 944 fw->base = cxl_fmw_base; 945 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 946 "cxl-fixed-memory-region", fw->size); 947 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 948 cxl_fmw_base += fw->size; 949 cxl_resv_end = cxl_fmw_base; 950 } 951 } 952 } 953 954 /* Initialize PC system firmware */ 955 pc_system_firmware_init(pcms, rom_memory); 956 957 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 958 if (machine_require_guest_memfd(machine)) { 959 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 960 PC_ROM_SIZE, &error_fatal); 961 } else { 962 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 963 &error_fatal); 964 if (pcmc->pci_enabled) { 965 memory_region_set_readonly(option_rom_mr, true); 966 } 967 } 968 memory_region_add_subregion_overlap(rom_memory, 969 PC_ROM_MIN_VGA, 970 option_rom_mr, 971 1); 972 973 fw_cfg = fw_cfg_arch_create(machine, 974 x86ms->boot_cpus, x86ms->apic_id_limit); 975 976 rom_set_fw(fw_cfg); 977 978 if (machine->device_memory) { 979 uint64_t *val = g_malloc(sizeof(*val)); 980 uint64_t res_mem_end; 981 982 if (pcms->cxl_devices_state.is_enabled) { 983 res_mem_end = cxl_resv_end; 984 } else { 985 res_mem_end = machine->device_memory->base 986 + memory_region_size(&machine->device_memory->mr); 987 } 988 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 989 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 990 } 991 992 if (linux_boot) { 993 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 994 } 995 996 for (i = 0; i < nb_option_roms; i++) { 997 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 998 } 999 x86ms->fw_cfg = fw_cfg; 1000 1001 /* Init default IOAPIC address space */ 1002 x86ms->ioapic_as = &address_space_memory; 1003 1004 /* Init ACPI memory hotplug IO base address */ 1005 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1006 } 1007 1008 /* 1009 * The 64bit pci hole starts after "above 4G RAM" and 1010 * potentially the space reserved for memory hotplug. 1011 */ 1012 uint64_t pc_pci_hole64_start(void) 1013 { 1014 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1015 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1016 MachineState *ms = MACHINE(pcms); 1017 uint64_t hole64_start = 0; 1018 ram_addr_t size = 0; 1019 1020 if (pcms->cxl_devices_state.is_enabled) { 1021 hole64_start = pc_get_cxl_range_end(pcms); 1022 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1023 pc_get_device_memory_range(pcms, &hole64_start, &size); 1024 hole64_start += size; 1025 } else { 1026 hole64_start = pc_above_4g_end(pcms); 1027 } 1028 1029 return ROUND_UP(hole64_start, 1 * GiB); 1030 } 1031 1032 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1033 { 1034 DeviceState *dev = NULL; 1035 1036 if (pci_bus) { 1037 PCIDevice *pcidev = pci_vga_init(pci_bus); 1038 dev = pcidev ? &pcidev->qdev : NULL; 1039 } else if (isa_bus) { 1040 ISADevice *isadev = isa_vga_init(isa_bus); 1041 dev = isadev ? DEVICE(isadev) : NULL; 1042 } 1043 1044 return dev; 1045 } 1046 1047 static const MemoryRegionOps ioport80_io_ops = { 1048 .write = ioport80_write, 1049 .read = ioport80_read, 1050 .endianness = DEVICE_LITTLE_ENDIAN, 1051 .impl = { 1052 .min_access_size = 1, 1053 .max_access_size = 1, 1054 }, 1055 }; 1056 1057 static const MemoryRegionOps ioportF0_io_ops = { 1058 .write = ioportF0_write, 1059 .read = ioportF0_read, 1060 .endianness = DEVICE_LITTLE_ENDIAN, 1061 .impl = { 1062 .min_access_size = 1, 1063 .max_access_size = 1, 1064 }, 1065 }; 1066 1067 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1068 bool create_i8042, bool no_vmport, Error **errp) 1069 { 1070 int i; 1071 DriveInfo *fd[MAX_FD]; 1072 qemu_irq *a20_line; 1073 ISADevice *i8042, *port92, *vmmouse; 1074 1075 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1076 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1077 1078 for (i = 0; i < MAX_FD; i++) { 1079 fd[i] = drive_get(IF_FLOPPY, 0, i); 1080 create_fdctrl |= !!fd[i]; 1081 } 1082 if (create_fdctrl) { 1083 #ifdef CONFIG_FDC_ISA 1084 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1085 if (fdc) { 1086 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1087 isa_fdc_init_drives(fdc, fd); 1088 } 1089 #endif 1090 } 1091 1092 if (!create_i8042) { 1093 if (!no_vmport) { 1094 error_setg(errp, 1095 "vmport requires the i8042 controller to be enabled"); 1096 } 1097 return; 1098 } 1099 1100 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1101 if (!no_vmport) { 1102 isa_create_simple(isa_bus, TYPE_VMPORT); 1103 vmmouse = isa_try_new("vmmouse"); 1104 } else { 1105 vmmouse = NULL; 1106 } 1107 if (vmmouse) { 1108 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1109 &error_abort); 1110 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1111 } 1112 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1113 1114 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1115 qdev_connect_gpio_out_named(DEVICE(i8042), 1116 I8042_A20_LINE, 0, a20_line[0]); 1117 qdev_connect_gpio_out_named(DEVICE(port92), 1118 PORT92_A20_LINE, 0, a20_line[1]); 1119 g_free(a20_line); 1120 } 1121 1122 void pc_basic_device_init(struct PCMachineState *pcms, 1123 ISABus *isa_bus, qemu_irq *gsi, 1124 ISADevice *rtc_state, 1125 bool create_fdctrl, 1126 uint32_t hpet_irqs) 1127 { 1128 int i; 1129 DeviceState *hpet = NULL; 1130 int pit_isa_irq = 0; 1131 qemu_irq pit_alt_irq = NULL; 1132 ISADevice *pit = NULL; 1133 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1134 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1135 X86MachineState *x86ms = X86_MACHINE(pcms); 1136 1137 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1138 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1139 1140 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1141 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1142 1143 /* 1144 * Check if an HPET shall be created. 1145 */ 1146 if (pcms->hpet_enabled) { 1147 qemu_irq rtc_irq; 1148 1149 hpet = qdev_try_new(TYPE_HPET); 1150 if (!hpet) { 1151 error_report("couldn't create HPET device"); 1152 exit(1); 1153 } 1154 /* 1155 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1156 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1157 * the property, use whatever mask they specified. 1158 */ 1159 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1160 HPET_INTCAP, NULL); 1161 if (!compat) { 1162 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1163 } 1164 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1165 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1166 1167 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1168 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1169 } 1170 pit_isa_irq = -1; 1171 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1172 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1173 1174 /* overwrite connection created by south bridge */ 1175 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1176 } 1177 1178 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1179 "date"); 1180 1181 #ifdef CONFIG_XEN_EMU 1182 if (xen_mode == XEN_EMULATE) { 1183 xen_overlay_create(); 1184 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1185 xen_gnttab_create(); 1186 xen_xenstore_create(); 1187 if (pcms->pcibus) { 1188 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1189 } 1190 xen_bus_init(); 1191 } 1192 #endif 1193 1194 qemu_register_boot_set(pc_boot_set, pcms); 1195 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1196 MACHINE(pcms)->boot_config.order, &error_fatal); 1197 1198 if (!xen_enabled() && 1199 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1200 if (kvm_pit_in_kernel()) { 1201 pit = kvm_pit_init(isa_bus, 0x40); 1202 } else { 1203 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1204 } 1205 if (hpet) { 1206 /* connect PIT to output control line of the HPET */ 1207 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1208 } 1209 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1210 OBJECT(pit), &error_fatal); 1211 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1212 } 1213 1214 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1215 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1216 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1217 } 1218 1219 /* Super I/O */ 1220 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1221 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1222 1223 pcms->machine_done.notify = pc_machine_done; 1224 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1225 } 1226 1227 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1228 { 1229 MachineClass *mc = MACHINE_CLASS(pcmc); 1230 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1231 NICInfo *nd; 1232 1233 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1234 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1235 } 1236 1237 /* Anything remaining should be a PCI NIC */ 1238 if (pci_bus) { 1239 pci_init_nic_devices(pci_bus, mc->default_nic); 1240 } 1241 } 1242 1243 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1244 { 1245 qemu_irq *i8259; 1246 1247 if (kvm_pic_in_kernel()) { 1248 i8259 = kvm_i8259_init(isa_bus); 1249 } else if (xen_enabled()) { 1250 i8259 = xen_interrupt_controller_init(); 1251 } else { 1252 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1253 } 1254 1255 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1256 i8259_irqs[i] = i8259[i]; 1257 } 1258 1259 g_free(i8259); 1260 } 1261 1262 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1263 Error **errp) 1264 { 1265 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1266 const MachineState *ms = MACHINE(hotplug_dev); 1267 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1268 Error *local_err = NULL; 1269 1270 /* 1271 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1272 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1273 * addition to cover this case. 1274 */ 1275 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1276 error_setg(errp, 1277 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1278 return; 1279 } 1280 1281 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1282 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1283 return; 1284 } 1285 1286 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1287 if (local_err) { 1288 error_propagate(errp, local_err); 1289 return; 1290 } 1291 1292 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1293 } 1294 1295 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1296 DeviceState *dev, Error **errp) 1297 { 1298 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1299 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1300 MachineState *ms = MACHINE(hotplug_dev); 1301 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1302 1303 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1304 1305 if (is_nvdimm) { 1306 nvdimm_plug(ms->nvdimms_state); 1307 } 1308 1309 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1310 } 1311 1312 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1313 DeviceState *dev, Error **errp) 1314 { 1315 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1316 1317 /* 1318 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1319 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1320 * addition to cover this case. 1321 */ 1322 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1323 error_setg(errp, 1324 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1325 return; 1326 } 1327 1328 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1329 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1330 return; 1331 } 1332 1333 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1334 errp); 1335 } 1336 1337 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1338 DeviceState *dev, Error **errp) 1339 { 1340 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1341 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1342 Error *local_err = NULL; 1343 1344 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1345 if (local_err) { 1346 goto out; 1347 } 1348 1349 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1350 qdev_unrealize(dev); 1351 out: 1352 error_propagate(errp, local_err); 1353 } 1354 1355 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1356 DeviceState *dev, Error **errp) 1357 { 1358 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1359 g_assert(!dev->hotplugged); 1360 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1361 } 1362 1363 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1364 DeviceState *dev, Error **errp) 1365 { 1366 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1367 } 1368 1369 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1370 DeviceState *dev, Error **errp) 1371 { 1372 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1373 pc_memory_pre_plug(hotplug_dev, dev, errp); 1374 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1375 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1376 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1377 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1379 /* Declare the APIC range as the reserved MSI region */ 1380 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1381 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1382 QList *reserved_regions = qlist_new(); 1383 1384 qlist_append_str(reserved_regions, resv_prop_str); 1385 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1386 1387 g_free(resv_prop_str); 1388 } 1389 1390 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1391 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1392 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1393 1394 if (pcms->iommu) { 1395 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1396 "for x86 yet."); 1397 return; 1398 } 1399 pcms->iommu = dev; 1400 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1401 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1402 } 1403 } 1404 1405 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1406 DeviceState *dev, Error **errp) 1407 { 1408 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1409 pc_memory_plug(hotplug_dev, dev, errp); 1410 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1411 x86_cpu_plug(hotplug_dev, dev, errp); 1412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1413 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1415 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1416 } 1417 } 1418 1419 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1420 DeviceState *dev, Error **errp) 1421 { 1422 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1423 pc_memory_unplug_request(hotplug_dev, dev, errp); 1424 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1425 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1426 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1427 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1428 errp); 1429 } else { 1430 error_setg(errp, "acpi: device unplug request for not supported device" 1431 " type: %s", object_get_typename(OBJECT(dev))); 1432 } 1433 } 1434 1435 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1436 DeviceState *dev, Error **errp) 1437 { 1438 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1439 pc_memory_unplug(hotplug_dev, dev, errp); 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1441 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1443 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1444 } else { 1445 error_setg(errp, "acpi: device unplug for not supported device" 1446 " type: %s", object_get_typename(OBJECT(dev))); 1447 } 1448 } 1449 1450 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1451 DeviceState *dev) 1452 { 1453 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1454 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1455 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1456 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1457 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1458 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1459 return HOTPLUG_HANDLER(machine); 1460 } 1461 1462 return NULL; 1463 } 1464 1465 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1466 void *opaque, Error **errp) 1467 { 1468 PCMachineState *pcms = PC_MACHINE(obj); 1469 OnOffAuto vmport = pcms->vmport; 1470 1471 visit_type_OnOffAuto(v, name, &vmport, errp); 1472 } 1473 1474 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1475 void *opaque, Error **errp) 1476 { 1477 PCMachineState *pcms = PC_MACHINE(obj); 1478 1479 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1480 } 1481 1482 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1483 { 1484 PCMachineState *pcms = PC_MACHINE(obj); 1485 1486 return pcms->fd_bootchk; 1487 } 1488 1489 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1490 { 1491 PCMachineState *pcms = PC_MACHINE(obj); 1492 1493 pcms->fd_bootchk = value; 1494 } 1495 1496 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1497 { 1498 PCMachineState *pcms = PC_MACHINE(obj); 1499 1500 return pcms->smbus_enabled; 1501 } 1502 1503 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1504 { 1505 PCMachineState *pcms = PC_MACHINE(obj); 1506 1507 pcms->smbus_enabled = value; 1508 } 1509 1510 static bool pc_machine_get_sata(Object *obj, Error **errp) 1511 { 1512 PCMachineState *pcms = PC_MACHINE(obj); 1513 1514 return pcms->sata_enabled; 1515 } 1516 1517 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1518 { 1519 PCMachineState *pcms = PC_MACHINE(obj); 1520 1521 pcms->sata_enabled = value; 1522 } 1523 1524 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1525 { 1526 PCMachineState *pcms = PC_MACHINE(obj); 1527 1528 return pcms->hpet_enabled; 1529 } 1530 1531 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1532 { 1533 PCMachineState *pcms = PC_MACHINE(obj); 1534 1535 pcms->hpet_enabled = value; 1536 } 1537 1538 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1539 { 1540 PCMachineState *pcms = PC_MACHINE(obj); 1541 1542 return pcms->i8042_enabled; 1543 } 1544 1545 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1546 { 1547 PCMachineState *pcms = PC_MACHINE(obj); 1548 1549 pcms->i8042_enabled = value; 1550 } 1551 1552 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1553 { 1554 PCMachineState *pcms = PC_MACHINE(obj); 1555 1556 return pcms->default_bus_bypass_iommu; 1557 } 1558 1559 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1560 Error **errp) 1561 { 1562 PCMachineState *pcms = PC_MACHINE(obj); 1563 1564 pcms->default_bus_bypass_iommu = value; 1565 } 1566 1567 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1568 void *opaque, Error **errp) 1569 { 1570 PCMachineState *pcms = PC_MACHINE(obj); 1571 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1572 1573 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1574 } 1575 1576 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1577 void *opaque, Error **errp) 1578 { 1579 PCMachineState *pcms = PC_MACHINE(obj); 1580 1581 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1582 } 1583 1584 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1585 const char *name, void *opaque, 1586 Error **errp) 1587 { 1588 PCMachineState *pcms = PC_MACHINE(obj); 1589 uint64_t value = pcms->max_ram_below_4g; 1590 1591 visit_type_size(v, name, &value, errp); 1592 } 1593 1594 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1595 const char *name, void *opaque, 1596 Error **errp) 1597 { 1598 PCMachineState *pcms = PC_MACHINE(obj); 1599 uint64_t value; 1600 1601 if (!visit_type_size(v, name, &value, errp)) { 1602 return; 1603 } 1604 if (value > 4 * GiB) { 1605 error_setg(errp, 1606 "Machine option 'max-ram-below-4g=%"PRIu64 1607 "' expects size less than or equal to 4G", value); 1608 return; 1609 } 1610 1611 if (value < 1 * MiB) { 1612 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1613 "BIOS may not work with less than 1MiB", value); 1614 } 1615 1616 pcms->max_ram_below_4g = value; 1617 } 1618 1619 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1620 const char *name, void *opaque, 1621 Error **errp) 1622 { 1623 PCMachineState *pcms = PC_MACHINE(obj); 1624 uint64_t value = pcms->max_fw_size; 1625 1626 visit_type_size(v, name, &value, errp); 1627 } 1628 1629 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1630 const char *name, void *opaque, 1631 Error **errp) 1632 { 1633 PCMachineState *pcms = PC_MACHINE(obj); 1634 uint64_t value; 1635 1636 if (!visit_type_size(v, name, &value, errp)) { 1637 return; 1638 } 1639 1640 /* 1641 * We don't have a theoretically justifiable exact lower bound on the base 1642 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1643 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1644 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1645 * 16MiB in size. 1646 */ 1647 if (value > 16 * MiB) { 1648 error_setg(errp, 1649 "User specified max allowed firmware size %" PRIu64 " is " 1650 "greater than 16MiB. If combined firmware size exceeds " 1651 "16MiB the system may not boot, or experience intermittent" 1652 "stability issues.", 1653 value); 1654 return; 1655 } 1656 1657 pcms->max_fw_size = value; 1658 } 1659 1660 1661 static void pc_machine_initfn(Object *obj) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(obj); 1664 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1665 1666 #ifdef CONFIG_VMPORT 1667 pcms->vmport = ON_OFF_AUTO_AUTO; 1668 #else 1669 pcms->vmport = ON_OFF_AUTO_OFF; 1670 #endif /* CONFIG_VMPORT */ 1671 pcms->max_ram_below_4g = 0; /* use default */ 1672 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1673 pcms->south_bridge = pcmc->default_south_bridge; 1674 1675 /* acpi build is enabled by default if machine supports it */ 1676 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1677 pcms->smbus_enabled = true; 1678 pcms->sata_enabled = true; 1679 pcms->i8042_enabled = true; 1680 pcms->max_fw_size = 8 * MiB; 1681 #if defined(CONFIG_HPET) 1682 pcms->hpet_enabled = true; 1683 #endif 1684 pcms->fd_bootchk = true; 1685 pcms->default_bus_bypass_iommu = false; 1686 1687 pc_system_flash_create(pcms); 1688 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1689 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1690 OBJECT(pcms->pcspk), "audiodev"); 1691 if (pcmc->pci_enabled) { 1692 cxl_machine_init(obj, &pcms->cxl_devices_state); 1693 } 1694 } 1695 1696 static void pc_machine_reset(MachineState *machine, ResetType type) 1697 { 1698 CPUState *cs; 1699 X86CPU *cpu; 1700 1701 qemu_devices_reset(type); 1702 1703 /* Reset APIC after devices have been reset to cancel 1704 * any changes that qemu_devices_reset() might have done. 1705 */ 1706 CPU_FOREACH(cs) { 1707 cpu = X86_CPU(cs); 1708 1709 x86_cpu_after_reset(cpu); 1710 } 1711 } 1712 1713 static void pc_machine_wakeup(MachineState *machine) 1714 { 1715 cpu_synchronize_all_states(); 1716 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1717 cpu_synchronize_all_post_reset(); 1718 } 1719 1720 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1721 { 1722 X86IOMMUState *iommu = x86_iommu_get_default(); 1723 IntelIOMMUState *intel_iommu; 1724 1725 if (iommu && 1726 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1727 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1728 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1729 if (!intel_iommu->caching_mode) { 1730 error_setg(errp, "Device assignment is not allowed without " 1731 "enabling caching-mode=on for Intel IOMMU."); 1732 return false; 1733 } 1734 } 1735 1736 return true; 1737 } 1738 1739 static void pc_machine_class_init(ObjectClass *oc, const void *data) 1740 { 1741 MachineClass *mc = MACHINE_CLASS(oc); 1742 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1743 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1744 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1745 1746 pcmc->pci_enabled = true; 1747 pcmc->has_acpi_build = true; 1748 pcmc->smbios_defaults = true; 1749 pcmc->gigabyte_align = true; 1750 pcmc->has_reserved_memory = true; 1751 pcmc->enforce_amd_1tb_hole = true; 1752 pcmc->isa_bios_alias = true; 1753 pcmc->pvh_enabled = true; 1754 pcmc->kvmclock_create_always = true; 1755 x86mc->apic_xrupt_override = true; 1756 assert(!mc->get_hotplug_handler); 1757 mc->get_hotplug_handler = pc_get_hotplug_handler; 1758 mc->hotplug_allowed = pc_hotplug_allowed; 1759 mc->auto_enable_numa_with_memhp = true; 1760 mc->auto_enable_numa_with_memdev = true; 1761 mc->has_hotpluggable_cpus = true; 1762 mc->default_boot_order = "cad"; 1763 mc->block_default_type = IF_IDE; 1764 mc->max_cpus = 255; 1765 mc->reset = pc_machine_reset; 1766 mc->wakeup = pc_machine_wakeup; 1767 hc->pre_plug = pc_machine_device_pre_plug_cb; 1768 hc->plug = pc_machine_device_plug_cb; 1769 hc->unplug_request = pc_machine_device_unplug_request_cb; 1770 hc->unplug = pc_machine_device_unplug_cb; 1771 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1772 mc->nvdimm_supported = true; 1773 mc->smp_props.dies_supported = true; 1774 mc->smp_props.modules_supported = true; 1775 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1776 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1777 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1778 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1779 mc->default_ram_id = "pc.ram"; 1780 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1781 1782 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1783 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1784 NULL, NULL); 1785 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1786 "Maximum ram below the 4G boundary (32bit boundary)"); 1787 1788 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1789 pc_machine_get_vmport, pc_machine_set_vmport, 1790 NULL, NULL); 1791 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1792 "Enable vmport (pc & q35)"); 1793 1794 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1795 pc_machine_get_smbus, pc_machine_set_smbus); 1796 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1797 "Enable/disable system management bus"); 1798 1799 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1800 pc_machine_get_sata, pc_machine_set_sata); 1801 object_class_property_set_description(oc, PC_MACHINE_SATA, 1802 "Enable/disable Serial ATA bus"); 1803 1804 object_class_property_add_bool(oc, "hpet", 1805 pc_machine_get_hpet, pc_machine_set_hpet); 1806 object_class_property_set_description(oc, "hpet", 1807 "Enable/disable high precision event timer emulation"); 1808 1809 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1810 pc_machine_get_i8042, pc_machine_set_i8042); 1811 object_class_property_set_description(oc, PC_MACHINE_I8042, 1812 "Enable/disable Intel 8042 PS/2 controller emulation"); 1813 1814 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1815 pc_machine_get_default_bus_bypass_iommu, 1816 pc_machine_set_default_bus_bypass_iommu); 1817 1818 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1819 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1820 NULL, NULL); 1821 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1822 "Maximum combined firmware size"); 1823 1824 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1825 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1826 NULL, NULL); 1827 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1828 "SMBIOS Entry Point type [32, 64]"); 1829 1830 object_class_property_add_bool(oc, "fd-bootchk", 1831 pc_machine_get_fd_bootchk, 1832 pc_machine_set_fd_bootchk); 1833 } 1834 1835 static const TypeInfo pc_machine_info = { 1836 .name = TYPE_PC_MACHINE, 1837 .parent = TYPE_X86_MACHINE, 1838 .abstract = true, 1839 .instance_size = sizeof(PCMachineState), 1840 .instance_init = pc_machine_initfn, 1841 .class_size = sizeof(PCMachineClass), 1842 .class_init = pc_machine_class_init, 1843 .interfaces = (const InterfaceInfo[]) { 1844 { TYPE_HOTPLUG_HANDLER }, 1845 { } 1846 }, 1847 }; 1848 1849 static void pc_machine_register_types(void) 1850 { 1851 type_register_static(&pc_machine_info); 1852 } 1853 1854 type_init(pc_machine_register_types) 1855