1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/i386/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/cpu/icc_bus.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 81 * (128K) and other BIOS datastructures (less than 4K reported to be used at 82 * the moment, 32K should be enough for a while). */ 83 static unsigned acpi_data_size = 0x20000 + 0x8000; 84 void pc_set_legacy_acpi_data_size(void) 85 { 86 acpi_data_size = 0x10000; 87 } 88 89 #define BIOS_CFG_IOPORT 0x510 90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 95 96 #define E820_NR_ENTRIES 16 97 98 struct e820_entry { 99 uint64_t address; 100 uint64_t length; 101 uint32_t type; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 struct e820_table { 105 uint32_t count; 106 struct e820_entry entry[E820_NR_ENTRIES]; 107 } QEMU_PACKED __attribute((__aligned__(4))); 108 109 static struct e820_table e820_reserve; 110 static struct e820_entry *e820_table; 111 static unsigned e820_entries; 112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 113 114 void gsi_handler(void *opaque, int n, int level) 115 { 116 GSIState *s = opaque; 117 118 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 119 if (n < ISA_NUM_IRQS) { 120 qemu_set_irq(s->i8259_irq[n], level); 121 } 122 qemu_set_irq(s->ioapic_irq[n], level); 123 } 124 125 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 126 unsigned size) 127 { 128 } 129 130 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 131 { 132 return 0xffffffffffffffffULL; 133 } 134 135 /* MSDOS compatibility mode FPU exception support */ 136 static qemu_irq ferr_irq; 137 138 void pc_register_ferr_irq(qemu_irq irq) 139 { 140 ferr_irq = irq; 141 } 142 143 /* XXX: add IGNNE support */ 144 void cpu_set_ferr(CPUX86State *s) 145 { 146 qemu_irq_raise(ferr_irq); 147 } 148 149 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 150 unsigned size) 151 { 152 qemu_irq_lower(ferr_irq); 153 } 154 155 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 156 { 157 return 0xffffffffffffffffULL; 158 } 159 160 /* TSC handling */ 161 uint64_t cpu_get_tsc(CPUX86State *env) 162 { 163 return cpu_get_ticks(); 164 } 165 166 /* IRQ handling */ 167 int cpu_get_pic_interrupt(CPUX86State *env) 168 { 169 X86CPU *cpu = x86_env_get_cpu(env); 170 int intno; 171 172 intno = apic_get_interrupt(cpu->apic_state); 173 if (intno >= 0) { 174 return intno; 175 } 176 /* read the irq from the PIC */ 177 if (!apic_accept_pic_intr(cpu->apic_state)) { 178 return -1; 179 } 180 181 intno = pic_read_irq(isa_pic); 182 return intno; 183 } 184 185 static void pic_irq_request(void *opaque, int irq, int level) 186 { 187 CPUState *cs = first_cpu; 188 X86CPU *cpu = X86_CPU(cs); 189 190 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 191 if (cpu->apic_state) { 192 CPU_FOREACH(cs) { 193 cpu = X86_CPU(cs); 194 if (apic_accept_pic_intr(cpu->apic_state)) { 195 apic_deliver_pic_intr(cpu->apic_state, level); 196 } 197 } 198 } else { 199 if (level) { 200 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 201 } else { 202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 203 } 204 } 205 } 206 207 /* PC cmos mappings */ 208 209 #define REG_EQUIPMENT_BYTE 0x14 210 211 static int cmos_get_fd_drive_type(FDriveType fd0) 212 { 213 int val; 214 215 switch (fd0) { 216 case FDRIVE_DRV_144: 217 /* 1.44 Mb 3"5 drive */ 218 val = 4; 219 break; 220 case FDRIVE_DRV_288: 221 /* 2.88 Mb 3"5 drive */ 222 val = 5; 223 break; 224 case FDRIVE_DRV_120: 225 /* 1.2 Mb 5"5 drive */ 226 val = 2; 227 break; 228 case FDRIVE_DRV_NONE: 229 default: 230 val = 0; 231 break; 232 } 233 return val; 234 } 235 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 237 int16_t cylinders, int8_t heads, int8_t sectors) 238 { 239 rtc_set_memory(s, type_ofs, 47); 240 rtc_set_memory(s, info_ofs, cylinders); 241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 242 rtc_set_memory(s, info_ofs + 2, heads); 243 rtc_set_memory(s, info_ofs + 3, 0xff); 244 rtc_set_memory(s, info_ofs + 4, 0xff); 245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 246 rtc_set_memory(s, info_ofs + 6, cylinders); 247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 8, sectors); 249 } 250 251 /* convert boot_device letter to something recognizable by the bios */ 252 static int boot_device2nibble(char boot_device) 253 { 254 switch(boot_device) { 255 case 'a': 256 case 'b': 257 return 0x01; /* floppy boot */ 258 case 'c': 259 return 0x02; /* hard drive boot */ 260 case 'd': 261 return 0x03; /* CD-ROM boot */ 262 case 'n': 263 return 0x04; /* Network boot */ 264 } 265 return 0; 266 } 267 268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 269 { 270 #define PC_MAX_BOOT_DEVICES 3 271 int nbds, bds[3] = { 0, }; 272 int i; 273 274 nbds = strlen(boot_device); 275 if (nbds > PC_MAX_BOOT_DEVICES) { 276 error_setg(errp, "Too many boot devices for PC"); 277 return; 278 } 279 for (i = 0; i < nbds; i++) { 280 bds[i] = boot_device2nibble(boot_device[i]); 281 if (bds[i] == 0) { 282 error_setg(errp, "Invalid boot device for PC: '%c'", 283 boot_device[i]); 284 return; 285 } 286 } 287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 289 } 290 291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 292 { 293 set_boot_dev(opaque, boot_device, errp); 294 } 295 296 typedef struct pc_cmos_init_late_arg { 297 ISADevice *rtc_state; 298 BusState *idebus[2]; 299 } pc_cmos_init_late_arg; 300 301 static void pc_cmos_init_late(void *opaque) 302 { 303 pc_cmos_init_late_arg *arg = opaque; 304 ISADevice *s = arg->rtc_state; 305 int16_t cylinders; 306 int8_t heads, sectors; 307 int val; 308 int i, trans; 309 310 val = 0; 311 if (ide_get_geometry(arg->idebus[0], 0, 312 &cylinders, &heads, §ors) >= 0) { 313 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 314 val |= 0xf0; 315 } 316 if (ide_get_geometry(arg->idebus[0], 1, 317 &cylinders, &heads, §ors) >= 0) { 318 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 319 val |= 0x0f; 320 } 321 rtc_set_memory(s, 0x12, val); 322 323 val = 0; 324 for (i = 0; i < 4; i++) { 325 /* NOTE: ide_get_geometry() returns the physical 326 geometry. It is always such that: 1 <= sects <= 63, 1 327 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 328 geometry can be different if a translation is done. */ 329 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 330 &cylinders, &heads, §ors) >= 0) { 331 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 332 assert((trans & ~3) == 0); 333 val |= trans << (i * 2); 334 } 335 } 336 rtc_set_memory(s, 0x39, val); 337 338 qemu_unregister_reset(pc_cmos_init_late, opaque); 339 } 340 341 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 342 const char *boot_device, MachineState *machine, 343 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 344 ISADevice *s) 345 { 346 int val, nb, i; 347 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 348 static pc_cmos_init_late_arg arg; 349 PCMachineState *pc_machine = PC_MACHINE(machine); 350 Error *local_err = NULL; 351 352 /* various important CMOS locations needed by PC/Bochs bios */ 353 354 /* memory size */ 355 /* base memory (first MiB) */ 356 val = MIN(ram_size / 1024, 640); 357 rtc_set_memory(s, 0x15, val); 358 rtc_set_memory(s, 0x16, val >> 8); 359 /* extended memory (next 64MiB) */ 360 if (ram_size > 1024 * 1024) { 361 val = (ram_size - 1024 * 1024) / 1024; 362 } else { 363 val = 0; 364 } 365 if (val > 65535) 366 val = 65535; 367 rtc_set_memory(s, 0x17, val); 368 rtc_set_memory(s, 0x18, val >> 8); 369 rtc_set_memory(s, 0x30, val); 370 rtc_set_memory(s, 0x31, val >> 8); 371 /* memory between 16MiB and 4GiB */ 372 if (ram_size > 16 * 1024 * 1024) { 373 val = (ram_size - 16 * 1024 * 1024) / 65536; 374 } else { 375 val = 0; 376 } 377 if (val > 65535) 378 val = 65535; 379 rtc_set_memory(s, 0x34, val); 380 rtc_set_memory(s, 0x35, val >> 8); 381 /* memory above 4GiB */ 382 val = above_4g_mem_size / 65536; 383 rtc_set_memory(s, 0x5b, val); 384 rtc_set_memory(s, 0x5c, val >> 8); 385 rtc_set_memory(s, 0x5d, val >> 16); 386 387 /* set the number of CPU */ 388 rtc_set_memory(s, 0x5f, smp_cpus - 1); 389 390 object_property_add_link(OBJECT(machine), "rtc_state", 391 TYPE_ISA_DEVICE, 392 (Object **)&pc_machine->rtc, 393 object_property_allow_set_link, 394 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 395 object_property_set_link(OBJECT(machine), OBJECT(s), 396 "rtc_state", &error_abort); 397 398 set_boot_dev(s, boot_device, &local_err); 399 if (local_err) { 400 error_report_err(local_err); 401 exit(1); 402 } 403 404 /* floppy type */ 405 if (floppy) { 406 for (i = 0; i < 2; i++) { 407 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 408 } 409 } 410 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 411 cmos_get_fd_drive_type(fd_type[1]); 412 rtc_set_memory(s, 0x10, val); 413 414 val = 0; 415 nb = 0; 416 if (fd_type[0] < FDRIVE_DRV_NONE) { 417 nb++; 418 } 419 if (fd_type[1] < FDRIVE_DRV_NONE) { 420 nb++; 421 } 422 switch (nb) { 423 case 0: 424 break; 425 case 1: 426 val |= 0x01; /* 1 drive, ready for boot */ 427 break; 428 case 2: 429 val |= 0x41; /* 2 drives, ready for boot */ 430 break; 431 } 432 val |= 0x02; /* FPU is there */ 433 val |= 0x04; /* PS/2 mouse installed */ 434 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 435 436 /* hard drives */ 437 arg.rtc_state = s; 438 arg.idebus[0] = idebus0; 439 arg.idebus[1] = idebus1; 440 qemu_register_reset(pc_cmos_init_late, &arg); 441 } 442 443 #define TYPE_PORT92 "port92" 444 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 445 446 /* port 92 stuff: could be split off */ 447 typedef struct Port92State { 448 ISADevice parent_obj; 449 450 MemoryRegion io; 451 uint8_t outport; 452 qemu_irq *a20_out; 453 } Port92State; 454 455 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 456 unsigned size) 457 { 458 Port92State *s = opaque; 459 int oldval = s->outport; 460 461 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 462 s->outport = val; 463 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 464 if ((val & 1) && !(oldval & 1)) { 465 qemu_system_reset_request(); 466 } 467 } 468 469 static uint64_t port92_read(void *opaque, hwaddr addr, 470 unsigned size) 471 { 472 Port92State *s = opaque; 473 uint32_t ret; 474 475 ret = s->outport; 476 DPRINTF("port92: read 0x%02x\n", ret); 477 return ret; 478 } 479 480 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 481 { 482 Port92State *s = PORT92(dev); 483 484 s->a20_out = a20_out; 485 } 486 487 static const VMStateDescription vmstate_port92_isa = { 488 .name = "port92", 489 .version_id = 1, 490 .minimum_version_id = 1, 491 .fields = (VMStateField[]) { 492 VMSTATE_UINT8(outport, Port92State), 493 VMSTATE_END_OF_LIST() 494 } 495 }; 496 497 static void port92_reset(DeviceState *d) 498 { 499 Port92State *s = PORT92(d); 500 501 s->outport &= ~1; 502 } 503 504 static const MemoryRegionOps port92_ops = { 505 .read = port92_read, 506 .write = port92_write, 507 .impl = { 508 .min_access_size = 1, 509 .max_access_size = 1, 510 }, 511 .endianness = DEVICE_LITTLE_ENDIAN, 512 }; 513 514 static void port92_initfn(Object *obj) 515 { 516 Port92State *s = PORT92(obj); 517 518 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 519 520 s->outport = 0; 521 } 522 523 static void port92_realizefn(DeviceState *dev, Error **errp) 524 { 525 ISADevice *isadev = ISA_DEVICE(dev); 526 Port92State *s = PORT92(dev); 527 528 isa_register_ioport(isadev, &s->io, 0x92); 529 } 530 531 static void port92_class_initfn(ObjectClass *klass, void *data) 532 { 533 DeviceClass *dc = DEVICE_CLASS(klass); 534 535 dc->realize = port92_realizefn; 536 dc->reset = port92_reset; 537 dc->vmsd = &vmstate_port92_isa; 538 /* 539 * Reason: unlike ordinary ISA devices, this one needs additional 540 * wiring: its A20 output line needs to be wired up by 541 * port92_init(). 542 */ 543 dc->cannot_instantiate_with_device_add_yet = true; 544 } 545 546 static const TypeInfo port92_info = { 547 .name = TYPE_PORT92, 548 .parent = TYPE_ISA_DEVICE, 549 .instance_size = sizeof(Port92State), 550 .instance_init = port92_initfn, 551 .class_init = port92_class_initfn, 552 }; 553 554 static void port92_register_types(void) 555 { 556 type_register_static(&port92_info); 557 } 558 559 type_init(port92_register_types) 560 561 static void handle_a20_line_change(void *opaque, int irq, int level) 562 { 563 X86CPU *cpu = opaque; 564 565 /* XXX: send to all CPUs ? */ 566 /* XXX: add logic to handle multiple A20 line sources */ 567 x86_cpu_set_a20(cpu, level); 568 } 569 570 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 571 { 572 int index = le32_to_cpu(e820_reserve.count); 573 struct e820_entry *entry; 574 575 if (type != E820_RAM) { 576 /* old FW_CFG_E820_TABLE entry -- reservations only */ 577 if (index >= E820_NR_ENTRIES) { 578 return -EBUSY; 579 } 580 entry = &e820_reserve.entry[index++]; 581 582 entry->address = cpu_to_le64(address); 583 entry->length = cpu_to_le64(length); 584 entry->type = cpu_to_le32(type); 585 586 e820_reserve.count = cpu_to_le32(index); 587 } 588 589 /* new "etc/e820" file -- include ram too */ 590 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 591 e820_table[e820_entries].address = cpu_to_le64(address); 592 e820_table[e820_entries].length = cpu_to_le64(length); 593 e820_table[e820_entries].type = cpu_to_le32(type); 594 e820_entries++; 595 596 return e820_entries; 597 } 598 599 int e820_get_num_entries(void) 600 { 601 return e820_entries; 602 } 603 604 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 605 { 606 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 607 *address = le64_to_cpu(e820_table[idx].address); 608 *length = le64_to_cpu(e820_table[idx].length); 609 return true; 610 } 611 return false; 612 } 613 614 /* Enables contiguous-apic-ID mode, for compatibility */ 615 static bool compat_apic_id_mode; 616 617 void enable_compat_apic_id_mode(void) 618 { 619 compat_apic_id_mode = true; 620 } 621 622 /* Calculates initial APIC ID for a specific CPU index 623 * 624 * Currently we need to be able to calculate the APIC ID from the CPU index 625 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 626 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 627 * all CPUs up to max_cpus. 628 */ 629 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 630 { 631 uint32_t correct_id; 632 static bool warned; 633 634 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 635 if (compat_apic_id_mode) { 636 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 637 error_report("APIC IDs set in compatibility mode, " 638 "CPU topology won't match the configuration"); 639 warned = true; 640 } 641 return cpu_index; 642 } else { 643 return correct_id; 644 } 645 } 646 647 /* Calculates the limit to CPU APIC ID values 648 * 649 * This function returns the limit for the APIC ID value, so that all 650 * CPU APIC IDs are < pc_apic_id_limit(). 651 * 652 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 653 */ 654 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 655 { 656 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 657 } 658 659 static FWCfgState *bochs_bios_init(void) 660 { 661 FWCfgState *fw_cfg; 662 uint8_t *smbios_tables, *smbios_anchor; 663 size_t smbios_tables_len, smbios_anchor_len; 664 uint64_t *numa_fw_cfg; 665 int i, j; 666 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 667 668 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 669 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 670 * 671 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 672 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 673 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 674 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 675 * may see". 676 * 677 * So, this means we must not use max_cpus, here, but the maximum possible 678 * APIC ID value, plus one. 679 * 680 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 681 * the APIC ID, not the "CPU index" 682 */ 683 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 684 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 685 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 686 acpi_tables, acpi_tables_len); 687 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 688 689 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 690 if (smbios_tables) { 691 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 692 smbios_tables, smbios_tables_len); 693 } 694 695 smbios_get_tables(&smbios_tables, &smbios_tables_len, 696 &smbios_anchor, &smbios_anchor_len); 697 if (smbios_anchor) { 698 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 699 smbios_tables, smbios_tables_len); 700 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 701 smbios_anchor, smbios_anchor_len); 702 } 703 704 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 705 &e820_reserve, sizeof(e820_reserve)); 706 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 707 sizeof(struct e820_entry) * e820_entries); 708 709 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 710 /* allocate memory for the NUMA channel: one (64bit) word for the number 711 * of nodes, one word for each VCPU->node and one word for each node to 712 * hold the amount of memory. 713 */ 714 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 715 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 716 for (i = 0; i < max_cpus; i++) { 717 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 718 assert(apic_id < apic_id_limit); 719 for (j = 0; j < nb_numa_nodes; j++) { 720 if (test_bit(i, numa_info[j].node_cpu)) { 721 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 722 break; 723 } 724 } 725 } 726 for (i = 0; i < nb_numa_nodes; i++) { 727 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 728 } 729 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 730 (1 + apic_id_limit + nb_numa_nodes) * 731 sizeof(*numa_fw_cfg)); 732 733 return fw_cfg; 734 } 735 736 static long get_file_size(FILE *f) 737 { 738 long where, size; 739 740 /* XXX: on Unix systems, using fstat() probably makes more sense */ 741 742 where = ftell(f); 743 fseek(f, 0, SEEK_END); 744 size = ftell(f); 745 fseek(f, where, SEEK_SET); 746 747 return size; 748 } 749 750 static void load_linux(FWCfgState *fw_cfg, 751 const char *kernel_filename, 752 const char *initrd_filename, 753 const char *kernel_cmdline, 754 hwaddr max_ram_size) 755 { 756 uint16_t protocol; 757 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 758 uint32_t initrd_max; 759 uint8_t header[8192], *setup, *kernel, *initrd_data; 760 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 761 FILE *f; 762 char *vmode; 763 764 /* Align to 16 bytes as a paranoia measure */ 765 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 766 767 /* load the kernel header */ 768 f = fopen(kernel_filename, "rb"); 769 if (!f || !(kernel_size = get_file_size(f)) || 770 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 771 MIN(ARRAY_SIZE(header), kernel_size)) { 772 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 773 kernel_filename, strerror(errno)); 774 exit(1); 775 } 776 777 /* kernel protocol version */ 778 #if 0 779 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 780 #endif 781 if (ldl_p(header+0x202) == 0x53726448) { 782 protocol = lduw_p(header+0x206); 783 } else { 784 /* This looks like a multiboot kernel. If it is, let's stop 785 treating it like a Linux kernel. */ 786 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 787 kernel_cmdline, kernel_size, header)) { 788 return; 789 } 790 protocol = 0; 791 } 792 793 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 794 /* Low kernel */ 795 real_addr = 0x90000; 796 cmdline_addr = 0x9a000 - cmdline_size; 797 prot_addr = 0x10000; 798 } else if (protocol < 0x202) { 799 /* High but ancient kernel */ 800 real_addr = 0x90000; 801 cmdline_addr = 0x9a000 - cmdline_size; 802 prot_addr = 0x100000; 803 } else { 804 /* High and recent kernel */ 805 real_addr = 0x10000; 806 cmdline_addr = 0x20000; 807 prot_addr = 0x100000; 808 } 809 810 #if 0 811 fprintf(stderr, 812 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 813 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 814 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 815 real_addr, 816 cmdline_addr, 817 prot_addr); 818 #endif 819 820 /* highest address for loading the initrd */ 821 if (protocol >= 0x203) { 822 initrd_max = ldl_p(header+0x22c); 823 } else { 824 initrd_max = 0x37ffffff; 825 } 826 827 if (initrd_max >= max_ram_size - acpi_data_size) { 828 initrd_max = max_ram_size - acpi_data_size - 1; 829 } 830 831 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 832 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 833 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 834 835 if (protocol >= 0x202) { 836 stl_p(header+0x228, cmdline_addr); 837 } else { 838 stw_p(header+0x20, 0xA33F); 839 stw_p(header+0x22, cmdline_addr-real_addr); 840 } 841 842 /* handle vga= parameter */ 843 vmode = strstr(kernel_cmdline, "vga="); 844 if (vmode) { 845 unsigned int video_mode; 846 /* skip "vga=" */ 847 vmode += 4; 848 if (!strncmp(vmode, "normal", 6)) { 849 video_mode = 0xffff; 850 } else if (!strncmp(vmode, "ext", 3)) { 851 video_mode = 0xfffe; 852 } else if (!strncmp(vmode, "ask", 3)) { 853 video_mode = 0xfffd; 854 } else { 855 video_mode = strtol(vmode, NULL, 0); 856 } 857 stw_p(header+0x1fa, video_mode); 858 } 859 860 /* loader type */ 861 /* High nybble = B reserved for QEMU; low nybble is revision number. 862 If this code is substantially changed, you may want to consider 863 incrementing the revision. */ 864 if (protocol >= 0x200) { 865 header[0x210] = 0xB0; 866 } 867 /* heap */ 868 if (protocol >= 0x201) { 869 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 870 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 871 } 872 873 /* load initrd */ 874 if (initrd_filename) { 875 if (protocol < 0x200) { 876 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 877 exit(1); 878 } 879 880 initrd_size = get_image_size(initrd_filename); 881 if (initrd_size < 0) { 882 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 883 initrd_filename, strerror(errno)); 884 exit(1); 885 } 886 887 initrd_addr = (initrd_max-initrd_size) & ~4095; 888 889 initrd_data = g_malloc(initrd_size); 890 load_image(initrd_filename, initrd_data); 891 892 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 893 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 894 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 895 896 stl_p(header+0x218, initrd_addr); 897 stl_p(header+0x21c, initrd_size); 898 } 899 900 /* load kernel and setup */ 901 setup_size = header[0x1f1]; 902 if (setup_size == 0) { 903 setup_size = 4; 904 } 905 setup_size = (setup_size+1)*512; 906 kernel_size -= setup_size; 907 908 setup = g_malloc(setup_size); 909 kernel = g_malloc(kernel_size); 910 fseek(f, 0, SEEK_SET); 911 if (fread(setup, 1, setup_size, f) != setup_size) { 912 fprintf(stderr, "fread() failed\n"); 913 exit(1); 914 } 915 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 916 fprintf(stderr, "fread() failed\n"); 917 exit(1); 918 } 919 fclose(f); 920 memcpy(setup, header, MIN(sizeof(header), setup_size)); 921 922 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 923 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 924 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 925 926 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 927 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 928 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 929 930 option_rom[nb_option_roms].name = "linuxboot.bin"; 931 option_rom[nb_option_roms].bootindex = 0; 932 nb_option_roms++; 933 } 934 935 #define NE2000_NB_MAX 6 936 937 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 938 0x280, 0x380 }; 939 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 940 941 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 942 { 943 static int nb_ne2k = 0; 944 945 if (nb_ne2k == NE2000_NB_MAX) 946 return; 947 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 948 ne2000_irq[nb_ne2k], nd); 949 nb_ne2k++; 950 } 951 952 DeviceState *cpu_get_current_apic(void) 953 { 954 if (current_cpu) { 955 X86CPU *cpu = X86_CPU(current_cpu); 956 return cpu->apic_state; 957 } else { 958 return NULL; 959 } 960 } 961 962 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 963 { 964 X86CPU *cpu = opaque; 965 966 if (level) { 967 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 968 } 969 } 970 971 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 972 DeviceState *icc_bridge, Error **errp) 973 { 974 X86CPU *cpu = NULL; 975 Error *local_err = NULL; 976 977 if (icc_bridge == NULL) { 978 error_setg(&local_err, "Invalid icc-bridge value"); 979 goto out; 980 } 981 982 cpu = cpu_x86_create(cpu_model, &local_err); 983 if (local_err != NULL) { 984 goto out; 985 } 986 987 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); 988 989 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 990 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 991 992 out: 993 if (local_err) { 994 error_propagate(errp, local_err); 995 object_unref(OBJECT(cpu)); 996 cpu = NULL; 997 } 998 return cpu; 999 } 1000 1001 static const char *current_cpu_model; 1002 1003 void pc_hot_add_cpu(const int64_t id, Error **errp) 1004 { 1005 DeviceState *icc_bridge; 1006 X86CPU *cpu; 1007 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1008 Error *local_err = NULL; 1009 1010 if (id < 0) { 1011 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1012 return; 1013 } 1014 1015 if (cpu_exists(apic_id)) { 1016 error_setg(errp, "Unable to add CPU: %" PRIi64 1017 ", it already exists", id); 1018 return; 1019 } 1020 1021 if (id >= max_cpus) { 1022 error_setg(errp, "Unable to add CPU: %" PRIi64 1023 ", max allowed: %d", id, max_cpus - 1); 1024 return; 1025 } 1026 1027 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1028 error_setg(errp, "Unable to add CPU: %" PRIi64 1029 ", resulting APIC ID (%" PRIi64 ") is too large", 1030 id, apic_id); 1031 return; 1032 } 1033 1034 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1035 TYPE_ICC_BRIDGE, NULL)); 1036 cpu = pc_new_cpu(current_cpu_model, apic_id, icc_bridge, &local_err); 1037 if (local_err) { 1038 error_propagate(errp, local_err); 1039 return; 1040 } 1041 object_unref(OBJECT(cpu)); 1042 } 1043 1044 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1045 { 1046 int i; 1047 X86CPU *cpu = NULL; 1048 Error *error = NULL; 1049 unsigned long apic_id_limit; 1050 1051 /* init CPUs */ 1052 if (cpu_model == NULL) { 1053 #ifdef TARGET_X86_64 1054 cpu_model = "qemu64"; 1055 #else 1056 cpu_model = "qemu32"; 1057 #endif 1058 } 1059 current_cpu_model = cpu_model; 1060 1061 apic_id_limit = pc_apic_id_limit(max_cpus); 1062 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1063 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1064 apic_id_limit - 1); 1065 exit(1); 1066 } 1067 1068 for (i = 0; i < smp_cpus; i++) { 1069 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1070 icc_bridge, &error); 1071 if (error) { 1072 error_report_err(error); 1073 exit(1); 1074 } 1075 object_unref(OBJECT(cpu)); 1076 } 1077 1078 /* map APIC MMIO area if CPU has APIC */ 1079 if (cpu && cpu->apic_state) { 1080 /* XXX: what if the base changes? */ 1081 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1082 APIC_DEFAULT_ADDRESS, 0x1000); 1083 } 1084 1085 /* tell smbios about cpuid version and features */ 1086 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1087 } 1088 1089 /* pci-info ROM file. Little endian format */ 1090 typedef struct PcRomPciInfo { 1091 uint64_t w32_min; 1092 uint64_t w32_max; 1093 uint64_t w64_min; 1094 uint64_t w64_max; 1095 } PcRomPciInfo; 1096 1097 typedef struct PcGuestInfoState { 1098 PcGuestInfo info; 1099 Notifier machine_done; 1100 } PcGuestInfoState; 1101 1102 static 1103 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1104 { 1105 PcGuestInfoState *guest_info_state = container_of(notifier, 1106 PcGuestInfoState, 1107 machine_done); 1108 PCIBus *bus = find_i440fx(); 1109 1110 if (bus) { 1111 int extra_hosts = 0; 1112 1113 QLIST_FOREACH(bus, &bus->child, sibling) { 1114 /* look for expander root buses */ 1115 if (pci_bus_is_root(bus)) { 1116 extra_hosts++; 1117 } 1118 } 1119 if (extra_hosts && guest_info_state->info.fw_cfg) { 1120 uint64_t *val = g_malloc(sizeof(*val)); 1121 *val = cpu_to_le64(extra_hosts); 1122 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1123 "etc/extra-pci-roots", val, sizeof(*val)); 1124 } 1125 } 1126 1127 acpi_setup(&guest_info_state->info); 1128 } 1129 1130 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1131 ram_addr_t above_4g_mem_size) 1132 { 1133 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1134 PcGuestInfo *guest_info = &guest_info_state->info; 1135 int i, j; 1136 1137 guest_info->ram_size_below_4g = below_4g_mem_size; 1138 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1139 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1140 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1141 guest_info->numa_nodes = nb_numa_nodes; 1142 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1143 sizeof *guest_info->node_mem); 1144 for (i = 0; i < nb_numa_nodes; i++) { 1145 guest_info->node_mem[i] = numa_info[i].node_mem; 1146 } 1147 1148 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1149 sizeof *guest_info->node_cpu); 1150 1151 for (i = 0; i < max_cpus; i++) { 1152 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1153 assert(apic_id < guest_info->apic_id_limit); 1154 for (j = 0; j < nb_numa_nodes; j++) { 1155 if (test_bit(i, numa_info[j].node_cpu)) { 1156 guest_info->node_cpu[apic_id] = j; 1157 break; 1158 } 1159 } 1160 } 1161 1162 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1163 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1164 return guest_info; 1165 } 1166 1167 /* setup pci memory address space mapping into system address space */ 1168 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1169 MemoryRegion *pci_address_space) 1170 { 1171 /* Set to lower priority than RAM */ 1172 memory_region_add_subregion_overlap(system_memory, 0x0, 1173 pci_address_space, -1); 1174 } 1175 1176 void pc_acpi_init(const char *default_dsdt) 1177 { 1178 char *filename; 1179 1180 if (acpi_tables != NULL) { 1181 /* manually set via -acpitable, leave it alone */ 1182 return; 1183 } 1184 1185 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1186 if (filename == NULL) { 1187 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1188 } else { 1189 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1190 &error_abort); 1191 Error *err = NULL; 1192 1193 qemu_opt_set(opts, "file", filename, &error_abort); 1194 1195 acpi_table_add_builtin(opts, &err); 1196 if (err) { 1197 error_report("WARNING: failed to load %s: %s", filename, 1198 error_get_pretty(err)); 1199 error_free(err); 1200 } 1201 g_free(filename); 1202 } 1203 } 1204 1205 FWCfgState *xen_load_linux(const char *kernel_filename, 1206 const char *kernel_cmdline, 1207 const char *initrd_filename, 1208 ram_addr_t below_4g_mem_size, 1209 PcGuestInfo *guest_info) 1210 { 1211 int i; 1212 FWCfgState *fw_cfg; 1213 1214 assert(kernel_filename != NULL); 1215 1216 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1217 rom_set_fw(fw_cfg); 1218 1219 load_linux(fw_cfg, kernel_filename, initrd_filename, 1220 kernel_cmdline, below_4g_mem_size); 1221 for (i = 0; i < nb_option_roms; i++) { 1222 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1223 !strcmp(option_rom[i].name, "multiboot.bin")); 1224 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1225 } 1226 guest_info->fw_cfg = fw_cfg; 1227 return fw_cfg; 1228 } 1229 1230 FWCfgState *pc_memory_init(MachineState *machine, 1231 MemoryRegion *system_memory, 1232 ram_addr_t below_4g_mem_size, 1233 ram_addr_t above_4g_mem_size, 1234 MemoryRegion *rom_memory, 1235 MemoryRegion **ram_memory, 1236 PcGuestInfo *guest_info) 1237 { 1238 int linux_boot, i; 1239 MemoryRegion *ram, *option_rom_mr; 1240 MemoryRegion *ram_below_4g, *ram_above_4g; 1241 FWCfgState *fw_cfg; 1242 PCMachineState *pcms = PC_MACHINE(machine); 1243 1244 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1245 1246 linux_boot = (machine->kernel_filename != NULL); 1247 1248 /* Allocate RAM. We allocate it as a single memory region and use 1249 * aliases to address portions of it, mostly for backwards compatibility 1250 * with older qemus that used qemu_ram_alloc(). 1251 */ 1252 ram = g_malloc(sizeof(*ram)); 1253 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1254 machine->ram_size); 1255 *ram_memory = ram; 1256 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1257 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1258 0, below_4g_mem_size); 1259 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1260 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1261 if (above_4g_mem_size > 0) { 1262 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1263 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1264 below_4g_mem_size, above_4g_mem_size); 1265 memory_region_add_subregion(system_memory, 0x100000000ULL, 1266 ram_above_4g); 1267 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1268 } 1269 1270 if (!guest_info->has_reserved_memory && 1271 (machine->ram_slots || 1272 (machine->maxram_size > machine->ram_size))) { 1273 MachineClass *mc = MACHINE_GET_CLASS(machine); 1274 1275 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1276 mc->name); 1277 exit(EXIT_FAILURE); 1278 } 1279 1280 /* initialize hotplug memory address space */ 1281 if (guest_info->has_reserved_memory && 1282 (machine->ram_size < machine->maxram_size)) { 1283 ram_addr_t hotplug_mem_size = 1284 machine->maxram_size - machine->ram_size; 1285 1286 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1287 error_report("unsupported amount of memory slots: %"PRIu64, 1288 machine->ram_slots); 1289 exit(EXIT_FAILURE); 1290 } 1291 1292 if (QEMU_ALIGN_UP(machine->maxram_size, 1293 TARGET_PAGE_SIZE) != machine->maxram_size) { 1294 error_report("maximum memory size must by aligned to multiple of " 1295 "%d bytes", TARGET_PAGE_SIZE); 1296 exit(EXIT_FAILURE); 1297 } 1298 1299 pcms->hotplug_memory.base = 1300 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1301 1302 if (pcms->enforce_aligned_dimm) { 1303 /* size hotplug region assuming 1G page max alignment per slot */ 1304 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1305 } 1306 1307 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1308 hotplug_mem_size) { 1309 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1310 machine->maxram_size); 1311 exit(EXIT_FAILURE); 1312 } 1313 1314 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1315 "hotplug-memory", hotplug_mem_size); 1316 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1317 &pcms->hotplug_memory.mr); 1318 } 1319 1320 /* Initialize PC system firmware */ 1321 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1322 1323 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1324 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1325 &error_abort); 1326 vmstate_register_ram_global(option_rom_mr); 1327 memory_region_add_subregion_overlap(rom_memory, 1328 PC_ROM_MIN_VGA, 1329 option_rom_mr, 1330 1); 1331 1332 fw_cfg = bochs_bios_init(); 1333 rom_set_fw(fw_cfg); 1334 1335 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1336 uint64_t *val = g_malloc(sizeof(*val)); 1337 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory.base, 0x1ULL << 30)); 1338 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1339 } 1340 1341 if (linux_boot) { 1342 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1343 machine->kernel_cmdline, below_4g_mem_size); 1344 } 1345 1346 for (i = 0; i < nb_option_roms; i++) { 1347 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1348 } 1349 guest_info->fw_cfg = fw_cfg; 1350 return fw_cfg; 1351 } 1352 1353 qemu_irq pc_allocate_cpu_irq(void) 1354 { 1355 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1356 } 1357 1358 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1359 { 1360 DeviceState *dev = NULL; 1361 1362 if (pci_bus) { 1363 PCIDevice *pcidev = pci_vga_init(pci_bus); 1364 dev = pcidev ? &pcidev->qdev : NULL; 1365 } else if (isa_bus) { 1366 ISADevice *isadev = isa_vga_init(isa_bus); 1367 dev = isadev ? DEVICE(isadev) : NULL; 1368 } 1369 return dev; 1370 } 1371 1372 static void cpu_request_exit(void *opaque, int irq, int level) 1373 { 1374 CPUState *cpu = current_cpu; 1375 1376 if (cpu && level) { 1377 cpu_exit(cpu); 1378 } 1379 } 1380 1381 static const MemoryRegionOps ioport80_io_ops = { 1382 .write = ioport80_write, 1383 .read = ioport80_read, 1384 .endianness = DEVICE_NATIVE_ENDIAN, 1385 .impl = { 1386 .min_access_size = 1, 1387 .max_access_size = 1, 1388 }, 1389 }; 1390 1391 static const MemoryRegionOps ioportF0_io_ops = { 1392 .write = ioportF0_write, 1393 .read = ioportF0_read, 1394 .endianness = DEVICE_NATIVE_ENDIAN, 1395 .impl = { 1396 .min_access_size = 1, 1397 .max_access_size = 1, 1398 }, 1399 }; 1400 1401 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1402 ISADevice **rtc_state, 1403 bool create_fdctrl, 1404 ISADevice **floppy, 1405 bool no_vmport, 1406 uint32 hpet_irqs) 1407 { 1408 int i; 1409 DriveInfo *fd[MAX_FD]; 1410 DeviceState *hpet = NULL; 1411 int pit_isa_irq = 0; 1412 qemu_irq pit_alt_irq = NULL; 1413 qemu_irq rtc_irq = NULL; 1414 qemu_irq *a20_line; 1415 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1416 qemu_irq *cpu_exit_irq; 1417 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1418 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1419 1420 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1421 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1422 1423 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1424 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1425 1426 /* 1427 * Check if an HPET shall be created. 1428 * 1429 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1430 * when the HPET wants to take over. Thus we have to disable the latter. 1431 */ 1432 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1433 /* In order to set property, here not using sysbus_try_create_simple */ 1434 hpet = qdev_try_create(NULL, TYPE_HPET); 1435 if (hpet) { 1436 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1437 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1438 * IRQ8 and IRQ2. 1439 */ 1440 uint8_t compat = object_property_get_int(OBJECT(hpet), 1441 HPET_INTCAP, NULL); 1442 if (!compat) { 1443 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1444 } 1445 qdev_init_nofail(hpet); 1446 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1447 1448 for (i = 0; i < GSI_NUM_PINS; i++) { 1449 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1450 } 1451 pit_isa_irq = -1; 1452 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1453 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1454 } 1455 } 1456 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1457 1458 qemu_register_boot_set(pc_boot_set, *rtc_state); 1459 1460 if (!xen_enabled()) { 1461 if (kvm_irqchip_in_kernel()) { 1462 pit = kvm_pit_init(isa_bus, 0x40); 1463 } else { 1464 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1465 } 1466 if (hpet) { 1467 /* connect PIT to output control line of the HPET */ 1468 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1469 } 1470 pcspk_init(isa_bus, pit); 1471 } 1472 1473 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1474 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1475 1476 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1477 i8042 = isa_create_simple(isa_bus, "i8042"); 1478 i8042_setup_a20_line(i8042, &a20_line[0]); 1479 if (!no_vmport) { 1480 vmport_init(isa_bus); 1481 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1482 } else { 1483 vmmouse = NULL; 1484 } 1485 if (vmmouse) { 1486 DeviceState *dev = DEVICE(vmmouse); 1487 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1488 qdev_init_nofail(dev); 1489 } 1490 port92 = isa_create_simple(isa_bus, "port92"); 1491 port92_init(port92, &a20_line[1]); 1492 1493 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1494 DMA_init(0, cpu_exit_irq); 1495 1496 for(i = 0; i < MAX_FD; i++) { 1497 fd[i] = drive_get(IF_FLOPPY, 0, i); 1498 create_fdctrl |= !!fd[i]; 1499 } 1500 *floppy = create_fdctrl ? fdctrl_init_isa(isa_bus, fd) : NULL; 1501 } 1502 1503 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1504 { 1505 int i; 1506 1507 for (i = 0; i < nb_nics; i++) { 1508 NICInfo *nd = &nd_table[i]; 1509 1510 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1511 pc_init_ne2k_isa(isa_bus, nd); 1512 } else { 1513 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1514 } 1515 } 1516 } 1517 1518 void pc_pci_device_init(PCIBus *pci_bus) 1519 { 1520 int max_bus; 1521 int bus; 1522 1523 max_bus = drive_get_max_bus(IF_SCSI); 1524 for (bus = 0; bus <= max_bus; bus++) { 1525 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1526 } 1527 } 1528 1529 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1530 { 1531 DeviceState *dev; 1532 SysBusDevice *d; 1533 unsigned int i; 1534 1535 if (kvm_irqchip_in_kernel()) { 1536 dev = qdev_create(NULL, "kvm-ioapic"); 1537 } else { 1538 dev = qdev_create(NULL, "ioapic"); 1539 } 1540 if (parent_name) { 1541 object_property_add_child(object_resolve_path(parent_name, NULL), 1542 "ioapic", OBJECT(dev), NULL); 1543 } 1544 qdev_init_nofail(dev); 1545 d = SYS_BUS_DEVICE(dev); 1546 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1547 1548 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1549 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1550 } 1551 } 1552 1553 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1554 DeviceState *dev, Error **errp) 1555 { 1556 HotplugHandlerClass *hhc; 1557 Error *local_err = NULL; 1558 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1559 PCDIMMDevice *dimm = PC_DIMM(dev); 1560 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1561 MemoryRegion *mr = ddc->get_memory_region(dimm); 1562 uint64_t align = TARGET_PAGE_SIZE; 1563 1564 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1565 align = memory_region_get_alignment(mr); 1566 } 1567 1568 if (!pcms->acpi_dev) { 1569 error_setg(&local_err, 1570 "memory hotplug is not enabled: missing acpi device"); 1571 goto out; 1572 } 1573 1574 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1575 if (local_err) { 1576 goto out; 1577 } 1578 1579 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1580 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1581 out: 1582 error_propagate(errp, local_err); 1583 } 1584 1585 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1586 DeviceState *dev, Error **errp) 1587 { 1588 HotplugHandlerClass *hhc; 1589 Error *local_err = NULL; 1590 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1591 1592 if (!pcms->acpi_dev) { 1593 error_setg(&local_err, 1594 "memory hotplug is not enabled: missing acpi device"); 1595 goto out; 1596 } 1597 1598 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1599 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1600 1601 out: 1602 error_propagate(errp, local_err); 1603 } 1604 1605 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1606 DeviceState *dev, Error **errp) 1607 { 1608 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1609 PCDIMMDevice *dimm = PC_DIMM(dev); 1610 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1611 MemoryRegion *mr = ddc->get_memory_region(dimm); 1612 HotplugHandlerClass *hhc; 1613 Error *local_err = NULL; 1614 1615 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1616 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1617 1618 if (local_err) { 1619 goto out; 1620 } 1621 1622 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1623 object_unparent(OBJECT(dev)); 1624 1625 out: 1626 error_propagate(errp, local_err); 1627 } 1628 1629 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1630 DeviceState *dev, Error **errp) 1631 { 1632 HotplugHandlerClass *hhc; 1633 Error *local_err = NULL; 1634 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1635 1636 if (!dev->hotplugged) { 1637 goto out; 1638 } 1639 1640 if (!pcms->acpi_dev) { 1641 error_setg(&local_err, 1642 "cpu hotplug is not enabled: missing acpi device"); 1643 goto out; 1644 } 1645 1646 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1647 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1648 if (local_err) { 1649 goto out; 1650 } 1651 1652 /* increment the number of CPUs */ 1653 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1654 out: 1655 error_propagate(errp, local_err); 1656 } 1657 1658 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1659 DeviceState *dev, Error **errp) 1660 { 1661 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1662 pc_dimm_plug(hotplug_dev, dev, errp); 1663 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1664 pc_cpu_plug(hotplug_dev, dev, errp); 1665 } 1666 } 1667 1668 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1669 DeviceState *dev, Error **errp) 1670 { 1671 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1672 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1673 } else { 1674 error_setg(errp, "acpi: device unplug request for not supported device" 1675 " type: %s", object_get_typename(OBJECT(dev))); 1676 } 1677 } 1678 1679 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1680 DeviceState *dev, Error **errp) 1681 { 1682 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1683 pc_dimm_unplug(hotplug_dev, dev, errp); 1684 } else { 1685 error_setg(errp, "acpi: device unplug for not supported device" 1686 " type: %s", object_get_typename(OBJECT(dev))); 1687 } 1688 } 1689 1690 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1691 DeviceState *dev) 1692 { 1693 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1694 1695 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1696 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1697 return HOTPLUG_HANDLER(machine); 1698 } 1699 1700 return pcmc->get_hotplug_handler ? 1701 pcmc->get_hotplug_handler(machine, dev) : NULL; 1702 } 1703 1704 static void 1705 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1706 const char *name, Error **errp) 1707 { 1708 PCMachineState *pcms = PC_MACHINE(obj); 1709 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1710 1711 visit_type_int(v, &value, name, errp); 1712 } 1713 1714 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1715 void *opaque, const char *name, 1716 Error **errp) 1717 { 1718 PCMachineState *pcms = PC_MACHINE(obj); 1719 uint64_t value = pcms->max_ram_below_4g; 1720 1721 visit_type_size(v, &value, name, errp); 1722 } 1723 1724 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1725 void *opaque, const char *name, 1726 Error **errp) 1727 { 1728 PCMachineState *pcms = PC_MACHINE(obj); 1729 Error *error = NULL; 1730 uint64_t value; 1731 1732 visit_type_size(v, &value, name, &error); 1733 if (error) { 1734 error_propagate(errp, error); 1735 return; 1736 } 1737 if (value > (1ULL << 32)) { 1738 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1739 "Machine option 'max-ram-below-4g=%"PRIu64 1740 "' expects size less than or equal to 4G", value); 1741 error_propagate(errp, error); 1742 return; 1743 } 1744 1745 if (value < (1ULL << 20)) { 1746 error_report("Warning: small max_ram_below_4g(%"PRIu64 1747 ") less than 1M. BIOS may not work..", 1748 value); 1749 } 1750 1751 pcms->max_ram_below_4g = value; 1752 } 1753 1754 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1755 const char *name, Error **errp) 1756 { 1757 PCMachineState *pcms = PC_MACHINE(obj); 1758 OnOffAuto vmport = pcms->vmport; 1759 1760 visit_type_OnOffAuto(v, &vmport, name, errp); 1761 } 1762 1763 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1764 const char *name, Error **errp) 1765 { 1766 PCMachineState *pcms = PC_MACHINE(obj); 1767 1768 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1769 } 1770 1771 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1772 { 1773 PCMachineState *pcms = PC_MACHINE(obj); 1774 1775 return pcms->enforce_aligned_dimm; 1776 } 1777 1778 static void pc_machine_initfn(Object *obj) 1779 { 1780 PCMachineState *pcms = PC_MACHINE(obj); 1781 1782 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1783 pc_machine_get_hotplug_memory_region_size, 1784 NULL, NULL, NULL, NULL); 1785 1786 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1787 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1788 pc_machine_get_max_ram_below_4g, 1789 pc_machine_set_max_ram_below_4g, 1790 NULL, NULL, NULL); 1791 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1792 "Maximum ram below the 4G boundary (32bit boundary)", 1793 NULL); 1794 1795 pcms->vmport = ON_OFF_AUTO_AUTO; 1796 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1797 pc_machine_get_vmport, 1798 pc_machine_set_vmport, 1799 NULL, NULL, NULL); 1800 object_property_set_description(obj, PC_MACHINE_VMPORT, 1801 "Enable vmport (pc & q35)", 1802 NULL); 1803 1804 pcms->enforce_aligned_dimm = true; 1805 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1806 pc_machine_get_aligned_dimm, 1807 NULL, NULL); 1808 } 1809 1810 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1811 { 1812 unsigned pkg_id, core_id, smt_id; 1813 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1814 &pkg_id, &core_id, &smt_id); 1815 return pkg_id; 1816 } 1817 1818 static void pc_machine_class_init(ObjectClass *oc, void *data) 1819 { 1820 MachineClass *mc = MACHINE_CLASS(oc); 1821 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1822 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1823 1824 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1825 mc->get_hotplug_handler = pc_get_hotpug_handler; 1826 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1827 hc->plug = pc_machine_device_plug_cb; 1828 hc->unplug_request = pc_machine_device_unplug_request_cb; 1829 hc->unplug = pc_machine_device_unplug_cb; 1830 } 1831 1832 static const TypeInfo pc_machine_info = { 1833 .name = TYPE_PC_MACHINE, 1834 .parent = TYPE_MACHINE, 1835 .abstract = true, 1836 .instance_size = sizeof(PCMachineState), 1837 .instance_init = pc_machine_initfn, 1838 .class_size = sizeof(PCMachineClass), 1839 .class_init = pc_machine_class_init, 1840 .interfaces = (InterfaceInfo[]) { 1841 { TYPE_HOTPLUG_HANDLER }, 1842 { } 1843 }, 1844 }; 1845 1846 static void pc_machine_register_types(void) 1847 { 1848 type_register_static(&pc_machine_info); 1849 } 1850 1851 type_init(pc_machine_register_types) 1852