1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_9_0[] = { 82 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 83 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 84 { "sev-guest", "legacy-vm-type", "true" }, 85 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 86 }; 87 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 88 89 GlobalProperty pc_compat_8_2[] = {}; 90 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 91 92 GlobalProperty pc_compat_8_1[] = {}; 93 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 94 95 GlobalProperty pc_compat_8_0[] = { 96 { "virtio-mem", "unplugged-inaccessible", "auto" }, 97 }; 98 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 99 100 GlobalProperty pc_compat_7_2[] = { 101 { "ICH9-LPC", "noreboot", "true" }, 102 }; 103 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 104 105 GlobalProperty pc_compat_7_1[] = {}; 106 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 107 108 GlobalProperty pc_compat_7_0[] = {}; 109 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 110 111 GlobalProperty pc_compat_6_2[] = { 112 { "virtio-mem", "unplugged-inaccessible", "off" }, 113 }; 114 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 115 116 GlobalProperty pc_compat_6_1[] = { 117 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 118 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 119 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 120 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 121 }; 122 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 123 124 GlobalProperty pc_compat_6_0[] = { 125 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 126 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 127 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 128 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 129 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 130 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 131 }; 132 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 133 134 GlobalProperty pc_compat_5_2[] = { 135 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 136 }; 137 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 138 139 GlobalProperty pc_compat_5_1[] = { 140 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 141 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 142 }; 143 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 144 145 GlobalProperty pc_compat_5_0[] = { 146 }; 147 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 148 149 GlobalProperty pc_compat_4_2[] = { 150 { "mch", "smbase-smram", "off" }, 151 }; 152 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 153 154 GlobalProperty pc_compat_4_1[] = {}; 155 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 156 157 GlobalProperty pc_compat_4_0[] = {}; 158 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 159 160 GlobalProperty pc_compat_3_1[] = { 161 { "intel-iommu", "dma-drain", "off" }, 162 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 163 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 164 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 165 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 166 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 167 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 168 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 169 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 170 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 171 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 172 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 173 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 174 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 175 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 176 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 177 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 178 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 179 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 180 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 181 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 182 }; 183 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 184 185 GlobalProperty pc_compat_3_0[] = { 186 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 187 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 188 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 189 }; 190 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 191 192 GlobalProperty pc_compat_2_12[] = { 193 { TYPE_X86_CPU, "legacy-cache", "on" }, 194 { TYPE_X86_CPU, "topoext", "off" }, 195 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 196 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 197 }; 198 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 199 200 GlobalProperty pc_compat_2_11[] = { 201 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 202 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 203 }; 204 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 205 206 GlobalProperty pc_compat_2_10[] = { 207 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 208 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 209 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 210 }; 211 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 212 213 GlobalProperty pc_compat_2_9[] = { 214 { "mch", "extended-tseg-mbytes", "0" }, 215 }; 216 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 217 218 GlobalProperty pc_compat_2_8[] = { 219 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 220 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 221 { "ICH9-LPC", "x-smi-broadcast", "off" }, 222 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 223 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 224 }; 225 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 226 227 GlobalProperty pc_compat_2_7[] = { 228 { TYPE_X86_CPU, "l3-cache", "off" }, 229 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 230 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 231 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 232 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 233 { "isa-pcspk", "migrate", "off" }, 234 }; 235 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 236 237 GlobalProperty pc_compat_2_6[] = { 238 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 239 { "vmxnet3", "romfile", "" }, 240 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 241 { "apic-common", "legacy-instance-id", "on", } 242 }; 243 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 244 245 GlobalProperty pc_compat_2_5[] = {}; 246 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 247 248 GlobalProperty pc_compat_2_4[] = { 249 PC_CPU_MODEL_IDS("2.4.0") 250 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 251 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 252 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 253 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 254 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 255 { TYPE_X86_CPU, "check", "off" }, 256 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 257 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 258 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 259 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 260 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 261 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 262 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 263 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 264 }; 265 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 266 267 GlobalProperty pc_compat_2_3[] = { 268 PC_CPU_MODEL_IDS("2.3.0") 269 { TYPE_X86_CPU, "arat", "off" }, 270 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 271 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 272 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 273 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 274 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 275 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 276 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 277 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 281 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 282 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 283 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 284 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 285 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 286 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 287 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 288 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 289 }; 290 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 291 292 GlobalProperty pc_compat_2_2[] = { 293 PC_CPU_MODEL_IDS("2.2.0") 294 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 303 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 307 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 308 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 309 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 310 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 311 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 312 }; 313 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 314 315 GlobalProperty pc_compat_2_1[] = { 316 PC_CPU_MODEL_IDS("2.1.0") 317 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 318 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 319 }; 320 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 321 322 GlobalProperty pc_compat_2_0[] = { 323 PC_CPU_MODEL_IDS("2.0.0") 324 { "virtio-scsi-pci", "any_layout", "off" }, 325 { "PIIX4_PM", "memory-hotplug-support", "off" }, 326 { "apic", "version", "0x11" }, 327 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 328 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 329 { "pci-serial", "prog_if", "0" }, 330 { "pci-serial-2x", "prog_if", "0" }, 331 { "pci-serial-4x", "prog_if", "0" }, 332 { "virtio-net-pci", "guest_announce", "off" }, 333 { "ICH9-LPC", "memory-hotplug-support", "off" }, 334 }; 335 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 336 337 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 338 { 339 GSIState *s; 340 341 s = g_new0(GSIState, 1); 342 if (kvm_ioapic_in_kernel()) { 343 kvm_pc_setup_irq_routing(pci_enabled); 344 } 345 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 346 347 return s; 348 } 349 350 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 351 unsigned size) 352 { 353 } 354 355 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 356 { 357 return 0xffffffffffffffffULL; 358 } 359 360 /* MS-DOS compatibility mode FPU exception support */ 361 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 362 unsigned size) 363 { 364 if (tcg_enabled()) { 365 cpu_set_ignne(); 366 } 367 } 368 369 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 370 { 371 return 0xffffffffffffffffULL; 372 } 373 374 /* PC cmos mappings */ 375 376 #define REG_EQUIPMENT_BYTE 0x14 377 378 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 379 int16_t cylinders, int8_t heads, int8_t sectors) 380 { 381 mc146818rtc_set_cmos_data(s, type_ofs, 47); 382 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 383 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 384 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 385 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 386 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 387 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 388 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 389 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 390 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 391 } 392 393 /* convert boot_device letter to something recognizable by the bios */ 394 static int boot_device2nibble(char boot_device) 395 { 396 switch(boot_device) { 397 case 'a': 398 case 'b': 399 return 0x01; /* floppy boot */ 400 case 'c': 401 return 0x02; /* hard drive boot */ 402 case 'd': 403 return 0x03; /* CD-ROM boot */ 404 case 'n': 405 return 0x04; /* Network boot */ 406 } 407 return 0; 408 } 409 410 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 411 const char *boot_device, Error **errp) 412 { 413 #define PC_MAX_BOOT_DEVICES 3 414 int nbds, bds[3] = { 0, }; 415 int i; 416 417 nbds = strlen(boot_device); 418 if (nbds > PC_MAX_BOOT_DEVICES) { 419 error_setg(errp, "Too many boot devices for PC"); 420 return; 421 } 422 for (i = 0; i < nbds; i++) { 423 bds[i] = boot_device2nibble(boot_device[i]); 424 if (bds[i] == 0) { 425 error_setg(errp, "Invalid boot device for PC: '%c'", 426 boot_device[i]); 427 return; 428 } 429 } 430 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 431 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 432 } 433 434 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 435 { 436 PCMachineState *pcms = opaque; 437 X86MachineState *x86ms = X86_MACHINE(pcms); 438 439 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 440 } 441 442 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 443 { 444 int val, nb; 445 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 446 FLOPPY_DRIVE_TYPE_NONE }; 447 448 #ifdef CONFIG_FDC_ISA 449 /* floppy type */ 450 if (floppy) { 451 for (int i = 0; i < 2; i++) { 452 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 453 } 454 } 455 #endif 456 457 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 458 cmos_get_fd_drive_type(fd_type[1]); 459 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 460 461 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 462 nb = 0; 463 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 464 nb++; 465 } 466 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 467 nb++; 468 } 469 switch (nb) { 470 case 0: 471 break; 472 case 1: 473 val |= 0x01; /* 1 drive, ready for boot */ 474 break; 475 case 2: 476 val |= 0x41; /* 2 drives, ready for boot */ 477 break; 478 } 479 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 480 } 481 482 typedef struct check_fdc_state { 483 ISADevice *floppy; 484 bool multiple; 485 } CheckFdcState; 486 487 static int check_fdc(Object *obj, void *opaque) 488 { 489 CheckFdcState *state = opaque; 490 Object *fdc; 491 uint32_t iobase; 492 Error *local_err = NULL; 493 494 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 495 if (!fdc) { 496 return 0; 497 } 498 499 iobase = object_property_get_uint(obj, "iobase", &local_err); 500 if (local_err || iobase != 0x3f0) { 501 error_free(local_err); 502 return 0; 503 } 504 505 if (state->floppy) { 506 state->multiple = true; 507 } else { 508 state->floppy = ISA_DEVICE(obj); 509 } 510 return 0; 511 } 512 513 static const char * const fdc_container_path[] = { 514 "/unattached", "/peripheral", "/peripheral-anon" 515 }; 516 517 /* 518 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 519 * and ACPI objects. 520 */ 521 static ISADevice *pc_find_fdc0(void) 522 { 523 int i; 524 Object *container; 525 CheckFdcState state = { 0 }; 526 527 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 528 container = container_get(qdev_get_machine(), fdc_container_path[i]); 529 object_child_foreach(container, check_fdc, &state); 530 } 531 532 if (state.multiple) { 533 warn_report("multiple floppy disk controllers with " 534 "iobase=0x3f0 have been found"); 535 error_printf("the one being picked for CMOS setup might not reflect " 536 "your intent"); 537 } 538 539 return state.floppy; 540 } 541 542 static void pc_cmos_init_late(PCMachineState *pcms) 543 { 544 X86MachineState *x86ms = X86_MACHINE(pcms); 545 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 546 int16_t cylinders; 547 int8_t heads, sectors; 548 int val; 549 int i, trans; 550 551 val = 0; 552 if (pcms->idebus[0] && 553 ide_get_geometry(pcms->idebus[0], 0, 554 &cylinders, &heads, §ors) >= 0) { 555 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 556 val |= 0xf0; 557 } 558 if (pcms->idebus[0] && 559 ide_get_geometry(pcms->idebus[0], 1, 560 &cylinders, &heads, §ors) >= 0) { 561 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 562 val |= 0x0f; 563 } 564 mc146818rtc_set_cmos_data(s, 0x12, val); 565 566 val = 0; 567 for (i = 0; i < 4; i++) { 568 /* NOTE: ide_get_geometry() returns the physical 569 geometry. It is always such that: 1 <= sects <= 63, 1 570 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 571 geometry can be different if a translation is done. */ 572 BusState *idebus = pcms->idebus[i / 2]; 573 if (idebus && 574 ide_get_geometry(idebus, i % 2, 575 &cylinders, &heads, §ors) >= 0) { 576 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 577 assert((trans & ~3) == 0); 578 val |= trans << (i * 2); 579 } 580 } 581 mc146818rtc_set_cmos_data(s, 0x39, val); 582 583 pc_cmos_init_floppy(s, pc_find_fdc0()); 584 585 /* various important CMOS locations needed by PC/Bochs bios */ 586 587 /* memory size */ 588 /* base memory (first MiB) */ 589 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 590 mc146818rtc_set_cmos_data(s, 0x15, val); 591 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 592 /* extended memory (next 64MiB) */ 593 if (x86ms->below_4g_mem_size > 1 * MiB) { 594 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 595 } else { 596 val = 0; 597 } 598 if (val > 65535) 599 val = 65535; 600 mc146818rtc_set_cmos_data(s, 0x17, val); 601 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 602 mc146818rtc_set_cmos_data(s, 0x30, val); 603 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 604 /* memory between 16MiB and 4GiB */ 605 if (x86ms->below_4g_mem_size > 16 * MiB) { 606 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 607 } else { 608 val = 0; 609 } 610 if (val > 65535) 611 val = 65535; 612 mc146818rtc_set_cmos_data(s, 0x34, val); 613 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 614 /* memory above 4GiB */ 615 val = x86ms->above_4g_mem_size / 65536; 616 mc146818rtc_set_cmos_data(s, 0x5b, val); 617 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 618 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 619 620 val = 0; 621 val |= 0x02; /* FPU is there */ 622 val |= 0x04; /* PS/2 mouse installed */ 623 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 624 } 625 626 static void handle_a20_line_change(void *opaque, int irq, int level) 627 { 628 X86CPU *cpu = opaque; 629 630 /* XXX: send to all CPUs ? */ 631 /* XXX: add logic to handle multiple A20 line sources */ 632 x86_cpu_set_a20(cpu, level); 633 } 634 635 #define NE2000_NB_MAX 6 636 637 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 638 0x280, 0x380 }; 639 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 640 641 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 642 { 643 static int nb_ne2k = 0; 644 645 if (nb_ne2k == NE2000_NB_MAX) { 646 error_setg(errp, 647 "maximum number of ISA NE2000 devices exceeded"); 648 return false; 649 } 650 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 651 ne2000_irq[nb_ne2k], nd); 652 nb_ne2k++; 653 return true; 654 } 655 656 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 657 { 658 X86CPU *cpu = opaque; 659 660 if (level) { 661 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 662 } 663 } 664 665 static 666 void pc_machine_done(Notifier *notifier, void *data) 667 { 668 PCMachineState *pcms = container_of(notifier, 669 PCMachineState, machine_done); 670 X86MachineState *x86ms = X86_MACHINE(pcms); 671 672 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 673 &error_fatal); 674 675 if (pcms->cxl_devices_state.is_enabled) { 676 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 677 } 678 679 /* set the number of CPUs */ 680 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 681 682 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 683 684 acpi_setup(); 685 if (x86ms->fw_cfg) { 686 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 687 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 688 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 689 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 690 } 691 692 pc_cmos_init_late(pcms); 693 } 694 695 /* setup pci memory address space mapping into system address space */ 696 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 697 MemoryRegion *pci_address_space) 698 { 699 /* Set to lower priority than RAM */ 700 memory_region_add_subregion_overlap(system_memory, 0x0, 701 pci_address_space, -1); 702 } 703 704 void xen_load_linux(PCMachineState *pcms) 705 { 706 int i; 707 FWCfgState *fw_cfg; 708 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 709 X86MachineState *x86ms = X86_MACHINE(pcms); 710 711 assert(MACHINE(pcms)->kernel_filename != NULL); 712 713 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 714 &address_space_memory); 715 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 716 rom_set_fw(fw_cfg); 717 718 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 719 pcmc->pvh_enabled); 720 for (i = 0; i < nb_option_roms; i++) { 721 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 722 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 723 !strcmp(option_rom[i].name, "pvh.bin") || 724 !strcmp(option_rom[i].name, "multiboot.bin") || 725 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 726 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 727 } 728 x86ms->fw_cfg = fw_cfg; 729 } 730 731 #define PC_ROM_MIN_VGA 0xc0000 732 #define PC_ROM_MIN_OPTION 0xc8000 733 #define PC_ROM_MAX 0xe0000 734 #define PC_ROM_ALIGN 0x800 735 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 736 737 static hwaddr pc_above_4g_end(PCMachineState *pcms) 738 { 739 X86MachineState *x86ms = X86_MACHINE(pcms); 740 741 if (pcms->sgx_epc.size != 0) { 742 return sgx_epc_above_4g_end(&pcms->sgx_epc); 743 } 744 745 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 746 } 747 748 static void pc_get_device_memory_range(PCMachineState *pcms, 749 hwaddr *base, 750 ram_addr_t *device_mem_size) 751 { 752 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 753 MachineState *machine = MACHINE(pcms); 754 ram_addr_t size; 755 hwaddr addr; 756 757 size = machine->maxram_size - machine->ram_size; 758 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 759 760 if (pcmc->enforce_aligned_dimm) { 761 /* size device region assuming 1G page max alignment per slot */ 762 size += (1 * GiB) * machine->ram_slots; 763 } 764 765 *base = addr; 766 *device_mem_size = size; 767 } 768 769 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 770 { 771 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 772 MachineState *ms = MACHINE(pcms); 773 hwaddr cxl_base; 774 ram_addr_t size; 775 776 if (pcmc->has_reserved_memory && 777 (ms->ram_size < ms->maxram_size)) { 778 pc_get_device_memory_range(pcms, &cxl_base, &size); 779 cxl_base += size; 780 } else { 781 cxl_base = pc_above_4g_end(pcms); 782 } 783 784 return cxl_base; 785 } 786 787 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 788 { 789 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 790 791 if (pcms->cxl_devices_state.fixed_windows) { 792 GList *it; 793 794 start = ROUND_UP(start, 256 * MiB); 795 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 796 CXLFixedWindow *fw = it->data; 797 start += fw->size; 798 } 799 } 800 801 return start; 802 } 803 804 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 805 { 806 X86CPU *cpu = X86_CPU(first_cpu); 807 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 808 MachineState *ms = MACHINE(pcms); 809 810 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 811 /* 64-bit systems */ 812 return pc_pci_hole64_start() + pci_hole64_size - 1; 813 } 814 815 /* 32-bit systems */ 816 if (pcmc->broken_32bit_mem_addr_check) { 817 /* old value for compatibility reasons */ 818 return ((hwaddr)1 << cpu->phys_bits) - 1; 819 } 820 821 /* 822 * 32-bit systems don't have hole64 but they might have a region for 823 * memory devices. Even if additional hotplugged memory devices might 824 * not be usable by most guest OSes, we need to still consider them for 825 * calculating the highest possible GPA so that we can properly report 826 * if someone configures them on a CPU that cannot possibly address them. 827 */ 828 if (pcmc->has_reserved_memory && 829 (ms->ram_size < ms->maxram_size)) { 830 hwaddr devmem_start; 831 ram_addr_t devmem_size; 832 833 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 834 devmem_start += devmem_size; 835 return devmem_start - 1; 836 } 837 838 /* configuration without any memory hotplug */ 839 return pc_above_4g_end(pcms) - 1; 840 } 841 842 /* 843 * AMD systems with an IOMMU have an additional hole close to the 844 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 845 * on kernel version, VFIO may or may not let you DMA map those ranges. 846 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 847 * with certain memory sizes. It's also wrong to use those IOVA ranges 848 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 849 * The ranges reserved for Hyper-Transport are: 850 * 851 * FD_0000_0000h - FF_FFFF_FFFFh 852 * 853 * The ranges represent the following: 854 * 855 * Base Address Top Address Use 856 * 857 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 858 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 859 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 860 * FD_F910_0000h FD_F91F_FFFFh System Management 861 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 862 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 863 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 864 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 865 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 866 * FE_2000_0000h FF_FFFF_FFFFh Reserved 867 * 868 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 869 * Table 3: Special Address Controls (GPA) for more information. 870 */ 871 #define AMD_HT_START 0xfd00000000UL 872 #define AMD_HT_END 0xffffffffffUL 873 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 874 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 875 876 void pc_memory_init(PCMachineState *pcms, 877 MemoryRegion *system_memory, 878 MemoryRegion *rom_memory, 879 uint64_t pci_hole64_size) 880 { 881 int linux_boot, i; 882 MemoryRegion *option_rom_mr; 883 MemoryRegion *ram_below_4g, *ram_above_4g; 884 FWCfgState *fw_cfg; 885 MachineState *machine = MACHINE(pcms); 886 MachineClass *mc = MACHINE_GET_CLASS(machine); 887 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 888 X86MachineState *x86ms = X86_MACHINE(pcms); 889 hwaddr maxphysaddr, maxusedaddr; 890 hwaddr cxl_base, cxl_resv_end = 0; 891 X86CPU *cpu = X86_CPU(first_cpu); 892 893 assert(machine->ram_size == x86ms->below_4g_mem_size + 894 x86ms->above_4g_mem_size); 895 896 linux_boot = (machine->kernel_filename != NULL); 897 898 /* 899 * The HyperTransport range close to the 1T boundary is unique to AMD 900 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 901 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 902 * older machine types (<= 7.0) for compatibility purposes. 903 */ 904 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 905 /* Bail out if max possible address does not cross HT range */ 906 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 907 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 908 } 909 910 /* 911 * Advertise the HT region if address space covers the reserved 912 * region or if we relocate. 913 */ 914 if (cpu->phys_bits >= 40) { 915 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 916 } 917 } 918 919 /* 920 * phys-bits is required to be appropriately configured 921 * to make sure max used GPA is reachable. 922 */ 923 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 924 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 925 if (maxphysaddr < maxusedaddr) { 926 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 927 " phys-bits too low (%u)", 928 maxphysaddr, maxusedaddr, cpu->phys_bits); 929 exit(EXIT_FAILURE); 930 } 931 932 /* 933 * Split single memory region and use aliases to address portions of it, 934 * done for backwards compatibility with older qemus. 935 */ 936 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 937 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 938 0, x86ms->below_4g_mem_size); 939 memory_region_add_subregion(system_memory, 0, ram_below_4g); 940 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 941 if (x86ms->above_4g_mem_size > 0) { 942 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 943 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 944 machine->ram, 945 x86ms->below_4g_mem_size, 946 x86ms->above_4g_mem_size); 947 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 948 ram_above_4g); 949 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 950 E820_RAM); 951 } 952 953 if (pcms->sgx_epc.size != 0) { 954 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 955 } 956 957 if (!pcmc->has_reserved_memory && 958 (machine->ram_slots || 959 (machine->maxram_size > machine->ram_size))) { 960 961 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 962 mc->name); 963 exit(EXIT_FAILURE); 964 } 965 966 /* initialize device memory address space */ 967 if (pcmc->has_reserved_memory && 968 (machine->ram_size < machine->maxram_size)) { 969 ram_addr_t device_mem_size; 970 hwaddr device_mem_base; 971 972 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 973 error_report("unsupported amount of memory slots: %"PRIu64, 974 machine->ram_slots); 975 exit(EXIT_FAILURE); 976 } 977 978 if (QEMU_ALIGN_UP(machine->maxram_size, 979 TARGET_PAGE_SIZE) != machine->maxram_size) { 980 error_report("maximum memory size must by aligned to multiple of " 981 "%d bytes", TARGET_PAGE_SIZE); 982 exit(EXIT_FAILURE); 983 } 984 985 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 986 987 if (device_mem_base + device_mem_size < device_mem_size) { 988 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 989 machine->maxram_size); 990 exit(EXIT_FAILURE); 991 } 992 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 993 } 994 995 if (pcms->cxl_devices_state.is_enabled) { 996 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 997 hwaddr cxl_size = MiB; 998 999 cxl_base = pc_get_cxl_range_start(pcms); 1000 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1001 memory_region_add_subregion(system_memory, cxl_base, mr); 1002 cxl_resv_end = cxl_base + cxl_size; 1003 if (pcms->cxl_devices_state.fixed_windows) { 1004 hwaddr cxl_fmw_base; 1005 GList *it; 1006 1007 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1008 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1009 CXLFixedWindow *fw = it->data; 1010 1011 fw->base = cxl_fmw_base; 1012 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1013 "cxl-fixed-memory-region", fw->size); 1014 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1015 cxl_fmw_base += fw->size; 1016 cxl_resv_end = cxl_fmw_base; 1017 } 1018 } 1019 } 1020 1021 /* Initialize PC system firmware */ 1022 pc_system_firmware_init(pcms, rom_memory); 1023 1024 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1025 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1026 &error_fatal); 1027 if (pcmc->pci_enabled) { 1028 memory_region_set_readonly(option_rom_mr, true); 1029 } 1030 memory_region_add_subregion_overlap(rom_memory, 1031 PC_ROM_MIN_VGA, 1032 option_rom_mr, 1033 1); 1034 1035 fw_cfg = fw_cfg_arch_create(machine, 1036 x86ms->boot_cpus, x86ms->apic_id_limit); 1037 1038 rom_set_fw(fw_cfg); 1039 1040 if (machine->device_memory) { 1041 uint64_t *val = g_malloc(sizeof(*val)); 1042 uint64_t res_mem_end = machine->device_memory->base; 1043 1044 if (!pcmc->broken_reserved_end) { 1045 res_mem_end += memory_region_size(&machine->device_memory->mr); 1046 } 1047 1048 if (pcms->cxl_devices_state.is_enabled) { 1049 res_mem_end = cxl_resv_end; 1050 } 1051 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1052 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1053 } 1054 1055 if (linux_boot) { 1056 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1057 pcmc->pvh_enabled); 1058 } 1059 1060 for (i = 0; i < nb_option_roms; i++) { 1061 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1062 } 1063 x86ms->fw_cfg = fw_cfg; 1064 1065 /* Init default IOAPIC address space */ 1066 x86ms->ioapic_as = &address_space_memory; 1067 1068 /* Init ACPI memory hotplug IO base address */ 1069 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1070 } 1071 1072 /* 1073 * The 64bit pci hole starts after "above 4G RAM" and 1074 * potentially the space reserved for memory hotplug. 1075 */ 1076 uint64_t pc_pci_hole64_start(void) 1077 { 1078 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1079 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1080 MachineState *ms = MACHINE(pcms); 1081 uint64_t hole64_start = 0; 1082 ram_addr_t size = 0; 1083 1084 if (pcms->cxl_devices_state.is_enabled) { 1085 hole64_start = pc_get_cxl_range_end(pcms); 1086 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1087 pc_get_device_memory_range(pcms, &hole64_start, &size); 1088 if (!pcmc->broken_reserved_end) { 1089 hole64_start += size; 1090 } 1091 } else { 1092 hole64_start = pc_above_4g_end(pcms); 1093 } 1094 1095 return ROUND_UP(hole64_start, 1 * GiB); 1096 } 1097 1098 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1099 { 1100 DeviceState *dev = NULL; 1101 1102 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1103 if (pci_bus) { 1104 PCIDevice *pcidev = pci_vga_init(pci_bus); 1105 dev = pcidev ? &pcidev->qdev : NULL; 1106 } else if (isa_bus) { 1107 ISADevice *isadev = isa_vga_init(isa_bus); 1108 dev = isadev ? DEVICE(isadev) : NULL; 1109 } 1110 rom_reset_order_override(); 1111 return dev; 1112 } 1113 1114 static const MemoryRegionOps ioport80_io_ops = { 1115 .write = ioport80_write, 1116 .read = ioport80_read, 1117 .endianness = DEVICE_NATIVE_ENDIAN, 1118 .impl = { 1119 .min_access_size = 1, 1120 .max_access_size = 1, 1121 }, 1122 }; 1123 1124 static const MemoryRegionOps ioportF0_io_ops = { 1125 .write = ioportF0_write, 1126 .read = ioportF0_read, 1127 .endianness = DEVICE_NATIVE_ENDIAN, 1128 .impl = { 1129 .min_access_size = 1, 1130 .max_access_size = 1, 1131 }, 1132 }; 1133 1134 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1135 bool create_i8042, bool no_vmport) 1136 { 1137 int i; 1138 DriveInfo *fd[MAX_FD]; 1139 qemu_irq *a20_line; 1140 ISADevice *i8042, *port92, *vmmouse; 1141 1142 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1143 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1144 1145 for (i = 0; i < MAX_FD; i++) { 1146 fd[i] = drive_get(IF_FLOPPY, 0, i); 1147 create_fdctrl |= !!fd[i]; 1148 } 1149 if (create_fdctrl) { 1150 #ifdef CONFIG_FDC_ISA 1151 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1152 if (fdc) { 1153 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1154 isa_fdc_init_drives(fdc, fd); 1155 } 1156 #endif 1157 } 1158 1159 if (!create_i8042) { 1160 return; 1161 } 1162 1163 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1164 if (!no_vmport) { 1165 isa_create_simple(isa_bus, TYPE_VMPORT); 1166 vmmouse = isa_try_new("vmmouse"); 1167 } else { 1168 vmmouse = NULL; 1169 } 1170 if (vmmouse) { 1171 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1172 &error_abort); 1173 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1174 } 1175 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1176 1177 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1178 qdev_connect_gpio_out_named(DEVICE(i8042), 1179 I8042_A20_LINE, 0, a20_line[0]); 1180 qdev_connect_gpio_out_named(DEVICE(port92), 1181 PORT92_A20_LINE, 0, a20_line[1]); 1182 g_free(a20_line); 1183 } 1184 1185 void pc_basic_device_init(struct PCMachineState *pcms, 1186 ISABus *isa_bus, qemu_irq *gsi, 1187 ISADevice *rtc_state, 1188 bool create_fdctrl, 1189 uint32_t hpet_irqs) 1190 { 1191 int i; 1192 DeviceState *hpet = NULL; 1193 int pit_isa_irq = 0; 1194 qemu_irq pit_alt_irq = NULL; 1195 ISADevice *pit = NULL; 1196 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1197 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1198 X86MachineState *x86ms = X86_MACHINE(pcms); 1199 1200 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1201 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1202 1203 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1204 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1205 1206 /* 1207 * Check if an HPET shall be created. 1208 */ 1209 if (pcms->hpet_enabled) { 1210 qemu_irq rtc_irq; 1211 1212 hpet = qdev_try_new(TYPE_HPET); 1213 if (!hpet) { 1214 error_report("couldn't create HPET device"); 1215 exit(1); 1216 } 1217 /* 1218 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1219 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1220 * the property, use whatever mask they specified. 1221 */ 1222 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1223 HPET_INTCAP, NULL); 1224 if (!compat) { 1225 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1226 } 1227 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1228 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1229 1230 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1231 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1232 } 1233 pit_isa_irq = -1; 1234 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1235 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1236 1237 /* overwrite connection created by south bridge */ 1238 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1239 } 1240 1241 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1242 "date"); 1243 1244 #ifdef CONFIG_XEN_EMU 1245 if (xen_mode == XEN_EMULATE) { 1246 xen_overlay_create(); 1247 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1248 xen_gnttab_create(); 1249 xen_xenstore_create(); 1250 if (pcms->pcibus) { 1251 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1252 } 1253 xen_bus_init(); 1254 } 1255 #endif 1256 1257 qemu_register_boot_set(pc_boot_set, pcms); 1258 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1259 MACHINE(pcms)->boot_config.order, &error_fatal); 1260 1261 if (!xen_enabled() && 1262 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1263 if (kvm_pit_in_kernel()) { 1264 pit = kvm_pit_init(isa_bus, 0x40); 1265 } else { 1266 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1267 } 1268 if (hpet) { 1269 /* connect PIT to output control line of the HPET */ 1270 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1271 } 1272 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1273 OBJECT(pit), &error_fatal); 1274 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1275 } 1276 1277 /* Super I/O */ 1278 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1279 pcms->vmport != ON_OFF_AUTO_ON); 1280 } 1281 1282 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1283 { 1284 MachineClass *mc = MACHINE_CLASS(pcmc); 1285 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1286 NICInfo *nd; 1287 1288 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1289 1290 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1291 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1292 } 1293 1294 /* Anything remaining should be a PCI NIC */ 1295 pci_init_nic_devices(pci_bus, mc->default_nic); 1296 1297 rom_reset_order_override(); 1298 } 1299 1300 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1301 { 1302 qemu_irq *i8259; 1303 1304 if (kvm_pic_in_kernel()) { 1305 i8259 = kvm_i8259_init(isa_bus); 1306 } else if (xen_enabled()) { 1307 i8259 = xen_interrupt_controller_init(); 1308 } else { 1309 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1310 } 1311 1312 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1313 i8259_irqs[i] = i8259[i]; 1314 } 1315 1316 g_free(i8259); 1317 } 1318 1319 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1320 Error **errp) 1321 { 1322 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1323 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1324 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1325 const MachineState *ms = MACHINE(hotplug_dev); 1326 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1327 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1328 Error *local_err = NULL; 1329 1330 /* 1331 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1332 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1333 * addition to cover this case. 1334 */ 1335 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1336 error_setg(errp, 1337 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1338 return; 1339 } 1340 1341 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1342 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1343 return; 1344 } 1345 1346 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1347 if (local_err) { 1348 error_propagate(errp, local_err); 1349 return; 1350 } 1351 1352 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1353 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1354 } 1355 1356 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1357 DeviceState *dev, Error **errp) 1358 { 1359 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1360 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1361 MachineState *ms = MACHINE(hotplug_dev); 1362 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1363 1364 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1365 1366 if (is_nvdimm) { 1367 nvdimm_plug(ms->nvdimms_state); 1368 } 1369 1370 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1371 } 1372 1373 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1374 DeviceState *dev, Error **errp) 1375 { 1376 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1377 1378 /* 1379 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1380 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1381 * addition to cover this case. 1382 */ 1383 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1384 error_setg(errp, 1385 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1386 return; 1387 } 1388 1389 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1390 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1391 return; 1392 } 1393 1394 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1395 errp); 1396 } 1397 1398 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1399 DeviceState *dev, Error **errp) 1400 { 1401 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1402 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1403 Error *local_err = NULL; 1404 1405 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1406 if (local_err) { 1407 goto out; 1408 } 1409 1410 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1411 qdev_unrealize(dev); 1412 out: 1413 error_propagate(errp, local_err); 1414 } 1415 1416 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1417 DeviceState *dev, Error **errp) 1418 { 1419 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1420 g_assert(!dev->hotplugged); 1421 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1422 errp); 1423 } 1424 1425 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1426 DeviceState *dev, Error **errp) 1427 { 1428 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1429 } 1430 1431 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1432 DeviceState *dev, Error **errp) 1433 { 1434 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1435 pc_memory_pre_plug(hotplug_dev, dev, errp); 1436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1437 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1439 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1441 /* Declare the APIC range as the reserved MSI region */ 1442 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1443 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1444 QList *reserved_regions = qlist_new(); 1445 1446 qlist_append_str(reserved_regions, resv_prop_str); 1447 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1448 1449 g_free(resv_prop_str); 1450 } 1451 1452 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1453 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1454 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1455 1456 if (pcms->iommu) { 1457 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1458 "for x86 yet."); 1459 return; 1460 } 1461 pcms->iommu = dev; 1462 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1463 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1464 } 1465 } 1466 1467 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1468 DeviceState *dev, Error **errp) 1469 { 1470 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1471 pc_memory_plug(hotplug_dev, dev, errp); 1472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1473 x86_cpu_plug(hotplug_dev, dev, errp); 1474 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1475 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1476 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1477 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1478 } 1479 } 1480 1481 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1482 DeviceState *dev, Error **errp) 1483 { 1484 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1485 pc_memory_unplug_request(hotplug_dev, dev, errp); 1486 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1487 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1488 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1489 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1490 errp); 1491 } else { 1492 error_setg(errp, "acpi: device unplug request for not supported device" 1493 " type: %s", object_get_typename(OBJECT(dev))); 1494 } 1495 } 1496 1497 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1498 DeviceState *dev, Error **errp) 1499 { 1500 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1501 pc_memory_unplug(hotplug_dev, dev, errp); 1502 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1503 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1504 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1505 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1506 } else { 1507 error_setg(errp, "acpi: device unplug for not supported device" 1508 " type: %s", object_get_typename(OBJECT(dev))); 1509 } 1510 } 1511 1512 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1513 DeviceState *dev) 1514 { 1515 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1516 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1517 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1518 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1519 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1520 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1521 return HOTPLUG_HANDLER(machine); 1522 } 1523 1524 return NULL; 1525 } 1526 1527 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1528 void *opaque, Error **errp) 1529 { 1530 PCMachineState *pcms = PC_MACHINE(obj); 1531 OnOffAuto vmport = pcms->vmport; 1532 1533 visit_type_OnOffAuto(v, name, &vmport, errp); 1534 } 1535 1536 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1537 void *opaque, Error **errp) 1538 { 1539 PCMachineState *pcms = PC_MACHINE(obj); 1540 1541 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1542 } 1543 1544 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 1548 return pcms->fd_bootchk; 1549 } 1550 1551 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1552 { 1553 PCMachineState *pcms = PC_MACHINE(obj); 1554 1555 pcms->fd_bootchk = value; 1556 } 1557 1558 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1559 { 1560 PCMachineState *pcms = PC_MACHINE(obj); 1561 1562 return pcms->smbus_enabled; 1563 } 1564 1565 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1566 { 1567 PCMachineState *pcms = PC_MACHINE(obj); 1568 1569 pcms->smbus_enabled = value; 1570 } 1571 1572 static bool pc_machine_get_sata(Object *obj, Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 1576 return pcms->sata_enabled; 1577 } 1578 1579 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 1583 pcms->sata_enabled = value; 1584 } 1585 1586 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1587 { 1588 PCMachineState *pcms = PC_MACHINE(obj); 1589 1590 return pcms->hpet_enabled; 1591 } 1592 1593 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1594 { 1595 PCMachineState *pcms = PC_MACHINE(obj); 1596 1597 pcms->hpet_enabled = value; 1598 } 1599 1600 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1601 { 1602 PCMachineState *pcms = PC_MACHINE(obj); 1603 1604 return pcms->i8042_enabled; 1605 } 1606 1607 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1608 { 1609 PCMachineState *pcms = PC_MACHINE(obj); 1610 1611 pcms->i8042_enabled = value; 1612 } 1613 1614 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1615 { 1616 PCMachineState *pcms = PC_MACHINE(obj); 1617 1618 return pcms->default_bus_bypass_iommu; 1619 } 1620 1621 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1622 Error **errp) 1623 { 1624 PCMachineState *pcms = PC_MACHINE(obj); 1625 1626 pcms->default_bus_bypass_iommu = value; 1627 } 1628 1629 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1630 void *opaque, Error **errp) 1631 { 1632 PCMachineState *pcms = PC_MACHINE(obj); 1633 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1634 1635 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1636 } 1637 1638 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1639 void *opaque, Error **errp) 1640 { 1641 PCMachineState *pcms = PC_MACHINE(obj); 1642 1643 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1644 } 1645 1646 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1647 const char *name, void *opaque, 1648 Error **errp) 1649 { 1650 PCMachineState *pcms = PC_MACHINE(obj); 1651 uint64_t value = pcms->max_ram_below_4g; 1652 1653 visit_type_size(v, name, &value, errp); 1654 } 1655 1656 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1657 const char *name, void *opaque, 1658 Error **errp) 1659 { 1660 PCMachineState *pcms = PC_MACHINE(obj); 1661 uint64_t value; 1662 1663 if (!visit_type_size(v, name, &value, errp)) { 1664 return; 1665 } 1666 if (value > 4 * GiB) { 1667 error_setg(errp, 1668 "Machine option 'max-ram-below-4g=%"PRIu64 1669 "' expects size less than or equal to 4G", value); 1670 return; 1671 } 1672 1673 if (value < 1 * MiB) { 1674 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1675 "BIOS may not work with less than 1MiB", value); 1676 } 1677 1678 pcms->max_ram_below_4g = value; 1679 } 1680 1681 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1682 const char *name, void *opaque, 1683 Error **errp) 1684 { 1685 PCMachineState *pcms = PC_MACHINE(obj); 1686 uint64_t value = pcms->max_fw_size; 1687 1688 visit_type_size(v, name, &value, errp); 1689 } 1690 1691 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1692 const char *name, void *opaque, 1693 Error **errp) 1694 { 1695 PCMachineState *pcms = PC_MACHINE(obj); 1696 uint64_t value; 1697 1698 if (!visit_type_size(v, name, &value, errp)) { 1699 return; 1700 } 1701 1702 /* 1703 * We don't have a theoretically justifiable exact lower bound on the base 1704 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1705 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1706 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1707 * 16MiB in size. 1708 */ 1709 if (value > 16 * MiB) { 1710 error_setg(errp, 1711 "User specified max allowed firmware size %" PRIu64 " is " 1712 "greater than 16MiB. If combined firmware size exceeds " 1713 "16MiB the system may not boot, or experience intermittent" 1714 "stability issues.", 1715 value); 1716 return; 1717 } 1718 1719 pcms->max_fw_size = value; 1720 } 1721 1722 1723 static void pc_machine_initfn(Object *obj) 1724 { 1725 PCMachineState *pcms = PC_MACHINE(obj); 1726 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1727 1728 #ifdef CONFIG_VMPORT 1729 pcms->vmport = ON_OFF_AUTO_AUTO; 1730 #else 1731 pcms->vmport = ON_OFF_AUTO_OFF; 1732 #endif /* CONFIG_VMPORT */ 1733 pcms->max_ram_below_4g = 0; /* use default */ 1734 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1735 pcms->south_bridge = pcmc->default_south_bridge; 1736 1737 /* acpi build is enabled by default if machine supports it */ 1738 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1739 pcms->smbus_enabled = true; 1740 pcms->sata_enabled = true; 1741 pcms->i8042_enabled = true; 1742 pcms->max_fw_size = 8 * MiB; 1743 #ifdef CONFIG_HPET 1744 pcms->hpet_enabled = true; 1745 #endif 1746 pcms->fd_bootchk = true; 1747 pcms->default_bus_bypass_iommu = false; 1748 1749 pc_system_flash_create(pcms); 1750 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1751 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1752 OBJECT(pcms->pcspk), "audiodev"); 1753 if (pcmc->pci_enabled) { 1754 cxl_machine_init(obj, &pcms->cxl_devices_state); 1755 } 1756 1757 pcms->machine_done.notify = pc_machine_done; 1758 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1759 } 1760 1761 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1762 { 1763 CPUState *cs; 1764 X86CPU *cpu; 1765 1766 qemu_devices_reset(reason); 1767 1768 /* Reset APIC after devices have been reset to cancel 1769 * any changes that qemu_devices_reset() might have done. 1770 */ 1771 CPU_FOREACH(cs) { 1772 cpu = X86_CPU(cs); 1773 1774 x86_cpu_after_reset(cpu); 1775 } 1776 } 1777 1778 static void pc_machine_wakeup(MachineState *machine) 1779 { 1780 cpu_synchronize_all_states(); 1781 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1782 cpu_synchronize_all_post_reset(); 1783 } 1784 1785 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1786 { 1787 X86IOMMUState *iommu = x86_iommu_get_default(); 1788 IntelIOMMUState *intel_iommu; 1789 1790 if (iommu && 1791 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1792 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1793 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1794 if (!intel_iommu->caching_mode) { 1795 error_setg(errp, "Device assignment is not allowed without " 1796 "enabling caching-mode=on for Intel IOMMU."); 1797 return false; 1798 } 1799 } 1800 1801 return true; 1802 } 1803 1804 static void pc_machine_class_init(ObjectClass *oc, void *data) 1805 { 1806 MachineClass *mc = MACHINE_CLASS(oc); 1807 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1808 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1809 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1810 1811 pcmc->pci_enabled = true; 1812 pcmc->has_acpi_build = true; 1813 pcmc->rsdp_in_ram = true; 1814 pcmc->smbios_defaults = true; 1815 pcmc->smbios_uuid_encoded = true; 1816 pcmc->gigabyte_align = true; 1817 pcmc->has_reserved_memory = true; 1818 pcmc->enforce_aligned_dimm = true; 1819 pcmc->enforce_amd_1tb_hole = true; 1820 pcmc->isa_bios_alias = true; 1821 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1822 * to be used at the moment, 32K should be enough for a while. */ 1823 pcmc->acpi_data_size = 0x20000 + 0x8000; 1824 pcmc->pvh_enabled = true; 1825 pcmc->kvmclock_create_always = true; 1826 pcmc->resizable_acpi_blob = true; 1827 x86mc->apic_xrupt_override = true; 1828 assert(!mc->get_hotplug_handler); 1829 mc->get_hotplug_handler = pc_get_hotplug_handler; 1830 mc->hotplug_allowed = pc_hotplug_allowed; 1831 mc->auto_enable_numa_with_memhp = true; 1832 mc->auto_enable_numa_with_memdev = true; 1833 mc->has_hotpluggable_cpus = true; 1834 mc->default_boot_order = "cad"; 1835 mc->block_default_type = IF_IDE; 1836 mc->max_cpus = 255; 1837 mc->reset = pc_machine_reset; 1838 mc->wakeup = pc_machine_wakeup; 1839 hc->pre_plug = pc_machine_device_pre_plug_cb; 1840 hc->plug = pc_machine_device_plug_cb; 1841 hc->unplug_request = pc_machine_device_unplug_request_cb; 1842 hc->unplug = pc_machine_device_unplug_cb; 1843 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1844 mc->nvdimm_supported = true; 1845 mc->smp_props.dies_supported = true; 1846 mc->smp_props.modules_supported = true; 1847 mc->default_ram_id = "pc.ram"; 1848 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1849 1850 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1851 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1852 NULL, NULL); 1853 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1854 "Maximum ram below the 4G boundary (32bit boundary)"); 1855 1856 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1857 pc_machine_get_vmport, pc_machine_set_vmport, 1858 NULL, NULL); 1859 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1860 "Enable vmport (pc & q35)"); 1861 1862 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1863 pc_machine_get_smbus, pc_machine_set_smbus); 1864 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1865 "Enable/disable system management bus"); 1866 1867 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1868 pc_machine_get_sata, pc_machine_set_sata); 1869 object_class_property_set_description(oc, PC_MACHINE_SATA, 1870 "Enable/disable Serial ATA bus"); 1871 1872 object_class_property_add_bool(oc, "hpet", 1873 pc_machine_get_hpet, pc_machine_set_hpet); 1874 object_class_property_set_description(oc, "hpet", 1875 "Enable/disable high precision event timer emulation"); 1876 1877 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1878 pc_machine_get_i8042, pc_machine_set_i8042); 1879 1880 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1881 pc_machine_get_default_bus_bypass_iommu, 1882 pc_machine_set_default_bus_bypass_iommu); 1883 1884 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1885 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1886 NULL, NULL); 1887 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1888 "Maximum combined firmware size"); 1889 1890 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1891 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1892 NULL, NULL); 1893 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1894 "SMBIOS Entry Point type [32, 64]"); 1895 1896 object_class_property_add_bool(oc, "fd-bootchk", 1897 pc_machine_get_fd_bootchk, 1898 pc_machine_set_fd_bootchk); 1899 } 1900 1901 static const TypeInfo pc_machine_info = { 1902 .name = TYPE_PC_MACHINE, 1903 .parent = TYPE_X86_MACHINE, 1904 .abstract = true, 1905 .instance_size = sizeof(PCMachineState), 1906 .instance_init = pc_machine_initfn, 1907 .class_size = sizeof(PCMachineClass), 1908 .class_init = pc_machine_class_init, 1909 .interfaces = (InterfaceInfo[]) { 1910 { TYPE_HOTPLUG_HANDLER }, 1911 { } 1912 }, 1913 }; 1914 1915 static void pc_machine_register_types(void) 1916 { 1917 type_register_static(&pc_machine_info); 1918 } 1919 1920 type_init(pc_machine_register_types) 1921