1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/qapi-visit-machine.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-iommu.h" 88 #include "hw/virtio/virtio-pmem-pci.h" 89 #include "hw/virtio/virtio-mem-pci.h" 90 #include "hw/mem/memory-device.h" 91 #include "sysemu/replay.h" 92 #include "qapi/qmp/qerror.h" 93 #include "e820_memory_layout.h" 94 #include "fw_cfg.h" 95 #include "trace.h" 96 #include CONFIG_DEVICES 97 98 GlobalProperty pc_compat_6_2[] = { 99 { "virtio-mem", "unplugged-inaccessible", "off" }, 100 }; 101 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 102 103 GlobalProperty pc_compat_6_1[] = { 104 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 105 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 106 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 107 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 108 }; 109 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 110 111 GlobalProperty pc_compat_6_0[] = { 112 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 113 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 114 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 115 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 116 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 117 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 118 }; 119 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 120 121 GlobalProperty pc_compat_5_2[] = { 122 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 123 }; 124 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 125 126 GlobalProperty pc_compat_5_1[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 128 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 129 }; 130 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 131 132 GlobalProperty pc_compat_5_0[] = { 133 }; 134 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 135 136 GlobalProperty pc_compat_4_2[] = { 137 { "mch", "smbase-smram", "off" }, 138 }; 139 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 140 141 GlobalProperty pc_compat_4_1[] = {}; 142 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 143 144 GlobalProperty pc_compat_4_0[] = {}; 145 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 146 147 GlobalProperty pc_compat_3_1[] = { 148 { "intel-iommu", "dma-drain", "off" }, 149 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 150 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 151 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 152 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 153 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 154 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 155 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 156 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 159 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 160 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 161 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 162 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 163 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 164 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 165 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 168 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 169 }; 170 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 171 172 GlobalProperty pc_compat_3_0[] = { 173 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 174 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 175 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 176 }; 177 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 178 179 GlobalProperty pc_compat_2_12[] = { 180 { TYPE_X86_CPU, "legacy-cache", "on" }, 181 { TYPE_X86_CPU, "topoext", "off" }, 182 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 183 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 184 }; 185 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 186 187 GlobalProperty pc_compat_2_11[] = { 188 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 189 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 190 }; 191 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 192 193 GlobalProperty pc_compat_2_10[] = { 194 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 195 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 196 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 197 }; 198 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 199 200 GlobalProperty pc_compat_2_9[] = { 201 { "mch", "extended-tseg-mbytes", "0" }, 202 }; 203 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 204 205 GlobalProperty pc_compat_2_8[] = { 206 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 207 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 208 { "ICH9-LPC", "x-smi-broadcast", "off" }, 209 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 210 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 211 }; 212 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 213 214 GlobalProperty pc_compat_2_7[] = { 215 { TYPE_X86_CPU, "l3-cache", "off" }, 216 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 217 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 218 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 219 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 220 { "isa-pcspk", "migrate", "off" }, 221 }; 222 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 223 224 GlobalProperty pc_compat_2_6[] = { 225 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 226 { "vmxnet3", "romfile", "" }, 227 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 228 { "apic-common", "legacy-instance-id", "on", } 229 }; 230 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 231 232 GlobalProperty pc_compat_2_5[] = {}; 233 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 234 235 GlobalProperty pc_compat_2_4[] = { 236 PC_CPU_MODEL_IDS("2.4.0") 237 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 238 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 239 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 240 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 241 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 242 { TYPE_X86_CPU, "check", "off" }, 243 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 244 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 245 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 246 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 247 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 248 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 249 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 250 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 251 }; 252 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 253 254 GlobalProperty pc_compat_2_3[] = { 255 PC_CPU_MODEL_IDS("2.3.0") 256 { TYPE_X86_CPU, "arat", "off" }, 257 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 258 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 259 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 260 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 261 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 262 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 264 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 265 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 267 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 268 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 269 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 276 }; 277 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 278 279 GlobalProperty pc_compat_2_2[] = { 280 PC_CPU_MODEL_IDS("2.2.0") 281 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 282 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 283 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 284 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 285 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 286 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 296 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 297 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 298 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 299 }; 300 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 301 302 GlobalProperty pc_compat_2_1[] = { 303 PC_CPU_MODEL_IDS("2.1.0") 304 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 305 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 306 }; 307 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 308 309 GlobalProperty pc_compat_2_0[] = { 310 PC_CPU_MODEL_IDS("2.0.0") 311 { "virtio-scsi-pci", "any_layout", "off" }, 312 { "PIIX4_PM", "memory-hotplug-support", "off" }, 313 { "apic", "version", "0x11" }, 314 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 315 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 316 { "pci-serial", "prog_if", "0" }, 317 { "pci-serial-2x", "prog_if", "0" }, 318 { "pci-serial-4x", "prog_if", "0" }, 319 { "virtio-net-pci", "guest_announce", "off" }, 320 { "ICH9-LPC", "memory-hotplug-support", "off" }, 321 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 322 { "ioh3420", COMPAT_PROP_PCP, "off" }, 323 }; 324 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 325 326 GlobalProperty pc_compat_1_7[] = { 327 PC_CPU_MODEL_IDS("1.7.0") 328 { TYPE_USB_DEVICE, "msos-desc", "no" }, 329 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 330 { "hpet", HPET_INTCAP, "4" }, 331 }; 332 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 333 334 GlobalProperty pc_compat_1_6[] = { 335 PC_CPU_MODEL_IDS("1.6.0") 336 { "e1000", "mitigation", "off" }, 337 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 338 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 339 { "i440FX-pcihost", "short_root_bus", "1" }, 340 { "q35-pcihost", "short_root_bus", "1" }, 341 }; 342 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 343 344 GlobalProperty pc_compat_1_5[] = { 345 PC_CPU_MODEL_IDS("1.5.0") 346 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 347 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 348 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 349 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 350 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 351 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 352 { "virtio-net-pci", "any_layout", "off" }, 353 { TYPE_X86_CPU, "pmu", "on" }, 354 { "i440FX-pcihost", "short_root_bus", "0" }, 355 { "q35-pcihost", "short_root_bus", "0" }, 356 }; 357 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 358 359 GlobalProperty pc_compat_1_4[] = { 360 PC_CPU_MODEL_IDS("1.4.0") 361 { "scsi-hd", "discard_granularity", "0" }, 362 { "scsi-cd", "discard_granularity", "0" }, 363 { "ide-hd", "discard_granularity", "0" }, 364 { "ide-cd", "discard_granularity", "0" }, 365 { "virtio-blk-pci", "discard_granularity", "0" }, 366 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 367 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 368 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 369 { "e1000", "romfile", "pxe-e1000.rom" }, 370 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 371 { "pcnet", "romfile", "pxe-pcnet.rom" }, 372 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 373 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 374 { "486-" TYPE_X86_CPU, "model", "0" }, 375 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 376 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 377 }; 378 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 379 380 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 381 { 382 GSIState *s; 383 384 s = g_new0(GSIState, 1); 385 if (kvm_ioapic_in_kernel()) { 386 kvm_pc_setup_irq_routing(pci_enabled); 387 } 388 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 389 390 return s; 391 } 392 393 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 394 unsigned size) 395 { 396 } 397 398 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 399 { 400 return 0xffffffffffffffffULL; 401 } 402 403 /* MSDOS compatibility mode FPU exception support */ 404 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 405 unsigned size) 406 { 407 if (tcg_enabled()) { 408 cpu_set_ignne(); 409 } 410 } 411 412 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 413 { 414 return 0xffffffffffffffffULL; 415 } 416 417 /* PC cmos mappings */ 418 419 #define REG_EQUIPMENT_BYTE 0x14 420 421 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 422 int16_t cylinders, int8_t heads, int8_t sectors) 423 { 424 rtc_set_memory(s, type_ofs, 47); 425 rtc_set_memory(s, info_ofs, cylinders); 426 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 427 rtc_set_memory(s, info_ofs + 2, heads); 428 rtc_set_memory(s, info_ofs + 3, 0xff); 429 rtc_set_memory(s, info_ofs + 4, 0xff); 430 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 431 rtc_set_memory(s, info_ofs + 6, cylinders); 432 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 433 rtc_set_memory(s, info_ofs + 8, sectors); 434 } 435 436 /* convert boot_device letter to something recognizable by the bios */ 437 static int boot_device2nibble(char boot_device) 438 { 439 switch(boot_device) { 440 case 'a': 441 case 'b': 442 return 0x01; /* floppy boot */ 443 case 'c': 444 return 0x02; /* hard drive boot */ 445 case 'd': 446 return 0x03; /* CD-ROM boot */ 447 case 'n': 448 return 0x04; /* Network boot */ 449 } 450 return 0; 451 } 452 453 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 454 { 455 #define PC_MAX_BOOT_DEVICES 3 456 int nbds, bds[3] = { 0, }; 457 int i; 458 459 nbds = strlen(boot_device); 460 if (nbds > PC_MAX_BOOT_DEVICES) { 461 error_setg(errp, "Too many boot devices for PC"); 462 return; 463 } 464 for (i = 0; i < nbds; i++) { 465 bds[i] = boot_device2nibble(boot_device[i]); 466 if (bds[i] == 0) { 467 error_setg(errp, "Invalid boot device for PC: '%c'", 468 boot_device[i]); 469 return; 470 } 471 } 472 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 473 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 474 } 475 476 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 477 { 478 set_boot_dev(opaque, boot_device, errp); 479 } 480 481 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 482 { 483 int val, nb, i; 484 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 485 FLOPPY_DRIVE_TYPE_NONE }; 486 487 /* floppy type */ 488 if (floppy) { 489 for (i = 0; i < 2; i++) { 490 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 491 } 492 } 493 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 494 cmos_get_fd_drive_type(fd_type[1]); 495 rtc_set_memory(rtc_state, 0x10, val); 496 497 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 498 nb = 0; 499 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 500 nb++; 501 } 502 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 503 nb++; 504 } 505 switch (nb) { 506 case 0: 507 break; 508 case 1: 509 val |= 0x01; /* 1 drive, ready for boot */ 510 break; 511 case 2: 512 val |= 0x41; /* 2 drives, ready for boot */ 513 break; 514 } 515 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 516 } 517 518 typedef struct pc_cmos_init_late_arg { 519 ISADevice *rtc_state; 520 BusState *idebus[2]; 521 } pc_cmos_init_late_arg; 522 523 typedef struct check_fdc_state { 524 ISADevice *floppy; 525 bool multiple; 526 } CheckFdcState; 527 528 static int check_fdc(Object *obj, void *opaque) 529 { 530 CheckFdcState *state = opaque; 531 Object *fdc; 532 uint32_t iobase; 533 Error *local_err = NULL; 534 535 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 536 if (!fdc) { 537 return 0; 538 } 539 540 iobase = object_property_get_uint(obj, "iobase", &local_err); 541 if (local_err || iobase != 0x3f0) { 542 error_free(local_err); 543 return 0; 544 } 545 546 if (state->floppy) { 547 state->multiple = true; 548 } else { 549 state->floppy = ISA_DEVICE(obj); 550 } 551 return 0; 552 } 553 554 static const char * const fdc_container_path[] = { 555 "/unattached", "/peripheral", "/peripheral-anon" 556 }; 557 558 /* 559 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 560 * and ACPI objects. 561 */ 562 ISADevice *pc_find_fdc0(void) 563 { 564 int i; 565 Object *container; 566 CheckFdcState state = { 0 }; 567 568 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 569 container = container_get(qdev_get_machine(), fdc_container_path[i]); 570 object_child_foreach(container, check_fdc, &state); 571 } 572 573 if (state.multiple) { 574 warn_report("multiple floppy disk controllers with " 575 "iobase=0x3f0 have been found"); 576 error_printf("the one being picked for CMOS setup might not reflect " 577 "your intent"); 578 } 579 580 return state.floppy; 581 } 582 583 static void pc_cmos_init_late(void *opaque) 584 { 585 pc_cmos_init_late_arg *arg = opaque; 586 ISADevice *s = arg->rtc_state; 587 int16_t cylinders; 588 int8_t heads, sectors; 589 int val; 590 int i, trans; 591 592 val = 0; 593 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 594 &cylinders, &heads, §ors) >= 0) { 595 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 596 val |= 0xf0; 597 } 598 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 599 &cylinders, &heads, §ors) >= 0) { 600 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 601 val |= 0x0f; 602 } 603 rtc_set_memory(s, 0x12, val); 604 605 val = 0; 606 for (i = 0; i < 4; i++) { 607 /* NOTE: ide_get_geometry() returns the physical 608 geometry. It is always such that: 1 <= sects <= 63, 1 609 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 610 geometry can be different if a translation is done. */ 611 if (arg->idebus[i / 2] && 612 ide_get_geometry(arg->idebus[i / 2], i % 2, 613 &cylinders, &heads, §ors) >= 0) { 614 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 615 assert((trans & ~3) == 0); 616 val |= trans << (i * 2); 617 } 618 } 619 rtc_set_memory(s, 0x39, val); 620 621 pc_cmos_init_floppy(s, pc_find_fdc0()); 622 623 qemu_unregister_reset(pc_cmos_init_late, opaque); 624 } 625 626 void pc_cmos_init(PCMachineState *pcms, 627 BusState *idebus0, BusState *idebus1, 628 ISADevice *s) 629 { 630 int val; 631 static pc_cmos_init_late_arg arg; 632 X86MachineState *x86ms = X86_MACHINE(pcms); 633 634 /* various important CMOS locations needed by PC/Bochs bios */ 635 636 /* memory size */ 637 /* base memory (first MiB) */ 638 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 639 rtc_set_memory(s, 0x15, val); 640 rtc_set_memory(s, 0x16, val >> 8); 641 /* extended memory (next 64MiB) */ 642 if (x86ms->below_4g_mem_size > 1 * MiB) { 643 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 644 } else { 645 val = 0; 646 } 647 if (val > 65535) 648 val = 65535; 649 rtc_set_memory(s, 0x17, val); 650 rtc_set_memory(s, 0x18, val >> 8); 651 rtc_set_memory(s, 0x30, val); 652 rtc_set_memory(s, 0x31, val >> 8); 653 /* memory between 16MiB and 4GiB */ 654 if (x86ms->below_4g_mem_size > 16 * MiB) { 655 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 656 } else { 657 val = 0; 658 } 659 if (val > 65535) 660 val = 65535; 661 rtc_set_memory(s, 0x34, val); 662 rtc_set_memory(s, 0x35, val >> 8); 663 /* memory above 4GiB */ 664 val = x86ms->above_4g_mem_size / 65536; 665 rtc_set_memory(s, 0x5b, val); 666 rtc_set_memory(s, 0x5c, val >> 8); 667 rtc_set_memory(s, 0x5d, val >> 16); 668 669 object_property_add_link(OBJECT(pcms), "rtc_state", 670 TYPE_ISA_DEVICE, 671 (Object **)&x86ms->rtc, 672 object_property_allow_set_link, 673 OBJ_PROP_LINK_STRONG); 674 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 675 &error_abort); 676 677 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 678 679 val = 0; 680 val |= 0x02; /* FPU is there */ 681 val |= 0x04; /* PS/2 mouse installed */ 682 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 683 684 /* hard drives and FDC */ 685 arg.rtc_state = s; 686 arg.idebus[0] = idebus0; 687 arg.idebus[1] = idebus1; 688 qemu_register_reset(pc_cmos_init_late, &arg); 689 } 690 691 static void handle_a20_line_change(void *opaque, int irq, int level) 692 { 693 X86CPU *cpu = opaque; 694 695 /* XXX: send to all CPUs ? */ 696 /* XXX: add logic to handle multiple A20 line sources */ 697 x86_cpu_set_a20(cpu, level); 698 } 699 700 #define NE2000_NB_MAX 6 701 702 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 703 0x280, 0x380 }; 704 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 705 706 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 707 { 708 static int nb_ne2k = 0; 709 710 if (nb_ne2k == NE2000_NB_MAX) 711 return; 712 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 713 ne2000_irq[nb_ne2k], nd); 714 nb_ne2k++; 715 } 716 717 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 718 { 719 X86CPU *cpu = opaque; 720 721 if (level) { 722 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 723 } 724 } 725 726 static 727 void pc_machine_done(Notifier *notifier, void *data) 728 { 729 PCMachineState *pcms = container_of(notifier, 730 PCMachineState, machine_done); 731 X86MachineState *x86ms = X86_MACHINE(pcms); 732 733 /* set the number of CPUs */ 734 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 735 736 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 737 738 acpi_setup(); 739 if (x86ms->fw_cfg) { 740 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 741 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 742 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 743 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 744 } 745 746 747 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 748 !kvm_irqchip_in_kernel()) { 749 error_report("current -smp configuration requires kernel " 750 "irqchip support."); 751 exit(EXIT_FAILURE); 752 } 753 } 754 755 void pc_guest_info_init(PCMachineState *pcms) 756 { 757 X86MachineState *x86ms = X86_MACHINE(pcms); 758 759 x86ms->apic_xrupt_override = true; 760 pcms->machine_done.notify = pc_machine_done; 761 qemu_add_machine_init_done_notifier(&pcms->machine_done); 762 } 763 764 /* setup pci memory address space mapping into system address space */ 765 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 766 MemoryRegion *pci_address_space) 767 { 768 /* Set to lower priority than RAM */ 769 memory_region_add_subregion_overlap(system_memory, 0x0, 770 pci_address_space, -1); 771 } 772 773 void xen_load_linux(PCMachineState *pcms) 774 { 775 int i; 776 FWCfgState *fw_cfg; 777 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 778 X86MachineState *x86ms = X86_MACHINE(pcms); 779 780 assert(MACHINE(pcms)->kernel_filename != NULL); 781 782 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 783 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 784 rom_set_fw(fw_cfg); 785 786 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 787 pcmc->pvh_enabled); 788 for (i = 0; i < nb_option_roms; i++) { 789 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 790 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 791 !strcmp(option_rom[i].name, "pvh.bin") || 792 !strcmp(option_rom[i].name, "multiboot.bin") || 793 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 794 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 795 } 796 x86ms->fw_cfg = fw_cfg; 797 } 798 799 #define PC_ROM_MIN_VGA 0xc0000 800 #define PC_ROM_MIN_OPTION 0xc8000 801 #define PC_ROM_MAX 0xe0000 802 #define PC_ROM_ALIGN 0x800 803 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 804 805 void pc_memory_init(PCMachineState *pcms, 806 MemoryRegion *system_memory, 807 MemoryRegion *rom_memory, 808 MemoryRegion **ram_memory) 809 { 810 int linux_boot, i; 811 MemoryRegion *option_rom_mr; 812 MemoryRegion *ram_below_4g, *ram_above_4g; 813 FWCfgState *fw_cfg; 814 MachineState *machine = MACHINE(pcms); 815 MachineClass *mc = MACHINE_GET_CLASS(machine); 816 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 817 X86MachineState *x86ms = X86_MACHINE(pcms); 818 819 assert(machine->ram_size == x86ms->below_4g_mem_size + 820 x86ms->above_4g_mem_size); 821 822 linux_boot = (machine->kernel_filename != NULL); 823 824 /* 825 * Split single memory region and use aliases to address portions of it, 826 * done for backwards compatibility with older qemus. 827 */ 828 *ram_memory = machine->ram; 829 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 830 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 831 0, x86ms->below_4g_mem_size); 832 memory_region_add_subregion(system_memory, 0, ram_below_4g); 833 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 834 if (x86ms->above_4g_mem_size > 0) { 835 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 836 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 837 machine->ram, 838 x86ms->below_4g_mem_size, 839 x86ms->above_4g_mem_size); 840 memory_region_add_subregion(system_memory, 0x100000000ULL, 841 ram_above_4g); 842 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 843 } 844 845 if (pcms->sgx_epc.size != 0) { 846 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 847 } 848 849 if (!pcmc->has_reserved_memory && 850 (machine->ram_slots || 851 (machine->maxram_size > machine->ram_size))) { 852 853 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 854 mc->name); 855 exit(EXIT_FAILURE); 856 } 857 858 /* always allocate the device memory information */ 859 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 860 861 /* initialize device memory address space */ 862 if (pcmc->has_reserved_memory && 863 (machine->ram_size < machine->maxram_size)) { 864 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 865 866 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 867 error_report("unsupported amount of memory slots: %"PRIu64, 868 machine->ram_slots); 869 exit(EXIT_FAILURE); 870 } 871 872 if (QEMU_ALIGN_UP(machine->maxram_size, 873 TARGET_PAGE_SIZE) != machine->maxram_size) { 874 error_report("maximum memory size must by aligned to multiple of " 875 "%d bytes", TARGET_PAGE_SIZE); 876 exit(EXIT_FAILURE); 877 } 878 879 if (pcms->sgx_epc.size != 0) { 880 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 881 } else { 882 machine->device_memory->base = 883 0x100000000ULL + x86ms->above_4g_mem_size; 884 } 885 886 machine->device_memory->base = 887 ROUND_UP(machine->device_memory->base, 1 * GiB); 888 889 if (pcmc->enforce_aligned_dimm) { 890 /* size device region assuming 1G page max alignment per slot */ 891 device_mem_size += (1 * GiB) * machine->ram_slots; 892 } 893 894 if ((machine->device_memory->base + device_mem_size) < 895 device_mem_size) { 896 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 897 machine->maxram_size); 898 exit(EXIT_FAILURE); 899 } 900 901 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 902 "device-memory", device_mem_size); 903 memory_region_add_subregion(system_memory, machine->device_memory->base, 904 &machine->device_memory->mr); 905 } 906 907 /* Initialize PC system firmware */ 908 pc_system_firmware_init(pcms, rom_memory); 909 910 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 911 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 912 &error_fatal); 913 if (pcmc->pci_enabled) { 914 memory_region_set_readonly(option_rom_mr, true); 915 } 916 memory_region_add_subregion_overlap(rom_memory, 917 PC_ROM_MIN_VGA, 918 option_rom_mr, 919 1); 920 921 fw_cfg = fw_cfg_arch_create(machine, 922 x86ms->boot_cpus, x86ms->apic_id_limit); 923 924 rom_set_fw(fw_cfg); 925 926 if (pcmc->has_reserved_memory && machine->device_memory->base) { 927 uint64_t *val = g_malloc(sizeof(*val)); 928 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 929 uint64_t res_mem_end = machine->device_memory->base; 930 931 if (!pcmc->broken_reserved_end) { 932 res_mem_end += memory_region_size(&machine->device_memory->mr); 933 } 934 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 935 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 936 } 937 938 if (linux_boot) { 939 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 940 pcmc->pvh_enabled); 941 } 942 943 for (i = 0; i < nb_option_roms; i++) { 944 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 945 } 946 x86ms->fw_cfg = fw_cfg; 947 948 /* Init default IOAPIC address space */ 949 x86ms->ioapic_as = &address_space_memory; 950 951 /* Init ACPI memory hotplug IO base address */ 952 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 953 } 954 955 /* 956 * The 64bit pci hole starts after "above 4G RAM" and 957 * potentially the space reserved for memory hotplug. 958 */ 959 uint64_t pc_pci_hole64_start(void) 960 { 961 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 962 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 963 MachineState *ms = MACHINE(pcms); 964 X86MachineState *x86ms = X86_MACHINE(pcms); 965 uint64_t hole64_start = 0; 966 967 if (pcmc->has_reserved_memory && ms->device_memory->base) { 968 hole64_start = ms->device_memory->base; 969 if (!pcmc->broken_reserved_end) { 970 hole64_start += memory_region_size(&ms->device_memory->mr); 971 } 972 } else if (pcms->sgx_epc.size != 0) { 973 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 974 } else { 975 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 976 } 977 978 return ROUND_UP(hole64_start, 1 * GiB); 979 } 980 981 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 982 { 983 DeviceState *dev = NULL; 984 985 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 986 if (pci_bus) { 987 PCIDevice *pcidev = pci_vga_init(pci_bus); 988 dev = pcidev ? &pcidev->qdev : NULL; 989 } else if (isa_bus) { 990 ISADevice *isadev = isa_vga_init(isa_bus); 991 dev = isadev ? DEVICE(isadev) : NULL; 992 } 993 rom_reset_order_override(); 994 return dev; 995 } 996 997 static const MemoryRegionOps ioport80_io_ops = { 998 .write = ioport80_write, 999 .read = ioport80_read, 1000 .endianness = DEVICE_NATIVE_ENDIAN, 1001 .impl = { 1002 .min_access_size = 1, 1003 .max_access_size = 1, 1004 }, 1005 }; 1006 1007 static const MemoryRegionOps ioportF0_io_ops = { 1008 .write = ioportF0_write, 1009 .read = ioportF0_read, 1010 .endianness = DEVICE_NATIVE_ENDIAN, 1011 .impl = { 1012 .min_access_size = 1, 1013 .max_access_size = 1, 1014 }, 1015 }; 1016 1017 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1018 { 1019 int i; 1020 DriveInfo *fd[MAX_FD]; 1021 qemu_irq *a20_line; 1022 ISADevice *fdc, *i8042, *port92, *vmmouse; 1023 1024 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1025 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1026 1027 for (i = 0; i < MAX_FD; i++) { 1028 fd[i] = drive_get(IF_FLOPPY, 0, i); 1029 create_fdctrl |= !!fd[i]; 1030 } 1031 if (create_fdctrl) { 1032 fdc = isa_new(TYPE_ISA_FDC); 1033 if (fdc) { 1034 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1035 isa_fdc_init_drives(fdc, fd); 1036 } 1037 } 1038 1039 i8042 = isa_create_simple(isa_bus, "i8042"); 1040 if (!no_vmport) { 1041 isa_create_simple(isa_bus, TYPE_VMPORT); 1042 vmmouse = isa_try_new("vmmouse"); 1043 } else { 1044 vmmouse = NULL; 1045 } 1046 if (vmmouse) { 1047 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1048 &error_abort); 1049 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1050 } 1051 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1052 1053 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1054 i8042_setup_a20_line(i8042, a20_line[0]); 1055 qdev_connect_gpio_out_named(DEVICE(port92), 1056 PORT92_A20_LINE, 0, a20_line[1]); 1057 g_free(a20_line); 1058 } 1059 1060 void pc_basic_device_init(struct PCMachineState *pcms, 1061 ISABus *isa_bus, qemu_irq *gsi, 1062 ISADevice **rtc_state, 1063 bool create_fdctrl, 1064 uint32_t hpet_irqs) 1065 { 1066 int i; 1067 DeviceState *hpet = NULL; 1068 int pit_isa_irq = 0; 1069 qemu_irq pit_alt_irq = NULL; 1070 qemu_irq rtc_irq = NULL; 1071 ISADevice *pit = NULL; 1072 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1073 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1074 1075 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1076 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1077 1078 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1079 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1080 1081 /* 1082 * Check if an HPET shall be created. 1083 * 1084 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1085 * when the HPET wants to take over. Thus we have to disable the latter. 1086 */ 1087 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1088 kvm_has_pit_state2())) { 1089 hpet = qdev_try_new(TYPE_HPET); 1090 if (!hpet) { 1091 error_report("couldn't create HPET device"); 1092 exit(1); 1093 } 1094 /* 1095 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1096 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1097 * IRQ2. 1098 */ 1099 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1100 HPET_INTCAP, NULL); 1101 if (!compat) { 1102 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1103 } 1104 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1105 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1106 1107 for (i = 0; i < GSI_NUM_PINS; i++) { 1108 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1109 } 1110 pit_isa_irq = -1; 1111 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1112 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1113 } 1114 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1115 1116 qemu_register_boot_set(pc_boot_set, *rtc_state); 1117 1118 if (!xen_enabled() && pcms->pit_enabled) { 1119 if (kvm_pit_in_kernel()) { 1120 pit = kvm_pit_init(isa_bus, 0x40); 1121 } else { 1122 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1123 } 1124 if (hpet) { 1125 /* connect PIT to output control line of the HPET */ 1126 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1127 } 1128 pcspk_init(pcms->pcspk, isa_bus, pit); 1129 } 1130 1131 i8257_dma_init(isa_bus, 0); 1132 1133 /* Super I/O */ 1134 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1135 } 1136 1137 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1138 { 1139 int i; 1140 1141 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1142 for (i = 0; i < nb_nics; i++) { 1143 NICInfo *nd = &nd_table[i]; 1144 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1145 1146 if (g_str_equal(model, "ne2k_isa")) { 1147 pc_init_ne2k_isa(isa_bus, nd); 1148 } else { 1149 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1150 } 1151 } 1152 rom_reset_order_override(); 1153 } 1154 1155 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1156 { 1157 qemu_irq *i8259; 1158 1159 if (kvm_pic_in_kernel()) { 1160 i8259 = kvm_i8259_init(isa_bus); 1161 } else if (xen_enabled()) { 1162 i8259 = xen_interrupt_controller_init(); 1163 } else { 1164 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1165 } 1166 1167 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1168 i8259_irqs[i] = i8259[i]; 1169 } 1170 1171 g_free(i8259); 1172 } 1173 1174 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1175 Error **errp) 1176 { 1177 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1178 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1179 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1180 const MachineState *ms = MACHINE(hotplug_dev); 1181 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1182 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1183 Error *local_err = NULL; 1184 1185 /* 1186 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1187 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1188 * addition to cover this case. 1189 */ 1190 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1191 error_setg(errp, 1192 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1193 return; 1194 } 1195 1196 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1197 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1198 return; 1199 } 1200 1201 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1202 if (local_err) { 1203 error_propagate(errp, local_err); 1204 return; 1205 } 1206 1207 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1208 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1209 } 1210 1211 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1212 DeviceState *dev, Error **errp) 1213 { 1214 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1215 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1216 MachineState *ms = MACHINE(hotplug_dev); 1217 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1218 1219 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1220 1221 if (is_nvdimm) { 1222 nvdimm_plug(ms->nvdimms_state); 1223 } 1224 1225 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1226 } 1227 1228 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1229 DeviceState *dev, Error **errp) 1230 { 1231 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1232 1233 /* 1234 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1235 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1236 * addition to cover this case. 1237 */ 1238 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1239 error_setg(errp, 1240 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1241 return; 1242 } 1243 1244 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1245 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1246 return; 1247 } 1248 1249 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1250 errp); 1251 } 1252 1253 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1254 DeviceState *dev, Error **errp) 1255 { 1256 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1257 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1258 Error *local_err = NULL; 1259 1260 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1261 if (local_err) { 1262 goto out; 1263 } 1264 1265 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1266 qdev_unrealize(dev); 1267 out: 1268 error_propagate(errp, local_err); 1269 } 1270 1271 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1272 DeviceState *dev, Error **errp) 1273 { 1274 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1275 Error *local_err = NULL; 1276 1277 if (!hotplug_dev2 && dev->hotplugged) { 1278 /* 1279 * Without a bus hotplug handler, we cannot control the plug/unplug 1280 * order. We should never reach this point when hotplugging on x86, 1281 * however, better add a safety net. 1282 */ 1283 error_setg(errp, "hotplug of virtio based memory devices not supported" 1284 " on this bus."); 1285 return; 1286 } 1287 /* 1288 * First, see if we can plug this memory device at all. If that 1289 * succeeds, branch of to the actual hotplug handler. 1290 */ 1291 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1292 &local_err); 1293 if (!local_err && hotplug_dev2) { 1294 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1295 } 1296 error_propagate(errp, local_err); 1297 } 1298 1299 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1300 DeviceState *dev, Error **errp) 1301 { 1302 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1303 Error *local_err = NULL; 1304 1305 /* 1306 * Plug the memory device first and then branch off to the actual 1307 * hotplug handler. If that one fails, we can easily undo the memory 1308 * device bits. 1309 */ 1310 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1311 if (hotplug_dev2) { 1312 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1313 if (local_err) { 1314 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1315 } 1316 } 1317 error_propagate(errp, local_err); 1318 } 1319 1320 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1321 DeviceState *dev, Error **errp) 1322 { 1323 /* We don't support hot unplug of virtio based memory devices */ 1324 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1325 } 1326 1327 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1328 DeviceState *dev, Error **errp) 1329 { 1330 /* We don't support hot unplug of virtio based memory devices */ 1331 } 1332 1333 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1334 DeviceState *dev, Error **errp) 1335 { 1336 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1337 pc_memory_pre_plug(hotplug_dev, dev, errp); 1338 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1339 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1340 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1341 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1342 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1343 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1344 /* Declare the APIC range as the reserved MSI region */ 1345 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1346 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1347 1348 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1349 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1350 resv_prop_str, errp); 1351 g_free(resv_prop_str); 1352 } 1353 1354 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1355 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1356 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1357 1358 if (pcms->iommu) { 1359 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1360 "for x86 yet."); 1361 return; 1362 } 1363 pcms->iommu = dev; 1364 } 1365 } 1366 1367 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1371 pc_memory_plug(hotplug_dev, dev, errp); 1372 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1373 x86_cpu_plug(hotplug_dev, dev, errp); 1374 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1375 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1376 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1377 } 1378 } 1379 1380 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1381 DeviceState *dev, Error **errp) 1382 { 1383 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1384 pc_memory_unplug_request(hotplug_dev, dev, errp); 1385 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1386 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1388 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1389 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1390 } else { 1391 error_setg(errp, "acpi: device unplug request for not supported device" 1392 " type: %s", object_get_typename(OBJECT(dev))); 1393 } 1394 } 1395 1396 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1397 DeviceState *dev, Error **errp) 1398 { 1399 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1400 pc_memory_unplug(hotplug_dev, dev, errp); 1401 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1402 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1403 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1404 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1405 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1406 } else { 1407 error_setg(errp, "acpi: device unplug for not supported device" 1408 " type: %s", object_get_typename(OBJECT(dev))); 1409 } 1410 } 1411 1412 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1413 DeviceState *dev) 1414 { 1415 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1416 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1417 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1418 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1419 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1420 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1421 return HOTPLUG_HANDLER(machine); 1422 } 1423 1424 return NULL; 1425 } 1426 1427 static void 1428 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1429 const char *name, void *opaque, 1430 Error **errp) 1431 { 1432 MachineState *ms = MACHINE(obj); 1433 int64_t value = 0; 1434 1435 if (ms->device_memory) { 1436 value = memory_region_size(&ms->device_memory->mr); 1437 } 1438 1439 visit_type_int(v, name, &value, errp); 1440 } 1441 1442 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1443 void *opaque, Error **errp) 1444 { 1445 PCMachineState *pcms = PC_MACHINE(obj); 1446 OnOffAuto vmport = pcms->vmport; 1447 1448 visit_type_OnOffAuto(v, name, &vmport, errp); 1449 } 1450 1451 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1452 void *opaque, Error **errp) 1453 { 1454 PCMachineState *pcms = PC_MACHINE(obj); 1455 1456 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1457 } 1458 1459 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1460 { 1461 PCMachineState *pcms = PC_MACHINE(obj); 1462 1463 return pcms->smbus_enabled; 1464 } 1465 1466 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1467 { 1468 PCMachineState *pcms = PC_MACHINE(obj); 1469 1470 pcms->smbus_enabled = value; 1471 } 1472 1473 static bool pc_machine_get_sata(Object *obj, Error **errp) 1474 { 1475 PCMachineState *pcms = PC_MACHINE(obj); 1476 1477 return pcms->sata_enabled; 1478 } 1479 1480 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1481 { 1482 PCMachineState *pcms = PC_MACHINE(obj); 1483 1484 pcms->sata_enabled = value; 1485 } 1486 1487 static bool pc_machine_get_pit(Object *obj, Error **errp) 1488 { 1489 PCMachineState *pcms = PC_MACHINE(obj); 1490 1491 return pcms->pit_enabled; 1492 } 1493 1494 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1495 { 1496 PCMachineState *pcms = PC_MACHINE(obj); 1497 1498 pcms->pit_enabled = value; 1499 } 1500 1501 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1502 { 1503 PCMachineState *pcms = PC_MACHINE(obj); 1504 1505 return pcms->hpet_enabled; 1506 } 1507 1508 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1509 { 1510 PCMachineState *pcms = PC_MACHINE(obj); 1511 1512 pcms->hpet_enabled = value; 1513 } 1514 1515 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 return pcms->default_bus_bypass_iommu; 1520 } 1521 1522 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1523 Error **errp) 1524 { 1525 PCMachineState *pcms = PC_MACHINE(obj); 1526 1527 pcms->default_bus_bypass_iommu = value; 1528 } 1529 1530 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1531 void *opaque, Error **errp) 1532 { 1533 PCMachineState *pcms = PC_MACHINE(obj); 1534 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1535 1536 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1537 } 1538 1539 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1540 void *opaque, Error **errp) 1541 { 1542 PCMachineState *pcms = PC_MACHINE(obj); 1543 1544 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1545 } 1546 1547 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1548 const char *name, void *opaque, 1549 Error **errp) 1550 { 1551 PCMachineState *pcms = PC_MACHINE(obj); 1552 uint64_t value = pcms->max_ram_below_4g; 1553 1554 visit_type_size(v, name, &value, errp); 1555 } 1556 1557 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1558 const char *name, void *opaque, 1559 Error **errp) 1560 { 1561 PCMachineState *pcms = PC_MACHINE(obj); 1562 uint64_t value; 1563 1564 if (!visit_type_size(v, name, &value, errp)) { 1565 return; 1566 } 1567 if (value > 4 * GiB) { 1568 error_setg(errp, 1569 "Machine option 'max-ram-below-4g=%"PRIu64 1570 "' expects size less than or equal to 4G", value); 1571 return; 1572 } 1573 1574 if (value < 1 * MiB) { 1575 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1576 "BIOS may not work with less than 1MiB", value); 1577 } 1578 1579 pcms->max_ram_below_4g = value; 1580 } 1581 1582 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1583 const char *name, void *opaque, 1584 Error **errp) 1585 { 1586 PCMachineState *pcms = PC_MACHINE(obj); 1587 uint64_t value = pcms->max_fw_size; 1588 1589 visit_type_size(v, name, &value, errp); 1590 } 1591 1592 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1593 const char *name, void *opaque, 1594 Error **errp) 1595 { 1596 PCMachineState *pcms = PC_MACHINE(obj); 1597 Error *error = NULL; 1598 uint64_t value; 1599 1600 visit_type_size(v, name, &value, &error); 1601 if (error) { 1602 error_propagate(errp, error); 1603 return; 1604 } 1605 1606 /* 1607 * We don't have a theoretically justifiable exact lower bound on the base 1608 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1609 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1610 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1611 * size. 1612 */ 1613 if (value > 16 * MiB) { 1614 error_setg(errp, 1615 "User specified max allowed firmware size %" PRIu64 " is " 1616 "greater than 16MiB. If combined firwmare size exceeds " 1617 "16MiB the system may not boot, or experience intermittent" 1618 "stability issues.", 1619 value); 1620 return; 1621 } 1622 1623 pcms->max_fw_size = value; 1624 } 1625 1626 1627 static void pc_machine_initfn(Object *obj) 1628 { 1629 PCMachineState *pcms = PC_MACHINE(obj); 1630 1631 #ifdef CONFIG_VMPORT 1632 pcms->vmport = ON_OFF_AUTO_AUTO; 1633 #else 1634 pcms->vmport = ON_OFF_AUTO_OFF; 1635 #endif /* CONFIG_VMPORT */ 1636 pcms->max_ram_below_4g = 0; /* use default */ 1637 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1638 1639 /* acpi build is enabled by default if machine supports it */ 1640 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1641 pcms->smbus_enabled = true; 1642 pcms->sata_enabled = true; 1643 pcms->pit_enabled = true; 1644 pcms->max_fw_size = 8 * MiB; 1645 #ifdef CONFIG_HPET 1646 pcms->hpet_enabled = true; 1647 #endif 1648 pcms->default_bus_bypass_iommu = false; 1649 1650 pc_system_flash_create(pcms); 1651 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1652 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1653 OBJECT(pcms->pcspk), "audiodev"); 1654 } 1655 1656 static void pc_machine_reset(MachineState *machine) 1657 { 1658 CPUState *cs; 1659 X86CPU *cpu; 1660 1661 qemu_devices_reset(); 1662 1663 /* Reset APIC after devices have been reset to cancel 1664 * any changes that qemu_devices_reset() might have done. 1665 */ 1666 CPU_FOREACH(cs) { 1667 cpu = X86_CPU(cs); 1668 1669 if (cpu->apic_state) { 1670 device_legacy_reset(cpu->apic_state); 1671 } 1672 } 1673 } 1674 1675 static void pc_machine_wakeup(MachineState *machine) 1676 { 1677 cpu_synchronize_all_states(); 1678 pc_machine_reset(machine); 1679 cpu_synchronize_all_post_reset(); 1680 } 1681 1682 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1683 { 1684 X86IOMMUState *iommu = x86_iommu_get_default(); 1685 IntelIOMMUState *intel_iommu; 1686 1687 if (iommu && 1688 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1689 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1690 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1691 if (!intel_iommu->caching_mode) { 1692 error_setg(errp, "Device assignment is not allowed without " 1693 "enabling caching-mode=on for Intel IOMMU."); 1694 return false; 1695 } 1696 } 1697 1698 return true; 1699 } 1700 1701 static void pc_machine_class_init(ObjectClass *oc, void *data) 1702 { 1703 MachineClass *mc = MACHINE_CLASS(oc); 1704 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1705 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1706 1707 pcmc->pci_enabled = true; 1708 pcmc->has_acpi_build = true; 1709 pcmc->rsdp_in_ram = true; 1710 pcmc->smbios_defaults = true; 1711 pcmc->smbios_uuid_encoded = true; 1712 pcmc->gigabyte_align = true; 1713 pcmc->has_reserved_memory = true; 1714 pcmc->kvmclock_enabled = true; 1715 pcmc->enforce_aligned_dimm = true; 1716 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1717 * to be used at the moment, 32K should be enough for a while. */ 1718 pcmc->acpi_data_size = 0x20000 + 0x8000; 1719 pcmc->pvh_enabled = true; 1720 pcmc->kvmclock_create_always = true; 1721 assert(!mc->get_hotplug_handler); 1722 mc->get_hotplug_handler = pc_get_hotplug_handler; 1723 mc->hotplug_allowed = pc_hotplug_allowed; 1724 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1725 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1726 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1727 mc->auto_enable_numa_with_memhp = true; 1728 mc->auto_enable_numa_with_memdev = true; 1729 mc->has_hotpluggable_cpus = true; 1730 mc->default_boot_order = "cad"; 1731 mc->block_default_type = IF_IDE; 1732 mc->max_cpus = 255; 1733 mc->reset = pc_machine_reset; 1734 mc->wakeup = pc_machine_wakeup; 1735 hc->pre_plug = pc_machine_device_pre_plug_cb; 1736 hc->plug = pc_machine_device_plug_cb; 1737 hc->unplug_request = pc_machine_device_unplug_request_cb; 1738 hc->unplug = pc_machine_device_unplug_cb; 1739 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1740 mc->nvdimm_supported = true; 1741 mc->smp_props.dies_supported = true; 1742 mc->default_ram_id = "pc.ram"; 1743 1744 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1745 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1746 NULL, NULL); 1747 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1748 "Maximum ram below the 4G boundary (32bit boundary)"); 1749 1750 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1751 pc_machine_get_device_memory_region_size, NULL, 1752 NULL, NULL); 1753 1754 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1755 pc_machine_get_vmport, pc_machine_set_vmport, 1756 NULL, NULL); 1757 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1758 "Enable vmport (pc & q35)"); 1759 1760 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1761 pc_machine_get_smbus, pc_machine_set_smbus); 1762 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1763 "Enable/disable system management bus"); 1764 1765 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1766 pc_machine_get_sata, pc_machine_set_sata); 1767 object_class_property_set_description(oc, PC_MACHINE_SATA, 1768 "Enable/disable Serial ATA bus"); 1769 1770 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1771 pc_machine_get_pit, pc_machine_set_pit); 1772 object_class_property_set_description(oc, PC_MACHINE_PIT, 1773 "Enable/disable Intel 8254 programmable interval timer emulation"); 1774 1775 object_class_property_add_bool(oc, "hpet", 1776 pc_machine_get_hpet, pc_machine_set_hpet); 1777 object_class_property_set_description(oc, "hpet", 1778 "Enable/disable high precision event timer emulation"); 1779 1780 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1781 pc_machine_get_default_bus_bypass_iommu, 1782 pc_machine_set_default_bus_bypass_iommu); 1783 1784 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1785 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1786 NULL, NULL); 1787 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1788 "Maximum combined firmware size"); 1789 1790 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1791 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1792 NULL, NULL); 1793 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1794 "SMBIOS Entry Point type [32, 64]"); 1795 } 1796 1797 static const TypeInfo pc_machine_info = { 1798 .name = TYPE_PC_MACHINE, 1799 .parent = TYPE_X86_MACHINE, 1800 .abstract = true, 1801 .instance_size = sizeof(PCMachineState), 1802 .instance_init = pc_machine_initfn, 1803 .class_size = sizeof(PCMachineClass), 1804 .class_init = pc_machine_class_init, 1805 .interfaces = (InterfaceInfo[]) { 1806 { TYPE_HOTPLUG_HANDLER }, 1807 { } 1808 }, 1809 }; 1810 1811 static void pc_machine_register_types(void) 1812 { 1813 type_register_static(&pc_machine_info); 1814 } 1815 1816 type_init(pc_machine_register_types) 1817