1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/qapi-visit-machine.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-iommu.h" 88 #include "hw/virtio/virtio-pmem-pci.h" 89 #include "hw/virtio/virtio-mem-pci.h" 90 #include "hw/mem/memory-device.h" 91 #include "sysemu/replay.h" 92 #include "qapi/qmp/qerror.h" 93 #include "e820_memory_layout.h" 94 #include "fw_cfg.h" 95 #include "trace.h" 96 #include CONFIG_DEVICES 97 98 GlobalProperty pc_compat_7_0[] = {}; 99 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 100 101 GlobalProperty pc_compat_6_2[] = { 102 { "virtio-mem", "unplugged-inaccessible", "off" }, 103 }; 104 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 105 106 GlobalProperty pc_compat_6_1[] = { 107 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 108 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 109 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 110 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 111 }; 112 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 113 114 GlobalProperty pc_compat_6_0[] = { 115 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 116 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 117 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 118 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 119 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 120 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 121 }; 122 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 123 124 GlobalProperty pc_compat_5_2[] = { 125 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 126 }; 127 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 128 129 GlobalProperty pc_compat_5_1[] = { 130 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 131 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 132 }; 133 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 134 135 GlobalProperty pc_compat_5_0[] = { 136 }; 137 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 138 139 GlobalProperty pc_compat_4_2[] = { 140 { "mch", "smbase-smram", "off" }, 141 }; 142 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 143 144 GlobalProperty pc_compat_4_1[] = {}; 145 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 146 147 GlobalProperty pc_compat_4_0[] = {}; 148 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 149 150 GlobalProperty pc_compat_3_1[] = { 151 { "intel-iommu", "dma-drain", "off" }, 152 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 153 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 154 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 156 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 157 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 159 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 164 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 165 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 171 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 172 }; 173 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 174 175 GlobalProperty pc_compat_3_0[] = { 176 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 177 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 178 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 179 }; 180 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 181 182 GlobalProperty pc_compat_2_12[] = { 183 { TYPE_X86_CPU, "legacy-cache", "on" }, 184 { TYPE_X86_CPU, "topoext", "off" }, 185 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 186 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 187 }; 188 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 189 190 GlobalProperty pc_compat_2_11[] = { 191 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 192 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 193 }; 194 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 195 196 GlobalProperty pc_compat_2_10[] = { 197 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 198 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 199 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 200 }; 201 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 202 203 GlobalProperty pc_compat_2_9[] = { 204 { "mch", "extended-tseg-mbytes", "0" }, 205 }; 206 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 207 208 GlobalProperty pc_compat_2_8[] = { 209 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 210 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 211 { "ICH9-LPC", "x-smi-broadcast", "off" }, 212 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 213 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 214 }; 215 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 216 217 GlobalProperty pc_compat_2_7[] = { 218 { TYPE_X86_CPU, "l3-cache", "off" }, 219 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 220 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 221 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 223 { "isa-pcspk", "migrate", "off" }, 224 }; 225 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 226 227 GlobalProperty pc_compat_2_6[] = { 228 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 229 { "vmxnet3", "romfile", "" }, 230 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 231 { "apic-common", "legacy-instance-id", "on", } 232 }; 233 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 234 235 GlobalProperty pc_compat_2_5[] = {}; 236 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 237 238 GlobalProperty pc_compat_2_4[] = { 239 PC_CPU_MODEL_IDS("2.4.0") 240 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 241 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 242 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 245 { TYPE_X86_CPU, "check", "off" }, 246 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 247 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 248 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 249 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 250 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 251 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 252 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 254 }; 255 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 256 257 GlobalProperty pc_compat_2_3[] = { 258 PC_CPU_MODEL_IDS("2.3.0") 259 { TYPE_X86_CPU, "arat", "off" }, 260 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 261 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 262 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 263 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 265 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 266 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 268 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 269 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 279 }; 280 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 281 282 GlobalProperty pc_compat_2_2[] = { 283 PC_CPU_MODEL_IDS("2.2.0") 284 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 285 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 286 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 299 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 300 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 }; 303 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 304 305 GlobalProperty pc_compat_2_1[] = { 306 PC_CPU_MODEL_IDS("2.1.0") 307 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 308 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 309 }; 310 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 311 312 GlobalProperty pc_compat_2_0[] = { 313 PC_CPU_MODEL_IDS("2.0.0") 314 { "virtio-scsi-pci", "any_layout", "off" }, 315 { "PIIX4_PM", "memory-hotplug-support", "off" }, 316 { "apic", "version", "0x11" }, 317 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 318 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 319 { "pci-serial", "prog_if", "0" }, 320 { "pci-serial-2x", "prog_if", "0" }, 321 { "pci-serial-4x", "prog_if", "0" }, 322 { "virtio-net-pci", "guest_announce", "off" }, 323 { "ICH9-LPC", "memory-hotplug-support", "off" }, 324 }; 325 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 326 327 GlobalProperty pc_compat_1_7[] = { 328 PC_CPU_MODEL_IDS("1.7.0") 329 { TYPE_USB_DEVICE, "msos-desc", "no" }, 330 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 331 { "hpet", HPET_INTCAP, "4" }, 332 }; 333 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 334 335 GlobalProperty pc_compat_1_6[] = { 336 PC_CPU_MODEL_IDS("1.6.0") 337 { "e1000", "mitigation", "off" }, 338 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 339 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 340 { "i440FX-pcihost", "short_root_bus", "1" }, 341 { "q35-pcihost", "short_root_bus", "1" }, 342 }; 343 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 344 345 GlobalProperty pc_compat_1_5[] = { 346 PC_CPU_MODEL_IDS("1.5.0") 347 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 348 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 349 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 350 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 351 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 352 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 353 { "virtio-net-pci", "any_layout", "off" }, 354 { TYPE_X86_CPU, "pmu", "on" }, 355 { "i440FX-pcihost", "short_root_bus", "0" }, 356 { "q35-pcihost", "short_root_bus", "0" }, 357 }; 358 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 359 360 GlobalProperty pc_compat_1_4[] = { 361 PC_CPU_MODEL_IDS("1.4.0") 362 { "scsi-hd", "discard_granularity", "0" }, 363 { "scsi-cd", "discard_granularity", "0" }, 364 { "ide-hd", "discard_granularity", "0" }, 365 { "ide-cd", "discard_granularity", "0" }, 366 { "virtio-blk-pci", "discard_granularity", "0" }, 367 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 368 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 369 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 370 { "e1000", "romfile", "pxe-e1000.rom" }, 371 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 372 { "pcnet", "romfile", "pxe-pcnet.rom" }, 373 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 374 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 375 { "486-" TYPE_X86_CPU, "model", "0" }, 376 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 377 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 378 }; 379 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 380 381 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 382 { 383 GSIState *s; 384 385 s = g_new0(GSIState, 1); 386 if (kvm_ioapic_in_kernel()) { 387 kvm_pc_setup_irq_routing(pci_enabled); 388 } 389 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 390 391 return s; 392 } 393 394 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 395 unsigned size) 396 { 397 } 398 399 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 400 { 401 return 0xffffffffffffffffULL; 402 } 403 404 /* MSDOS compatibility mode FPU exception support */ 405 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 406 unsigned size) 407 { 408 if (tcg_enabled()) { 409 cpu_set_ignne(); 410 } 411 } 412 413 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 414 { 415 return 0xffffffffffffffffULL; 416 } 417 418 /* PC cmos mappings */ 419 420 #define REG_EQUIPMENT_BYTE 0x14 421 422 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 423 int16_t cylinders, int8_t heads, int8_t sectors) 424 { 425 rtc_set_memory(s, type_ofs, 47); 426 rtc_set_memory(s, info_ofs, cylinders); 427 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 428 rtc_set_memory(s, info_ofs + 2, heads); 429 rtc_set_memory(s, info_ofs + 3, 0xff); 430 rtc_set_memory(s, info_ofs + 4, 0xff); 431 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 432 rtc_set_memory(s, info_ofs + 6, cylinders); 433 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 434 rtc_set_memory(s, info_ofs + 8, sectors); 435 } 436 437 /* convert boot_device letter to something recognizable by the bios */ 438 static int boot_device2nibble(char boot_device) 439 { 440 switch(boot_device) { 441 case 'a': 442 case 'b': 443 return 0x01; /* floppy boot */ 444 case 'c': 445 return 0x02; /* hard drive boot */ 446 case 'd': 447 return 0x03; /* CD-ROM boot */ 448 case 'n': 449 return 0x04; /* Network boot */ 450 } 451 return 0; 452 } 453 454 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 455 { 456 #define PC_MAX_BOOT_DEVICES 3 457 int nbds, bds[3] = { 0, }; 458 int i; 459 460 nbds = strlen(boot_device); 461 if (nbds > PC_MAX_BOOT_DEVICES) { 462 error_setg(errp, "Too many boot devices for PC"); 463 return; 464 } 465 for (i = 0; i < nbds; i++) { 466 bds[i] = boot_device2nibble(boot_device[i]); 467 if (bds[i] == 0) { 468 error_setg(errp, "Invalid boot device for PC: '%c'", 469 boot_device[i]); 470 return; 471 } 472 } 473 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 474 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 475 } 476 477 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 478 { 479 set_boot_dev(opaque, boot_device, errp); 480 } 481 482 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 483 { 484 int val, nb, i; 485 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 486 FLOPPY_DRIVE_TYPE_NONE }; 487 488 /* floppy type */ 489 if (floppy) { 490 for (i = 0; i < 2; i++) { 491 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 492 } 493 } 494 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 495 cmos_get_fd_drive_type(fd_type[1]); 496 rtc_set_memory(rtc_state, 0x10, val); 497 498 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 499 nb = 0; 500 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 501 nb++; 502 } 503 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 504 nb++; 505 } 506 switch (nb) { 507 case 0: 508 break; 509 case 1: 510 val |= 0x01; /* 1 drive, ready for boot */ 511 break; 512 case 2: 513 val |= 0x41; /* 2 drives, ready for boot */ 514 break; 515 } 516 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 517 } 518 519 typedef struct pc_cmos_init_late_arg { 520 ISADevice *rtc_state; 521 BusState *idebus[2]; 522 } pc_cmos_init_late_arg; 523 524 typedef struct check_fdc_state { 525 ISADevice *floppy; 526 bool multiple; 527 } CheckFdcState; 528 529 static int check_fdc(Object *obj, void *opaque) 530 { 531 CheckFdcState *state = opaque; 532 Object *fdc; 533 uint32_t iobase; 534 Error *local_err = NULL; 535 536 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 537 if (!fdc) { 538 return 0; 539 } 540 541 iobase = object_property_get_uint(obj, "iobase", &local_err); 542 if (local_err || iobase != 0x3f0) { 543 error_free(local_err); 544 return 0; 545 } 546 547 if (state->floppy) { 548 state->multiple = true; 549 } else { 550 state->floppy = ISA_DEVICE(obj); 551 } 552 return 0; 553 } 554 555 static const char * const fdc_container_path[] = { 556 "/unattached", "/peripheral", "/peripheral-anon" 557 }; 558 559 /* 560 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 561 * and ACPI objects. 562 */ 563 ISADevice *pc_find_fdc0(void) 564 { 565 int i; 566 Object *container; 567 CheckFdcState state = { 0 }; 568 569 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 570 container = container_get(qdev_get_machine(), fdc_container_path[i]); 571 object_child_foreach(container, check_fdc, &state); 572 } 573 574 if (state.multiple) { 575 warn_report("multiple floppy disk controllers with " 576 "iobase=0x3f0 have been found"); 577 error_printf("the one being picked for CMOS setup might not reflect " 578 "your intent"); 579 } 580 581 return state.floppy; 582 } 583 584 static void pc_cmos_init_late(void *opaque) 585 { 586 pc_cmos_init_late_arg *arg = opaque; 587 ISADevice *s = arg->rtc_state; 588 int16_t cylinders; 589 int8_t heads, sectors; 590 int val; 591 int i, trans; 592 593 val = 0; 594 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 595 &cylinders, &heads, §ors) >= 0) { 596 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 597 val |= 0xf0; 598 } 599 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 600 &cylinders, &heads, §ors) >= 0) { 601 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 602 val |= 0x0f; 603 } 604 rtc_set_memory(s, 0x12, val); 605 606 val = 0; 607 for (i = 0; i < 4; i++) { 608 /* NOTE: ide_get_geometry() returns the physical 609 geometry. It is always such that: 1 <= sects <= 63, 1 610 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 611 geometry can be different if a translation is done. */ 612 if (arg->idebus[i / 2] && 613 ide_get_geometry(arg->idebus[i / 2], i % 2, 614 &cylinders, &heads, §ors) >= 0) { 615 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 616 assert((trans & ~3) == 0); 617 val |= trans << (i * 2); 618 } 619 } 620 rtc_set_memory(s, 0x39, val); 621 622 pc_cmos_init_floppy(s, pc_find_fdc0()); 623 624 qemu_unregister_reset(pc_cmos_init_late, opaque); 625 } 626 627 void pc_cmos_init(PCMachineState *pcms, 628 BusState *idebus0, BusState *idebus1, 629 ISADevice *s) 630 { 631 int val; 632 static pc_cmos_init_late_arg arg; 633 X86MachineState *x86ms = X86_MACHINE(pcms); 634 635 /* various important CMOS locations needed by PC/Bochs bios */ 636 637 /* memory size */ 638 /* base memory (first MiB) */ 639 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 640 rtc_set_memory(s, 0x15, val); 641 rtc_set_memory(s, 0x16, val >> 8); 642 /* extended memory (next 64MiB) */ 643 if (x86ms->below_4g_mem_size > 1 * MiB) { 644 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 645 } else { 646 val = 0; 647 } 648 if (val > 65535) 649 val = 65535; 650 rtc_set_memory(s, 0x17, val); 651 rtc_set_memory(s, 0x18, val >> 8); 652 rtc_set_memory(s, 0x30, val); 653 rtc_set_memory(s, 0x31, val >> 8); 654 /* memory between 16MiB and 4GiB */ 655 if (x86ms->below_4g_mem_size > 16 * MiB) { 656 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 657 } else { 658 val = 0; 659 } 660 if (val > 65535) 661 val = 65535; 662 rtc_set_memory(s, 0x34, val); 663 rtc_set_memory(s, 0x35, val >> 8); 664 /* memory above 4GiB */ 665 val = x86ms->above_4g_mem_size / 65536; 666 rtc_set_memory(s, 0x5b, val); 667 rtc_set_memory(s, 0x5c, val >> 8); 668 rtc_set_memory(s, 0x5d, val >> 16); 669 670 object_property_add_link(OBJECT(pcms), "rtc_state", 671 TYPE_ISA_DEVICE, 672 (Object **)&x86ms->rtc, 673 object_property_allow_set_link, 674 OBJ_PROP_LINK_STRONG); 675 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 676 &error_abort); 677 678 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 679 680 val = 0; 681 val |= 0x02; /* FPU is there */ 682 val |= 0x04; /* PS/2 mouse installed */ 683 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 684 685 /* hard drives and FDC */ 686 arg.rtc_state = s; 687 arg.idebus[0] = idebus0; 688 arg.idebus[1] = idebus1; 689 qemu_register_reset(pc_cmos_init_late, &arg); 690 } 691 692 static void handle_a20_line_change(void *opaque, int irq, int level) 693 { 694 X86CPU *cpu = opaque; 695 696 /* XXX: send to all CPUs ? */ 697 /* XXX: add logic to handle multiple A20 line sources */ 698 x86_cpu_set_a20(cpu, level); 699 } 700 701 #define NE2000_NB_MAX 6 702 703 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 704 0x280, 0x380 }; 705 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 706 707 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 708 { 709 static int nb_ne2k = 0; 710 711 if (nb_ne2k == NE2000_NB_MAX) 712 return; 713 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 714 ne2000_irq[nb_ne2k], nd); 715 nb_ne2k++; 716 } 717 718 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 719 { 720 X86CPU *cpu = opaque; 721 722 if (level) { 723 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 724 } 725 } 726 727 static 728 void pc_machine_done(Notifier *notifier, void *data) 729 { 730 PCMachineState *pcms = container_of(notifier, 731 PCMachineState, machine_done); 732 X86MachineState *x86ms = X86_MACHINE(pcms); 733 734 /* set the number of CPUs */ 735 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 736 737 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 738 739 acpi_setup(); 740 if (x86ms->fw_cfg) { 741 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 742 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 743 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 744 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 745 } 746 747 748 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 749 !kvm_irqchip_in_kernel()) { 750 error_report("current -smp configuration requires kernel " 751 "irqchip support."); 752 exit(EXIT_FAILURE); 753 } 754 } 755 756 void pc_guest_info_init(PCMachineState *pcms) 757 { 758 X86MachineState *x86ms = X86_MACHINE(pcms); 759 760 x86ms->apic_xrupt_override = true; 761 pcms->machine_done.notify = pc_machine_done; 762 qemu_add_machine_init_done_notifier(&pcms->machine_done); 763 } 764 765 /* setup pci memory address space mapping into system address space */ 766 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 767 MemoryRegion *pci_address_space) 768 { 769 /* Set to lower priority than RAM */ 770 memory_region_add_subregion_overlap(system_memory, 0x0, 771 pci_address_space, -1); 772 } 773 774 void xen_load_linux(PCMachineState *pcms) 775 { 776 int i; 777 FWCfgState *fw_cfg; 778 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 779 X86MachineState *x86ms = X86_MACHINE(pcms); 780 781 assert(MACHINE(pcms)->kernel_filename != NULL); 782 783 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 784 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 785 rom_set_fw(fw_cfg); 786 787 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 788 pcmc->pvh_enabled); 789 for (i = 0; i < nb_option_roms; i++) { 790 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 791 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 792 !strcmp(option_rom[i].name, "pvh.bin") || 793 !strcmp(option_rom[i].name, "multiboot.bin") || 794 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 795 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 796 } 797 x86ms->fw_cfg = fw_cfg; 798 } 799 800 #define PC_ROM_MIN_VGA 0xc0000 801 #define PC_ROM_MIN_OPTION 0xc8000 802 #define PC_ROM_MAX 0xe0000 803 #define PC_ROM_ALIGN 0x800 804 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 805 806 void pc_memory_init(PCMachineState *pcms, 807 MemoryRegion *system_memory, 808 MemoryRegion *rom_memory, 809 MemoryRegion **ram_memory) 810 { 811 int linux_boot, i; 812 MemoryRegion *option_rom_mr; 813 MemoryRegion *ram_below_4g, *ram_above_4g; 814 FWCfgState *fw_cfg; 815 MachineState *machine = MACHINE(pcms); 816 MachineClass *mc = MACHINE_GET_CLASS(machine); 817 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 818 X86MachineState *x86ms = X86_MACHINE(pcms); 819 820 assert(machine->ram_size == x86ms->below_4g_mem_size + 821 x86ms->above_4g_mem_size); 822 823 linux_boot = (machine->kernel_filename != NULL); 824 825 /* 826 * Split single memory region and use aliases to address portions of it, 827 * done for backwards compatibility with older qemus. 828 */ 829 *ram_memory = machine->ram; 830 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 831 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 832 0, x86ms->below_4g_mem_size); 833 memory_region_add_subregion(system_memory, 0, ram_below_4g); 834 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 835 if (x86ms->above_4g_mem_size > 0) { 836 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 837 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 838 machine->ram, 839 x86ms->below_4g_mem_size, 840 x86ms->above_4g_mem_size); 841 memory_region_add_subregion(system_memory, 0x100000000ULL, 842 ram_above_4g); 843 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 844 } 845 846 if (pcms->sgx_epc.size != 0) { 847 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 848 } 849 850 if (!pcmc->has_reserved_memory && 851 (machine->ram_slots || 852 (machine->maxram_size > machine->ram_size))) { 853 854 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 855 mc->name); 856 exit(EXIT_FAILURE); 857 } 858 859 /* always allocate the device memory information */ 860 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 861 862 /* initialize device memory address space */ 863 if (pcmc->has_reserved_memory && 864 (machine->ram_size < machine->maxram_size)) { 865 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 866 867 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 868 error_report("unsupported amount of memory slots: %"PRIu64, 869 machine->ram_slots); 870 exit(EXIT_FAILURE); 871 } 872 873 if (QEMU_ALIGN_UP(machine->maxram_size, 874 TARGET_PAGE_SIZE) != machine->maxram_size) { 875 error_report("maximum memory size must by aligned to multiple of " 876 "%d bytes", TARGET_PAGE_SIZE); 877 exit(EXIT_FAILURE); 878 } 879 880 if (pcms->sgx_epc.size != 0) { 881 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 882 } else { 883 machine->device_memory->base = 884 0x100000000ULL + x86ms->above_4g_mem_size; 885 } 886 887 machine->device_memory->base = 888 ROUND_UP(machine->device_memory->base, 1 * GiB); 889 890 if (pcmc->enforce_aligned_dimm) { 891 /* size device region assuming 1G page max alignment per slot */ 892 device_mem_size += (1 * GiB) * machine->ram_slots; 893 } 894 895 if ((machine->device_memory->base + device_mem_size) < 896 device_mem_size) { 897 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 898 machine->maxram_size); 899 exit(EXIT_FAILURE); 900 } 901 902 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 903 "device-memory", device_mem_size); 904 memory_region_add_subregion(system_memory, machine->device_memory->base, 905 &machine->device_memory->mr); 906 } 907 908 /* Initialize PC system firmware */ 909 pc_system_firmware_init(pcms, rom_memory); 910 911 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 912 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 913 &error_fatal); 914 if (pcmc->pci_enabled) { 915 memory_region_set_readonly(option_rom_mr, true); 916 } 917 memory_region_add_subregion_overlap(rom_memory, 918 PC_ROM_MIN_VGA, 919 option_rom_mr, 920 1); 921 922 fw_cfg = fw_cfg_arch_create(machine, 923 x86ms->boot_cpus, x86ms->apic_id_limit); 924 925 rom_set_fw(fw_cfg); 926 927 if (pcmc->has_reserved_memory && machine->device_memory->base) { 928 uint64_t *val = g_malloc(sizeof(*val)); 929 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 930 uint64_t res_mem_end = machine->device_memory->base; 931 932 if (!pcmc->broken_reserved_end) { 933 res_mem_end += memory_region_size(&machine->device_memory->mr); 934 } 935 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 936 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 937 } 938 939 if (linux_boot) { 940 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 941 pcmc->pvh_enabled); 942 } 943 944 for (i = 0; i < nb_option_roms; i++) { 945 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 946 } 947 x86ms->fw_cfg = fw_cfg; 948 949 /* Init default IOAPIC address space */ 950 x86ms->ioapic_as = &address_space_memory; 951 952 /* Init ACPI memory hotplug IO base address */ 953 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 954 } 955 956 /* 957 * The 64bit pci hole starts after "above 4G RAM" and 958 * potentially the space reserved for memory hotplug. 959 */ 960 uint64_t pc_pci_hole64_start(void) 961 { 962 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 963 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 964 MachineState *ms = MACHINE(pcms); 965 X86MachineState *x86ms = X86_MACHINE(pcms); 966 uint64_t hole64_start = 0; 967 968 if (pcmc->has_reserved_memory && ms->device_memory->base) { 969 hole64_start = ms->device_memory->base; 970 if (!pcmc->broken_reserved_end) { 971 hole64_start += memory_region_size(&ms->device_memory->mr); 972 } 973 } else if (pcms->sgx_epc.size != 0) { 974 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 975 } else { 976 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 977 } 978 979 return ROUND_UP(hole64_start, 1 * GiB); 980 } 981 982 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 983 { 984 DeviceState *dev = NULL; 985 986 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 987 if (pci_bus) { 988 PCIDevice *pcidev = pci_vga_init(pci_bus); 989 dev = pcidev ? &pcidev->qdev : NULL; 990 } else if (isa_bus) { 991 ISADevice *isadev = isa_vga_init(isa_bus); 992 dev = isadev ? DEVICE(isadev) : NULL; 993 } 994 rom_reset_order_override(); 995 return dev; 996 } 997 998 static const MemoryRegionOps ioport80_io_ops = { 999 .write = ioport80_write, 1000 .read = ioport80_read, 1001 .endianness = DEVICE_NATIVE_ENDIAN, 1002 .impl = { 1003 .min_access_size = 1, 1004 .max_access_size = 1, 1005 }, 1006 }; 1007 1008 static const MemoryRegionOps ioportF0_io_ops = { 1009 .write = ioportF0_write, 1010 .read = ioportF0_read, 1011 .endianness = DEVICE_NATIVE_ENDIAN, 1012 .impl = { 1013 .min_access_size = 1, 1014 .max_access_size = 1, 1015 }, 1016 }; 1017 1018 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1019 bool create_i8042, bool no_vmport) 1020 { 1021 int i; 1022 DriveInfo *fd[MAX_FD]; 1023 qemu_irq *a20_line; 1024 ISADevice *fdc, *i8042, *port92, *vmmouse; 1025 1026 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1027 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1028 1029 for (i = 0; i < MAX_FD; i++) { 1030 fd[i] = drive_get(IF_FLOPPY, 0, i); 1031 create_fdctrl |= !!fd[i]; 1032 } 1033 if (create_fdctrl) { 1034 fdc = isa_new(TYPE_ISA_FDC); 1035 if (fdc) { 1036 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1037 isa_fdc_init_drives(fdc, fd); 1038 } 1039 } 1040 1041 if (!create_i8042) { 1042 return; 1043 } 1044 1045 i8042 = isa_create_simple(isa_bus, "i8042"); 1046 if (!no_vmport) { 1047 isa_create_simple(isa_bus, TYPE_VMPORT); 1048 vmmouse = isa_try_new("vmmouse"); 1049 } else { 1050 vmmouse = NULL; 1051 } 1052 if (vmmouse) { 1053 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1054 &error_abort); 1055 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1056 } 1057 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1058 1059 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1060 i8042_setup_a20_line(i8042, a20_line[0]); 1061 qdev_connect_gpio_out_named(DEVICE(port92), 1062 PORT92_A20_LINE, 0, a20_line[1]); 1063 g_free(a20_line); 1064 } 1065 1066 void pc_basic_device_init(struct PCMachineState *pcms, 1067 ISABus *isa_bus, qemu_irq *gsi, 1068 ISADevice **rtc_state, 1069 bool create_fdctrl, 1070 uint32_t hpet_irqs) 1071 { 1072 int i; 1073 DeviceState *hpet = NULL; 1074 int pit_isa_irq = 0; 1075 qemu_irq pit_alt_irq = NULL; 1076 qemu_irq rtc_irq = NULL; 1077 ISADevice *pit = NULL; 1078 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1079 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1080 1081 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1082 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1083 1084 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1085 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1086 1087 /* 1088 * Check if an HPET shall be created. 1089 * 1090 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1091 * when the HPET wants to take over. Thus we have to disable the latter. 1092 */ 1093 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1094 kvm_has_pit_state2())) { 1095 hpet = qdev_try_new(TYPE_HPET); 1096 if (!hpet) { 1097 error_report("couldn't create HPET device"); 1098 exit(1); 1099 } 1100 /* 1101 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1102 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1103 * IRQ2. 1104 */ 1105 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1106 HPET_INTCAP, NULL); 1107 if (!compat) { 1108 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1109 } 1110 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1111 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1112 1113 for (i = 0; i < GSI_NUM_PINS; i++) { 1114 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1115 } 1116 pit_isa_irq = -1; 1117 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1118 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1119 } 1120 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1121 1122 qemu_register_boot_set(pc_boot_set, *rtc_state); 1123 1124 if (!xen_enabled() && pcms->pit_enabled) { 1125 if (kvm_pit_in_kernel()) { 1126 pit = kvm_pit_init(isa_bus, 0x40); 1127 } else { 1128 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1129 } 1130 if (hpet) { 1131 /* connect PIT to output control line of the HPET */ 1132 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1133 } 1134 pcspk_init(pcms->pcspk, isa_bus, pit); 1135 } 1136 1137 i8257_dma_init(isa_bus, 0); 1138 1139 /* Super I/O */ 1140 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1141 pcms->vmport != ON_OFF_AUTO_ON); 1142 } 1143 1144 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1145 { 1146 int i; 1147 1148 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1149 for (i = 0; i < nb_nics; i++) { 1150 NICInfo *nd = &nd_table[i]; 1151 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1152 1153 if (g_str_equal(model, "ne2k_isa")) { 1154 pc_init_ne2k_isa(isa_bus, nd); 1155 } else { 1156 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1157 } 1158 } 1159 rom_reset_order_override(); 1160 } 1161 1162 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1163 { 1164 qemu_irq *i8259; 1165 1166 if (kvm_pic_in_kernel()) { 1167 i8259 = kvm_i8259_init(isa_bus); 1168 } else if (xen_enabled()) { 1169 i8259 = xen_interrupt_controller_init(); 1170 } else { 1171 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1172 } 1173 1174 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1175 i8259_irqs[i] = i8259[i]; 1176 } 1177 1178 g_free(i8259); 1179 } 1180 1181 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1182 Error **errp) 1183 { 1184 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1185 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1186 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1187 const MachineState *ms = MACHINE(hotplug_dev); 1188 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1189 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1190 Error *local_err = NULL; 1191 1192 /* 1193 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1194 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1195 * addition to cover this case. 1196 */ 1197 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1198 error_setg(errp, 1199 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1200 return; 1201 } 1202 1203 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1204 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1205 return; 1206 } 1207 1208 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1209 if (local_err) { 1210 error_propagate(errp, local_err); 1211 return; 1212 } 1213 1214 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1215 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1216 } 1217 1218 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1219 DeviceState *dev, Error **errp) 1220 { 1221 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1222 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1223 MachineState *ms = MACHINE(hotplug_dev); 1224 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1225 1226 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1227 1228 if (is_nvdimm) { 1229 nvdimm_plug(ms->nvdimms_state); 1230 } 1231 1232 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1233 } 1234 1235 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1236 DeviceState *dev, Error **errp) 1237 { 1238 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1239 1240 /* 1241 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1242 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1243 * addition to cover this case. 1244 */ 1245 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1246 error_setg(errp, 1247 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1248 return; 1249 } 1250 1251 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1252 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1253 return; 1254 } 1255 1256 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1257 errp); 1258 } 1259 1260 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1261 DeviceState *dev, Error **errp) 1262 { 1263 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1264 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1265 Error *local_err = NULL; 1266 1267 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1268 if (local_err) { 1269 goto out; 1270 } 1271 1272 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1273 qdev_unrealize(dev); 1274 out: 1275 error_propagate(errp, local_err); 1276 } 1277 1278 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1279 DeviceState *dev, Error **errp) 1280 { 1281 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1282 Error *local_err = NULL; 1283 1284 if (!hotplug_dev2 && dev->hotplugged) { 1285 /* 1286 * Without a bus hotplug handler, we cannot control the plug/unplug 1287 * order. We should never reach this point when hotplugging on x86, 1288 * however, better add a safety net. 1289 */ 1290 error_setg(errp, "hotplug of virtio based memory devices not supported" 1291 " on this bus."); 1292 return; 1293 } 1294 /* 1295 * First, see if we can plug this memory device at all. If that 1296 * succeeds, branch of to the actual hotplug handler. 1297 */ 1298 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1299 &local_err); 1300 if (!local_err && hotplug_dev2) { 1301 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1302 } 1303 error_propagate(errp, local_err); 1304 } 1305 1306 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1307 DeviceState *dev, Error **errp) 1308 { 1309 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1310 Error *local_err = NULL; 1311 1312 /* 1313 * Plug the memory device first and then branch off to the actual 1314 * hotplug handler. If that one fails, we can easily undo the memory 1315 * device bits. 1316 */ 1317 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1318 if (hotplug_dev2) { 1319 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1320 if (local_err) { 1321 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1322 } 1323 } 1324 error_propagate(errp, local_err); 1325 } 1326 1327 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1328 DeviceState *dev, Error **errp) 1329 { 1330 /* We don't support hot unplug of virtio based memory devices */ 1331 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1332 } 1333 1334 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1335 DeviceState *dev, Error **errp) 1336 { 1337 /* We don't support hot unplug of virtio based memory devices */ 1338 } 1339 1340 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1341 DeviceState *dev, Error **errp) 1342 { 1343 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1344 pc_memory_pre_plug(hotplug_dev, dev, errp); 1345 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1346 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1347 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1348 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1349 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1350 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1351 /* Declare the APIC range as the reserved MSI region */ 1352 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1353 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1354 1355 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1356 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1357 resv_prop_str, errp); 1358 g_free(resv_prop_str); 1359 } 1360 1361 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1362 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1363 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1364 1365 if (pcms->iommu) { 1366 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1367 "for x86 yet."); 1368 return; 1369 } 1370 pcms->iommu = dev; 1371 } 1372 } 1373 1374 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1375 DeviceState *dev, Error **errp) 1376 { 1377 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1378 pc_memory_plug(hotplug_dev, dev, errp); 1379 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1380 x86_cpu_plug(hotplug_dev, dev, errp); 1381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1382 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1383 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1384 } 1385 } 1386 1387 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1388 DeviceState *dev, Error **errp) 1389 { 1390 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1391 pc_memory_unplug_request(hotplug_dev, dev, errp); 1392 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1393 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1394 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1395 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1396 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1397 } else { 1398 error_setg(errp, "acpi: device unplug request for not supported device" 1399 " type: %s", object_get_typename(OBJECT(dev))); 1400 } 1401 } 1402 1403 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1404 DeviceState *dev, Error **errp) 1405 { 1406 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1407 pc_memory_unplug(hotplug_dev, dev, errp); 1408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1409 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1410 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1411 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1412 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1413 } else { 1414 error_setg(errp, "acpi: device unplug for not supported device" 1415 " type: %s", object_get_typename(OBJECT(dev))); 1416 } 1417 } 1418 1419 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1420 DeviceState *dev) 1421 { 1422 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1423 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1424 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1425 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1426 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1427 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1428 return HOTPLUG_HANDLER(machine); 1429 } 1430 1431 return NULL; 1432 } 1433 1434 static void 1435 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1436 const char *name, void *opaque, 1437 Error **errp) 1438 { 1439 MachineState *ms = MACHINE(obj); 1440 int64_t value = 0; 1441 1442 if (ms->device_memory) { 1443 value = memory_region_size(&ms->device_memory->mr); 1444 } 1445 1446 visit_type_int(v, name, &value, errp); 1447 } 1448 1449 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1450 void *opaque, Error **errp) 1451 { 1452 PCMachineState *pcms = PC_MACHINE(obj); 1453 OnOffAuto vmport = pcms->vmport; 1454 1455 visit_type_OnOffAuto(v, name, &vmport, errp); 1456 } 1457 1458 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1459 void *opaque, Error **errp) 1460 { 1461 PCMachineState *pcms = PC_MACHINE(obj); 1462 1463 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1464 } 1465 1466 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1467 { 1468 PCMachineState *pcms = PC_MACHINE(obj); 1469 1470 return pcms->smbus_enabled; 1471 } 1472 1473 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1474 { 1475 PCMachineState *pcms = PC_MACHINE(obj); 1476 1477 pcms->smbus_enabled = value; 1478 } 1479 1480 static bool pc_machine_get_sata(Object *obj, Error **errp) 1481 { 1482 PCMachineState *pcms = PC_MACHINE(obj); 1483 1484 return pcms->sata_enabled; 1485 } 1486 1487 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1488 { 1489 PCMachineState *pcms = PC_MACHINE(obj); 1490 1491 pcms->sata_enabled = value; 1492 } 1493 1494 static bool pc_machine_get_pit(Object *obj, Error **errp) 1495 { 1496 PCMachineState *pcms = PC_MACHINE(obj); 1497 1498 return pcms->pit_enabled; 1499 } 1500 1501 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1502 { 1503 PCMachineState *pcms = PC_MACHINE(obj); 1504 1505 pcms->pit_enabled = value; 1506 } 1507 1508 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1509 { 1510 PCMachineState *pcms = PC_MACHINE(obj); 1511 1512 return pcms->hpet_enabled; 1513 } 1514 1515 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 pcms->hpet_enabled = value; 1520 } 1521 1522 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 1526 return pcms->i8042_enabled; 1527 } 1528 1529 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1530 { 1531 PCMachineState *pcms = PC_MACHINE(obj); 1532 1533 pcms->i8042_enabled = value; 1534 } 1535 1536 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 1540 return pcms->default_bus_bypass_iommu; 1541 } 1542 1543 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1544 Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 1548 pcms->default_bus_bypass_iommu = value; 1549 } 1550 1551 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1552 void *opaque, Error **errp) 1553 { 1554 PCMachineState *pcms = PC_MACHINE(obj); 1555 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1556 1557 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1558 } 1559 1560 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1561 void *opaque, Error **errp) 1562 { 1563 PCMachineState *pcms = PC_MACHINE(obj); 1564 1565 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1566 } 1567 1568 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1569 const char *name, void *opaque, 1570 Error **errp) 1571 { 1572 PCMachineState *pcms = PC_MACHINE(obj); 1573 uint64_t value = pcms->max_ram_below_4g; 1574 1575 visit_type_size(v, name, &value, errp); 1576 } 1577 1578 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1579 const char *name, void *opaque, 1580 Error **errp) 1581 { 1582 PCMachineState *pcms = PC_MACHINE(obj); 1583 uint64_t value; 1584 1585 if (!visit_type_size(v, name, &value, errp)) { 1586 return; 1587 } 1588 if (value > 4 * GiB) { 1589 error_setg(errp, 1590 "Machine option 'max-ram-below-4g=%"PRIu64 1591 "' expects size less than or equal to 4G", value); 1592 return; 1593 } 1594 1595 if (value < 1 * MiB) { 1596 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1597 "BIOS may not work with less than 1MiB", value); 1598 } 1599 1600 pcms->max_ram_below_4g = value; 1601 } 1602 1603 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1604 const char *name, void *opaque, 1605 Error **errp) 1606 { 1607 PCMachineState *pcms = PC_MACHINE(obj); 1608 uint64_t value = pcms->max_fw_size; 1609 1610 visit_type_size(v, name, &value, errp); 1611 } 1612 1613 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1614 const char *name, void *opaque, 1615 Error **errp) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 Error *error = NULL; 1619 uint64_t value; 1620 1621 visit_type_size(v, name, &value, &error); 1622 if (error) { 1623 error_propagate(errp, error); 1624 return; 1625 } 1626 1627 /* 1628 * We don't have a theoretically justifiable exact lower bound on the base 1629 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1630 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1631 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1632 * size. 1633 */ 1634 if (value > 16 * MiB) { 1635 error_setg(errp, 1636 "User specified max allowed firmware size %" PRIu64 " is " 1637 "greater than 16MiB. If combined firwmare size exceeds " 1638 "16MiB the system may not boot, or experience intermittent" 1639 "stability issues.", 1640 value); 1641 return; 1642 } 1643 1644 pcms->max_fw_size = value; 1645 } 1646 1647 1648 static void pc_machine_initfn(Object *obj) 1649 { 1650 PCMachineState *pcms = PC_MACHINE(obj); 1651 1652 #ifdef CONFIG_VMPORT 1653 pcms->vmport = ON_OFF_AUTO_AUTO; 1654 #else 1655 pcms->vmport = ON_OFF_AUTO_OFF; 1656 #endif /* CONFIG_VMPORT */ 1657 pcms->max_ram_below_4g = 0; /* use default */ 1658 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1659 1660 /* acpi build is enabled by default if machine supports it */ 1661 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1662 pcms->smbus_enabled = true; 1663 pcms->sata_enabled = true; 1664 pcms->pit_enabled = true; 1665 pcms->i8042_enabled = true; 1666 pcms->max_fw_size = 8 * MiB; 1667 #ifdef CONFIG_HPET 1668 pcms->hpet_enabled = true; 1669 #endif 1670 pcms->default_bus_bypass_iommu = false; 1671 1672 pc_system_flash_create(pcms); 1673 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1674 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1675 OBJECT(pcms->pcspk), "audiodev"); 1676 } 1677 1678 static void pc_machine_reset(MachineState *machine) 1679 { 1680 CPUState *cs; 1681 X86CPU *cpu; 1682 1683 qemu_devices_reset(); 1684 1685 /* Reset APIC after devices have been reset to cancel 1686 * any changes that qemu_devices_reset() might have done. 1687 */ 1688 CPU_FOREACH(cs) { 1689 cpu = X86_CPU(cs); 1690 1691 if (cpu->apic_state) { 1692 device_legacy_reset(cpu->apic_state); 1693 } 1694 } 1695 } 1696 1697 static void pc_machine_wakeup(MachineState *machine) 1698 { 1699 cpu_synchronize_all_states(); 1700 pc_machine_reset(machine); 1701 cpu_synchronize_all_post_reset(); 1702 } 1703 1704 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1705 { 1706 X86IOMMUState *iommu = x86_iommu_get_default(); 1707 IntelIOMMUState *intel_iommu; 1708 1709 if (iommu && 1710 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1711 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1712 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1713 if (!intel_iommu->caching_mode) { 1714 error_setg(errp, "Device assignment is not allowed without " 1715 "enabling caching-mode=on for Intel IOMMU."); 1716 return false; 1717 } 1718 } 1719 1720 return true; 1721 } 1722 1723 static void pc_machine_class_init(ObjectClass *oc, void *data) 1724 { 1725 MachineClass *mc = MACHINE_CLASS(oc); 1726 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1727 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1728 1729 pcmc->pci_enabled = true; 1730 pcmc->has_acpi_build = true; 1731 pcmc->rsdp_in_ram = true; 1732 pcmc->smbios_defaults = true; 1733 pcmc->smbios_uuid_encoded = true; 1734 pcmc->gigabyte_align = true; 1735 pcmc->has_reserved_memory = true; 1736 pcmc->kvmclock_enabled = true; 1737 pcmc->enforce_aligned_dimm = true; 1738 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1739 * to be used at the moment, 32K should be enough for a while. */ 1740 pcmc->acpi_data_size = 0x20000 + 0x8000; 1741 pcmc->pvh_enabled = true; 1742 pcmc->kvmclock_create_always = true; 1743 assert(!mc->get_hotplug_handler); 1744 mc->get_hotplug_handler = pc_get_hotplug_handler; 1745 mc->hotplug_allowed = pc_hotplug_allowed; 1746 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1747 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1748 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1749 mc->auto_enable_numa_with_memhp = true; 1750 mc->auto_enable_numa_with_memdev = true; 1751 mc->has_hotpluggable_cpus = true; 1752 mc->default_boot_order = "cad"; 1753 mc->block_default_type = IF_IDE; 1754 mc->max_cpus = 255; 1755 mc->reset = pc_machine_reset; 1756 mc->wakeup = pc_machine_wakeup; 1757 hc->pre_plug = pc_machine_device_pre_plug_cb; 1758 hc->plug = pc_machine_device_plug_cb; 1759 hc->unplug_request = pc_machine_device_unplug_request_cb; 1760 hc->unplug = pc_machine_device_unplug_cb; 1761 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1762 mc->nvdimm_supported = true; 1763 mc->smp_props.dies_supported = true; 1764 mc->default_ram_id = "pc.ram"; 1765 1766 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1767 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1768 NULL, NULL); 1769 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1770 "Maximum ram below the 4G boundary (32bit boundary)"); 1771 1772 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1773 pc_machine_get_device_memory_region_size, NULL, 1774 NULL, NULL); 1775 1776 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1777 pc_machine_get_vmport, pc_machine_set_vmport, 1778 NULL, NULL); 1779 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1780 "Enable vmport (pc & q35)"); 1781 1782 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1783 pc_machine_get_smbus, pc_machine_set_smbus); 1784 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1785 "Enable/disable system management bus"); 1786 1787 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1788 pc_machine_get_sata, pc_machine_set_sata); 1789 object_class_property_set_description(oc, PC_MACHINE_SATA, 1790 "Enable/disable Serial ATA bus"); 1791 1792 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1793 pc_machine_get_pit, pc_machine_set_pit); 1794 object_class_property_set_description(oc, PC_MACHINE_PIT, 1795 "Enable/disable Intel 8254 programmable interval timer emulation"); 1796 1797 object_class_property_add_bool(oc, "hpet", 1798 pc_machine_get_hpet, pc_machine_set_hpet); 1799 object_class_property_set_description(oc, "hpet", 1800 "Enable/disable high precision event timer emulation"); 1801 1802 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1803 pc_machine_get_i8042, pc_machine_set_i8042); 1804 1805 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1806 pc_machine_get_default_bus_bypass_iommu, 1807 pc_machine_set_default_bus_bypass_iommu); 1808 1809 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1810 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1811 NULL, NULL); 1812 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1813 "Maximum combined firmware size"); 1814 1815 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1816 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1817 NULL, NULL); 1818 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1819 "SMBIOS Entry Point type [32, 64]"); 1820 } 1821 1822 static const TypeInfo pc_machine_info = { 1823 .name = TYPE_PC_MACHINE, 1824 .parent = TYPE_X86_MACHINE, 1825 .abstract = true, 1826 .instance_size = sizeof(PCMachineState), 1827 .instance_init = pc_machine_initfn, 1828 .class_size = sizeof(PCMachineClass), 1829 .class_init = pc_machine_class_init, 1830 .interfaces = (InterfaceInfo[]) { 1831 { TYPE_HOTPLUG_HANDLER }, 1832 { } 1833 }, 1834 }; 1835 1836 static void pc_machine_register_types(void) 1837 { 1838 type_register_static(&pc_machine_info); 1839 } 1840 1841 type_init(pc_machine_register_types) 1842