1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "multiboot.h" 45 #include "hw/timer/mc146818rtc.h" 46 #include "hw/dma/i8257.h" 47 #include "hw/timer/i8254.h" 48 #include "hw/input/i8042.h" 49 #include "hw/audio/pcspk.h" 50 #include "hw/pci/msi.h" 51 #include "hw/sysbus.h" 52 #include "sysemu/sysemu.h" 53 #include "sysemu/tcg.h" 54 #include "sysemu/numa.h" 55 #include "sysemu/kvm.h" 56 #include "sysemu/qtest.h" 57 #include "kvm_i386.h" 58 #include "hw/xen/xen.h" 59 #include "hw/xen/start_info.h" 60 #include "ui/qemu-spice.h" 61 #include "exec/memory.h" 62 #include "exec/address-spaces.h" 63 #include "sysemu/arch_init.h" 64 #include "qemu/bitmap.h" 65 #include "qemu/config-file.h" 66 #include "qemu/error-report.h" 67 #include "qemu/option.h" 68 #include "hw/acpi/acpi.h" 69 #include "hw/acpi/cpu_hotplug.h" 70 #include "hw/boards.h" 71 #include "acpi-build.h" 72 #include "hw/mem/pc-dimm.h" 73 #include "qapi/error.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qapi/visitor.h" 76 #include "qom/cpu.h" 77 #include "hw/nmi.h" 78 #include "hw/usb.h" 79 #include "hw/i386/intel_iommu.h" 80 #include "hw/net/ne2000-isa.h" 81 #include "standard-headers/asm-x86/bootparam.h" 82 83 /* debug PC/ISA interrupts */ 84 //#define DEBUG_IRQ 85 86 #ifdef DEBUG_IRQ 87 #define DPRINTF(fmt, ...) \ 88 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 89 #else 90 #define DPRINTF(fmt, ...) 91 #endif 92 93 #define E820_NR_ENTRIES 16 94 95 struct e820_entry { 96 uint64_t address; 97 uint64_t length; 98 uint32_t type; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 struct e820_table { 102 uint32_t count; 103 struct e820_entry entry[E820_NR_ENTRIES]; 104 } QEMU_PACKED __attribute((__aligned__(4))); 105 106 static struct e820_table e820_reserve; 107 static struct e820_entry *e820_table; 108 static unsigned e820_entries; 109 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 110 111 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 112 static size_t pvh_start_addr; 113 114 GlobalProperty pc_compat_4_0[] = {}; 115 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 116 117 GlobalProperty pc_compat_3_1[] = { 118 { "intel-iommu", "dma-drain", "off" }, 119 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 120 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 121 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 122 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 123 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 124 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 125 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 126 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 127 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 128 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 129 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 130 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 131 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 132 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 133 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 136 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 137 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 138 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 139 }; 140 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 141 142 GlobalProperty pc_compat_3_0[] = { 143 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 144 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 145 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 146 }; 147 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 148 149 GlobalProperty pc_compat_2_12[] = { 150 { TYPE_X86_CPU, "legacy-cache", "on" }, 151 { TYPE_X86_CPU, "topoext", "off" }, 152 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 153 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 154 }; 155 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 156 157 GlobalProperty pc_compat_2_11[] = { 158 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 159 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 160 }; 161 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 162 163 GlobalProperty pc_compat_2_10[] = { 164 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 165 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 166 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 167 }; 168 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 169 170 GlobalProperty pc_compat_2_9[] = { 171 { "mch", "extended-tseg-mbytes", "0" }, 172 }; 173 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 174 175 GlobalProperty pc_compat_2_8[] = { 176 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 177 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 178 { "ICH9-LPC", "x-smi-broadcast", "off" }, 179 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 180 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 181 }; 182 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 183 184 GlobalProperty pc_compat_2_7[] = { 185 { TYPE_X86_CPU, "l3-cache", "off" }, 186 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 187 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 188 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 189 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 190 { "isa-pcspk", "migrate", "off" }, 191 }; 192 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 193 194 GlobalProperty pc_compat_2_6[] = { 195 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 196 { "vmxnet3", "romfile", "" }, 197 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 198 { "apic-common", "legacy-instance-id", "on", } 199 }; 200 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 201 202 GlobalProperty pc_compat_2_5[] = {}; 203 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 204 205 GlobalProperty pc_compat_2_4[] = { 206 PC_CPU_MODEL_IDS("2.4.0") 207 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 208 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 209 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 210 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 211 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 212 { TYPE_X86_CPU, "check", "off" }, 213 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 214 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 215 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 216 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 217 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 218 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 219 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 220 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 221 }; 222 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 223 224 GlobalProperty pc_compat_2_3[] = { 225 PC_CPU_MODEL_IDS("2.3.0") 226 { TYPE_X86_CPU, "arat", "off" }, 227 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 228 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 229 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 230 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 231 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 232 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 233 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 234 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 235 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 236 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 246 }; 247 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 248 249 GlobalProperty pc_compat_2_2[] = { 250 PC_CPU_MODEL_IDS("2.2.0") 251 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 252 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 266 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 267 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 268 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 269 }; 270 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 271 272 GlobalProperty pc_compat_2_1[] = { 273 PC_CPU_MODEL_IDS("2.1.0") 274 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 275 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 276 }; 277 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 278 279 GlobalProperty pc_compat_2_0[] = { 280 PC_CPU_MODEL_IDS("2.0.0") 281 { "virtio-scsi-pci", "any_layout", "off" }, 282 { "PIIX4_PM", "memory-hotplug-support", "off" }, 283 { "apic", "version", "0x11" }, 284 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 285 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 286 { "pci-serial", "prog_if", "0" }, 287 { "pci-serial-2x", "prog_if", "0" }, 288 { "pci-serial-4x", "prog_if", "0" }, 289 { "virtio-net-pci", "guest_announce", "off" }, 290 { "ICH9-LPC", "memory-hotplug-support", "off" }, 291 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 292 { "ioh3420", COMPAT_PROP_PCP, "off" }, 293 }; 294 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 295 296 GlobalProperty pc_compat_1_7[] = { 297 PC_CPU_MODEL_IDS("1.7.0") 298 { TYPE_USB_DEVICE, "msos-desc", "no" }, 299 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 300 { "hpet", HPET_INTCAP, "4" }, 301 }; 302 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 303 304 GlobalProperty pc_compat_1_6[] = { 305 PC_CPU_MODEL_IDS("1.6.0") 306 { "e1000", "mitigation", "off" }, 307 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 308 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 309 { "i440FX-pcihost", "short_root_bus", "1" }, 310 { "q35-pcihost", "short_root_bus", "1" }, 311 }; 312 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 313 314 GlobalProperty pc_compat_1_5[] = { 315 PC_CPU_MODEL_IDS("1.5.0") 316 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 317 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 318 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 319 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 320 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 321 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 322 { "virtio-net-pci", "any_layout", "off" }, 323 { TYPE_X86_CPU, "pmu", "on" }, 324 { "i440FX-pcihost", "short_root_bus", "0" }, 325 { "q35-pcihost", "short_root_bus", "0" }, 326 }; 327 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 328 329 GlobalProperty pc_compat_1_4[] = { 330 PC_CPU_MODEL_IDS("1.4.0") 331 { "scsi-hd", "discard_granularity", "0" }, 332 { "scsi-cd", "discard_granularity", "0" }, 333 { "scsi-disk", "discard_granularity", "0" }, 334 { "ide-hd", "discard_granularity", "0" }, 335 { "ide-cd", "discard_granularity", "0" }, 336 { "ide-drive", "discard_granularity", "0" }, 337 { "virtio-blk-pci", "discard_granularity", "0" }, 338 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 339 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 340 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 341 { "e1000", "romfile", "pxe-e1000.rom" }, 342 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 343 { "pcnet", "romfile", "pxe-pcnet.rom" }, 344 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 345 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 346 { "486-" TYPE_X86_CPU, "model", "0" }, 347 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 348 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 349 }; 350 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 351 352 void gsi_handler(void *opaque, int n, int level) 353 { 354 GSIState *s = opaque; 355 356 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 357 if (n < ISA_NUM_IRQS) { 358 qemu_set_irq(s->i8259_irq[n], level); 359 } 360 qemu_set_irq(s->ioapic_irq[n], level); 361 } 362 363 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 364 unsigned size) 365 { 366 } 367 368 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 369 { 370 return 0xffffffffffffffffULL; 371 } 372 373 /* MSDOS compatibility mode FPU exception support */ 374 static qemu_irq ferr_irq; 375 376 void pc_register_ferr_irq(qemu_irq irq) 377 { 378 ferr_irq = irq; 379 } 380 381 /* XXX: add IGNNE support */ 382 void cpu_set_ferr(CPUX86State *s) 383 { 384 qemu_irq_raise(ferr_irq); 385 } 386 387 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 388 unsigned size) 389 { 390 qemu_irq_lower(ferr_irq); 391 } 392 393 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 394 { 395 return 0xffffffffffffffffULL; 396 } 397 398 /* TSC handling */ 399 uint64_t cpu_get_tsc(CPUX86State *env) 400 { 401 return cpu_get_ticks(); 402 } 403 404 /* IRQ handling */ 405 int cpu_get_pic_interrupt(CPUX86State *env) 406 { 407 X86CPU *cpu = env_archcpu(env); 408 int intno; 409 410 if (!kvm_irqchip_in_kernel()) { 411 intno = apic_get_interrupt(cpu->apic_state); 412 if (intno >= 0) { 413 return intno; 414 } 415 /* read the irq from the PIC */ 416 if (!apic_accept_pic_intr(cpu->apic_state)) { 417 return -1; 418 } 419 } 420 421 intno = pic_read_irq(isa_pic); 422 return intno; 423 } 424 425 static void pic_irq_request(void *opaque, int irq, int level) 426 { 427 CPUState *cs = first_cpu; 428 X86CPU *cpu = X86_CPU(cs); 429 430 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 431 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 432 CPU_FOREACH(cs) { 433 cpu = X86_CPU(cs); 434 if (apic_accept_pic_intr(cpu->apic_state)) { 435 apic_deliver_pic_intr(cpu->apic_state, level); 436 } 437 } 438 } else { 439 if (level) { 440 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 441 } else { 442 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 443 } 444 } 445 } 446 447 /* PC cmos mappings */ 448 449 #define REG_EQUIPMENT_BYTE 0x14 450 451 int cmos_get_fd_drive_type(FloppyDriveType fd0) 452 { 453 int val; 454 455 switch (fd0) { 456 case FLOPPY_DRIVE_TYPE_144: 457 /* 1.44 Mb 3"5 drive */ 458 val = 4; 459 break; 460 case FLOPPY_DRIVE_TYPE_288: 461 /* 2.88 Mb 3"5 drive */ 462 val = 5; 463 break; 464 case FLOPPY_DRIVE_TYPE_120: 465 /* 1.2 Mb 5"5 drive */ 466 val = 2; 467 break; 468 case FLOPPY_DRIVE_TYPE_NONE: 469 default: 470 val = 0; 471 break; 472 } 473 return val; 474 } 475 476 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 477 int16_t cylinders, int8_t heads, int8_t sectors) 478 { 479 rtc_set_memory(s, type_ofs, 47); 480 rtc_set_memory(s, info_ofs, cylinders); 481 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 482 rtc_set_memory(s, info_ofs + 2, heads); 483 rtc_set_memory(s, info_ofs + 3, 0xff); 484 rtc_set_memory(s, info_ofs + 4, 0xff); 485 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 486 rtc_set_memory(s, info_ofs + 6, cylinders); 487 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 488 rtc_set_memory(s, info_ofs + 8, sectors); 489 } 490 491 /* convert boot_device letter to something recognizable by the bios */ 492 static int boot_device2nibble(char boot_device) 493 { 494 switch(boot_device) { 495 case 'a': 496 case 'b': 497 return 0x01; /* floppy boot */ 498 case 'c': 499 return 0x02; /* hard drive boot */ 500 case 'd': 501 return 0x03; /* CD-ROM boot */ 502 case 'n': 503 return 0x04; /* Network boot */ 504 } 505 return 0; 506 } 507 508 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 509 { 510 #define PC_MAX_BOOT_DEVICES 3 511 int nbds, bds[3] = { 0, }; 512 int i; 513 514 nbds = strlen(boot_device); 515 if (nbds > PC_MAX_BOOT_DEVICES) { 516 error_setg(errp, "Too many boot devices for PC"); 517 return; 518 } 519 for (i = 0; i < nbds; i++) { 520 bds[i] = boot_device2nibble(boot_device[i]); 521 if (bds[i] == 0) { 522 error_setg(errp, "Invalid boot device for PC: '%c'", 523 boot_device[i]); 524 return; 525 } 526 } 527 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 528 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 529 } 530 531 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 532 { 533 set_boot_dev(opaque, boot_device, errp); 534 } 535 536 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 537 { 538 int val, nb, i; 539 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 540 FLOPPY_DRIVE_TYPE_NONE }; 541 542 /* floppy type */ 543 if (floppy) { 544 for (i = 0; i < 2; i++) { 545 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 546 } 547 } 548 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 549 cmos_get_fd_drive_type(fd_type[1]); 550 rtc_set_memory(rtc_state, 0x10, val); 551 552 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 553 nb = 0; 554 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 555 nb++; 556 } 557 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 558 nb++; 559 } 560 switch (nb) { 561 case 0: 562 break; 563 case 1: 564 val |= 0x01; /* 1 drive, ready for boot */ 565 break; 566 case 2: 567 val |= 0x41; /* 2 drives, ready for boot */ 568 break; 569 } 570 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 571 } 572 573 typedef struct pc_cmos_init_late_arg { 574 ISADevice *rtc_state; 575 BusState *idebus[2]; 576 } pc_cmos_init_late_arg; 577 578 typedef struct check_fdc_state { 579 ISADevice *floppy; 580 bool multiple; 581 } CheckFdcState; 582 583 static int check_fdc(Object *obj, void *opaque) 584 { 585 CheckFdcState *state = opaque; 586 Object *fdc; 587 uint32_t iobase; 588 Error *local_err = NULL; 589 590 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 591 if (!fdc) { 592 return 0; 593 } 594 595 iobase = object_property_get_uint(obj, "iobase", &local_err); 596 if (local_err || iobase != 0x3f0) { 597 error_free(local_err); 598 return 0; 599 } 600 601 if (state->floppy) { 602 state->multiple = true; 603 } else { 604 state->floppy = ISA_DEVICE(obj); 605 } 606 return 0; 607 } 608 609 static const char * const fdc_container_path[] = { 610 "/unattached", "/peripheral", "/peripheral-anon" 611 }; 612 613 /* 614 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 615 * and ACPI objects. 616 */ 617 ISADevice *pc_find_fdc0(void) 618 { 619 int i; 620 Object *container; 621 CheckFdcState state = { 0 }; 622 623 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 624 container = container_get(qdev_get_machine(), fdc_container_path[i]); 625 object_child_foreach(container, check_fdc, &state); 626 } 627 628 if (state.multiple) { 629 warn_report("multiple floppy disk controllers with " 630 "iobase=0x3f0 have been found"); 631 error_printf("the one being picked for CMOS setup might not reflect " 632 "your intent"); 633 } 634 635 return state.floppy; 636 } 637 638 static void pc_cmos_init_late(void *opaque) 639 { 640 pc_cmos_init_late_arg *arg = opaque; 641 ISADevice *s = arg->rtc_state; 642 int16_t cylinders; 643 int8_t heads, sectors; 644 int val; 645 int i, trans; 646 647 val = 0; 648 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 649 &cylinders, &heads, §ors) >= 0) { 650 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 651 val |= 0xf0; 652 } 653 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 654 &cylinders, &heads, §ors) >= 0) { 655 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 656 val |= 0x0f; 657 } 658 rtc_set_memory(s, 0x12, val); 659 660 val = 0; 661 for (i = 0; i < 4; i++) { 662 /* NOTE: ide_get_geometry() returns the physical 663 geometry. It is always such that: 1 <= sects <= 63, 1 664 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 665 geometry can be different if a translation is done. */ 666 if (arg->idebus[i / 2] && 667 ide_get_geometry(arg->idebus[i / 2], i % 2, 668 &cylinders, &heads, §ors) >= 0) { 669 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 670 assert((trans & ~3) == 0); 671 val |= trans << (i * 2); 672 } 673 } 674 rtc_set_memory(s, 0x39, val); 675 676 pc_cmos_init_floppy(s, pc_find_fdc0()); 677 678 qemu_unregister_reset(pc_cmos_init_late, opaque); 679 } 680 681 void pc_cmos_init(PCMachineState *pcms, 682 BusState *idebus0, BusState *idebus1, 683 ISADevice *s) 684 { 685 int val; 686 static pc_cmos_init_late_arg arg; 687 688 /* various important CMOS locations needed by PC/Bochs bios */ 689 690 /* memory size */ 691 /* base memory (first MiB) */ 692 val = MIN(pcms->below_4g_mem_size / KiB, 640); 693 rtc_set_memory(s, 0x15, val); 694 rtc_set_memory(s, 0x16, val >> 8); 695 /* extended memory (next 64MiB) */ 696 if (pcms->below_4g_mem_size > 1 * MiB) { 697 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 698 } else { 699 val = 0; 700 } 701 if (val > 65535) 702 val = 65535; 703 rtc_set_memory(s, 0x17, val); 704 rtc_set_memory(s, 0x18, val >> 8); 705 rtc_set_memory(s, 0x30, val); 706 rtc_set_memory(s, 0x31, val >> 8); 707 /* memory between 16MiB and 4GiB */ 708 if (pcms->below_4g_mem_size > 16 * MiB) { 709 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 710 } else { 711 val = 0; 712 } 713 if (val > 65535) 714 val = 65535; 715 rtc_set_memory(s, 0x34, val); 716 rtc_set_memory(s, 0x35, val >> 8); 717 /* memory above 4GiB */ 718 val = pcms->above_4g_mem_size / 65536; 719 rtc_set_memory(s, 0x5b, val); 720 rtc_set_memory(s, 0x5c, val >> 8); 721 rtc_set_memory(s, 0x5d, val >> 16); 722 723 object_property_add_link(OBJECT(pcms), "rtc_state", 724 TYPE_ISA_DEVICE, 725 (Object **)&pcms->rtc, 726 object_property_allow_set_link, 727 OBJ_PROP_LINK_STRONG, &error_abort); 728 object_property_set_link(OBJECT(pcms), OBJECT(s), 729 "rtc_state", &error_abort); 730 731 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 732 733 val = 0; 734 val |= 0x02; /* FPU is there */ 735 val |= 0x04; /* PS/2 mouse installed */ 736 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 737 738 /* hard drives and FDC */ 739 arg.rtc_state = s; 740 arg.idebus[0] = idebus0; 741 arg.idebus[1] = idebus1; 742 qemu_register_reset(pc_cmos_init_late, &arg); 743 } 744 745 #define TYPE_PORT92 "port92" 746 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 747 748 /* port 92 stuff: could be split off */ 749 typedef struct Port92State { 750 ISADevice parent_obj; 751 752 MemoryRegion io; 753 uint8_t outport; 754 qemu_irq a20_out; 755 } Port92State; 756 757 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 758 unsigned size) 759 { 760 Port92State *s = opaque; 761 int oldval = s->outport; 762 763 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 764 s->outport = val; 765 qemu_set_irq(s->a20_out, (val >> 1) & 1); 766 if ((val & 1) && !(oldval & 1)) { 767 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 768 } 769 } 770 771 static uint64_t port92_read(void *opaque, hwaddr addr, 772 unsigned size) 773 { 774 Port92State *s = opaque; 775 uint32_t ret; 776 777 ret = s->outport; 778 DPRINTF("port92: read 0x%02x\n", ret); 779 return ret; 780 } 781 782 static void port92_init(ISADevice *dev, qemu_irq a20_out) 783 { 784 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 785 } 786 787 static const VMStateDescription vmstate_port92_isa = { 788 .name = "port92", 789 .version_id = 1, 790 .minimum_version_id = 1, 791 .fields = (VMStateField[]) { 792 VMSTATE_UINT8(outport, Port92State), 793 VMSTATE_END_OF_LIST() 794 } 795 }; 796 797 static void port92_reset(DeviceState *d) 798 { 799 Port92State *s = PORT92(d); 800 801 s->outport &= ~1; 802 } 803 804 static const MemoryRegionOps port92_ops = { 805 .read = port92_read, 806 .write = port92_write, 807 .impl = { 808 .min_access_size = 1, 809 .max_access_size = 1, 810 }, 811 .endianness = DEVICE_LITTLE_ENDIAN, 812 }; 813 814 static void port92_initfn(Object *obj) 815 { 816 Port92State *s = PORT92(obj); 817 818 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 819 820 s->outport = 0; 821 822 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 823 } 824 825 static void port92_realizefn(DeviceState *dev, Error **errp) 826 { 827 ISADevice *isadev = ISA_DEVICE(dev); 828 Port92State *s = PORT92(dev); 829 830 isa_register_ioport(isadev, &s->io, 0x92); 831 } 832 833 static void port92_class_initfn(ObjectClass *klass, void *data) 834 { 835 DeviceClass *dc = DEVICE_CLASS(klass); 836 837 dc->realize = port92_realizefn; 838 dc->reset = port92_reset; 839 dc->vmsd = &vmstate_port92_isa; 840 /* 841 * Reason: unlike ordinary ISA devices, this one needs additional 842 * wiring: its A20 output line needs to be wired up by 843 * port92_init(). 844 */ 845 dc->user_creatable = false; 846 } 847 848 static const TypeInfo port92_info = { 849 .name = TYPE_PORT92, 850 .parent = TYPE_ISA_DEVICE, 851 .instance_size = sizeof(Port92State), 852 .instance_init = port92_initfn, 853 .class_init = port92_class_initfn, 854 }; 855 856 static void port92_register_types(void) 857 { 858 type_register_static(&port92_info); 859 } 860 861 type_init(port92_register_types) 862 863 static void handle_a20_line_change(void *opaque, int irq, int level) 864 { 865 X86CPU *cpu = opaque; 866 867 /* XXX: send to all CPUs ? */ 868 /* XXX: add logic to handle multiple A20 line sources */ 869 x86_cpu_set_a20(cpu, level); 870 } 871 872 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 873 { 874 int index = le32_to_cpu(e820_reserve.count); 875 struct e820_entry *entry; 876 877 if (type != E820_RAM) { 878 /* old FW_CFG_E820_TABLE entry -- reservations only */ 879 if (index >= E820_NR_ENTRIES) { 880 return -EBUSY; 881 } 882 entry = &e820_reserve.entry[index++]; 883 884 entry->address = cpu_to_le64(address); 885 entry->length = cpu_to_le64(length); 886 entry->type = cpu_to_le32(type); 887 888 e820_reserve.count = cpu_to_le32(index); 889 } 890 891 /* new "etc/e820" file -- include ram too */ 892 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 893 e820_table[e820_entries].address = cpu_to_le64(address); 894 e820_table[e820_entries].length = cpu_to_le64(length); 895 e820_table[e820_entries].type = cpu_to_le32(type); 896 e820_entries++; 897 898 return e820_entries; 899 } 900 901 int e820_get_num_entries(void) 902 { 903 return e820_entries; 904 } 905 906 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 907 { 908 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 909 *address = le64_to_cpu(e820_table[idx].address); 910 *length = le64_to_cpu(e820_table[idx].length); 911 return true; 912 } 913 return false; 914 } 915 916 /* Enables contiguous-apic-ID mode, for compatibility */ 917 static bool compat_apic_id_mode; 918 919 void enable_compat_apic_id_mode(void) 920 { 921 compat_apic_id_mode = true; 922 } 923 924 /* Calculates initial APIC ID for a specific CPU index 925 * 926 * Currently we need to be able to calculate the APIC ID from the CPU index 927 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 928 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 929 * all CPUs up to max_cpus. 930 */ 931 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 932 { 933 uint32_t correct_id; 934 static bool warned; 935 936 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 937 if (compat_apic_id_mode) { 938 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 939 error_report("APIC IDs set in compatibility mode, " 940 "CPU topology won't match the configuration"); 941 warned = true; 942 } 943 return cpu_index; 944 } else { 945 return correct_id; 946 } 947 } 948 949 static void pc_build_smbios(PCMachineState *pcms) 950 { 951 uint8_t *smbios_tables, *smbios_anchor; 952 size_t smbios_tables_len, smbios_anchor_len; 953 struct smbios_phys_mem_area *mem_array; 954 unsigned i, array_count; 955 MachineState *ms = MACHINE(pcms); 956 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 957 958 /* tell smbios about cpuid version and features */ 959 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 960 961 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 962 if (smbios_tables) { 963 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 964 smbios_tables, smbios_tables_len); 965 } 966 967 /* build the array of physical mem area from e820 table */ 968 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 969 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 970 uint64_t addr, len; 971 972 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 973 mem_array[array_count].address = addr; 974 mem_array[array_count].length = len; 975 array_count++; 976 } 977 } 978 smbios_get_tables(mem_array, array_count, 979 &smbios_tables, &smbios_tables_len, 980 &smbios_anchor, &smbios_anchor_len); 981 g_free(mem_array); 982 983 if (smbios_anchor) { 984 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 985 smbios_tables, smbios_tables_len); 986 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 987 smbios_anchor, smbios_anchor_len); 988 } 989 } 990 991 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 992 { 993 FWCfgState *fw_cfg; 994 uint64_t *numa_fw_cfg; 995 int i; 996 const CPUArchIdList *cpus; 997 MachineClass *mc = MACHINE_GET_CLASS(pcms); 998 999 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 1000 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1001 1002 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1003 * 1004 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1005 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1006 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1007 * for CPU hotplug also uses APIC ID and not "CPU index". 1008 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1009 * but the "limit to the APIC ID values SeaBIOS may see". 1010 * 1011 * So for compatibility reasons with old BIOSes we are stuck with 1012 * "etc/max-cpus" actually being apic_id_limit 1013 */ 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1015 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1016 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1017 acpi_tables, acpi_tables_len); 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1019 1020 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1021 &e820_reserve, sizeof(e820_reserve)); 1022 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1023 sizeof(struct e820_entry) * e820_entries); 1024 1025 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1026 /* allocate memory for the NUMA channel: one (64bit) word for the number 1027 * of nodes, one word for each VCPU->node and one word for each node to 1028 * hold the amount of memory. 1029 */ 1030 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1031 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1032 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1033 for (i = 0; i < cpus->len; i++) { 1034 unsigned int apic_id = cpus->cpus[i].arch_id; 1035 assert(apic_id < pcms->apic_id_limit); 1036 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1037 } 1038 for (i = 0; i < nb_numa_nodes; i++) { 1039 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1040 cpu_to_le64(numa_info[i].node_mem); 1041 } 1042 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1043 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1044 sizeof(*numa_fw_cfg)); 1045 1046 return fw_cfg; 1047 } 1048 1049 static long get_file_size(FILE *f) 1050 { 1051 long where, size; 1052 1053 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1054 1055 where = ftell(f); 1056 fseek(f, 0, SEEK_END); 1057 size = ftell(f); 1058 fseek(f, where, SEEK_SET); 1059 1060 return size; 1061 } 1062 1063 struct setup_data { 1064 uint64_t next; 1065 uint32_t type; 1066 uint32_t len; 1067 uint8_t data[0]; 1068 } __attribute__((packed)); 1069 1070 1071 /* 1072 * The entry point into the kernel for PVH boot is different from 1073 * the native entry point. The PVH entry is defined by the x86/HVM 1074 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 1075 * 1076 * This function is passed to load_elf() when it is called from 1077 * load_elfboot() which then additionally checks for an ELF Note of 1078 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 1079 * parse the PVH entry address from the ELF Note. 1080 * 1081 * Due to trickery in elf_opts.h, load_elf() is actually available as 1082 * load_elf32() or load_elf64() and this routine needs to be able 1083 * to deal with being called as 32 or 64 bit. 1084 * 1085 * The address of the PVH entry point is saved to the 'pvh_start_addr' 1086 * global variable. (although the entry point is 32-bit, the kernel 1087 * binary can be either 32-bit or 64-bit). 1088 */ 1089 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 1090 { 1091 size_t *elf_note_data_addr; 1092 1093 /* Check if ELF Note header passed in is valid */ 1094 if (arg1 == NULL) { 1095 return 0; 1096 } 1097 1098 if (is64) { 1099 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 1100 uint64_t nhdr_size64 = sizeof(struct elf64_note); 1101 uint64_t phdr_align = *(uint64_t *)arg2; 1102 uint64_t nhdr_namesz = nhdr64->n_namesz; 1103 1104 elf_note_data_addr = 1105 ((void *)nhdr64) + nhdr_size64 + 1106 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1107 } else { 1108 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 1109 uint32_t nhdr_size32 = sizeof(struct elf32_note); 1110 uint32_t phdr_align = *(uint32_t *)arg2; 1111 uint32_t nhdr_namesz = nhdr32->n_namesz; 1112 1113 elf_note_data_addr = 1114 ((void *)nhdr32) + nhdr_size32 + 1115 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1116 } 1117 1118 pvh_start_addr = *elf_note_data_addr; 1119 1120 return pvh_start_addr; 1121 } 1122 1123 static bool load_elfboot(const char *kernel_filename, 1124 int kernel_file_size, 1125 uint8_t *header, 1126 size_t pvh_xen_start_addr, 1127 FWCfgState *fw_cfg) 1128 { 1129 uint32_t flags = 0; 1130 uint32_t mh_load_addr = 0; 1131 uint32_t elf_kernel_size = 0; 1132 uint64_t elf_entry; 1133 uint64_t elf_low, elf_high; 1134 int kernel_size; 1135 1136 if (ldl_p(header) != 0x464c457f) { 1137 return false; /* no elfboot */ 1138 } 1139 1140 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 1141 flags = elf_is64 ? 1142 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 1143 1144 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 1145 error_report("elfboot unsupported flags = %x", flags); 1146 exit(1); 1147 } 1148 1149 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 1150 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1151 NULL, &elf_note_type, &elf_entry, 1152 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1153 0, 0); 1154 1155 if (kernel_size < 0) { 1156 error_report("Error while loading elf kernel"); 1157 exit(1); 1158 } 1159 mh_load_addr = elf_low; 1160 elf_kernel_size = elf_high - elf_low; 1161 1162 if (pvh_start_addr == 0) { 1163 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1164 exit(1); 1165 } 1166 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1167 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1168 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1169 1170 return true; 1171 } 1172 1173 static void load_linux(PCMachineState *pcms, 1174 FWCfgState *fw_cfg) 1175 { 1176 uint16_t protocol; 1177 int setup_size, kernel_size, cmdline_size; 1178 int dtb_size, setup_data_offset; 1179 uint32_t initrd_max; 1180 uint8_t header[8192], *setup, *kernel; 1181 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1182 FILE *f; 1183 char *vmode; 1184 MachineState *machine = MACHINE(pcms); 1185 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1186 struct setup_data *setup_data; 1187 const char *kernel_filename = machine->kernel_filename; 1188 const char *initrd_filename = machine->initrd_filename; 1189 const char *dtb_filename = machine->dtb; 1190 const char *kernel_cmdline = machine->kernel_cmdline; 1191 1192 /* Align to 16 bytes as a paranoia measure */ 1193 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1194 1195 /* load the kernel header */ 1196 f = fopen(kernel_filename, "rb"); 1197 if (!f || !(kernel_size = get_file_size(f)) || 1198 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1199 MIN(ARRAY_SIZE(header), kernel_size)) { 1200 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1201 kernel_filename, strerror(errno)); 1202 exit(1); 1203 } 1204 1205 /* kernel protocol version */ 1206 #if 0 1207 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1208 #endif 1209 if (ldl_p(header+0x202) == 0x53726448) { 1210 protocol = lduw_p(header+0x206); 1211 } else { 1212 /* 1213 * This could be a multiboot kernel. If it is, let's stop treating it 1214 * like a Linux kernel. 1215 * Note: some multiboot images could be in the ELF format (the same of 1216 * PVH), so we try multiboot first since we check the multiboot magic 1217 * header before to load it. 1218 */ 1219 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1220 kernel_cmdline, kernel_size, header)) { 1221 return; 1222 } 1223 /* 1224 * Check if the file is an uncompressed kernel file (ELF) and load it, 1225 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1226 * If load_elfboot() is successful, populate the fw_cfg info. 1227 */ 1228 if (pcmc->pvh_enabled && 1229 load_elfboot(kernel_filename, kernel_size, 1230 header, pvh_start_addr, fw_cfg)) { 1231 fclose(f); 1232 1233 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1234 strlen(kernel_cmdline) + 1); 1235 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1236 1237 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1238 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1239 header, sizeof(header)); 1240 1241 /* load initrd */ 1242 if (initrd_filename) { 1243 gsize initrd_size; 1244 gchar *initrd_data; 1245 GError *gerr = NULL; 1246 1247 if (!g_file_get_contents(initrd_filename, &initrd_data, 1248 &initrd_size, &gerr)) { 1249 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1250 initrd_filename, gerr->message); 1251 exit(1); 1252 } 1253 1254 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1255 if (initrd_size >= initrd_max) { 1256 fprintf(stderr, "qemu: initrd is too large, cannot support." 1257 "(max: %"PRIu32", need %"PRId64")\n", 1258 initrd_max, (uint64_t)initrd_size); 1259 exit(1); 1260 } 1261 1262 initrd_addr = (initrd_max - initrd_size) & ~4095; 1263 1264 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1265 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1266 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1267 initrd_size); 1268 } 1269 1270 option_rom[nb_option_roms].bootindex = 0; 1271 option_rom[nb_option_roms].name = "pvh.bin"; 1272 nb_option_roms++; 1273 1274 return; 1275 } 1276 protocol = 0; 1277 } 1278 1279 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1280 /* Low kernel */ 1281 real_addr = 0x90000; 1282 cmdline_addr = 0x9a000 - cmdline_size; 1283 prot_addr = 0x10000; 1284 } else if (protocol < 0x202) { 1285 /* High but ancient kernel */ 1286 real_addr = 0x90000; 1287 cmdline_addr = 0x9a000 - cmdline_size; 1288 prot_addr = 0x100000; 1289 } else { 1290 /* High and recent kernel */ 1291 real_addr = 0x10000; 1292 cmdline_addr = 0x20000; 1293 prot_addr = 0x100000; 1294 } 1295 1296 #if 0 1297 fprintf(stderr, 1298 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1299 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1300 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1301 real_addr, 1302 cmdline_addr, 1303 prot_addr); 1304 #endif 1305 1306 /* highest address for loading the initrd */ 1307 if (protocol >= 0x20c && 1308 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1309 /* 1310 * Linux has supported initrd up to 4 GB for a very long time (2007, 1311 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1312 * though it only sets initrd_max to 2 GB to "work around bootloader 1313 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1314 * has supported this. 1315 * 1316 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1317 * be loaded into any address. 1318 * 1319 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1320 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1321 * field). 1322 * 1323 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1324 */ 1325 initrd_max = UINT32_MAX; 1326 } else if (protocol >= 0x203) { 1327 initrd_max = ldl_p(header+0x22c); 1328 } else { 1329 initrd_max = 0x37ffffff; 1330 } 1331 1332 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1333 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1334 } 1335 1336 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1337 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1338 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1339 1340 if (protocol >= 0x202) { 1341 stl_p(header+0x228, cmdline_addr); 1342 } else { 1343 stw_p(header+0x20, 0xA33F); 1344 stw_p(header+0x22, cmdline_addr-real_addr); 1345 } 1346 1347 /* handle vga= parameter */ 1348 vmode = strstr(kernel_cmdline, "vga="); 1349 if (vmode) { 1350 unsigned int video_mode; 1351 /* skip "vga=" */ 1352 vmode += 4; 1353 if (!strncmp(vmode, "normal", 6)) { 1354 video_mode = 0xffff; 1355 } else if (!strncmp(vmode, "ext", 3)) { 1356 video_mode = 0xfffe; 1357 } else if (!strncmp(vmode, "ask", 3)) { 1358 video_mode = 0xfffd; 1359 } else { 1360 video_mode = strtol(vmode, NULL, 0); 1361 } 1362 stw_p(header+0x1fa, video_mode); 1363 } 1364 1365 /* loader type */ 1366 /* High nybble = B reserved for QEMU; low nybble is revision number. 1367 If this code is substantially changed, you may want to consider 1368 incrementing the revision. */ 1369 if (protocol >= 0x200) { 1370 header[0x210] = 0xB0; 1371 } 1372 /* heap */ 1373 if (protocol >= 0x201) { 1374 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1375 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1376 } 1377 1378 /* load initrd */ 1379 if (initrd_filename) { 1380 gsize initrd_size; 1381 gchar *initrd_data; 1382 GError *gerr = NULL; 1383 1384 if (protocol < 0x200) { 1385 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1386 exit(1); 1387 } 1388 1389 if (!g_file_get_contents(initrd_filename, &initrd_data, 1390 &initrd_size, &gerr)) { 1391 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1392 initrd_filename, gerr->message); 1393 exit(1); 1394 } 1395 if (initrd_size >= initrd_max) { 1396 fprintf(stderr, "qemu: initrd is too large, cannot support." 1397 "(max: %"PRIu32", need %"PRId64")\n", 1398 initrd_max, (uint64_t)initrd_size); 1399 exit(1); 1400 } 1401 1402 initrd_addr = (initrd_max-initrd_size) & ~4095; 1403 1404 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1405 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1406 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1407 1408 stl_p(header+0x218, initrd_addr); 1409 stl_p(header+0x21c, initrd_size); 1410 } 1411 1412 /* load kernel and setup */ 1413 setup_size = header[0x1f1]; 1414 if (setup_size == 0) { 1415 setup_size = 4; 1416 } 1417 setup_size = (setup_size+1)*512; 1418 if (setup_size > kernel_size) { 1419 fprintf(stderr, "qemu: invalid kernel header\n"); 1420 exit(1); 1421 } 1422 kernel_size -= setup_size; 1423 1424 setup = g_malloc(setup_size); 1425 kernel = g_malloc(kernel_size); 1426 fseek(f, 0, SEEK_SET); 1427 if (fread(setup, 1, setup_size, f) != setup_size) { 1428 fprintf(stderr, "fread() failed\n"); 1429 exit(1); 1430 } 1431 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1432 fprintf(stderr, "fread() failed\n"); 1433 exit(1); 1434 } 1435 fclose(f); 1436 1437 /* append dtb to kernel */ 1438 if (dtb_filename) { 1439 if (protocol < 0x209) { 1440 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1441 exit(1); 1442 } 1443 1444 dtb_size = get_image_size(dtb_filename); 1445 if (dtb_size <= 0) { 1446 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1447 dtb_filename, strerror(errno)); 1448 exit(1); 1449 } 1450 1451 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1452 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1453 kernel = g_realloc(kernel, kernel_size); 1454 1455 stq_p(header+0x250, prot_addr + setup_data_offset); 1456 1457 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1458 setup_data->next = 0; 1459 setup_data->type = cpu_to_le32(SETUP_DTB); 1460 setup_data->len = cpu_to_le32(dtb_size); 1461 1462 load_image_size(dtb_filename, setup_data->data, dtb_size); 1463 } 1464 1465 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1466 1467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1468 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1469 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1470 1471 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1472 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1473 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1474 1475 option_rom[nb_option_roms].bootindex = 0; 1476 option_rom[nb_option_roms].name = "linuxboot.bin"; 1477 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1478 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1479 } 1480 nb_option_roms++; 1481 } 1482 1483 #define NE2000_NB_MAX 6 1484 1485 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1486 0x280, 0x380 }; 1487 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1488 1489 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1490 { 1491 static int nb_ne2k = 0; 1492 1493 if (nb_ne2k == NE2000_NB_MAX) 1494 return; 1495 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1496 ne2000_irq[nb_ne2k], nd); 1497 nb_ne2k++; 1498 } 1499 1500 DeviceState *cpu_get_current_apic(void) 1501 { 1502 if (current_cpu) { 1503 X86CPU *cpu = X86_CPU(current_cpu); 1504 return cpu->apic_state; 1505 } else { 1506 return NULL; 1507 } 1508 } 1509 1510 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1511 { 1512 X86CPU *cpu = opaque; 1513 1514 if (level) { 1515 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1516 } 1517 } 1518 1519 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) 1520 { 1521 Object *cpu = NULL; 1522 Error *local_err = NULL; 1523 1524 cpu = object_new(typename); 1525 1526 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1527 object_property_set_bool(cpu, true, "realized", &local_err); 1528 1529 object_unref(cpu); 1530 error_propagate(errp, local_err); 1531 } 1532 1533 void pc_hot_add_cpu(const int64_t id, Error **errp) 1534 { 1535 MachineState *ms = MACHINE(qdev_get_machine()); 1536 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1537 Error *local_err = NULL; 1538 1539 if (id < 0) { 1540 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1541 return; 1542 } 1543 1544 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1545 error_setg(errp, "Unable to add CPU: %" PRIi64 1546 ", resulting APIC ID (%" PRIi64 ") is too large", 1547 id, apic_id); 1548 return; 1549 } 1550 1551 pc_new_cpu(ms->cpu_type, apic_id, &local_err); 1552 if (local_err) { 1553 error_propagate(errp, local_err); 1554 return; 1555 } 1556 } 1557 1558 void pc_cpus_init(PCMachineState *pcms) 1559 { 1560 int i; 1561 const CPUArchIdList *possible_cpus; 1562 MachineState *ms = MACHINE(pcms); 1563 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1564 1565 /* Calculates the limit to CPU APIC ID values 1566 * 1567 * Limit for the APIC ID value, so that all 1568 * CPU APIC IDs are < pcms->apic_id_limit. 1569 * 1570 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1571 */ 1572 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1573 possible_cpus = mc->possible_cpu_arch_ids(ms); 1574 for (i = 0; i < smp_cpus; i++) { 1575 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, 1576 &error_fatal); 1577 } 1578 } 1579 1580 static void pc_build_feature_control_file(PCMachineState *pcms) 1581 { 1582 MachineState *ms = MACHINE(pcms); 1583 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1584 CPUX86State *env = &cpu->env; 1585 uint32_t unused, ecx, edx; 1586 uint64_t feature_control_bits = 0; 1587 uint64_t *val; 1588 1589 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1590 if (ecx & CPUID_EXT_VMX) { 1591 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1592 } 1593 1594 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1595 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1596 (env->mcg_cap & MCG_LMCE_P)) { 1597 feature_control_bits |= FEATURE_CONTROL_LMCE; 1598 } 1599 1600 if (!feature_control_bits) { 1601 return; 1602 } 1603 1604 val = g_malloc(sizeof(*val)); 1605 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1606 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1607 } 1608 1609 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1610 { 1611 if (cpus_count > 0xff) { 1612 /* If the number of CPUs can't be represented in 8 bits, the 1613 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1614 * to make old BIOSes fail more predictably. 1615 */ 1616 rtc_set_memory(rtc, 0x5f, 0); 1617 } else { 1618 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1619 } 1620 } 1621 1622 static 1623 void pc_machine_done(Notifier *notifier, void *data) 1624 { 1625 PCMachineState *pcms = container_of(notifier, 1626 PCMachineState, machine_done); 1627 PCIBus *bus = pcms->bus; 1628 1629 /* set the number of CPUs */ 1630 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1631 1632 if (bus) { 1633 int extra_hosts = 0; 1634 1635 QLIST_FOREACH(bus, &bus->child, sibling) { 1636 /* look for expander root buses */ 1637 if (pci_bus_is_root(bus)) { 1638 extra_hosts++; 1639 } 1640 } 1641 if (extra_hosts && pcms->fw_cfg) { 1642 uint64_t *val = g_malloc(sizeof(*val)); 1643 *val = cpu_to_le64(extra_hosts); 1644 fw_cfg_add_file(pcms->fw_cfg, 1645 "etc/extra-pci-roots", val, sizeof(*val)); 1646 } 1647 } 1648 1649 acpi_setup(); 1650 if (pcms->fw_cfg) { 1651 pc_build_smbios(pcms); 1652 pc_build_feature_control_file(pcms); 1653 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1654 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1655 } 1656 1657 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1658 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1659 1660 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1661 iommu->intr_eim != ON_OFF_AUTO_ON) { 1662 error_report("current -smp configuration requires " 1663 "Extended Interrupt Mode enabled. " 1664 "You can add an IOMMU using: " 1665 "-device intel-iommu,intremap=on,eim=on"); 1666 exit(EXIT_FAILURE); 1667 } 1668 } 1669 } 1670 1671 void pc_guest_info_init(PCMachineState *pcms) 1672 { 1673 int i; 1674 1675 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1676 pcms->numa_nodes = nb_numa_nodes; 1677 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1678 sizeof *pcms->node_mem); 1679 for (i = 0; i < nb_numa_nodes; i++) { 1680 pcms->node_mem[i] = numa_info[i].node_mem; 1681 } 1682 1683 pcms->machine_done.notify = pc_machine_done; 1684 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1685 } 1686 1687 /* setup pci memory address space mapping into system address space */ 1688 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1689 MemoryRegion *pci_address_space) 1690 { 1691 /* Set to lower priority than RAM */ 1692 memory_region_add_subregion_overlap(system_memory, 0x0, 1693 pci_address_space, -1); 1694 } 1695 1696 void xen_load_linux(PCMachineState *pcms) 1697 { 1698 int i; 1699 FWCfgState *fw_cfg; 1700 1701 assert(MACHINE(pcms)->kernel_filename != NULL); 1702 1703 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1704 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1705 rom_set_fw(fw_cfg); 1706 1707 load_linux(pcms, fw_cfg); 1708 for (i = 0; i < nb_option_roms; i++) { 1709 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1710 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1711 !strcmp(option_rom[i].name, "pvh.bin") || 1712 !strcmp(option_rom[i].name, "multiboot.bin")); 1713 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1714 } 1715 pcms->fw_cfg = fw_cfg; 1716 } 1717 1718 void pc_memory_init(PCMachineState *pcms, 1719 MemoryRegion *system_memory, 1720 MemoryRegion *rom_memory, 1721 MemoryRegion **ram_memory) 1722 { 1723 int linux_boot, i; 1724 MemoryRegion *ram, *option_rom_mr; 1725 MemoryRegion *ram_below_4g, *ram_above_4g; 1726 FWCfgState *fw_cfg; 1727 MachineState *machine = MACHINE(pcms); 1728 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1729 1730 assert(machine->ram_size == pcms->below_4g_mem_size + 1731 pcms->above_4g_mem_size); 1732 1733 linux_boot = (machine->kernel_filename != NULL); 1734 1735 /* Allocate RAM. We allocate it as a single memory region and use 1736 * aliases to address portions of it, mostly for backwards compatibility 1737 * with older qemus that used qemu_ram_alloc(). 1738 */ 1739 ram = g_malloc(sizeof(*ram)); 1740 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1741 machine->ram_size); 1742 *ram_memory = ram; 1743 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1744 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1745 0, pcms->below_4g_mem_size); 1746 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1747 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1748 if (pcms->above_4g_mem_size > 0) { 1749 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1750 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1751 pcms->below_4g_mem_size, 1752 pcms->above_4g_mem_size); 1753 memory_region_add_subregion(system_memory, 0x100000000ULL, 1754 ram_above_4g); 1755 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1756 } 1757 1758 if (!pcmc->has_reserved_memory && 1759 (machine->ram_slots || 1760 (machine->maxram_size > machine->ram_size))) { 1761 MachineClass *mc = MACHINE_GET_CLASS(machine); 1762 1763 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1764 mc->name); 1765 exit(EXIT_FAILURE); 1766 } 1767 1768 /* always allocate the device memory information */ 1769 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1770 1771 /* initialize device memory address space */ 1772 if (pcmc->has_reserved_memory && 1773 (machine->ram_size < machine->maxram_size)) { 1774 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1775 1776 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1777 error_report("unsupported amount of memory slots: %"PRIu64, 1778 machine->ram_slots); 1779 exit(EXIT_FAILURE); 1780 } 1781 1782 if (QEMU_ALIGN_UP(machine->maxram_size, 1783 TARGET_PAGE_SIZE) != machine->maxram_size) { 1784 error_report("maximum memory size must by aligned to multiple of " 1785 "%d bytes", TARGET_PAGE_SIZE); 1786 exit(EXIT_FAILURE); 1787 } 1788 1789 machine->device_memory->base = 1790 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1791 1792 if (pcmc->enforce_aligned_dimm) { 1793 /* size device region assuming 1G page max alignment per slot */ 1794 device_mem_size += (1 * GiB) * machine->ram_slots; 1795 } 1796 1797 if ((machine->device_memory->base + device_mem_size) < 1798 device_mem_size) { 1799 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1800 machine->maxram_size); 1801 exit(EXIT_FAILURE); 1802 } 1803 1804 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1805 "device-memory", device_mem_size); 1806 memory_region_add_subregion(system_memory, machine->device_memory->base, 1807 &machine->device_memory->mr); 1808 } 1809 1810 /* Initialize PC system firmware */ 1811 pc_system_firmware_init(pcms, rom_memory); 1812 1813 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1814 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1815 &error_fatal); 1816 if (pcmc->pci_enabled) { 1817 memory_region_set_readonly(option_rom_mr, true); 1818 } 1819 memory_region_add_subregion_overlap(rom_memory, 1820 PC_ROM_MIN_VGA, 1821 option_rom_mr, 1822 1); 1823 1824 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1825 1826 rom_set_fw(fw_cfg); 1827 1828 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1829 uint64_t *val = g_malloc(sizeof(*val)); 1830 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1831 uint64_t res_mem_end = machine->device_memory->base; 1832 1833 if (!pcmc->broken_reserved_end) { 1834 res_mem_end += memory_region_size(&machine->device_memory->mr); 1835 } 1836 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1837 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1838 } 1839 1840 if (linux_boot) { 1841 load_linux(pcms, fw_cfg); 1842 } 1843 1844 for (i = 0; i < nb_option_roms; i++) { 1845 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1846 } 1847 pcms->fw_cfg = fw_cfg; 1848 1849 /* Init default IOAPIC address space */ 1850 pcms->ioapic_as = &address_space_memory; 1851 } 1852 1853 /* 1854 * The 64bit pci hole starts after "above 4G RAM" and 1855 * potentially the space reserved for memory hotplug. 1856 */ 1857 uint64_t pc_pci_hole64_start(void) 1858 { 1859 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1860 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1861 MachineState *ms = MACHINE(pcms); 1862 uint64_t hole64_start = 0; 1863 1864 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1865 hole64_start = ms->device_memory->base; 1866 if (!pcmc->broken_reserved_end) { 1867 hole64_start += memory_region_size(&ms->device_memory->mr); 1868 } 1869 } else { 1870 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1871 } 1872 1873 return ROUND_UP(hole64_start, 1 * GiB); 1874 } 1875 1876 qemu_irq pc_allocate_cpu_irq(void) 1877 { 1878 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1879 } 1880 1881 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1882 { 1883 DeviceState *dev = NULL; 1884 1885 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1886 if (pci_bus) { 1887 PCIDevice *pcidev = pci_vga_init(pci_bus); 1888 dev = pcidev ? &pcidev->qdev : NULL; 1889 } else if (isa_bus) { 1890 ISADevice *isadev = isa_vga_init(isa_bus); 1891 dev = isadev ? DEVICE(isadev) : NULL; 1892 } 1893 rom_reset_order_override(); 1894 return dev; 1895 } 1896 1897 static const MemoryRegionOps ioport80_io_ops = { 1898 .write = ioport80_write, 1899 .read = ioport80_read, 1900 .endianness = DEVICE_NATIVE_ENDIAN, 1901 .impl = { 1902 .min_access_size = 1, 1903 .max_access_size = 1, 1904 }, 1905 }; 1906 1907 static const MemoryRegionOps ioportF0_io_ops = { 1908 .write = ioportF0_write, 1909 .read = ioportF0_read, 1910 .endianness = DEVICE_NATIVE_ENDIAN, 1911 .impl = { 1912 .min_access_size = 1, 1913 .max_access_size = 1, 1914 }, 1915 }; 1916 1917 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1918 { 1919 int i; 1920 DriveInfo *fd[MAX_FD]; 1921 qemu_irq *a20_line; 1922 ISADevice *i8042, *port92, *vmmouse; 1923 1924 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1925 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1926 1927 for (i = 0; i < MAX_FD; i++) { 1928 fd[i] = drive_get(IF_FLOPPY, 0, i); 1929 create_fdctrl |= !!fd[i]; 1930 } 1931 if (create_fdctrl) { 1932 fdctrl_init_isa(isa_bus, fd); 1933 } 1934 1935 i8042 = isa_create_simple(isa_bus, "i8042"); 1936 if (!no_vmport) { 1937 vmport_init(isa_bus); 1938 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1939 } else { 1940 vmmouse = NULL; 1941 } 1942 if (vmmouse) { 1943 DeviceState *dev = DEVICE(vmmouse); 1944 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1945 qdev_init_nofail(dev); 1946 } 1947 port92 = isa_create_simple(isa_bus, "port92"); 1948 1949 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1950 i8042_setup_a20_line(i8042, a20_line[0]); 1951 port92_init(port92, a20_line[1]); 1952 g_free(a20_line); 1953 } 1954 1955 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1956 ISADevice **rtc_state, 1957 bool create_fdctrl, 1958 bool no_vmport, 1959 bool has_pit, 1960 uint32_t hpet_irqs) 1961 { 1962 int i; 1963 DeviceState *hpet = NULL; 1964 int pit_isa_irq = 0; 1965 qemu_irq pit_alt_irq = NULL; 1966 qemu_irq rtc_irq = NULL; 1967 ISADevice *pit = NULL; 1968 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1969 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1970 1971 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1972 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1973 1974 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1975 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1976 1977 /* 1978 * Check if an HPET shall be created. 1979 * 1980 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1981 * when the HPET wants to take over. Thus we have to disable the latter. 1982 */ 1983 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1984 /* In order to set property, here not using sysbus_try_create_simple */ 1985 hpet = qdev_try_create(NULL, TYPE_HPET); 1986 if (hpet) { 1987 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1988 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1989 * IRQ8 and IRQ2. 1990 */ 1991 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1992 HPET_INTCAP, NULL); 1993 if (!compat) { 1994 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1995 } 1996 qdev_init_nofail(hpet); 1997 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1998 1999 for (i = 0; i < GSI_NUM_PINS; i++) { 2000 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 2001 } 2002 pit_isa_irq = -1; 2003 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 2004 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 2005 } 2006 } 2007 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 2008 2009 qemu_register_boot_set(pc_boot_set, *rtc_state); 2010 2011 if (!xen_enabled() && has_pit) { 2012 if (kvm_pit_in_kernel()) { 2013 pit = kvm_pit_init(isa_bus, 0x40); 2014 } else { 2015 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 2016 } 2017 if (hpet) { 2018 /* connect PIT to output control line of the HPET */ 2019 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 2020 } 2021 pcspk_init(isa_bus, pit); 2022 } 2023 2024 i8257_dma_init(isa_bus, 0); 2025 2026 /* Super I/O */ 2027 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 2028 } 2029 2030 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 2031 { 2032 int i; 2033 2034 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 2035 for (i = 0; i < nb_nics; i++) { 2036 NICInfo *nd = &nd_table[i]; 2037 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 2038 2039 if (g_str_equal(model, "ne2k_isa")) { 2040 pc_init_ne2k_isa(isa_bus, nd); 2041 } else { 2042 pci_nic_init_nofail(nd, pci_bus, model, NULL); 2043 } 2044 } 2045 rom_reset_order_override(); 2046 } 2047 2048 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 2049 { 2050 DeviceState *dev; 2051 SysBusDevice *d; 2052 unsigned int i; 2053 2054 if (kvm_ioapic_in_kernel()) { 2055 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 2056 } else { 2057 dev = qdev_create(NULL, TYPE_IOAPIC); 2058 } 2059 if (parent_name) { 2060 object_property_add_child(object_resolve_path(parent_name, NULL), 2061 "ioapic", OBJECT(dev), NULL); 2062 } 2063 qdev_init_nofail(dev); 2064 d = SYS_BUS_DEVICE(dev); 2065 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2066 2067 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2068 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2069 } 2070 } 2071 2072 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2073 Error **errp) 2074 { 2075 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2076 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2077 const MachineState *ms = MACHINE(hotplug_dev); 2078 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2079 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2080 Error *local_err = NULL; 2081 2082 /* 2083 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2084 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2085 * addition to cover this case. 2086 */ 2087 if (!pcms->acpi_dev || !acpi_enabled) { 2088 error_setg(errp, 2089 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2090 return; 2091 } 2092 2093 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2094 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2095 return; 2096 } 2097 2098 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 2099 if (local_err) { 2100 error_propagate(errp, local_err); 2101 return; 2102 } 2103 2104 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2105 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2106 } 2107 2108 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2109 DeviceState *dev, Error **errp) 2110 { 2111 Error *local_err = NULL; 2112 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2113 MachineState *ms = MACHINE(hotplug_dev); 2114 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2115 2116 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2117 if (local_err) { 2118 goto out; 2119 } 2120 2121 if (is_nvdimm) { 2122 nvdimm_plug(ms->nvdimms_state); 2123 } 2124 2125 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2126 out: 2127 error_propagate(errp, local_err); 2128 } 2129 2130 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2131 DeviceState *dev, Error **errp) 2132 { 2133 Error *local_err = NULL; 2134 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2135 2136 /* 2137 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2138 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2139 * addition to cover this case. 2140 */ 2141 if (!pcms->acpi_dev || !acpi_enabled) { 2142 error_setg(&local_err, 2143 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2144 goto out; 2145 } 2146 2147 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2148 error_setg(&local_err, 2149 "nvdimm device hot unplug is not supported yet."); 2150 goto out; 2151 } 2152 2153 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2154 &local_err); 2155 out: 2156 error_propagate(errp, local_err); 2157 } 2158 2159 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2160 DeviceState *dev, Error **errp) 2161 { 2162 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2163 Error *local_err = NULL; 2164 2165 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2166 if (local_err) { 2167 goto out; 2168 } 2169 2170 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2171 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2172 out: 2173 error_propagate(errp, local_err); 2174 } 2175 2176 static int pc_apic_cmp(const void *a, const void *b) 2177 { 2178 CPUArchId *apic_a = (CPUArchId *)a; 2179 CPUArchId *apic_b = (CPUArchId *)b; 2180 2181 return apic_a->arch_id - apic_b->arch_id; 2182 } 2183 2184 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2185 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2186 * entry corresponding to CPU's apic_id returns NULL. 2187 */ 2188 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2189 { 2190 CPUArchId apic_id, *found_cpu; 2191 2192 apic_id.arch_id = id; 2193 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2194 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2195 pc_apic_cmp); 2196 if (found_cpu && idx) { 2197 *idx = found_cpu - ms->possible_cpus->cpus; 2198 } 2199 return found_cpu; 2200 } 2201 2202 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2203 DeviceState *dev, Error **errp) 2204 { 2205 CPUArchId *found_cpu; 2206 Error *local_err = NULL; 2207 X86CPU *cpu = X86_CPU(dev); 2208 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2209 2210 if (pcms->acpi_dev) { 2211 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2212 if (local_err) { 2213 goto out; 2214 } 2215 } 2216 2217 /* increment the number of CPUs */ 2218 pcms->boot_cpus++; 2219 if (pcms->rtc) { 2220 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2221 } 2222 if (pcms->fw_cfg) { 2223 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2224 } 2225 2226 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2227 found_cpu->cpu = OBJECT(dev); 2228 out: 2229 error_propagate(errp, local_err); 2230 } 2231 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2232 DeviceState *dev, Error **errp) 2233 { 2234 int idx = -1; 2235 Error *local_err = NULL; 2236 X86CPU *cpu = X86_CPU(dev); 2237 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2238 2239 if (!pcms->acpi_dev) { 2240 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2241 goto out; 2242 } 2243 2244 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2245 assert(idx != -1); 2246 if (idx == 0) { 2247 error_setg(&local_err, "Boot CPU is unpluggable"); 2248 goto out; 2249 } 2250 2251 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2252 &local_err); 2253 if (local_err) { 2254 goto out; 2255 } 2256 2257 out: 2258 error_propagate(errp, local_err); 2259 2260 } 2261 2262 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2263 DeviceState *dev, Error **errp) 2264 { 2265 CPUArchId *found_cpu; 2266 Error *local_err = NULL; 2267 X86CPU *cpu = X86_CPU(dev); 2268 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2269 2270 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2271 if (local_err) { 2272 goto out; 2273 } 2274 2275 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2276 found_cpu->cpu = NULL; 2277 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2278 2279 /* decrement the number of CPUs */ 2280 pcms->boot_cpus--; 2281 /* Update the number of CPUs in CMOS */ 2282 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2283 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2284 out: 2285 error_propagate(errp, local_err); 2286 } 2287 2288 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2289 DeviceState *dev, Error **errp) 2290 { 2291 int idx; 2292 CPUState *cs; 2293 CPUArchId *cpu_slot; 2294 X86CPUTopoInfo topo; 2295 X86CPU *cpu = X86_CPU(dev); 2296 MachineState *ms = MACHINE(hotplug_dev); 2297 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2298 2299 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2300 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2301 ms->cpu_type); 2302 return; 2303 } 2304 2305 /* if APIC ID is not set, set it based on socket/core/thread properties */ 2306 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2307 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 2308 2309 if (cpu->socket_id < 0) { 2310 error_setg(errp, "CPU socket-id is not set"); 2311 return; 2312 } else if (cpu->socket_id > max_socket) { 2313 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2314 cpu->socket_id, max_socket); 2315 return; 2316 } 2317 if (cpu->core_id < 0) { 2318 error_setg(errp, "CPU core-id is not set"); 2319 return; 2320 } else if (cpu->core_id > (smp_cores - 1)) { 2321 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2322 cpu->core_id, smp_cores - 1); 2323 return; 2324 } 2325 if (cpu->thread_id < 0) { 2326 error_setg(errp, "CPU thread-id is not set"); 2327 return; 2328 } else if (cpu->thread_id > (smp_threads - 1)) { 2329 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2330 cpu->thread_id, smp_threads - 1); 2331 return; 2332 } 2333 2334 topo.pkg_id = cpu->socket_id; 2335 topo.core_id = cpu->core_id; 2336 topo.smt_id = cpu->thread_id; 2337 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 2338 } 2339 2340 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2341 if (!cpu_slot) { 2342 MachineState *ms = MACHINE(pcms); 2343 2344 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2345 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 2346 " APIC ID %" PRIu32 ", valid index range 0:%d", 2347 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 2348 ms->possible_cpus->len - 1); 2349 return; 2350 } 2351 2352 if (cpu_slot->cpu) { 2353 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2354 idx, cpu->apic_id); 2355 return; 2356 } 2357 2358 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2359 * so that machine_query_hotpluggable_cpus would show correct values 2360 */ 2361 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2362 * once -smp refactoring is complete and there will be CPU private 2363 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2364 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2365 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2366 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2367 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2368 return; 2369 } 2370 cpu->socket_id = topo.pkg_id; 2371 2372 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2373 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2374 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2375 return; 2376 } 2377 cpu->core_id = topo.core_id; 2378 2379 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2380 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2381 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2382 return; 2383 } 2384 cpu->thread_id = topo.smt_id; 2385 2386 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 2387 !kvm_hv_vpindex_settable()) { 2388 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2389 return; 2390 } 2391 2392 cs = CPU(cpu); 2393 cs->cpu_index = idx; 2394 2395 numa_cpu_pre_plug(cpu_slot, dev, errp); 2396 } 2397 2398 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2399 DeviceState *dev, Error **errp) 2400 { 2401 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2402 pc_memory_pre_plug(hotplug_dev, dev, errp); 2403 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2404 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2405 } 2406 } 2407 2408 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2409 DeviceState *dev, Error **errp) 2410 { 2411 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2412 pc_memory_plug(hotplug_dev, dev, errp); 2413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2414 pc_cpu_plug(hotplug_dev, dev, errp); 2415 } 2416 } 2417 2418 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2419 DeviceState *dev, Error **errp) 2420 { 2421 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2422 pc_memory_unplug_request(hotplug_dev, dev, errp); 2423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2424 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2425 } else { 2426 error_setg(errp, "acpi: device unplug request for not supported device" 2427 " type: %s", object_get_typename(OBJECT(dev))); 2428 } 2429 } 2430 2431 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2432 DeviceState *dev, Error **errp) 2433 { 2434 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2435 pc_memory_unplug(hotplug_dev, dev, errp); 2436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2437 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2438 } else { 2439 error_setg(errp, "acpi: device unplug for not supported device" 2440 " type: %s", object_get_typename(OBJECT(dev))); 2441 } 2442 } 2443 2444 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2445 DeviceState *dev) 2446 { 2447 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2448 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2449 return HOTPLUG_HANDLER(machine); 2450 } 2451 2452 return NULL; 2453 } 2454 2455 static void 2456 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2457 const char *name, void *opaque, 2458 Error **errp) 2459 { 2460 MachineState *ms = MACHINE(obj); 2461 int64_t value = memory_region_size(&ms->device_memory->mr); 2462 2463 visit_type_int(v, name, &value, errp); 2464 } 2465 2466 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2467 const char *name, void *opaque, 2468 Error **errp) 2469 { 2470 PCMachineState *pcms = PC_MACHINE(obj); 2471 uint64_t value = pcms->max_ram_below_4g; 2472 2473 visit_type_size(v, name, &value, errp); 2474 } 2475 2476 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2477 const char *name, void *opaque, 2478 Error **errp) 2479 { 2480 PCMachineState *pcms = PC_MACHINE(obj); 2481 Error *error = NULL; 2482 uint64_t value; 2483 2484 visit_type_size(v, name, &value, &error); 2485 if (error) { 2486 error_propagate(errp, error); 2487 return; 2488 } 2489 if (value > 4 * GiB) { 2490 error_setg(&error, 2491 "Machine option 'max-ram-below-4g=%"PRIu64 2492 "' expects size less than or equal to 4G", value); 2493 error_propagate(errp, error); 2494 return; 2495 } 2496 2497 if (value < 1 * MiB) { 2498 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2499 "BIOS may not work with less than 1MiB", value); 2500 } 2501 2502 pcms->max_ram_below_4g = value; 2503 } 2504 2505 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2506 void *opaque, Error **errp) 2507 { 2508 PCMachineState *pcms = PC_MACHINE(obj); 2509 OnOffAuto vmport = pcms->vmport; 2510 2511 visit_type_OnOffAuto(v, name, &vmport, errp); 2512 } 2513 2514 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2515 void *opaque, Error **errp) 2516 { 2517 PCMachineState *pcms = PC_MACHINE(obj); 2518 2519 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2520 } 2521 2522 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2523 { 2524 bool smm_available = false; 2525 2526 if (pcms->smm == ON_OFF_AUTO_OFF) { 2527 return false; 2528 } 2529 2530 if (tcg_enabled() || qtest_enabled()) { 2531 smm_available = true; 2532 } else if (kvm_enabled()) { 2533 smm_available = kvm_has_smm(); 2534 } 2535 2536 if (smm_available) { 2537 return true; 2538 } 2539 2540 if (pcms->smm == ON_OFF_AUTO_ON) { 2541 error_report("System Management Mode not supported by this hypervisor."); 2542 exit(1); 2543 } 2544 return false; 2545 } 2546 2547 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2548 void *opaque, Error **errp) 2549 { 2550 PCMachineState *pcms = PC_MACHINE(obj); 2551 OnOffAuto smm = pcms->smm; 2552 2553 visit_type_OnOffAuto(v, name, &smm, errp); 2554 } 2555 2556 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2557 void *opaque, Error **errp) 2558 { 2559 PCMachineState *pcms = PC_MACHINE(obj); 2560 2561 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2562 } 2563 2564 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2565 { 2566 PCMachineState *pcms = PC_MACHINE(obj); 2567 2568 return pcms->smbus_enabled; 2569 } 2570 2571 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2572 { 2573 PCMachineState *pcms = PC_MACHINE(obj); 2574 2575 pcms->smbus_enabled = value; 2576 } 2577 2578 static bool pc_machine_get_sata(Object *obj, Error **errp) 2579 { 2580 PCMachineState *pcms = PC_MACHINE(obj); 2581 2582 return pcms->sata_enabled; 2583 } 2584 2585 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2586 { 2587 PCMachineState *pcms = PC_MACHINE(obj); 2588 2589 pcms->sata_enabled = value; 2590 } 2591 2592 static bool pc_machine_get_pit(Object *obj, Error **errp) 2593 { 2594 PCMachineState *pcms = PC_MACHINE(obj); 2595 2596 return pcms->pit_enabled; 2597 } 2598 2599 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2600 { 2601 PCMachineState *pcms = PC_MACHINE(obj); 2602 2603 pcms->pit_enabled = value; 2604 } 2605 2606 static void pc_machine_initfn(Object *obj) 2607 { 2608 PCMachineState *pcms = PC_MACHINE(obj); 2609 2610 pcms->max_ram_below_4g = 0; /* use default */ 2611 pcms->smm = ON_OFF_AUTO_AUTO; 2612 pcms->vmport = ON_OFF_AUTO_AUTO; 2613 /* acpi build is enabled by default if machine supports it */ 2614 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2615 pcms->smbus_enabled = true; 2616 pcms->sata_enabled = true; 2617 pcms->pit_enabled = true; 2618 2619 pc_system_flash_create(pcms); 2620 } 2621 2622 static void pc_machine_reset(void) 2623 { 2624 CPUState *cs; 2625 X86CPU *cpu; 2626 2627 qemu_devices_reset(); 2628 2629 /* Reset APIC after devices have been reset to cancel 2630 * any changes that qemu_devices_reset() might have done. 2631 */ 2632 CPU_FOREACH(cs) { 2633 cpu = X86_CPU(cs); 2634 2635 if (cpu->apic_state) { 2636 device_reset(cpu->apic_state); 2637 } 2638 } 2639 } 2640 2641 static CpuInstanceProperties 2642 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2643 { 2644 MachineClass *mc = MACHINE_GET_CLASS(ms); 2645 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2646 2647 assert(cpu_index < possible_cpus->len); 2648 return possible_cpus->cpus[cpu_index].props; 2649 } 2650 2651 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2652 { 2653 X86CPUTopoInfo topo; 2654 2655 assert(idx < ms->possible_cpus->len); 2656 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2657 smp_cores, smp_threads, &topo); 2658 return topo.pkg_id % nb_numa_nodes; 2659 } 2660 2661 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2662 { 2663 int i; 2664 2665 if (ms->possible_cpus) { 2666 /* 2667 * make sure that max_cpus hasn't changed since the first use, i.e. 2668 * -smp hasn't been parsed after it 2669 */ 2670 assert(ms->possible_cpus->len == max_cpus); 2671 return ms->possible_cpus; 2672 } 2673 2674 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2675 sizeof(CPUArchId) * max_cpus); 2676 ms->possible_cpus->len = max_cpus; 2677 for (i = 0; i < ms->possible_cpus->len; i++) { 2678 X86CPUTopoInfo topo; 2679 2680 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2681 ms->possible_cpus->cpus[i].vcpus_count = 1; 2682 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 2683 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2684 smp_cores, smp_threads, &topo); 2685 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2686 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2687 ms->possible_cpus->cpus[i].props.has_core_id = true; 2688 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2689 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2690 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2691 } 2692 return ms->possible_cpus; 2693 } 2694 2695 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2696 { 2697 /* cpu index isn't used */ 2698 CPUState *cs; 2699 2700 CPU_FOREACH(cs) { 2701 X86CPU *cpu = X86_CPU(cs); 2702 2703 if (!cpu->apic_state) { 2704 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2705 } else { 2706 apic_deliver_nmi(cpu->apic_state); 2707 } 2708 } 2709 } 2710 2711 static void pc_machine_class_init(ObjectClass *oc, void *data) 2712 { 2713 MachineClass *mc = MACHINE_CLASS(oc); 2714 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2715 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2716 NMIClass *nc = NMI_CLASS(oc); 2717 2718 pcmc->pci_enabled = true; 2719 pcmc->has_acpi_build = true; 2720 pcmc->rsdp_in_ram = true; 2721 pcmc->smbios_defaults = true; 2722 pcmc->smbios_uuid_encoded = true; 2723 pcmc->gigabyte_align = true; 2724 pcmc->has_reserved_memory = true; 2725 pcmc->kvmclock_enabled = true; 2726 pcmc->enforce_aligned_dimm = true; 2727 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2728 * to be used at the moment, 32K should be enough for a while. */ 2729 pcmc->acpi_data_size = 0x20000 + 0x8000; 2730 pcmc->save_tsc_khz = true; 2731 pcmc->linuxboot_dma_enabled = true; 2732 pcmc->pvh_enabled = true; 2733 assert(!mc->get_hotplug_handler); 2734 mc->get_hotplug_handler = pc_get_hotplug_handler; 2735 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2736 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2737 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2738 mc->auto_enable_numa_with_memhp = true; 2739 mc->has_hotpluggable_cpus = true; 2740 mc->default_boot_order = "cad"; 2741 mc->hot_add_cpu = pc_hot_add_cpu; 2742 mc->block_default_type = IF_IDE; 2743 mc->max_cpus = 255; 2744 mc->reset = pc_machine_reset; 2745 hc->pre_plug = pc_machine_device_pre_plug_cb; 2746 hc->plug = pc_machine_device_plug_cb; 2747 hc->unplug_request = pc_machine_device_unplug_request_cb; 2748 hc->unplug = pc_machine_device_unplug_cb; 2749 nc->nmi_monitor_handler = x86_nmi; 2750 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2751 mc->nvdimm_supported = true; 2752 2753 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2754 pc_machine_get_device_memory_region_size, NULL, 2755 NULL, NULL, &error_abort); 2756 2757 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2758 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2759 NULL, NULL, &error_abort); 2760 2761 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2762 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2763 2764 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2765 pc_machine_get_smm, pc_machine_set_smm, 2766 NULL, NULL, &error_abort); 2767 object_class_property_set_description(oc, PC_MACHINE_SMM, 2768 "Enable SMM (pc & q35)", &error_abort); 2769 2770 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2771 pc_machine_get_vmport, pc_machine_set_vmport, 2772 NULL, NULL, &error_abort); 2773 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2774 "Enable vmport (pc & q35)", &error_abort); 2775 2776 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2777 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2778 2779 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2780 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2781 2782 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2783 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2784 } 2785 2786 static const TypeInfo pc_machine_info = { 2787 .name = TYPE_PC_MACHINE, 2788 .parent = TYPE_MACHINE, 2789 .abstract = true, 2790 .instance_size = sizeof(PCMachineState), 2791 .instance_init = pc_machine_initfn, 2792 .class_size = sizeof(PCMachineClass), 2793 .class_init = pc_machine_class_init, 2794 .interfaces = (InterfaceInfo[]) { 2795 { TYPE_HOTPLUG_HANDLER }, 2796 { TYPE_NMI }, 2797 { } 2798 }, 2799 }; 2800 2801 static void pc_machine_register_types(void) 2802 { 2803 type_register_static(&pc_machine_info); 2804 } 2805 2806 type_init(pc_machine_register_types) 2807