xref: /openbmc/qemu/hw/i386/pc.c (revision 057dc9a635fe37118a98b32e8bd9d8ed47b1a102)
1 /*
2  * QEMU PC System Emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/reset.h"
62 #include "sysemu/runstate.h"
63 #include "kvm/kvm_i386.h"
64 #include "hw/xen/xen.h"
65 #include "hw/xen/start_info.h"
66 #include "ui/qemu-spice.h"
67 #include "exec/memory.h"
68 #include "qemu/bitmap.h"
69 #include "qemu/config-file.h"
70 #include "qemu/error-report.h"
71 #include "qemu/option.h"
72 #include "qemu/cutils.h"
73 #include "hw/acpi/acpi.h"
74 #include "hw/acpi/cpu_hotplug.h"
75 #include "acpi-build.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "qapi/error.h"
79 #include "qapi/qapi-visit-common.h"
80 #include "qapi/visitor.h"
81 #include "hw/core/cpu.h"
82 #include "hw/usb.h"
83 #include "hw/i386/intel_iommu.h"
84 #include "hw/net/ne2000-isa.h"
85 #include "standard-headers/asm-x86/bootparam.h"
86 #include "hw/virtio/virtio-iommu.h"
87 #include "hw/virtio/virtio-pmem-pci.h"
88 #include "hw/virtio/virtio-mem-pci.h"
89 #include "hw/mem/memory-device.h"
90 #include "sysemu/replay.h"
91 #include "qapi/qmp/qerror.h"
92 #include "e820_memory_layout.h"
93 #include "fw_cfg.h"
94 #include "trace.h"
95 #include CONFIG_DEVICES
96 
97 GlobalProperty pc_compat_6_2[] = {};
98 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
99 
100 GlobalProperty pc_compat_6_1[] = {
101     { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
102     { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
103     { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
104     { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
105 };
106 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
107 
108 GlobalProperty pc_compat_6_0[] = {
109     { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
110     { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
111     { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
112     { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
113     { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
114     { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
115 };
116 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
117 
118 GlobalProperty pc_compat_5_2[] = {
119     { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
120 };
121 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
122 
123 GlobalProperty pc_compat_5_1[] = {
124     { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
125     { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
126 };
127 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
128 
129 GlobalProperty pc_compat_5_0[] = {
130 };
131 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
132 
133 GlobalProperty pc_compat_4_2[] = {
134     { "mch", "smbase-smram", "off" },
135 };
136 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
137 
138 GlobalProperty pc_compat_4_1[] = {};
139 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
140 
141 GlobalProperty pc_compat_4_0[] = {};
142 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
143 
144 GlobalProperty pc_compat_3_1[] = {
145     { "intel-iommu", "dma-drain", "off" },
146     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
147     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
148     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
149     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
150     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
151     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
152     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
153     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
154     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
155     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
156     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
157     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
158     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
159     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
160     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
161     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
162     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
163     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
164     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
165     { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
166 };
167 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
168 
169 GlobalProperty pc_compat_3_0[] = {
170     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
171     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
172     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
173 };
174 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
175 
176 GlobalProperty pc_compat_2_12[] = {
177     { TYPE_X86_CPU, "legacy-cache", "on" },
178     { TYPE_X86_CPU, "topoext", "off" },
179     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
180     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
181 };
182 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
183 
184 GlobalProperty pc_compat_2_11[] = {
185     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
186     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
187 };
188 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
189 
190 GlobalProperty pc_compat_2_10[] = {
191     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
192     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
193     { "q35-pcihost", "x-pci-hole64-fix", "off" },
194 };
195 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
196 
197 GlobalProperty pc_compat_2_9[] = {
198     { "mch", "extended-tseg-mbytes", "0" },
199 };
200 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
201 
202 GlobalProperty pc_compat_2_8[] = {
203     { TYPE_X86_CPU, "tcg-cpuid", "off" },
204     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
205     { "ICH9-LPC", "x-smi-broadcast", "off" },
206     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
207     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
208 };
209 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
210 
211 GlobalProperty pc_compat_2_7[] = {
212     { TYPE_X86_CPU, "l3-cache", "off" },
213     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
214     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
215     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
216     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
217     { "isa-pcspk", "migrate", "off" },
218 };
219 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
220 
221 GlobalProperty pc_compat_2_6[] = {
222     { TYPE_X86_CPU, "cpuid-0xb", "off" },
223     { "vmxnet3", "romfile", "" },
224     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
225     { "apic-common", "legacy-instance-id", "on", }
226 };
227 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
228 
229 GlobalProperty pc_compat_2_5[] = {};
230 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
231 
232 GlobalProperty pc_compat_2_4[] = {
233     PC_CPU_MODEL_IDS("2.4.0")
234     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
235     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
236     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
237     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
238     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
239     { TYPE_X86_CPU, "check", "off" },
240     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
241     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
242     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
243     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
244     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
245     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
246     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
247     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
248 };
249 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
250 
251 GlobalProperty pc_compat_2_3[] = {
252     PC_CPU_MODEL_IDS("2.3.0")
253     { TYPE_X86_CPU, "arat", "off" },
254     { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
255     { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
256     { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
257     { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
258     { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
259     { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
260     { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
261     { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
262     { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
263     { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
264     { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
265     { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
266     { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
267     { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
268     { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
269     { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270     { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271     { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272     { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
273 };
274 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
275 
276 GlobalProperty pc_compat_2_2[] = {
277     PC_CPU_MODEL_IDS("2.2.0")
278     { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
279     { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
280     { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
281     { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
282     { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
283     { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
284     { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
285     { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
286     { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
287     { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
288     { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
289     { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
290     { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
291     { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
292     { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
293     { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
294     { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
295     { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
296 };
297 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
298 
299 GlobalProperty pc_compat_2_1[] = {
300     PC_CPU_MODEL_IDS("2.1.0")
301     { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
302     { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
303 };
304 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
305 
306 GlobalProperty pc_compat_2_0[] = {
307     PC_CPU_MODEL_IDS("2.0.0")
308     { "virtio-scsi-pci", "any_layout", "off" },
309     { "PIIX4_PM", "memory-hotplug-support", "off" },
310     { "apic", "version", "0x11" },
311     { "nec-usb-xhci", "superspeed-ports-first", "off" },
312     { "nec-usb-xhci", "force-pcie-endcap", "on" },
313     { "pci-serial", "prog_if", "0" },
314     { "pci-serial-2x", "prog_if", "0" },
315     { "pci-serial-4x", "prog_if", "0" },
316     { "virtio-net-pci", "guest_announce", "off" },
317     { "ICH9-LPC", "memory-hotplug-support", "off" },
318     { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
319     { "ioh3420", COMPAT_PROP_PCP, "off" },
320 };
321 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
322 
323 GlobalProperty pc_compat_1_7[] = {
324     PC_CPU_MODEL_IDS("1.7.0")
325     { TYPE_USB_DEVICE, "msos-desc", "no" },
326     { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
327     { "hpet", HPET_INTCAP, "4" },
328 };
329 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
330 
331 GlobalProperty pc_compat_1_6[] = {
332     PC_CPU_MODEL_IDS("1.6.0")
333     { "e1000", "mitigation", "off" },
334     { "qemu64-" TYPE_X86_CPU, "model", "2" },
335     { "qemu32-" TYPE_X86_CPU, "model", "3" },
336     { "i440FX-pcihost", "short_root_bus", "1" },
337     { "q35-pcihost", "short_root_bus", "1" },
338 };
339 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
340 
341 GlobalProperty pc_compat_1_5[] = {
342     PC_CPU_MODEL_IDS("1.5.0")
343     { "Conroe-" TYPE_X86_CPU, "model", "2" },
344     { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
345     { "Penryn-" TYPE_X86_CPU, "model", "2" },
346     { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
347     { "Nehalem-" TYPE_X86_CPU, "model", "2" },
348     { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
349     { "virtio-net-pci", "any_layout", "off" },
350     { TYPE_X86_CPU, "pmu", "on" },
351     { "i440FX-pcihost", "short_root_bus", "0" },
352     { "q35-pcihost", "short_root_bus", "0" },
353 };
354 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
355 
356 GlobalProperty pc_compat_1_4[] = {
357     PC_CPU_MODEL_IDS("1.4.0")
358     { "scsi-hd", "discard_granularity", "0" },
359     { "scsi-cd", "discard_granularity", "0" },
360     { "ide-hd", "discard_granularity", "0" },
361     { "ide-cd", "discard_granularity", "0" },
362     { "virtio-blk-pci", "discard_granularity", "0" },
363     /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
364     { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
365     { "virtio-net-pci", "ctrl_guest_offloads", "off" },
366     { "e1000", "romfile", "pxe-e1000.rom" },
367     { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
368     { "pcnet", "romfile", "pxe-pcnet.rom" },
369     { "rtl8139", "romfile", "pxe-rtl8139.rom" },
370     { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
371     { "486-" TYPE_X86_CPU, "model", "0" },
372     { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
373     { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
374 };
375 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
376 
377 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
378 {
379     GSIState *s;
380 
381     s = g_new0(GSIState, 1);
382     if (kvm_ioapic_in_kernel()) {
383         kvm_pc_setup_irq_routing(pci_enabled);
384     }
385     *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
386 
387     return s;
388 }
389 
390 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
391                            unsigned size)
392 {
393 }
394 
395 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
396 {
397     return 0xffffffffffffffffULL;
398 }
399 
400 /* MSDOS compatibility mode FPU exception support */
401 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
402                            unsigned size)
403 {
404     if (tcg_enabled()) {
405         cpu_set_ignne();
406     }
407 }
408 
409 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
410 {
411     return 0xffffffffffffffffULL;
412 }
413 
414 /* PC cmos mappings */
415 
416 #define REG_EQUIPMENT_BYTE          0x14
417 
418 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
419                          int16_t cylinders, int8_t heads, int8_t sectors)
420 {
421     rtc_set_memory(s, type_ofs, 47);
422     rtc_set_memory(s, info_ofs, cylinders);
423     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
424     rtc_set_memory(s, info_ofs + 2, heads);
425     rtc_set_memory(s, info_ofs + 3, 0xff);
426     rtc_set_memory(s, info_ofs + 4, 0xff);
427     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
428     rtc_set_memory(s, info_ofs + 6, cylinders);
429     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
430     rtc_set_memory(s, info_ofs + 8, sectors);
431 }
432 
433 /* convert boot_device letter to something recognizable by the bios */
434 static int boot_device2nibble(char boot_device)
435 {
436     switch(boot_device) {
437     case 'a':
438     case 'b':
439         return 0x01; /* floppy boot */
440     case 'c':
441         return 0x02; /* hard drive boot */
442     case 'd':
443         return 0x03; /* CD-ROM boot */
444     case 'n':
445         return 0x04; /* Network boot */
446     }
447     return 0;
448 }
449 
450 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
451 {
452 #define PC_MAX_BOOT_DEVICES 3
453     int nbds, bds[3] = { 0, };
454     int i;
455 
456     nbds = strlen(boot_device);
457     if (nbds > PC_MAX_BOOT_DEVICES) {
458         error_setg(errp, "Too many boot devices for PC");
459         return;
460     }
461     for (i = 0; i < nbds; i++) {
462         bds[i] = boot_device2nibble(boot_device[i]);
463         if (bds[i] == 0) {
464             error_setg(errp, "Invalid boot device for PC: '%c'",
465                        boot_device[i]);
466             return;
467         }
468     }
469     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
470     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
471 }
472 
473 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
474 {
475     set_boot_dev(opaque, boot_device, errp);
476 }
477 
478 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
479 {
480     int val, nb, i;
481     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
482                                    FLOPPY_DRIVE_TYPE_NONE };
483 
484     /* floppy type */
485     if (floppy) {
486         for (i = 0; i < 2; i++) {
487             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
488         }
489     }
490     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
491         cmos_get_fd_drive_type(fd_type[1]);
492     rtc_set_memory(rtc_state, 0x10, val);
493 
494     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
495     nb = 0;
496     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
497         nb++;
498     }
499     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
500         nb++;
501     }
502     switch (nb) {
503     case 0:
504         break;
505     case 1:
506         val |= 0x01; /* 1 drive, ready for boot */
507         break;
508     case 2:
509         val |= 0x41; /* 2 drives, ready for boot */
510         break;
511     }
512     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
513 }
514 
515 typedef struct pc_cmos_init_late_arg {
516     ISADevice *rtc_state;
517     BusState *idebus[2];
518 } pc_cmos_init_late_arg;
519 
520 typedef struct check_fdc_state {
521     ISADevice *floppy;
522     bool multiple;
523 } CheckFdcState;
524 
525 static int check_fdc(Object *obj, void *opaque)
526 {
527     CheckFdcState *state = opaque;
528     Object *fdc;
529     uint32_t iobase;
530     Error *local_err = NULL;
531 
532     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
533     if (!fdc) {
534         return 0;
535     }
536 
537     iobase = object_property_get_uint(obj, "iobase", &local_err);
538     if (local_err || iobase != 0x3f0) {
539         error_free(local_err);
540         return 0;
541     }
542 
543     if (state->floppy) {
544         state->multiple = true;
545     } else {
546         state->floppy = ISA_DEVICE(obj);
547     }
548     return 0;
549 }
550 
551 static const char * const fdc_container_path[] = {
552     "/unattached", "/peripheral", "/peripheral-anon"
553 };
554 
555 /*
556  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
557  * and ACPI objects.
558  */
559 ISADevice *pc_find_fdc0(void)
560 {
561     int i;
562     Object *container;
563     CheckFdcState state = { 0 };
564 
565     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
566         container = container_get(qdev_get_machine(), fdc_container_path[i]);
567         object_child_foreach(container, check_fdc, &state);
568     }
569 
570     if (state.multiple) {
571         warn_report("multiple floppy disk controllers with "
572                     "iobase=0x3f0 have been found");
573         error_printf("the one being picked for CMOS setup might not reflect "
574                      "your intent");
575     }
576 
577     return state.floppy;
578 }
579 
580 static void pc_cmos_init_late(void *opaque)
581 {
582     pc_cmos_init_late_arg *arg = opaque;
583     ISADevice *s = arg->rtc_state;
584     int16_t cylinders;
585     int8_t heads, sectors;
586     int val;
587     int i, trans;
588 
589     val = 0;
590     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
591                                            &cylinders, &heads, &sectors) >= 0) {
592         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
593         val |= 0xf0;
594     }
595     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
596                                            &cylinders, &heads, &sectors) >= 0) {
597         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
598         val |= 0x0f;
599     }
600     rtc_set_memory(s, 0x12, val);
601 
602     val = 0;
603     for (i = 0; i < 4; i++) {
604         /* NOTE: ide_get_geometry() returns the physical
605            geometry.  It is always such that: 1 <= sects <= 63, 1
606            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
607            geometry can be different if a translation is done. */
608         if (arg->idebus[i / 2] &&
609             ide_get_geometry(arg->idebus[i / 2], i % 2,
610                              &cylinders, &heads, &sectors) >= 0) {
611             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
612             assert((trans & ~3) == 0);
613             val |= trans << (i * 2);
614         }
615     }
616     rtc_set_memory(s, 0x39, val);
617 
618     pc_cmos_init_floppy(s, pc_find_fdc0());
619 
620     qemu_unregister_reset(pc_cmos_init_late, opaque);
621 }
622 
623 void pc_cmos_init(PCMachineState *pcms,
624                   BusState *idebus0, BusState *idebus1,
625                   ISADevice *s)
626 {
627     int val;
628     static pc_cmos_init_late_arg arg;
629     X86MachineState *x86ms = X86_MACHINE(pcms);
630 
631     /* various important CMOS locations needed by PC/Bochs bios */
632 
633     /* memory size */
634     /* base memory (first MiB) */
635     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
636     rtc_set_memory(s, 0x15, val);
637     rtc_set_memory(s, 0x16, val >> 8);
638     /* extended memory (next 64MiB) */
639     if (x86ms->below_4g_mem_size > 1 * MiB) {
640         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
641     } else {
642         val = 0;
643     }
644     if (val > 65535)
645         val = 65535;
646     rtc_set_memory(s, 0x17, val);
647     rtc_set_memory(s, 0x18, val >> 8);
648     rtc_set_memory(s, 0x30, val);
649     rtc_set_memory(s, 0x31, val >> 8);
650     /* memory between 16MiB and 4GiB */
651     if (x86ms->below_4g_mem_size > 16 * MiB) {
652         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
653     } else {
654         val = 0;
655     }
656     if (val > 65535)
657         val = 65535;
658     rtc_set_memory(s, 0x34, val);
659     rtc_set_memory(s, 0x35, val >> 8);
660     /* memory above 4GiB */
661     val = x86ms->above_4g_mem_size / 65536;
662     rtc_set_memory(s, 0x5b, val);
663     rtc_set_memory(s, 0x5c, val >> 8);
664     rtc_set_memory(s, 0x5d, val >> 16);
665 
666     object_property_add_link(OBJECT(pcms), "rtc_state",
667                              TYPE_ISA_DEVICE,
668                              (Object **)&x86ms->rtc,
669                              object_property_allow_set_link,
670                              OBJ_PROP_LINK_STRONG);
671     object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
672                              &error_abort);
673 
674     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
675 
676     val = 0;
677     val |= 0x02; /* FPU is there */
678     val |= 0x04; /* PS/2 mouse installed */
679     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
680 
681     /* hard drives and FDC */
682     arg.rtc_state = s;
683     arg.idebus[0] = idebus0;
684     arg.idebus[1] = idebus1;
685     qemu_register_reset(pc_cmos_init_late, &arg);
686 }
687 
688 static void handle_a20_line_change(void *opaque, int irq, int level)
689 {
690     X86CPU *cpu = opaque;
691 
692     /* XXX: send to all CPUs ? */
693     /* XXX: add logic to handle multiple A20 line sources */
694     x86_cpu_set_a20(cpu, level);
695 }
696 
697 #define NE2000_NB_MAX 6
698 
699 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
700                                               0x280, 0x380 };
701 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
702 
703 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
704 {
705     static int nb_ne2k = 0;
706 
707     if (nb_ne2k == NE2000_NB_MAX)
708         return;
709     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
710                     ne2000_irq[nb_ne2k], nd);
711     nb_ne2k++;
712 }
713 
714 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
715 {
716     X86CPU *cpu = opaque;
717 
718     if (level) {
719         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
720     }
721 }
722 
723 static
724 void pc_machine_done(Notifier *notifier, void *data)
725 {
726     PCMachineState *pcms = container_of(notifier,
727                                         PCMachineState, machine_done);
728     X86MachineState *x86ms = X86_MACHINE(pcms);
729 
730     /* set the number of CPUs */
731     x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
732 
733     fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
734 
735     acpi_setup();
736     if (x86ms->fw_cfg) {
737         fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
738         fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
739         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
740         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
741     }
742 
743 
744     if (x86ms->apic_id_limit > 255 && !xen_enabled() &&
745         !kvm_irqchip_in_kernel()) {
746         error_report("current -smp configuration requires kernel "
747                      "irqchip support.");
748         exit(EXIT_FAILURE);
749     }
750 }
751 
752 void pc_guest_info_init(PCMachineState *pcms)
753 {
754     X86MachineState *x86ms = X86_MACHINE(pcms);
755 
756     x86ms->apic_xrupt_override = true;
757     pcms->machine_done.notify = pc_machine_done;
758     qemu_add_machine_init_done_notifier(&pcms->machine_done);
759 }
760 
761 /* setup pci memory address space mapping into system address space */
762 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
763                             MemoryRegion *pci_address_space)
764 {
765     /* Set to lower priority than RAM */
766     memory_region_add_subregion_overlap(system_memory, 0x0,
767                                         pci_address_space, -1);
768 }
769 
770 void xen_load_linux(PCMachineState *pcms)
771 {
772     int i;
773     FWCfgState *fw_cfg;
774     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
775     X86MachineState *x86ms = X86_MACHINE(pcms);
776 
777     assert(MACHINE(pcms)->kernel_filename != NULL);
778 
779     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
780     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
781     rom_set_fw(fw_cfg);
782 
783     x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
784                    pcmc->pvh_enabled);
785     for (i = 0; i < nb_option_roms; i++) {
786         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
787                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
788                !strcmp(option_rom[i].name, "pvh.bin") ||
789                !strcmp(option_rom[i].name, "multiboot.bin") ||
790                !strcmp(option_rom[i].name, "multiboot_dma.bin"));
791         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
792     }
793     x86ms->fw_cfg = fw_cfg;
794 }
795 
796 #define PC_ROM_MIN_VGA     0xc0000
797 #define PC_ROM_MIN_OPTION  0xc8000
798 #define PC_ROM_MAX         0xe0000
799 #define PC_ROM_ALIGN       0x800
800 #define PC_ROM_SIZE        (PC_ROM_MAX - PC_ROM_MIN_VGA)
801 
802 void pc_memory_init(PCMachineState *pcms,
803                     MemoryRegion *system_memory,
804                     MemoryRegion *rom_memory,
805                     MemoryRegion **ram_memory)
806 {
807     int linux_boot, i;
808     MemoryRegion *option_rom_mr;
809     MemoryRegion *ram_below_4g, *ram_above_4g;
810     FWCfgState *fw_cfg;
811     MachineState *machine = MACHINE(pcms);
812     MachineClass *mc = MACHINE_GET_CLASS(machine);
813     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
814     X86MachineState *x86ms = X86_MACHINE(pcms);
815 
816     assert(machine->ram_size == x86ms->below_4g_mem_size +
817                                 x86ms->above_4g_mem_size);
818 
819     linux_boot = (machine->kernel_filename != NULL);
820 
821     /*
822      * Split single memory region and use aliases to address portions of it,
823      * done for backwards compatibility with older qemus.
824      */
825     *ram_memory = machine->ram;
826     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
827     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
828                              0, x86ms->below_4g_mem_size);
829     memory_region_add_subregion(system_memory, 0, ram_below_4g);
830     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
831     if (x86ms->above_4g_mem_size > 0) {
832         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
833         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
834                                  machine->ram,
835                                  x86ms->below_4g_mem_size,
836                                  x86ms->above_4g_mem_size);
837         memory_region_add_subregion(system_memory, 0x100000000ULL,
838                                     ram_above_4g);
839         e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
840     }
841 
842     if (pcms->sgx_epc.size != 0) {
843         e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
844     }
845 
846     if (!pcmc->has_reserved_memory &&
847         (machine->ram_slots ||
848          (machine->maxram_size > machine->ram_size))) {
849 
850         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
851                      mc->name);
852         exit(EXIT_FAILURE);
853     }
854 
855     /* always allocate the device memory information */
856     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
857 
858     /* initialize device memory address space */
859     if (pcmc->has_reserved_memory &&
860         (machine->ram_size < machine->maxram_size)) {
861         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
862 
863         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
864             error_report("unsupported amount of memory slots: %"PRIu64,
865                          machine->ram_slots);
866             exit(EXIT_FAILURE);
867         }
868 
869         if (QEMU_ALIGN_UP(machine->maxram_size,
870                           TARGET_PAGE_SIZE) != machine->maxram_size) {
871             error_report("maximum memory size must by aligned to multiple of "
872                          "%d bytes", TARGET_PAGE_SIZE);
873             exit(EXIT_FAILURE);
874         }
875 
876         if (pcms->sgx_epc.size != 0) {
877             machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc);
878         } else {
879             machine->device_memory->base =
880                 0x100000000ULL + x86ms->above_4g_mem_size;
881         }
882 
883         machine->device_memory->base =
884             ROUND_UP(machine->device_memory->base, 1 * GiB);
885 
886         if (pcmc->enforce_aligned_dimm) {
887             /* size device region assuming 1G page max alignment per slot */
888             device_mem_size += (1 * GiB) * machine->ram_slots;
889         }
890 
891         if ((machine->device_memory->base + device_mem_size) <
892             device_mem_size) {
893             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
894                          machine->maxram_size);
895             exit(EXIT_FAILURE);
896         }
897 
898         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
899                            "device-memory", device_mem_size);
900         memory_region_add_subregion(system_memory, machine->device_memory->base,
901                                     &machine->device_memory->mr);
902     }
903 
904     /* Initialize PC system firmware */
905     pc_system_firmware_init(pcms, rom_memory);
906 
907     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
908     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
909                            &error_fatal);
910     if (pcmc->pci_enabled) {
911         memory_region_set_readonly(option_rom_mr, true);
912     }
913     memory_region_add_subregion_overlap(rom_memory,
914                                         PC_ROM_MIN_VGA,
915                                         option_rom_mr,
916                                         1);
917 
918     fw_cfg = fw_cfg_arch_create(machine,
919                                 x86ms->boot_cpus, x86ms->apic_id_limit);
920 
921     rom_set_fw(fw_cfg);
922 
923     if (pcmc->has_reserved_memory && machine->device_memory->base) {
924         uint64_t *val = g_malloc(sizeof(*val));
925         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
926         uint64_t res_mem_end = machine->device_memory->base;
927 
928         if (!pcmc->broken_reserved_end) {
929             res_mem_end += memory_region_size(&machine->device_memory->mr);
930         }
931         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
932         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
933     }
934 
935     if (linux_boot) {
936         x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
937                        pcmc->pvh_enabled);
938     }
939 
940     for (i = 0; i < nb_option_roms; i++) {
941         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
942     }
943     x86ms->fw_cfg = fw_cfg;
944 
945     /* Init default IOAPIC address space */
946     x86ms->ioapic_as = &address_space_memory;
947 
948     /* Init ACPI memory hotplug IO base address */
949     pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
950 }
951 
952 /*
953  * The 64bit pci hole starts after "above 4G RAM" and
954  * potentially the space reserved for memory hotplug.
955  */
956 uint64_t pc_pci_hole64_start(void)
957 {
958     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
959     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
960     MachineState *ms = MACHINE(pcms);
961     X86MachineState *x86ms = X86_MACHINE(pcms);
962     uint64_t hole64_start = 0;
963 
964     if (pcmc->has_reserved_memory && ms->device_memory->base) {
965         hole64_start = ms->device_memory->base;
966         if (!pcmc->broken_reserved_end) {
967             hole64_start += memory_region_size(&ms->device_memory->mr);
968         }
969     } else if (pcms->sgx_epc.size != 0) {
970             hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc);
971     } else {
972         hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
973     }
974 
975     return ROUND_UP(hole64_start, 1 * GiB);
976 }
977 
978 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
979 {
980     DeviceState *dev = NULL;
981 
982     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
983     if (pci_bus) {
984         PCIDevice *pcidev = pci_vga_init(pci_bus);
985         dev = pcidev ? &pcidev->qdev : NULL;
986     } else if (isa_bus) {
987         ISADevice *isadev = isa_vga_init(isa_bus);
988         dev = isadev ? DEVICE(isadev) : NULL;
989     }
990     rom_reset_order_override();
991     return dev;
992 }
993 
994 static const MemoryRegionOps ioport80_io_ops = {
995     .write = ioport80_write,
996     .read = ioport80_read,
997     .endianness = DEVICE_NATIVE_ENDIAN,
998     .impl = {
999         .min_access_size = 1,
1000         .max_access_size = 1,
1001     },
1002 };
1003 
1004 static const MemoryRegionOps ioportF0_io_ops = {
1005     .write = ioportF0_write,
1006     .read = ioportF0_read,
1007     .endianness = DEVICE_NATIVE_ENDIAN,
1008     .impl = {
1009         .min_access_size = 1,
1010         .max_access_size = 1,
1011     },
1012 };
1013 
1014 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1015 {
1016     int i;
1017     DriveInfo *fd[MAX_FD];
1018     qemu_irq *a20_line;
1019     ISADevice *fdc, *i8042, *port92, *vmmouse;
1020 
1021     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1022     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1023 
1024     for (i = 0; i < MAX_FD; i++) {
1025         fd[i] = drive_get(IF_FLOPPY, 0, i);
1026         create_fdctrl |= !!fd[i];
1027     }
1028     if (create_fdctrl) {
1029         fdc = isa_new(TYPE_ISA_FDC);
1030         if (fdc) {
1031             isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1032             isa_fdc_init_drives(fdc, fd);
1033         }
1034     }
1035 
1036     i8042 = isa_create_simple(isa_bus, "i8042");
1037     if (!no_vmport) {
1038         isa_create_simple(isa_bus, TYPE_VMPORT);
1039         vmmouse = isa_try_new("vmmouse");
1040     } else {
1041         vmmouse = NULL;
1042     }
1043     if (vmmouse) {
1044         object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042),
1045                                  &error_abort);
1046         isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1047     }
1048     port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1049 
1050     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1051     i8042_setup_a20_line(i8042, a20_line[0]);
1052     qdev_connect_gpio_out_named(DEVICE(port92),
1053                                 PORT92_A20_LINE, 0, a20_line[1]);
1054     g_free(a20_line);
1055 }
1056 
1057 void pc_basic_device_init(struct PCMachineState *pcms,
1058                           ISABus *isa_bus, qemu_irq *gsi,
1059                           ISADevice **rtc_state,
1060                           bool create_fdctrl,
1061                           uint32_t hpet_irqs)
1062 {
1063     int i;
1064     DeviceState *hpet = NULL;
1065     int pit_isa_irq = 0;
1066     qemu_irq pit_alt_irq = NULL;
1067     qemu_irq rtc_irq = NULL;
1068     ISADevice *pit = NULL;
1069     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1070     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1071 
1072     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1073     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1074 
1075     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1076     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1077 
1078     /*
1079      * Check if an HPET shall be created.
1080      *
1081      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1082      * when the HPET wants to take over. Thus we have to disable the latter.
1083      */
1084     if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1085                                kvm_has_pit_state2())) {
1086         hpet = qdev_try_new(TYPE_HPET);
1087         if (!hpet) {
1088             error_report("couldn't create HPET device");
1089             exit(1);
1090         }
1091         /*
1092          * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1093          * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1094          * IRQ2.
1095          */
1096         uint8_t compat = object_property_get_uint(OBJECT(hpet),
1097                 HPET_INTCAP, NULL);
1098         if (!compat) {
1099             qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1100         }
1101         sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1102         sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1103 
1104         for (i = 0; i < GSI_NUM_PINS; i++) {
1105             sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1106         }
1107         pit_isa_irq = -1;
1108         pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1109         rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1110     }
1111     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1112 
1113     qemu_register_boot_set(pc_boot_set, *rtc_state);
1114 
1115     if (!xen_enabled() && pcms->pit_enabled) {
1116         if (kvm_pit_in_kernel()) {
1117             pit = kvm_pit_init(isa_bus, 0x40);
1118         } else {
1119             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1120         }
1121         if (hpet) {
1122             /* connect PIT to output control line of the HPET */
1123             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1124         }
1125         pcspk_init(pcms->pcspk, isa_bus, pit);
1126     }
1127 
1128     i8257_dma_init(isa_bus, 0);
1129 
1130     /* Super I/O */
1131     pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON);
1132 }
1133 
1134 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1135 {
1136     int i;
1137 
1138     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1139     for (i = 0; i < nb_nics; i++) {
1140         NICInfo *nd = &nd_table[i];
1141         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1142 
1143         if (g_str_equal(model, "ne2k_isa")) {
1144             pc_init_ne2k_isa(isa_bus, nd);
1145         } else {
1146             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1147         }
1148     }
1149     rom_reset_order_override();
1150 }
1151 
1152 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1153 {
1154     qemu_irq *i8259;
1155 
1156     if (kvm_pic_in_kernel()) {
1157         i8259 = kvm_i8259_init(isa_bus);
1158     } else if (xen_enabled()) {
1159         i8259 = xen_interrupt_controller_init();
1160     } else {
1161         i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1162     }
1163 
1164     for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1165         i8259_irqs[i] = i8259[i];
1166     }
1167 
1168     g_free(i8259);
1169 }
1170 
1171 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1172                                Error **errp)
1173 {
1174     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1175     const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1176     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1177     const MachineState *ms = MACHINE(hotplug_dev);
1178     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1179     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1180     Error *local_err = NULL;
1181 
1182     /*
1183      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1184      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1185      * addition to cover this case.
1186      */
1187     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1188         error_setg(errp,
1189                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1190         return;
1191     }
1192 
1193     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1194         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1195         return;
1196     }
1197 
1198     hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1199     if (local_err) {
1200         error_propagate(errp, local_err);
1201         return;
1202     }
1203 
1204     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1205                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1206 }
1207 
1208 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1209                            DeviceState *dev, Error **errp)
1210 {
1211     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1212     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1213     MachineState *ms = MACHINE(hotplug_dev);
1214     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1215 
1216     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1217 
1218     if (is_nvdimm) {
1219         nvdimm_plug(ms->nvdimms_state);
1220     }
1221 
1222     hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1223 }
1224 
1225 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1226                                      DeviceState *dev, Error **errp)
1227 {
1228     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1229 
1230     /*
1231      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1232      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1233      * addition to cover this case.
1234      */
1235     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1236         error_setg(errp,
1237                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1238         return;
1239     }
1240 
1241     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1242         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1243         return;
1244     }
1245 
1246     hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1247                                    errp);
1248 }
1249 
1250 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1251                              DeviceState *dev, Error **errp)
1252 {
1253     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1254     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1255     Error *local_err = NULL;
1256 
1257     hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1258     if (local_err) {
1259         goto out;
1260     }
1261 
1262     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1263     qdev_unrealize(dev);
1264  out:
1265     error_propagate(errp, local_err);
1266 }
1267 
1268 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1269                                       DeviceState *dev, Error **errp)
1270 {
1271     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1272     Error *local_err = NULL;
1273 
1274     if (!hotplug_dev2 && dev->hotplugged) {
1275         /*
1276          * Without a bus hotplug handler, we cannot control the plug/unplug
1277          * order. We should never reach this point when hotplugging on x86,
1278          * however, better add a safety net.
1279          */
1280         error_setg(errp, "hotplug of virtio based memory devices not supported"
1281                    " on this bus.");
1282         return;
1283     }
1284     /*
1285      * First, see if we can plug this memory device at all. If that
1286      * succeeds, branch of to the actual hotplug handler.
1287      */
1288     memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1289                            &local_err);
1290     if (!local_err && hotplug_dev2) {
1291         hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1292     }
1293     error_propagate(errp, local_err);
1294 }
1295 
1296 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1297                                   DeviceState *dev, Error **errp)
1298 {
1299     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1300     Error *local_err = NULL;
1301 
1302     /*
1303      * Plug the memory device first and then branch off to the actual
1304      * hotplug handler. If that one fails, we can easily undo the memory
1305      * device bits.
1306      */
1307     memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1308     if (hotplug_dev2) {
1309         hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1310         if (local_err) {
1311             memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1312         }
1313     }
1314     error_propagate(errp, local_err);
1315 }
1316 
1317 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1318                                             DeviceState *dev, Error **errp)
1319 {
1320     /* We don't support hot unplug of virtio based memory devices */
1321     error_setg(errp, "virtio based memory devices cannot be unplugged.");
1322 }
1323 
1324 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1325                                     DeviceState *dev, Error **errp)
1326 {
1327     /* We don't support hot unplug of virtio based memory devices */
1328 }
1329 
1330 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1331                                           DeviceState *dev, Error **errp)
1332 {
1333     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1334         pc_memory_pre_plug(hotplug_dev, dev, errp);
1335     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1336         x86_cpu_pre_plug(hotplug_dev, dev, errp);
1337     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1338                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1339         pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1340     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1341         /* Declare the APIC range as the reserved MSI region */
1342         char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1343                                               VIRTIO_IOMMU_RESV_MEM_T_MSI);
1344 
1345         object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1346         object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1347                                 resv_prop_str, errp);
1348         g_free(resv_prop_str);
1349     }
1350 
1351     if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1352         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1353         PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1354 
1355         if (pcms->iommu) {
1356             error_setg(errp, "QEMU does not support multiple vIOMMUs "
1357                        "for x86 yet.");
1358             return;
1359         }
1360         pcms->iommu = dev;
1361     }
1362 }
1363 
1364 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1365                                       DeviceState *dev, Error **errp)
1366 {
1367     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1368         pc_memory_plug(hotplug_dev, dev, errp);
1369     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1370         x86_cpu_plug(hotplug_dev, dev, errp);
1371     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1372                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1373         pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1374     }
1375 }
1376 
1377 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1378                                                 DeviceState *dev, Error **errp)
1379 {
1380     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1381         pc_memory_unplug_request(hotplug_dev, dev, errp);
1382     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1383         x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1384     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1385                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1386         pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1387     } else {
1388         error_setg(errp, "acpi: device unplug request for not supported device"
1389                    " type: %s", object_get_typename(OBJECT(dev)));
1390     }
1391 }
1392 
1393 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1394                                         DeviceState *dev, Error **errp)
1395 {
1396     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1397         pc_memory_unplug(hotplug_dev, dev, errp);
1398     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1399         x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1400     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1401                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1402         pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1403     } else {
1404         error_setg(errp, "acpi: device unplug for not supported device"
1405                    " type: %s", object_get_typename(OBJECT(dev)));
1406     }
1407 }
1408 
1409 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1410                                              DeviceState *dev)
1411 {
1412     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1413         object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1414         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1415         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1416         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1417         object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1418         return HOTPLUG_HANDLER(machine);
1419     }
1420 
1421     return NULL;
1422 }
1423 
1424 static void
1425 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1426                                          const char *name, void *opaque,
1427                                          Error **errp)
1428 {
1429     MachineState *ms = MACHINE(obj);
1430     int64_t value = 0;
1431 
1432     if (ms->device_memory) {
1433         value = memory_region_size(&ms->device_memory->mr);
1434     }
1435 
1436     visit_type_int(v, name, &value, errp);
1437 }
1438 
1439 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1440                                   void *opaque, Error **errp)
1441 {
1442     PCMachineState *pcms = PC_MACHINE(obj);
1443     OnOffAuto vmport = pcms->vmport;
1444 
1445     visit_type_OnOffAuto(v, name, &vmport, errp);
1446 }
1447 
1448 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1449                                   void *opaque, Error **errp)
1450 {
1451     PCMachineState *pcms = PC_MACHINE(obj);
1452 
1453     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1454 }
1455 
1456 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1457 {
1458     PCMachineState *pcms = PC_MACHINE(obj);
1459 
1460     return pcms->smbus_enabled;
1461 }
1462 
1463 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1464 {
1465     PCMachineState *pcms = PC_MACHINE(obj);
1466 
1467     pcms->smbus_enabled = value;
1468 }
1469 
1470 static bool pc_machine_get_sata(Object *obj, Error **errp)
1471 {
1472     PCMachineState *pcms = PC_MACHINE(obj);
1473 
1474     return pcms->sata_enabled;
1475 }
1476 
1477 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1478 {
1479     PCMachineState *pcms = PC_MACHINE(obj);
1480 
1481     pcms->sata_enabled = value;
1482 }
1483 
1484 static bool pc_machine_get_pit(Object *obj, Error **errp)
1485 {
1486     PCMachineState *pcms = PC_MACHINE(obj);
1487 
1488     return pcms->pit_enabled;
1489 }
1490 
1491 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1492 {
1493     PCMachineState *pcms = PC_MACHINE(obj);
1494 
1495     pcms->pit_enabled = value;
1496 }
1497 
1498 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1499 {
1500     PCMachineState *pcms = PC_MACHINE(obj);
1501 
1502     return pcms->hpet_enabled;
1503 }
1504 
1505 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1506 {
1507     PCMachineState *pcms = PC_MACHINE(obj);
1508 
1509     pcms->hpet_enabled = value;
1510 }
1511 
1512 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1513 {
1514     PCMachineState *pcms = PC_MACHINE(obj);
1515 
1516     return pcms->default_bus_bypass_iommu;
1517 }
1518 
1519 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1520                                                     Error **errp)
1521 {
1522     PCMachineState *pcms = PC_MACHINE(obj);
1523 
1524     pcms->default_bus_bypass_iommu = value;
1525 }
1526 
1527 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1528                                             const char *name, void *opaque,
1529                                             Error **errp)
1530 {
1531     PCMachineState *pcms = PC_MACHINE(obj);
1532     uint64_t value = pcms->max_ram_below_4g;
1533 
1534     visit_type_size(v, name, &value, errp);
1535 }
1536 
1537 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1538                                             const char *name, void *opaque,
1539                                             Error **errp)
1540 {
1541     PCMachineState *pcms = PC_MACHINE(obj);
1542     uint64_t value;
1543 
1544     if (!visit_type_size(v, name, &value, errp)) {
1545         return;
1546     }
1547     if (value > 4 * GiB) {
1548         error_setg(errp,
1549                    "Machine option 'max-ram-below-4g=%"PRIu64
1550                    "' expects size less than or equal to 4G", value);
1551         return;
1552     }
1553 
1554     if (value < 1 * MiB) {
1555         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1556                     "BIOS may not work with less than 1MiB", value);
1557     }
1558 
1559     pcms->max_ram_below_4g = value;
1560 }
1561 
1562 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1563                                        const char *name, void *opaque,
1564                                        Error **errp)
1565 {
1566     PCMachineState *pcms = PC_MACHINE(obj);
1567     uint64_t value = pcms->max_fw_size;
1568 
1569     visit_type_size(v, name, &value, errp);
1570 }
1571 
1572 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1573                                        const char *name, void *opaque,
1574                                        Error **errp)
1575 {
1576     PCMachineState *pcms = PC_MACHINE(obj);
1577     Error *error = NULL;
1578     uint64_t value;
1579 
1580     visit_type_size(v, name, &value, &error);
1581     if (error) {
1582         error_propagate(errp, error);
1583         return;
1584     }
1585 
1586     /*
1587     * We don't have a theoretically justifiable exact lower bound on the base
1588     * address of any flash mapping. In practice, the IO-APIC MMIO range is
1589     * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1590     * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1591     * size.
1592     */
1593     if (value > 16 * MiB) {
1594         error_setg(errp,
1595                    "User specified max allowed firmware size %" PRIu64 " is "
1596                    "greater than 16MiB. If combined firwmare size exceeds "
1597                    "16MiB the system may not boot, or experience intermittent"
1598                    "stability issues.",
1599                    value);
1600         return;
1601     }
1602 
1603     pcms->max_fw_size = value;
1604 }
1605 
1606 
1607 static void pc_machine_initfn(Object *obj)
1608 {
1609     PCMachineState *pcms = PC_MACHINE(obj);
1610 
1611 #ifdef CONFIG_VMPORT
1612     pcms->vmport = ON_OFF_AUTO_AUTO;
1613 #else
1614     pcms->vmport = ON_OFF_AUTO_OFF;
1615 #endif /* CONFIG_VMPORT */
1616     pcms->max_ram_below_4g = 0; /* use default */
1617     /* acpi build is enabled by default if machine supports it */
1618     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1619     pcms->smbus_enabled = true;
1620     pcms->sata_enabled = true;
1621     pcms->pit_enabled = true;
1622     pcms->max_fw_size = 8 * MiB;
1623 #ifdef CONFIG_HPET
1624     pcms->hpet_enabled = true;
1625 #endif
1626     pcms->default_bus_bypass_iommu = false;
1627 
1628     pc_system_flash_create(pcms);
1629     pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1630     object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1631                               OBJECT(pcms->pcspk), "audiodev");
1632 }
1633 
1634 static void pc_machine_reset(MachineState *machine)
1635 {
1636     CPUState *cs;
1637     X86CPU *cpu;
1638 
1639     qemu_devices_reset();
1640 
1641     /* Reset APIC after devices have been reset to cancel
1642      * any changes that qemu_devices_reset() might have done.
1643      */
1644     CPU_FOREACH(cs) {
1645         cpu = X86_CPU(cs);
1646 
1647         if (cpu->apic_state) {
1648             device_legacy_reset(cpu->apic_state);
1649         }
1650     }
1651 }
1652 
1653 static void pc_machine_wakeup(MachineState *machine)
1654 {
1655     cpu_synchronize_all_states();
1656     pc_machine_reset(machine);
1657     cpu_synchronize_all_post_reset();
1658 }
1659 
1660 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1661 {
1662     X86IOMMUState *iommu = x86_iommu_get_default();
1663     IntelIOMMUState *intel_iommu;
1664 
1665     if (iommu &&
1666         object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1667         object_dynamic_cast((Object *)dev, "vfio-pci")) {
1668         intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1669         if (!intel_iommu->caching_mode) {
1670             error_setg(errp, "Device assignment is not allowed without "
1671                        "enabling caching-mode=on for Intel IOMMU.");
1672             return false;
1673         }
1674     }
1675 
1676     return true;
1677 }
1678 
1679 static void pc_machine_class_init(ObjectClass *oc, void *data)
1680 {
1681     MachineClass *mc = MACHINE_CLASS(oc);
1682     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1683     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1684 
1685     pcmc->pci_enabled = true;
1686     pcmc->has_acpi_build = true;
1687     pcmc->rsdp_in_ram = true;
1688     pcmc->smbios_defaults = true;
1689     pcmc->smbios_uuid_encoded = true;
1690     pcmc->gigabyte_align = true;
1691     pcmc->has_reserved_memory = true;
1692     pcmc->kvmclock_enabled = true;
1693     pcmc->enforce_aligned_dimm = true;
1694     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1695      * to be used at the moment, 32K should be enough for a while.  */
1696     pcmc->acpi_data_size = 0x20000 + 0x8000;
1697     pcmc->pvh_enabled = true;
1698     pcmc->kvmclock_create_always = true;
1699     assert(!mc->get_hotplug_handler);
1700     mc->get_hotplug_handler = pc_get_hotplug_handler;
1701     mc->hotplug_allowed = pc_hotplug_allowed;
1702     mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1703     mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1704     mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1705     mc->auto_enable_numa_with_memhp = true;
1706     mc->auto_enable_numa_with_memdev = true;
1707     mc->has_hotpluggable_cpus = true;
1708     mc->default_boot_order = "cad";
1709     mc->block_default_type = IF_IDE;
1710     mc->max_cpus = 255;
1711     mc->reset = pc_machine_reset;
1712     mc->wakeup = pc_machine_wakeup;
1713     hc->pre_plug = pc_machine_device_pre_plug_cb;
1714     hc->plug = pc_machine_device_plug_cb;
1715     hc->unplug_request = pc_machine_device_unplug_request_cb;
1716     hc->unplug = pc_machine_device_unplug_cb;
1717     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1718     mc->nvdimm_supported = true;
1719     mc->smp_props.dies_supported = true;
1720     mc->default_ram_id = "pc.ram";
1721 
1722     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1723         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1724         NULL, NULL);
1725     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1726         "Maximum ram below the 4G boundary (32bit boundary)");
1727 
1728     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1729         pc_machine_get_device_memory_region_size, NULL,
1730         NULL, NULL);
1731 
1732     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1733         pc_machine_get_vmport, pc_machine_set_vmport,
1734         NULL, NULL);
1735     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1736         "Enable vmport (pc & q35)");
1737 
1738     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1739         pc_machine_get_smbus, pc_machine_set_smbus);
1740 
1741     object_class_property_add_bool(oc, PC_MACHINE_SATA,
1742         pc_machine_get_sata, pc_machine_set_sata);
1743 
1744     object_class_property_add_bool(oc, PC_MACHINE_PIT,
1745         pc_machine_get_pit, pc_machine_set_pit);
1746 
1747     object_class_property_add_bool(oc, "hpet",
1748         pc_machine_get_hpet, pc_machine_set_hpet);
1749 
1750     object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1751         pc_machine_get_default_bus_bypass_iommu,
1752         pc_machine_set_default_bus_bypass_iommu);
1753 
1754     object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1755         pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1756         NULL, NULL);
1757     object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1758         "Maximum combined firmware size");
1759 }
1760 
1761 static const TypeInfo pc_machine_info = {
1762     .name = TYPE_PC_MACHINE,
1763     .parent = TYPE_X86_MACHINE,
1764     .abstract = true,
1765     .instance_size = sizeof(PCMachineState),
1766     .instance_init = pc_machine_initfn,
1767     .class_size = sizeof(PCMachineClass),
1768     .class_init = pc_machine_class_init,
1769     .interfaces = (InterfaceInfo[]) {
1770          { TYPE_HOTPLUG_HANDLER },
1771          { }
1772     },
1773 };
1774 
1775 static void pc_machine_register_types(void)
1776 {
1777     type_register_static(&pc_machine_info);
1778 }
1779 
1780 type_init(pc_machine_register_types)
1781