1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/cxl/cxl.h" 79 #include "hw/cxl/cxl_host.h" 80 #include "qapi/error.h" 81 #include "qapi/qapi-visit-common.h" 82 #include "qapi/qapi-visit-machine.h" 83 #include "qapi/visitor.h" 84 #include "hw/core/cpu.h" 85 #include "hw/usb.h" 86 #include "hw/i386/intel_iommu.h" 87 #include "hw/net/ne2000-isa.h" 88 #include "standard-headers/asm-x86/bootparam.h" 89 #include "hw/virtio/virtio-iommu.h" 90 #include "hw/virtio/virtio-pmem-pci.h" 91 #include "hw/virtio/virtio-mem-pci.h" 92 #include "hw/mem/memory-device.h" 93 #include "sysemu/replay.h" 94 #include "qapi/qmp/qerror.h" 95 #include "e820_memory_layout.h" 96 #include "fw_cfg.h" 97 #include "trace.h" 98 #include CONFIG_DEVICES 99 100 GlobalProperty pc_compat_7_0[] = {}; 101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 102 103 GlobalProperty pc_compat_6_2[] = { 104 { "virtio-mem", "unplugged-inaccessible", "off" }, 105 }; 106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 107 108 GlobalProperty pc_compat_6_1[] = { 109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 113 }; 114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 115 116 GlobalProperty pc_compat_6_0[] = { 117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 123 }; 124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 125 126 GlobalProperty pc_compat_5_2[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 128 }; 129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 130 131 GlobalProperty pc_compat_5_1[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 134 }; 135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 136 137 GlobalProperty pc_compat_5_0[] = { 138 }; 139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 140 141 GlobalProperty pc_compat_4_2[] = { 142 { "mch", "smbase-smram", "off" }, 143 }; 144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 145 146 GlobalProperty pc_compat_4_1[] = {}; 147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 148 149 GlobalProperty pc_compat_4_0[] = {}; 150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 151 152 GlobalProperty pc_compat_3_1[] = { 153 { "intel-iommu", "dma-drain", "off" }, 154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 174 }; 175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 176 177 GlobalProperty pc_compat_3_0[] = { 178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 181 }; 182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 183 184 GlobalProperty pc_compat_2_12[] = { 185 { TYPE_X86_CPU, "legacy-cache", "on" }, 186 { TYPE_X86_CPU, "topoext", "off" }, 187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 }; 190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 191 192 GlobalProperty pc_compat_2_11[] = { 193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 195 }; 196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 197 198 GlobalProperty pc_compat_2_10[] = { 199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 201 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 202 }; 203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 204 205 GlobalProperty pc_compat_2_9[] = { 206 { "mch", "extended-tseg-mbytes", "0" }, 207 }; 208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 209 210 GlobalProperty pc_compat_2_8[] = { 211 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 213 { "ICH9-LPC", "x-smi-broadcast", "off" }, 214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 216 }; 217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 218 219 GlobalProperty pc_compat_2_7[] = { 220 { TYPE_X86_CPU, "l3-cache", "off" }, 221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 225 { "isa-pcspk", "migrate", "off" }, 226 }; 227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 228 229 GlobalProperty pc_compat_2_6[] = { 230 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 231 { "vmxnet3", "romfile", "" }, 232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 233 { "apic-common", "legacy-instance-id", "on", } 234 }; 235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 236 237 GlobalProperty pc_compat_2_5[] = {}; 238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 239 240 GlobalProperty pc_compat_2_4[] = { 241 PC_CPU_MODEL_IDS("2.4.0") 242 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 247 { TYPE_X86_CPU, "check", "off" }, 248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 256 }; 257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 258 259 GlobalProperty pc_compat_2_3[] = { 260 PC_CPU_MODEL_IDS("2.3.0") 261 { TYPE_X86_CPU, "arat", "off" }, 262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 281 }; 282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 283 284 GlobalProperty pc_compat_2_2[] = { 285 PC_CPU_MODEL_IDS("2.2.0") 286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 304 }; 305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 306 307 GlobalProperty pc_compat_2_1[] = { 308 PC_CPU_MODEL_IDS("2.1.0") 309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 }; 312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 313 314 GlobalProperty pc_compat_2_0[] = { 315 PC_CPU_MODEL_IDS("2.0.0") 316 { "virtio-scsi-pci", "any_layout", "off" }, 317 { "PIIX4_PM", "memory-hotplug-support", "off" }, 318 { "apic", "version", "0x11" }, 319 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 320 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 321 { "pci-serial", "prog_if", "0" }, 322 { "pci-serial-2x", "prog_if", "0" }, 323 { "pci-serial-4x", "prog_if", "0" }, 324 { "virtio-net-pci", "guest_announce", "off" }, 325 { "ICH9-LPC", "memory-hotplug-support", "off" }, 326 }; 327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 328 329 GlobalProperty pc_compat_1_7[] = { 330 PC_CPU_MODEL_IDS("1.7.0") 331 { TYPE_USB_DEVICE, "msos-desc", "no" }, 332 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 333 { "hpet", HPET_INTCAP, "4" }, 334 }; 335 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 336 337 GlobalProperty pc_compat_1_6[] = { 338 PC_CPU_MODEL_IDS("1.6.0") 339 { "e1000", "mitigation", "off" }, 340 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 341 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 342 { "i440FX-pcihost", "short_root_bus", "1" }, 343 { "q35-pcihost", "short_root_bus", "1" }, 344 }; 345 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 346 347 GlobalProperty pc_compat_1_5[] = { 348 PC_CPU_MODEL_IDS("1.5.0") 349 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 350 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 351 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 352 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 353 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 354 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 355 { "virtio-net-pci", "any_layout", "off" }, 356 { TYPE_X86_CPU, "pmu", "on" }, 357 { "i440FX-pcihost", "short_root_bus", "0" }, 358 { "q35-pcihost", "short_root_bus", "0" }, 359 }; 360 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 361 362 GlobalProperty pc_compat_1_4[] = { 363 PC_CPU_MODEL_IDS("1.4.0") 364 { "scsi-hd", "discard_granularity", "0" }, 365 { "scsi-cd", "discard_granularity", "0" }, 366 { "ide-hd", "discard_granularity", "0" }, 367 { "ide-cd", "discard_granularity", "0" }, 368 { "virtio-blk-pci", "discard_granularity", "0" }, 369 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 370 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 371 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 372 { "e1000", "romfile", "pxe-e1000.rom" }, 373 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 374 { "pcnet", "romfile", "pxe-pcnet.rom" }, 375 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 376 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 377 { "486-" TYPE_X86_CPU, "model", "0" }, 378 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 379 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 380 }; 381 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 382 383 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 384 { 385 GSIState *s; 386 387 s = g_new0(GSIState, 1); 388 if (kvm_ioapic_in_kernel()) { 389 kvm_pc_setup_irq_routing(pci_enabled); 390 } 391 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 392 393 return s; 394 } 395 396 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 397 unsigned size) 398 { 399 } 400 401 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 402 { 403 return 0xffffffffffffffffULL; 404 } 405 406 /* MSDOS compatibility mode FPU exception support */ 407 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 408 unsigned size) 409 { 410 if (tcg_enabled()) { 411 cpu_set_ignne(); 412 } 413 } 414 415 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 416 { 417 return 0xffffffffffffffffULL; 418 } 419 420 /* PC cmos mappings */ 421 422 #define REG_EQUIPMENT_BYTE 0x14 423 424 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 425 int16_t cylinders, int8_t heads, int8_t sectors) 426 { 427 rtc_set_memory(s, type_ofs, 47); 428 rtc_set_memory(s, info_ofs, cylinders); 429 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 430 rtc_set_memory(s, info_ofs + 2, heads); 431 rtc_set_memory(s, info_ofs + 3, 0xff); 432 rtc_set_memory(s, info_ofs + 4, 0xff); 433 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 434 rtc_set_memory(s, info_ofs + 6, cylinders); 435 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 436 rtc_set_memory(s, info_ofs + 8, sectors); 437 } 438 439 /* convert boot_device letter to something recognizable by the bios */ 440 static int boot_device2nibble(char boot_device) 441 { 442 switch(boot_device) { 443 case 'a': 444 case 'b': 445 return 0x01; /* floppy boot */ 446 case 'c': 447 return 0x02; /* hard drive boot */ 448 case 'd': 449 return 0x03; /* CD-ROM boot */ 450 case 'n': 451 return 0x04; /* Network boot */ 452 } 453 return 0; 454 } 455 456 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 457 { 458 #define PC_MAX_BOOT_DEVICES 3 459 int nbds, bds[3] = { 0, }; 460 int i; 461 462 nbds = strlen(boot_device); 463 if (nbds > PC_MAX_BOOT_DEVICES) { 464 error_setg(errp, "Too many boot devices for PC"); 465 return; 466 } 467 for (i = 0; i < nbds; i++) { 468 bds[i] = boot_device2nibble(boot_device[i]); 469 if (bds[i] == 0) { 470 error_setg(errp, "Invalid boot device for PC: '%c'", 471 boot_device[i]); 472 return; 473 } 474 } 475 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 476 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 477 } 478 479 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 480 { 481 set_boot_dev(opaque, boot_device, errp); 482 } 483 484 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 485 { 486 int val, nb, i; 487 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 488 FLOPPY_DRIVE_TYPE_NONE }; 489 490 /* floppy type */ 491 if (floppy) { 492 for (i = 0; i < 2; i++) { 493 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 494 } 495 } 496 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 497 cmos_get_fd_drive_type(fd_type[1]); 498 rtc_set_memory(rtc_state, 0x10, val); 499 500 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 501 nb = 0; 502 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 503 nb++; 504 } 505 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 506 nb++; 507 } 508 switch (nb) { 509 case 0: 510 break; 511 case 1: 512 val |= 0x01; /* 1 drive, ready for boot */ 513 break; 514 case 2: 515 val |= 0x41; /* 2 drives, ready for boot */ 516 break; 517 } 518 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 519 } 520 521 typedef struct pc_cmos_init_late_arg { 522 ISADevice *rtc_state; 523 BusState *idebus[2]; 524 } pc_cmos_init_late_arg; 525 526 typedef struct check_fdc_state { 527 ISADevice *floppy; 528 bool multiple; 529 } CheckFdcState; 530 531 static int check_fdc(Object *obj, void *opaque) 532 { 533 CheckFdcState *state = opaque; 534 Object *fdc; 535 uint32_t iobase; 536 Error *local_err = NULL; 537 538 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 539 if (!fdc) { 540 return 0; 541 } 542 543 iobase = object_property_get_uint(obj, "iobase", &local_err); 544 if (local_err || iobase != 0x3f0) { 545 error_free(local_err); 546 return 0; 547 } 548 549 if (state->floppy) { 550 state->multiple = true; 551 } else { 552 state->floppy = ISA_DEVICE(obj); 553 } 554 return 0; 555 } 556 557 static const char * const fdc_container_path[] = { 558 "/unattached", "/peripheral", "/peripheral-anon" 559 }; 560 561 /* 562 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 563 * and ACPI objects. 564 */ 565 ISADevice *pc_find_fdc0(void) 566 { 567 int i; 568 Object *container; 569 CheckFdcState state = { 0 }; 570 571 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 572 container = container_get(qdev_get_machine(), fdc_container_path[i]); 573 object_child_foreach(container, check_fdc, &state); 574 } 575 576 if (state.multiple) { 577 warn_report("multiple floppy disk controllers with " 578 "iobase=0x3f0 have been found"); 579 error_printf("the one being picked for CMOS setup might not reflect " 580 "your intent"); 581 } 582 583 return state.floppy; 584 } 585 586 static void pc_cmos_init_late(void *opaque) 587 { 588 pc_cmos_init_late_arg *arg = opaque; 589 ISADevice *s = arg->rtc_state; 590 int16_t cylinders; 591 int8_t heads, sectors; 592 int val; 593 int i, trans; 594 595 val = 0; 596 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 597 &cylinders, &heads, §ors) >= 0) { 598 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 599 val |= 0xf0; 600 } 601 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 602 &cylinders, &heads, §ors) >= 0) { 603 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 604 val |= 0x0f; 605 } 606 rtc_set_memory(s, 0x12, val); 607 608 val = 0; 609 for (i = 0; i < 4; i++) { 610 /* NOTE: ide_get_geometry() returns the physical 611 geometry. It is always such that: 1 <= sects <= 63, 1 612 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 613 geometry can be different if a translation is done. */ 614 if (arg->idebus[i / 2] && 615 ide_get_geometry(arg->idebus[i / 2], i % 2, 616 &cylinders, &heads, §ors) >= 0) { 617 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 618 assert((trans & ~3) == 0); 619 val |= trans << (i * 2); 620 } 621 } 622 rtc_set_memory(s, 0x39, val); 623 624 pc_cmos_init_floppy(s, pc_find_fdc0()); 625 626 qemu_unregister_reset(pc_cmos_init_late, opaque); 627 } 628 629 void pc_cmos_init(PCMachineState *pcms, 630 BusState *idebus0, BusState *idebus1, 631 ISADevice *s) 632 { 633 int val; 634 static pc_cmos_init_late_arg arg; 635 X86MachineState *x86ms = X86_MACHINE(pcms); 636 637 /* various important CMOS locations needed by PC/Bochs bios */ 638 639 /* memory size */ 640 /* base memory (first MiB) */ 641 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 642 rtc_set_memory(s, 0x15, val); 643 rtc_set_memory(s, 0x16, val >> 8); 644 /* extended memory (next 64MiB) */ 645 if (x86ms->below_4g_mem_size > 1 * MiB) { 646 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 647 } else { 648 val = 0; 649 } 650 if (val > 65535) 651 val = 65535; 652 rtc_set_memory(s, 0x17, val); 653 rtc_set_memory(s, 0x18, val >> 8); 654 rtc_set_memory(s, 0x30, val); 655 rtc_set_memory(s, 0x31, val >> 8); 656 /* memory between 16MiB and 4GiB */ 657 if (x86ms->below_4g_mem_size > 16 * MiB) { 658 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 659 } else { 660 val = 0; 661 } 662 if (val > 65535) 663 val = 65535; 664 rtc_set_memory(s, 0x34, val); 665 rtc_set_memory(s, 0x35, val >> 8); 666 /* memory above 4GiB */ 667 val = x86ms->above_4g_mem_size / 65536; 668 rtc_set_memory(s, 0x5b, val); 669 rtc_set_memory(s, 0x5c, val >> 8); 670 rtc_set_memory(s, 0x5d, val >> 16); 671 672 object_property_add_link(OBJECT(pcms), "rtc_state", 673 TYPE_ISA_DEVICE, 674 (Object **)&x86ms->rtc, 675 object_property_allow_set_link, 676 OBJ_PROP_LINK_STRONG); 677 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 678 &error_abort); 679 680 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 681 682 val = 0; 683 val |= 0x02; /* FPU is there */ 684 val |= 0x04; /* PS/2 mouse installed */ 685 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 686 687 /* hard drives and FDC */ 688 arg.rtc_state = s; 689 arg.idebus[0] = idebus0; 690 arg.idebus[1] = idebus1; 691 qemu_register_reset(pc_cmos_init_late, &arg); 692 } 693 694 static void handle_a20_line_change(void *opaque, int irq, int level) 695 { 696 X86CPU *cpu = opaque; 697 698 /* XXX: send to all CPUs ? */ 699 /* XXX: add logic to handle multiple A20 line sources */ 700 x86_cpu_set_a20(cpu, level); 701 } 702 703 #define NE2000_NB_MAX 6 704 705 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 706 0x280, 0x380 }; 707 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 708 709 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 710 { 711 static int nb_ne2k = 0; 712 713 if (nb_ne2k == NE2000_NB_MAX) 714 return; 715 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 716 ne2000_irq[nb_ne2k], nd); 717 nb_ne2k++; 718 } 719 720 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 721 { 722 X86CPU *cpu = opaque; 723 724 if (level) { 725 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 726 } 727 } 728 729 static 730 void pc_machine_done(Notifier *notifier, void *data) 731 { 732 PCMachineState *pcms = container_of(notifier, 733 PCMachineState, machine_done); 734 X86MachineState *x86ms = X86_MACHINE(pcms); 735 736 /* set the number of CPUs */ 737 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 738 739 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 740 741 acpi_setup(); 742 if (x86ms->fw_cfg) { 743 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 744 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 745 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 746 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 747 } 748 } 749 750 void pc_guest_info_init(PCMachineState *pcms) 751 { 752 X86MachineState *x86ms = X86_MACHINE(pcms); 753 754 x86ms->apic_xrupt_override = true; 755 pcms->machine_done.notify = pc_machine_done; 756 qemu_add_machine_init_done_notifier(&pcms->machine_done); 757 } 758 759 /* setup pci memory address space mapping into system address space */ 760 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 761 MemoryRegion *pci_address_space) 762 { 763 /* Set to lower priority than RAM */ 764 memory_region_add_subregion_overlap(system_memory, 0x0, 765 pci_address_space, -1); 766 } 767 768 void xen_load_linux(PCMachineState *pcms) 769 { 770 int i; 771 FWCfgState *fw_cfg; 772 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 773 X86MachineState *x86ms = X86_MACHINE(pcms); 774 775 assert(MACHINE(pcms)->kernel_filename != NULL); 776 777 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 778 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 779 rom_set_fw(fw_cfg); 780 781 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 782 pcmc->pvh_enabled); 783 for (i = 0; i < nb_option_roms; i++) { 784 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 785 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 786 !strcmp(option_rom[i].name, "pvh.bin") || 787 !strcmp(option_rom[i].name, "multiboot.bin") || 788 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 789 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 790 } 791 x86ms->fw_cfg = fw_cfg; 792 } 793 794 #define PC_ROM_MIN_VGA 0xc0000 795 #define PC_ROM_MIN_OPTION 0xc8000 796 #define PC_ROM_MAX 0xe0000 797 #define PC_ROM_ALIGN 0x800 798 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 799 800 void pc_memory_init(PCMachineState *pcms, 801 MemoryRegion *system_memory, 802 MemoryRegion *rom_memory, 803 MemoryRegion **ram_memory) 804 { 805 int linux_boot, i; 806 MemoryRegion *option_rom_mr; 807 MemoryRegion *ram_below_4g, *ram_above_4g; 808 FWCfgState *fw_cfg; 809 MachineState *machine = MACHINE(pcms); 810 MachineClass *mc = MACHINE_GET_CLASS(machine); 811 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 812 X86MachineState *x86ms = X86_MACHINE(pcms); 813 hwaddr cxl_base, cxl_resv_end = 0; 814 815 assert(machine->ram_size == x86ms->below_4g_mem_size + 816 x86ms->above_4g_mem_size); 817 818 linux_boot = (machine->kernel_filename != NULL); 819 820 /* 821 * Split single memory region and use aliases to address portions of it, 822 * done for backwards compatibility with older qemus. 823 */ 824 *ram_memory = machine->ram; 825 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 826 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 827 0, x86ms->below_4g_mem_size); 828 memory_region_add_subregion(system_memory, 0, ram_below_4g); 829 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 830 if (x86ms->above_4g_mem_size > 0) { 831 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 832 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 833 machine->ram, 834 x86ms->below_4g_mem_size, 835 x86ms->above_4g_mem_size); 836 memory_region_add_subregion(system_memory, 0x100000000ULL, 837 ram_above_4g); 838 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 839 } 840 841 if (pcms->sgx_epc.size != 0) { 842 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 843 } 844 845 if (!pcmc->has_reserved_memory && 846 (machine->ram_slots || 847 (machine->maxram_size > machine->ram_size))) { 848 849 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 850 mc->name); 851 exit(EXIT_FAILURE); 852 } 853 854 /* always allocate the device memory information */ 855 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 856 857 /* initialize device memory address space */ 858 if (pcmc->has_reserved_memory && 859 (machine->ram_size < machine->maxram_size)) { 860 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 861 862 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 863 error_report("unsupported amount of memory slots: %"PRIu64, 864 machine->ram_slots); 865 exit(EXIT_FAILURE); 866 } 867 868 if (QEMU_ALIGN_UP(machine->maxram_size, 869 TARGET_PAGE_SIZE) != machine->maxram_size) { 870 error_report("maximum memory size must by aligned to multiple of " 871 "%d bytes", TARGET_PAGE_SIZE); 872 exit(EXIT_FAILURE); 873 } 874 875 if (pcms->sgx_epc.size != 0) { 876 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 877 } else { 878 machine->device_memory->base = 879 0x100000000ULL + x86ms->above_4g_mem_size; 880 } 881 882 machine->device_memory->base = 883 ROUND_UP(machine->device_memory->base, 1 * GiB); 884 885 if (pcmc->enforce_aligned_dimm) { 886 /* size device region assuming 1G page max alignment per slot */ 887 device_mem_size += (1 * GiB) * machine->ram_slots; 888 } 889 890 if ((machine->device_memory->base + device_mem_size) < 891 device_mem_size) { 892 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 893 machine->maxram_size); 894 exit(EXIT_FAILURE); 895 } 896 897 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 898 "device-memory", device_mem_size); 899 memory_region_add_subregion(system_memory, machine->device_memory->base, 900 &machine->device_memory->mr); 901 } 902 903 if (machine->cxl_devices_state->is_enabled) { 904 MemoryRegion *mr = &machine->cxl_devices_state->host_mr; 905 hwaddr cxl_size = MiB; 906 907 if (pcmc->has_reserved_memory && machine->device_memory->base) { 908 cxl_base = machine->device_memory->base; 909 if (!pcmc->broken_reserved_end) { 910 cxl_base += memory_region_size(&machine->device_memory->mr); 911 } 912 } else if (pcms->sgx_epc.size != 0) { 913 cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc); 914 } else { 915 cxl_base = 0x100000000ULL + x86ms->above_4g_mem_size; 916 } 917 918 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); 919 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 920 memory_region_add_subregion(system_memory, cxl_base, mr); 921 cxl_resv_end = cxl_base + cxl_size; 922 if (machine->cxl_devices_state->fixed_windows) { 923 hwaddr cxl_fmw_base; 924 GList *it; 925 926 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 927 for (it = machine->cxl_devices_state->fixed_windows; it; it = it->next) { 928 CXLFixedWindow *fw = it->data; 929 930 fw->base = cxl_fmw_base; 931 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 932 "cxl-fixed-memory-region", fw->size); 933 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 934 e820_add_entry(fw->base, fw->size, E820_RESERVED); 935 cxl_fmw_base += fw->size; 936 cxl_resv_end = cxl_fmw_base; 937 } 938 } 939 } 940 941 /* Initialize PC system firmware */ 942 pc_system_firmware_init(pcms, rom_memory); 943 944 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 945 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 946 &error_fatal); 947 if (pcmc->pci_enabled) { 948 memory_region_set_readonly(option_rom_mr, true); 949 } 950 memory_region_add_subregion_overlap(rom_memory, 951 PC_ROM_MIN_VGA, 952 option_rom_mr, 953 1); 954 955 fw_cfg = fw_cfg_arch_create(machine, 956 x86ms->boot_cpus, x86ms->apic_id_limit); 957 958 rom_set_fw(fw_cfg); 959 960 if (pcmc->has_reserved_memory && machine->device_memory->base) { 961 uint64_t *val = g_malloc(sizeof(*val)); 962 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 963 uint64_t res_mem_end = machine->device_memory->base; 964 965 if (!pcmc->broken_reserved_end) { 966 res_mem_end += memory_region_size(&machine->device_memory->mr); 967 } 968 969 if (machine->cxl_devices_state->is_enabled) { 970 res_mem_end = cxl_resv_end; 971 } 972 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 973 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 974 } 975 976 if (linux_boot) { 977 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 978 pcmc->pvh_enabled); 979 } 980 981 for (i = 0; i < nb_option_roms; i++) { 982 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 983 } 984 x86ms->fw_cfg = fw_cfg; 985 986 /* Init default IOAPIC address space */ 987 x86ms->ioapic_as = &address_space_memory; 988 989 /* Init ACPI memory hotplug IO base address */ 990 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 991 } 992 993 /* 994 * The 64bit pci hole starts after "above 4G RAM" and 995 * potentially the space reserved for memory hotplug. 996 */ 997 uint64_t pc_pci_hole64_start(void) 998 { 999 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1000 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1001 MachineState *ms = MACHINE(pcms); 1002 X86MachineState *x86ms = X86_MACHINE(pcms); 1003 uint64_t hole64_start = 0; 1004 1005 if (ms->cxl_devices_state->host_mr.addr) { 1006 hole64_start = ms->cxl_devices_state->host_mr.addr + 1007 memory_region_size(&ms->cxl_devices_state->host_mr); 1008 if (ms->cxl_devices_state->fixed_windows) { 1009 GList *it; 1010 for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) { 1011 CXLFixedWindow *fw = it->data; 1012 hole64_start = fw->mr.addr + memory_region_size(&fw->mr); 1013 } 1014 } 1015 } else if (pcmc->has_reserved_memory && ms->device_memory->base) { 1016 hole64_start = ms->device_memory->base; 1017 if (!pcmc->broken_reserved_end) { 1018 hole64_start += memory_region_size(&ms->device_memory->mr); 1019 } 1020 } else if (pcms->sgx_epc.size != 0) { 1021 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 1022 } else { 1023 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1024 } 1025 1026 return ROUND_UP(hole64_start, 1 * GiB); 1027 } 1028 1029 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1030 { 1031 DeviceState *dev = NULL; 1032 1033 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1034 if (pci_bus) { 1035 PCIDevice *pcidev = pci_vga_init(pci_bus); 1036 dev = pcidev ? &pcidev->qdev : NULL; 1037 } else if (isa_bus) { 1038 ISADevice *isadev = isa_vga_init(isa_bus); 1039 dev = isadev ? DEVICE(isadev) : NULL; 1040 } 1041 rom_reset_order_override(); 1042 return dev; 1043 } 1044 1045 static const MemoryRegionOps ioport80_io_ops = { 1046 .write = ioport80_write, 1047 .read = ioport80_read, 1048 .endianness = DEVICE_NATIVE_ENDIAN, 1049 .impl = { 1050 .min_access_size = 1, 1051 .max_access_size = 1, 1052 }, 1053 }; 1054 1055 static const MemoryRegionOps ioportF0_io_ops = { 1056 .write = ioportF0_write, 1057 .read = ioportF0_read, 1058 .endianness = DEVICE_NATIVE_ENDIAN, 1059 .impl = { 1060 .min_access_size = 1, 1061 .max_access_size = 1, 1062 }, 1063 }; 1064 1065 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1066 bool create_i8042, bool no_vmport) 1067 { 1068 int i; 1069 DriveInfo *fd[MAX_FD]; 1070 qemu_irq *a20_line; 1071 ISADevice *fdc, *i8042, *port92, *vmmouse; 1072 1073 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1074 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1075 1076 for (i = 0; i < MAX_FD; i++) { 1077 fd[i] = drive_get(IF_FLOPPY, 0, i); 1078 create_fdctrl |= !!fd[i]; 1079 } 1080 if (create_fdctrl) { 1081 fdc = isa_new(TYPE_ISA_FDC); 1082 if (fdc) { 1083 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1084 isa_fdc_init_drives(fdc, fd); 1085 } 1086 } 1087 1088 if (!create_i8042) { 1089 return; 1090 } 1091 1092 i8042 = isa_create_simple(isa_bus, "i8042"); 1093 if (!no_vmport) { 1094 isa_create_simple(isa_bus, TYPE_VMPORT); 1095 vmmouse = isa_try_new("vmmouse"); 1096 } else { 1097 vmmouse = NULL; 1098 } 1099 if (vmmouse) { 1100 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1101 &error_abort); 1102 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1103 } 1104 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1105 1106 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1107 i8042_setup_a20_line(i8042, a20_line[0]); 1108 qdev_connect_gpio_out_named(DEVICE(port92), 1109 PORT92_A20_LINE, 0, a20_line[1]); 1110 g_free(a20_line); 1111 } 1112 1113 void pc_basic_device_init(struct PCMachineState *pcms, 1114 ISABus *isa_bus, qemu_irq *gsi, 1115 ISADevice **rtc_state, 1116 bool create_fdctrl, 1117 uint32_t hpet_irqs) 1118 { 1119 int i; 1120 DeviceState *hpet = NULL; 1121 int pit_isa_irq = 0; 1122 qemu_irq pit_alt_irq = NULL; 1123 qemu_irq rtc_irq = NULL; 1124 ISADevice *pit = NULL; 1125 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1126 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1127 X86MachineState *x86ms = X86_MACHINE(pcms); 1128 1129 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1130 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1131 1132 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1133 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1134 1135 /* 1136 * Check if an HPET shall be created. 1137 * 1138 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1139 * when the HPET wants to take over. Thus we have to disable the latter. 1140 */ 1141 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1142 kvm_has_pit_state2())) { 1143 hpet = qdev_try_new(TYPE_HPET); 1144 if (!hpet) { 1145 error_report("couldn't create HPET device"); 1146 exit(1); 1147 } 1148 /* 1149 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1150 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1151 * IRQ2. 1152 */ 1153 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1154 HPET_INTCAP, NULL); 1155 if (!compat) { 1156 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1157 } 1158 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1159 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1160 1161 for (i = 0; i < GSI_NUM_PINS; i++) { 1162 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1163 } 1164 pit_isa_irq = -1; 1165 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1166 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1167 } 1168 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1169 1170 qemu_register_boot_set(pc_boot_set, *rtc_state); 1171 1172 if (!xen_enabled() && 1173 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1174 if (kvm_pit_in_kernel()) { 1175 pit = kvm_pit_init(isa_bus, 0x40); 1176 } else { 1177 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1178 } 1179 if (hpet) { 1180 /* connect PIT to output control line of the HPET */ 1181 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1182 } 1183 pcspk_init(pcms->pcspk, isa_bus, pit); 1184 } 1185 1186 i8257_dma_init(isa_bus, 0); 1187 1188 /* Super I/O */ 1189 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1190 pcms->vmport != ON_OFF_AUTO_ON); 1191 } 1192 1193 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1194 { 1195 int i; 1196 1197 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1198 for (i = 0; i < nb_nics; i++) { 1199 NICInfo *nd = &nd_table[i]; 1200 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1201 1202 if (g_str_equal(model, "ne2k_isa")) { 1203 pc_init_ne2k_isa(isa_bus, nd); 1204 } else { 1205 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1206 } 1207 } 1208 rom_reset_order_override(); 1209 } 1210 1211 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1212 { 1213 qemu_irq *i8259; 1214 1215 if (kvm_pic_in_kernel()) { 1216 i8259 = kvm_i8259_init(isa_bus); 1217 } else if (xen_enabled()) { 1218 i8259 = xen_interrupt_controller_init(); 1219 } else { 1220 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1221 } 1222 1223 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1224 i8259_irqs[i] = i8259[i]; 1225 } 1226 1227 g_free(i8259); 1228 } 1229 1230 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1231 Error **errp) 1232 { 1233 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1234 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1235 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1236 const MachineState *ms = MACHINE(hotplug_dev); 1237 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1238 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1239 Error *local_err = NULL; 1240 1241 /* 1242 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1243 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1244 * addition to cover this case. 1245 */ 1246 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1247 error_setg(errp, 1248 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1249 return; 1250 } 1251 1252 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1253 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1254 return; 1255 } 1256 1257 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1258 if (local_err) { 1259 error_propagate(errp, local_err); 1260 return; 1261 } 1262 1263 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1264 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1265 } 1266 1267 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1268 DeviceState *dev, Error **errp) 1269 { 1270 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1271 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1272 MachineState *ms = MACHINE(hotplug_dev); 1273 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1274 1275 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1276 1277 if (is_nvdimm) { 1278 nvdimm_plug(ms->nvdimms_state); 1279 } 1280 1281 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1282 } 1283 1284 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1285 DeviceState *dev, Error **errp) 1286 { 1287 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1288 1289 /* 1290 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1291 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1292 * addition to cover this case. 1293 */ 1294 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1295 error_setg(errp, 1296 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1297 return; 1298 } 1299 1300 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1301 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1302 return; 1303 } 1304 1305 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1306 errp); 1307 } 1308 1309 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1310 DeviceState *dev, Error **errp) 1311 { 1312 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1313 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1314 Error *local_err = NULL; 1315 1316 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1317 if (local_err) { 1318 goto out; 1319 } 1320 1321 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1322 qdev_unrealize(dev); 1323 out: 1324 error_propagate(errp, local_err); 1325 } 1326 1327 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1328 DeviceState *dev, Error **errp) 1329 { 1330 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1331 Error *local_err = NULL; 1332 1333 if (!hotplug_dev2 && dev->hotplugged) { 1334 /* 1335 * Without a bus hotplug handler, we cannot control the plug/unplug 1336 * order. We should never reach this point when hotplugging on x86, 1337 * however, better add a safety net. 1338 */ 1339 error_setg(errp, "hotplug of virtio based memory devices not supported" 1340 " on this bus."); 1341 return; 1342 } 1343 /* 1344 * First, see if we can plug this memory device at all. If that 1345 * succeeds, branch of to the actual hotplug handler. 1346 */ 1347 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1348 &local_err); 1349 if (!local_err && hotplug_dev2) { 1350 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1351 } 1352 error_propagate(errp, local_err); 1353 } 1354 1355 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1356 DeviceState *dev, Error **errp) 1357 { 1358 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1359 Error *local_err = NULL; 1360 1361 /* 1362 * Plug the memory device first and then branch off to the actual 1363 * hotplug handler. If that one fails, we can easily undo the memory 1364 * device bits. 1365 */ 1366 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1367 if (hotplug_dev2) { 1368 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1369 if (local_err) { 1370 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1371 } 1372 } 1373 error_propagate(errp, local_err); 1374 } 1375 1376 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1377 DeviceState *dev, Error **errp) 1378 { 1379 /* We don't support hot unplug of virtio based memory devices */ 1380 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1381 } 1382 1383 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1384 DeviceState *dev, Error **errp) 1385 { 1386 /* We don't support hot unplug of virtio based memory devices */ 1387 } 1388 1389 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1390 DeviceState *dev, Error **errp) 1391 { 1392 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1393 pc_memory_pre_plug(hotplug_dev, dev, errp); 1394 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1395 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1397 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1398 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1399 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1400 /* Declare the APIC range as the reserved MSI region */ 1401 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1402 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1403 1404 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1405 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1406 resv_prop_str, errp); 1407 g_free(resv_prop_str); 1408 } 1409 1410 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1411 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1412 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1413 1414 if (pcms->iommu) { 1415 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1416 "for x86 yet."); 1417 return; 1418 } 1419 pcms->iommu = dev; 1420 } 1421 } 1422 1423 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1424 DeviceState *dev, Error **errp) 1425 { 1426 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1427 pc_memory_plug(hotplug_dev, dev, errp); 1428 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1429 x86_cpu_plug(hotplug_dev, dev, errp); 1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1431 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1432 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1433 } 1434 } 1435 1436 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1437 DeviceState *dev, Error **errp) 1438 { 1439 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1440 pc_memory_unplug_request(hotplug_dev, dev, errp); 1441 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1442 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1443 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1444 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1445 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1446 } else { 1447 error_setg(errp, "acpi: device unplug request for not supported device" 1448 " type: %s", object_get_typename(OBJECT(dev))); 1449 } 1450 } 1451 1452 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1453 DeviceState *dev, Error **errp) 1454 { 1455 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1456 pc_memory_unplug(hotplug_dev, dev, errp); 1457 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1458 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1459 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1460 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1461 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1462 } else { 1463 error_setg(errp, "acpi: device unplug for not supported device" 1464 " type: %s", object_get_typename(OBJECT(dev))); 1465 } 1466 } 1467 1468 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1469 DeviceState *dev) 1470 { 1471 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1472 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1473 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1474 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1475 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1476 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1477 return HOTPLUG_HANDLER(machine); 1478 } 1479 1480 return NULL; 1481 } 1482 1483 static void 1484 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1485 const char *name, void *opaque, 1486 Error **errp) 1487 { 1488 MachineState *ms = MACHINE(obj); 1489 int64_t value = 0; 1490 1491 if (ms->device_memory) { 1492 value = memory_region_size(&ms->device_memory->mr); 1493 } 1494 1495 visit_type_int(v, name, &value, errp); 1496 } 1497 1498 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1499 void *opaque, Error **errp) 1500 { 1501 PCMachineState *pcms = PC_MACHINE(obj); 1502 OnOffAuto vmport = pcms->vmport; 1503 1504 visit_type_OnOffAuto(v, name, &vmport, errp); 1505 } 1506 1507 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1508 void *opaque, Error **errp) 1509 { 1510 PCMachineState *pcms = PC_MACHINE(obj); 1511 1512 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1513 } 1514 1515 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 return pcms->smbus_enabled; 1520 } 1521 1522 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 1526 pcms->smbus_enabled = value; 1527 } 1528 1529 static bool pc_machine_get_sata(Object *obj, Error **errp) 1530 { 1531 PCMachineState *pcms = PC_MACHINE(obj); 1532 1533 return pcms->sata_enabled; 1534 } 1535 1536 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 1540 pcms->sata_enabled = value; 1541 } 1542 1543 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1544 { 1545 PCMachineState *pcms = PC_MACHINE(obj); 1546 1547 return pcms->hpet_enabled; 1548 } 1549 1550 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1551 { 1552 PCMachineState *pcms = PC_MACHINE(obj); 1553 1554 pcms->hpet_enabled = value; 1555 } 1556 1557 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1558 { 1559 PCMachineState *pcms = PC_MACHINE(obj); 1560 1561 return pcms->i8042_enabled; 1562 } 1563 1564 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1565 { 1566 PCMachineState *pcms = PC_MACHINE(obj); 1567 1568 pcms->i8042_enabled = value; 1569 } 1570 1571 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1572 { 1573 PCMachineState *pcms = PC_MACHINE(obj); 1574 1575 return pcms->default_bus_bypass_iommu; 1576 } 1577 1578 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1579 Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 1583 pcms->default_bus_bypass_iommu = value; 1584 } 1585 1586 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1587 void *opaque, Error **errp) 1588 { 1589 PCMachineState *pcms = PC_MACHINE(obj); 1590 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1591 1592 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1593 } 1594 1595 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1596 void *opaque, Error **errp) 1597 { 1598 PCMachineState *pcms = PC_MACHINE(obj); 1599 1600 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1601 } 1602 1603 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1604 const char *name, void *opaque, 1605 Error **errp) 1606 { 1607 PCMachineState *pcms = PC_MACHINE(obj); 1608 uint64_t value = pcms->max_ram_below_4g; 1609 1610 visit_type_size(v, name, &value, errp); 1611 } 1612 1613 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1614 const char *name, void *opaque, 1615 Error **errp) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 uint64_t value; 1619 1620 if (!visit_type_size(v, name, &value, errp)) { 1621 return; 1622 } 1623 if (value > 4 * GiB) { 1624 error_setg(errp, 1625 "Machine option 'max-ram-below-4g=%"PRIu64 1626 "' expects size less than or equal to 4G", value); 1627 return; 1628 } 1629 1630 if (value < 1 * MiB) { 1631 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1632 "BIOS may not work with less than 1MiB", value); 1633 } 1634 1635 pcms->max_ram_below_4g = value; 1636 } 1637 1638 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1639 const char *name, void *opaque, 1640 Error **errp) 1641 { 1642 PCMachineState *pcms = PC_MACHINE(obj); 1643 uint64_t value = pcms->max_fw_size; 1644 1645 visit_type_size(v, name, &value, errp); 1646 } 1647 1648 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1649 const char *name, void *opaque, 1650 Error **errp) 1651 { 1652 PCMachineState *pcms = PC_MACHINE(obj); 1653 Error *error = NULL; 1654 uint64_t value; 1655 1656 visit_type_size(v, name, &value, &error); 1657 if (error) { 1658 error_propagate(errp, error); 1659 return; 1660 } 1661 1662 /* 1663 * We don't have a theoretically justifiable exact lower bound on the base 1664 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1665 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1666 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1667 * size. 1668 */ 1669 if (value > 16 * MiB) { 1670 error_setg(errp, 1671 "User specified max allowed firmware size %" PRIu64 " is " 1672 "greater than 16MiB. If combined firwmare size exceeds " 1673 "16MiB the system may not boot, or experience intermittent" 1674 "stability issues.", 1675 value); 1676 return; 1677 } 1678 1679 pcms->max_fw_size = value; 1680 } 1681 1682 1683 static void pc_machine_initfn(Object *obj) 1684 { 1685 PCMachineState *pcms = PC_MACHINE(obj); 1686 MachineState *ms = MACHINE(obj); 1687 1688 #ifdef CONFIG_VMPORT 1689 pcms->vmport = ON_OFF_AUTO_AUTO; 1690 #else 1691 pcms->vmport = ON_OFF_AUTO_OFF; 1692 #endif /* CONFIG_VMPORT */ 1693 pcms->max_ram_below_4g = 0; /* use default */ 1694 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1695 1696 /* acpi build is enabled by default if machine supports it */ 1697 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1698 pcms->smbus_enabled = true; 1699 pcms->sata_enabled = true; 1700 pcms->i8042_enabled = true; 1701 pcms->max_fw_size = 8 * MiB; 1702 #ifdef CONFIG_HPET 1703 pcms->hpet_enabled = true; 1704 #endif 1705 pcms->default_bus_bypass_iommu = false; 1706 1707 pc_system_flash_create(pcms); 1708 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1709 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1710 OBJECT(pcms->pcspk), "audiodev"); 1711 cxl_machine_init(obj, ms->cxl_devices_state); 1712 } 1713 1714 static void pc_machine_reset(MachineState *machine) 1715 { 1716 CPUState *cs; 1717 X86CPU *cpu; 1718 1719 qemu_devices_reset(); 1720 1721 /* Reset APIC after devices have been reset to cancel 1722 * any changes that qemu_devices_reset() might have done. 1723 */ 1724 CPU_FOREACH(cs) { 1725 cpu = X86_CPU(cs); 1726 1727 if (cpu->apic_state) { 1728 device_legacy_reset(cpu->apic_state); 1729 } 1730 } 1731 } 1732 1733 static void pc_machine_wakeup(MachineState *machine) 1734 { 1735 cpu_synchronize_all_states(); 1736 pc_machine_reset(machine); 1737 cpu_synchronize_all_post_reset(); 1738 } 1739 1740 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1741 { 1742 X86IOMMUState *iommu = x86_iommu_get_default(); 1743 IntelIOMMUState *intel_iommu; 1744 1745 if (iommu && 1746 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1747 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1748 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1749 if (!intel_iommu->caching_mode) { 1750 error_setg(errp, "Device assignment is not allowed without " 1751 "enabling caching-mode=on for Intel IOMMU."); 1752 return false; 1753 } 1754 } 1755 1756 return true; 1757 } 1758 1759 static void pc_machine_class_init(ObjectClass *oc, void *data) 1760 { 1761 MachineClass *mc = MACHINE_CLASS(oc); 1762 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1763 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1764 1765 pcmc->pci_enabled = true; 1766 pcmc->has_acpi_build = true; 1767 pcmc->rsdp_in_ram = true; 1768 pcmc->smbios_defaults = true; 1769 pcmc->smbios_uuid_encoded = true; 1770 pcmc->gigabyte_align = true; 1771 pcmc->has_reserved_memory = true; 1772 pcmc->kvmclock_enabled = true; 1773 pcmc->enforce_aligned_dimm = true; 1774 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1775 * to be used at the moment, 32K should be enough for a while. */ 1776 pcmc->acpi_data_size = 0x20000 + 0x8000; 1777 pcmc->pvh_enabled = true; 1778 pcmc->kvmclock_create_always = true; 1779 assert(!mc->get_hotplug_handler); 1780 mc->get_hotplug_handler = pc_get_hotplug_handler; 1781 mc->hotplug_allowed = pc_hotplug_allowed; 1782 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1783 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1784 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1785 mc->auto_enable_numa_with_memhp = true; 1786 mc->auto_enable_numa_with_memdev = true; 1787 mc->has_hotpluggable_cpus = true; 1788 mc->default_boot_order = "cad"; 1789 mc->block_default_type = IF_IDE; 1790 mc->max_cpus = 255; 1791 mc->reset = pc_machine_reset; 1792 mc->wakeup = pc_machine_wakeup; 1793 hc->pre_plug = pc_machine_device_pre_plug_cb; 1794 hc->plug = pc_machine_device_plug_cb; 1795 hc->unplug_request = pc_machine_device_unplug_request_cb; 1796 hc->unplug = pc_machine_device_unplug_cb; 1797 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1798 mc->nvdimm_supported = true; 1799 mc->smp_props.dies_supported = true; 1800 mc->cxl_supported = true; 1801 mc->default_ram_id = "pc.ram"; 1802 1803 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1804 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1805 NULL, NULL); 1806 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1807 "Maximum ram below the 4G boundary (32bit boundary)"); 1808 1809 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1810 pc_machine_get_device_memory_region_size, NULL, 1811 NULL, NULL); 1812 1813 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1814 pc_machine_get_vmport, pc_machine_set_vmport, 1815 NULL, NULL); 1816 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1817 "Enable vmport (pc & q35)"); 1818 1819 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1820 pc_machine_get_smbus, pc_machine_set_smbus); 1821 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1822 "Enable/disable system management bus"); 1823 1824 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1825 pc_machine_get_sata, pc_machine_set_sata); 1826 object_class_property_set_description(oc, PC_MACHINE_SATA, 1827 "Enable/disable Serial ATA bus"); 1828 1829 object_class_property_add_bool(oc, "hpet", 1830 pc_machine_get_hpet, pc_machine_set_hpet); 1831 object_class_property_set_description(oc, "hpet", 1832 "Enable/disable high precision event timer emulation"); 1833 1834 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1835 pc_machine_get_i8042, pc_machine_set_i8042); 1836 1837 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1838 pc_machine_get_default_bus_bypass_iommu, 1839 pc_machine_set_default_bus_bypass_iommu); 1840 1841 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1842 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1843 NULL, NULL); 1844 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1845 "Maximum combined firmware size"); 1846 1847 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1848 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1849 NULL, NULL); 1850 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1851 "SMBIOS Entry Point type [32, 64]"); 1852 } 1853 1854 static const TypeInfo pc_machine_info = { 1855 .name = TYPE_PC_MACHINE, 1856 .parent = TYPE_X86_MACHINE, 1857 .abstract = true, 1858 .instance_size = sizeof(PCMachineState), 1859 .instance_init = pc_machine_initfn, 1860 .class_size = sizeof(PCMachineClass), 1861 .class_init = pc_machine_class_init, 1862 .interfaces = (InterfaceInfo[]) { 1863 { TYPE_HOTPLUG_HANDLER }, 1864 { } 1865 }, 1866 }; 1867 1868 static void pc_machine_register_types(void) 1869 { 1870 type_register_static(&pc_machine_info); 1871 } 1872 1873 type_init(pc_machine_register_types) 1874