1 /* 2 * Copyright (c) 2018 Intel Corporation 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2 or later, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/error-report.h" 20 #include "qemu/cutils.h" 21 #include "qemu/units.h" 22 #include "qapi/error.h" 23 #include "qapi/visitor.h" 24 #include "qapi/qapi-visit-common.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "acpi-microvm.h" 31 32 #include "hw/loader.h" 33 #include "hw/irq.h" 34 #include "hw/kvm/clock.h" 35 #include "hw/i386/microvm.h" 36 #include "hw/i386/x86.h" 37 #include "target/i386/cpu.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/rtc/mc146818rtc.h" 41 #include "hw/char/serial.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/i386/topology.h" 44 #include "hw/i386/e820_memory_layout.h" 45 #include "hw/i386/fw_cfg.h" 46 #include "hw/virtio/virtio-mmio.h" 47 #include "hw/acpi/acpi.h" 48 #include "hw/acpi/generic_event_device.h" 49 #include "hw/pci-host/gpex.h" 50 51 #include "cpu.h" 52 #include "elf.h" 53 #include "kvm_i386.h" 54 #include "hw/xen/start_info.h" 55 56 #define MICROVM_QBOOT_FILENAME "qboot.rom" 57 #define MICROVM_BIOS_FILENAME "bios-microvm.bin" 58 59 static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s) 60 { 61 X86MachineState *x86ms = X86_MACHINE(mms); 62 int val; 63 64 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 65 rtc_set_memory(s, 0x15, val); 66 rtc_set_memory(s, 0x16, val >> 8); 67 /* extended memory (next 64MiB) */ 68 if (x86ms->below_4g_mem_size > 1 * MiB) { 69 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 70 } else { 71 val = 0; 72 } 73 if (val > 65535) { 74 val = 65535; 75 } 76 rtc_set_memory(s, 0x17, val); 77 rtc_set_memory(s, 0x18, val >> 8); 78 rtc_set_memory(s, 0x30, val); 79 rtc_set_memory(s, 0x31, val >> 8); 80 /* memory between 16MiB and 4GiB */ 81 if (x86ms->below_4g_mem_size > 16 * MiB) { 82 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 83 } else { 84 val = 0; 85 } 86 if (val > 65535) { 87 val = 65535; 88 } 89 rtc_set_memory(s, 0x34, val); 90 rtc_set_memory(s, 0x35, val >> 8); 91 /* memory above 4GiB */ 92 val = x86ms->above_4g_mem_size / 65536; 93 rtc_set_memory(s, 0x5b, val); 94 rtc_set_memory(s, 0x5c, val >> 8); 95 rtc_set_memory(s, 0x5d, val >> 16); 96 } 97 98 static void microvm_gsi_handler(void *opaque, int n, int level) 99 { 100 GSIState *s = opaque; 101 102 qemu_set_irq(s->ioapic_irq[n], level); 103 } 104 105 static void create_gpex(MicrovmMachineState *mms) 106 { 107 X86MachineState *x86ms = X86_MACHINE(mms); 108 MemoryRegion *mmio32_alias; 109 MemoryRegion *mmio64_alias; 110 MemoryRegion *mmio_reg; 111 MemoryRegion *ecam_alias; 112 MemoryRegion *ecam_reg; 113 DeviceState *dev; 114 int i; 115 116 dev = qdev_new(TYPE_GPEX_HOST); 117 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 118 119 /* Map only the first size_ecam bytes of ECAM space */ 120 ecam_alias = g_new0(MemoryRegion, 1); 121 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 122 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 123 ecam_reg, 0, mms->gpex.ecam.size); 124 memory_region_add_subregion(get_system_memory(), 125 mms->gpex.ecam.base, ecam_alias); 126 127 /* Map the MMIO window into system address space so as to expose 128 * the section of PCI MMIO space which starts at the same base address 129 * (ie 1:1 mapping for that part of PCI MMIO space visible through 130 * the window). 131 */ 132 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 133 if (mms->gpex.mmio32.size) { 134 mmio32_alias = g_new0(MemoryRegion, 1); 135 memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg, 136 mms->gpex.mmio32.base, mms->gpex.mmio32.size); 137 memory_region_add_subregion(get_system_memory(), 138 mms->gpex.mmio32.base, mmio32_alias); 139 } 140 if (mms->gpex.mmio64.size) { 141 mmio64_alias = g_new0(MemoryRegion, 1); 142 memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg, 143 mms->gpex.mmio64.base, mms->gpex.mmio64.size); 144 memory_region_add_subregion(get_system_memory(), 145 mms->gpex.mmio64.base, mmio64_alias); 146 } 147 148 for (i = 0; i < GPEX_NUM_IRQS; i++) { 149 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 150 x86ms->gsi[mms->gpex.irq + i]); 151 } 152 } 153 154 static void microvm_devices_init(MicrovmMachineState *mms) 155 { 156 X86MachineState *x86ms = X86_MACHINE(mms); 157 ISABus *isa_bus; 158 ISADevice *rtc_state; 159 GSIState *gsi_state; 160 int i; 161 162 /* Core components */ 163 164 gsi_state = g_malloc0(sizeof(*gsi_state)); 165 if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) { 166 x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 167 } else { 168 x86ms->gsi = qemu_allocate_irqs(microvm_gsi_handler, 169 gsi_state, GSI_NUM_PINS); 170 } 171 172 isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(), 173 &error_abort); 174 isa_bus_irqs(isa_bus, x86ms->gsi); 175 176 ioapic_init_gsi(gsi_state, "machine"); 177 178 kvmclock_create(); 179 180 mms->virtio_irq_base = x86_machine_is_acpi_enabled(x86ms) ? 16 : 5; 181 for (i = 0; i < VIRTIO_NUM_TRANSPORTS; i++) { 182 sysbus_create_simple("virtio-mmio", 183 VIRTIO_MMIO_BASE + i * 512, 184 x86ms->gsi[mms->virtio_irq_base + i]); 185 } 186 187 /* Optional and legacy devices */ 188 if (x86_machine_is_acpi_enabled(x86ms)) { 189 DeviceState *dev = qdev_new(TYPE_ACPI_GED_X86); 190 qdev_prop_set_uint32(dev, "ged-event", ACPI_GED_PWR_DOWN_EVT); 191 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, GED_MMIO_BASE); 192 /* sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, GED_MMIO_BASE_MEMHP); */ 193 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, GED_MMIO_BASE_REGS); 194 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 195 x86ms->gsi[GED_MMIO_IRQ]); 196 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 197 x86ms->acpi_dev = HOTPLUG_HANDLER(dev); 198 } 199 200 if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) { 201 /* use topmost 25% of the address space available */ 202 hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits; 203 if (phys_size > 0x1000000ll) { 204 mms->gpex.mmio64.size = phys_size / 4; 205 mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size; 206 } 207 mms->gpex.mmio32.base = PCIE_MMIO_BASE; 208 mms->gpex.mmio32.size = PCIE_MMIO_SIZE; 209 mms->gpex.ecam.base = PCIE_ECAM_BASE; 210 mms->gpex.ecam.size = PCIE_ECAM_SIZE; 211 mms->gpex.irq = PCIE_IRQ_BASE; 212 create_gpex(mms); 213 } 214 215 if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) { 216 qemu_irq *i8259; 217 218 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 219 for (i = 0; i < ISA_NUM_IRQS; i++) { 220 gsi_state->i8259_irq[i] = i8259[i]; 221 } 222 g_free(i8259); 223 } 224 225 if (mms->pit == ON_OFF_AUTO_ON || mms->pit == ON_OFF_AUTO_AUTO) { 226 if (kvm_pit_in_kernel()) { 227 kvm_pit_init(isa_bus, 0x40); 228 } else { 229 i8254_pit_init(isa_bus, 0x40, 0, NULL); 230 } 231 } 232 233 if (mms->rtc == ON_OFF_AUTO_ON || 234 (mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) { 235 rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL); 236 microvm_set_rtc(mms, rtc_state); 237 } 238 239 if (mms->isa_serial) { 240 serial_hds_isa_init(isa_bus, 0, 1); 241 } 242 243 if (bios_name == NULL) { 244 bios_name = x86_machine_is_acpi_enabled(x86ms) 245 ? MICROVM_BIOS_FILENAME 246 : MICROVM_QBOOT_FILENAME; 247 } 248 x86_bios_rom_init(get_system_memory(), true); 249 } 250 251 static void microvm_memory_init(MicrovmMachineState *mms) 252 { 253 MachineState *machine = MACHINE(mms); 254 X86MachineState *x86ms = X86_MACHINE(mms); 255 MemoryRegion *ram_below_4g, *ram_above_4g; 256 MemoryRegion *system_memory = get_system_memory(); 257 FWCfgState *fw_cfg; 258 ram_addr_t lowmem = 0xc0000000; /* 3G */ 259 int i; 260 261 if (machine->ram_size > lowmem) { 262 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 263 x86ms->below_4g_mem_size = lowmem; 264 } else { 265 x86ms->above_4g_mem_size = 0; 266 x86ms->below_4g_mem_size = machine->ram_size; 267 } 268 269 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 270 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 271 0, x86ms->below_4g_mem_size); 272 memory_region_add_subregion(system_memory, 0, ram_below_4g); 273 274 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 275 276 if (x86ms->above_4g_mem_size > 0) { 277 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 278 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 279 machine->ram, 280 x86ms->below_4g_mem_size, 281 x86ms->above_4g_mem_size); 282 memory_region_add_subregion(system_memory, 0x100000000ULL, 283 ram_above_4g); 284 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 285 } 286 287 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 288 &address_space_memory); 289 290 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus); 291 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus); 292 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 293 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 294 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 295 &e820_reserve, sizeof(e820_reserve)); 296 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 297 sizeof(struct e820_entry) * e820_get_num_entries()); 298 299 rom_set_fw(fw_cfg); 300 301 if (machine->kernel_filename != NULL) { 302 x86_load_linux(x86ms, fw_cfg, 0, true, true); 303 } 304 305 if (mms->option_roms) { 306 for (i = 0; i < nb_option_roms; i++) { 307 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 308 } 309 } 310 311 x86ms->fw_cfg = fw_cfg; 312 x86ms->ioapic_as = &address_space_memory; 313 } 314 315 static gchar *microvm_get_mmio_cmdline(gchar *name, uint32_t virtio_irq_base) 316 { 317 gchar *cmdline; 318 gchar *separator; 319 long int index; 320 int ret; 321 322 separator = g_strrstr(name, "."); 323 if (!separator) { 324 return NULL; 325 } 326 327 if (qemu_strtol(separator + 1, NULL, 10, &index) != 0) { 328 return NULL; 329 } 330 331 cmdline = g_malloc0(VIRTIO_CMDLINE_MAXLEN); 332 ret = g_snprintf(cmdline, VIRTIO_CMDLINE_MAXLEN, 333 " virtio_mmio.device=512@0x%lx:%ld", 334 VIRTIO_MMIO_BASE + index * 512, 335 virtio_irq_base + index); 336 if (ret < 0 || ret >= VIRTIO_CMDLINE_MAXLEN) { 337 g_free(cmdline); 338 return NULL; 339 } 340 341 return cmdline; 342 } 343 344 static void microvm_fix_kernel_cmdline(MachineState *machine) 345 { 346 X86MachineState *x86ms = X86_MACHINE(machine); 347 MicrovmMachineState *mms = MICROVM_MACHINE(machine); 348 BusState *bus; 349 BusChild *kid; 350 char *cmdline; 351 352 /* 353 * Find MMIO transports with attached devices, and add them to the kernel 354 * command line. 355 * 356 * Yes, this is a hack, but one that heavily improves the UX without 357 * introducing any significant issues. 358 */ 359 cmdline = g_strdup(machine->kernel_cmdline); 360 bus = sysbus_get_default(); 361 QTAILQ_FOREACH(kid, &bus->children, sibling) { 362 DeviceState *dev = kid->child; 363 ObjectClass *class = object_get_class(OBJECT(dev)); 364 365 if (class == object_class_by_name(TYPE_VIRTIO_MMIO)) { 366 VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev)); 367 VirtioBusState *mmio_virtio_bus = &mmio->bus; 368 BusState *mmio_bus = &mmio_virtio_bus->parent_obj; 369 370 if (!QTAILQ_EMPTY(&mmio_bus->children)) { 371 gchar *mmio_cmdline = microvm_get_mmio_cmdline 372 (mmio_bus->name, mms->virtio_irq_base); 373 if (mmio_cmdline) { 374 char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL); 375 g_free(mmio_cmdline); 376 g_free(cmdline); 377 cmdline = newcmd; 378 } 379 } 380 } 381 } 382 383 fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1); 384 fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline); 385 386 g_free(cmdline); 387 } 388 389 static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev, 390 DeviceState *dev, Error **errp) 391 { 392 X86CPU *cpu = X86_CPU(dev); 393 394 cpu->host_phys_bits = true; /* need reliable phys-bits */ 395 x86_cpu_pre_plug(hotplug_dev, dev, errp); 396 } 397 398 static void microvm_device_plug_cb(HotplugHandler *hotplug_dev, 399 DeviceState *dev, Error **errp) 400 { 401 x86_cpu_plug(hotplug_dev, dev, errp); 402 } 403 404 static void microvm_device_unplug_request_cb(HotplugHandler *hotplug_dev, 405 DeviceState *dev, Error **errp) 406 { 407 error_setg(errp, "unplug not supported by microvm"); 408 } 409 410 static void microvm_device_unplug_cb(HotplugHandler *hotplug_dev, 411 DeviceState *dev, Error **errp) 412 { 413 error_setg(errp, "unplug not supported by microvm"); 414 } 415 416 static HotplugHandler *microvm_get_hotplug_handler(MachineState *machine, 417 DeviceState *dev) 418 { 419 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 420 return HOTPLUG_HANDLER(machine); 421 } 422 return NULL; 423 } 424 425 static void microvm_machine_state_init(MachineState *machine) 426 { 427 MicrovmMachineState *mms = MICROVM_MACHINE(machine); 428 X86MachineState *x86ms = X86_MACHINE(machine); 429 Error *local_err = NULL; 430 431 microvm_memory_init(mms); 432 433 x86_cpus_init(x86ms, CPU_VERSION_LATEST); 434 if (local_err) { 435 error_report_err(local_err); 436 exit(1); 437 } 438 439 microvm_devices_init(mms); 440 } 441 442 static void microvm_machine_reset(MachineState *machine) 443 { 444 MicrovmMachineState *mms = MICROVM_MACHINE(machine); 445 CPUState *cs; 446 X86CPU *cpu; 447 448 if (!x86_machine_is_acpi_enabled(X86_MACHINE(machine)) && 449 machine->kernel_filename != NULL && 450 mms->auto_kernel_cmdline && !mms->kernel_cmdline_fixed) { 451 microvm_fix_kernel_cmdline(machine); 452 mms->kernel_cmdline_fixed = true; 453 } 454 455 qemu_devices_reset(); 456 457 CPU_FOREACH(cs) { 458 cpu = X86_CPU(cs); 459 460 if (cpu->apic_state) { 461 device_legacy_reset(cpu->apic_state); 462 } 463 } 464 } 465 466 static void microvm_machine_get_pic(Object *obj, Visitor *v, const char *name, 467 void *opaque, Error **errp) 468 { 469 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 470 OnOffAuto pic = mms->pic; 471 472 visit_type_OnOffAuto(v, name, &pic, errp); 473 } 474 475 static void microvm_machine_set_pic(Object *obj, Visitor *v, const char *name, 476 void *opaque, Error **errp) 477 { 478 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 479 480 visit_type_OnOffAuto(v, name, &mms->pic, errp); 481 } 482 483 static void microvm_machine_get_pit(Object *obj, Visitor *v, const char *name, 484 void *opaque, Error **errp) 485 { 486 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 487 OnOffAuto pit = mms->pit; 488 489 visit_type_OnOffAuto(v, name, &pit, errp); 490 } 491 492 static void microvm_machine_set_pit(Object *obj, Visitor *v, const char *name, 493 void *opaque, Error **errp) 494 { 495 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 496 497 visit_type_OnOffAuto(v, name, &mms->pit, errp); 498 } 499 500 static void microvm_machine_get_rtc(Object *obj, Visitor *v, const char *name, 501 void *opaque, Error **errp) 502 { 503 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 504 OnOffAuto rtc = mms->rtc; 505 506 visit_type_OnOffAuto(v, name, &rtc, errp); 507 } 508 509 static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name, 510 void *opaque, Error **errp) 511 { 512 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 513 514 visit_type_OnOffAuto(v, name, &mms->rtc, errp); 515 } 516 517 static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name, 518 void *opaque, Error **errp) 519 { 520 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 521 OnOffAuto pcie = mms->pcie; 522 523 visit_type_OnOffAuto(v, name, &pcie, errp); 524 } 525 526 static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name, 527 void *opaque, Error **errp) 528 { 529 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 530 531 visit_type_OnOffAuto(v, name, &mms->pcie, errp); 532 } 533 534 static bool microvm_machine_get_isa_serial(Object *obj, Error **errp) 535 { 536 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 537 538 return mms->isa_serial; 539 } 540 541 static void microvm_machine_set_isa_serial(Object *obj, bool value, 542 Error **errp) 543 { 544 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 545 546 mms->isa_serial = value; 547 } 548 549 static bool microvm_machine_get_option_roms(Object *obj, Error **errp) 550 { 551 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 552 553 return mms->option_roms; 554 } 555 556 static void microvm_machine_set_option_roms(Object *obj, bool value, 557 Error **errp) 558 { 559 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 560 561 mms->option_roms = value; 562 } 563 564 static bool microvm_machine_get_auto_kernel_cmdline(Object *obj, Error **errp) 565 { 566 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 567 568 return mms->auto_kernel_cmdline; 569 } 570 571 static void microvm_machine_set_auto_kernel_cmdline(Object *obj, bool value, 572 Error **errp) 573 { 574 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 575 576 mms->auto_kernel_cmdline = value; 577 } 578 579 static void microvm_machine_done(Notifier *notifier, void *data) 580 { 581 MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState, 582 machine_done); 583 584 acpi_setup_microvm(mms); 585 } 586 587 static void microvm_powerdown_req(Notifier *notifier, void *data) 588 { 589 MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState, 590 powerdown_req); 591 X86MachineState *x86ms = X86_MACHINE(mms); 592 593 if (x86ms->acpi_dev) { 594 Object *obj = OBJECT(x86ms->acpi_dev); 595 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(obj); 596 adevc->send_event(ACPI_DEVICE_IF(x86ms->acpi_dev), 597 ACPI_POWER_DOWN_STATUS); 598 } 599 } 600 601 static void microvm_machine_initfn(Object *obj) 602 { 603 MicrovmMachineState *mms = MICROVM_MACHINE(obj); 604 605 /* Configuration */ 606 mms->pic = ON_OFF_AUTO_AUTO; 607 mms->pit = ON_OFF_AUTO_AUTO; 608 mms->rtc = ON_OFF_AUTO_AUTO; 609 mms->pcie = ON_OFF_AUTO_AUTO; 610 mms->isa_serial = true; 611 mms->option_roms = true; 612 mms->auto_kernel_cmdline = true; 613 614 /* State */ 615 mms->kernel_cmdline_fixed = false; 616 617 mms->machine_done.notify = microvm_machine_done; 618 qemu_add_machine_init_done_notifier(&mms->machine_done); 619 mms->powerdown_req.notify = microvm_powerdown_req; 620 qemu_register_powerdown_notifier(&mms->powerdown_req); 621 } 622 623 static void microvm_class_init(ObjectClass *oc, void *data) 624 { 625 MachineClass *mc = MACHINE_CLASS(oc); 626 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 627 628 mc->init = microvm_machine_state_init; 629 630 mc->family = "microvm_i386"; 631 mc->desc = "microvm (i386)"; 632 mc->units_per_default_bus = 1; 633 mc->no_floppy = 1; 634 mc->max_cpus = 288; 635 mc->has_hotpluggable_cpus = false; 636 mc->auto_enable_numa_with_memhp = false; 637 mc->auto_enable_numa_with_memdev = false; 638 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 639 mc->nvdimm_supported = false; 640 mc->default_ram_id = "microvm.ram"; 641 642 /* Avoid relying too much on kernel components */ 643 mc->default_kernel_irqchip_split = true; 644 645 /* Machine class handlers */ 646 mc->reset = microvm_machine_reset; 647 648 /* hotplug (for cpu coldplug) */ 649 mc->get_hotplug_handler = microvm_get_hotplug_handler; 650 hc->pre_plug = microvm_device_pre_plug_cb; 651 hc->plug = microvm_device_plug_cb; 652 hc->unplug_request = microvm_device_unplug_request_cb; 653 hc->unplug = microvm_device_unplug_cb; 654 655 object_class_property_add(oc, MICROVM_MACHINE_PIC, "OnOffAuto", 656 microvm_machine_get_pic, 657 microvm_machine_set_pic, 658 NULL, NULL); 659 object_class_property_set_description(oc, MICROVM_MACHINE_PIC, 660 "Enable i8259 PIC"); 661 662 object_class_property_add(oc, MICROVM_MACHINE_PIT, "OnOffAuto", 663 microvm_machine_get_pit, 664 microvm_machine_set_pit, 665 NULL, NULL); 666 object_class_property_set_description(oc, MICROVM_MACHINE_PIT, 667 "Enable i8254 PIT"); 668 669 object_class_property_add(oc, MICROVM_MACHINE_RTC, "OnOffAuto", 670 microvm_machine_get_rtc, 671 microvm_machine_set_rtc, 672 NULL, NULL); 673 object_class_property_set_description(oc, MICROVM_MACHINE_RTC, 674 "Enable MC146818 RTC"); 675 676 object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto", 677 microvm_machine_get_pcie, 678 microvm_machine_set_pcie, 679 NULL, NULL); 680 object_class_property_set_description(oc, MICROVM_MACHINE_PCIE, 681 "Enable PCIe"); 682 683 object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL, 684 microvm_machine_get_isa_serial, 685 microvm_machine_set_isa_serial); 686 object_class_property_set_description(oc, MICROVM_MACHINE_ISA_SERIAL, 687 "Set off to disable the instantiation an ISA serial port"); 688 689 object_class_property_add_bool(oc, MICROVM_MACHINE_OPTION_ROMS, 690 microvm_machine_get_option_roms, 691 microvm_machine_set_option_roms); 692 object_class_property_set_description(oc, MICROVM_MACHINE_OPTION_ROMS, 693 "Set off to disable loading option ROMs"); 694 695 object_class_property_add_bool(oc, MICROVM_MACHINE_AUTO_KERNEL_CMDLINE, 696 microvm_machine_get_auto_kernel_cmdline, 697 microvm_machine_set_auto_kernel_cmdline); 698 object_class_property_set_description(oc, 699 MICROVM_MACHINE_AUTO_KERNEL_CMDLINE, 700 "Set off to disable adding virtio-mmio devices to the kernel cmdline"); 701 702 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 703 } 704 705 static const TypeInfo microvm_machine_info = { 706 .name = TYPE_MICROVM_MACHINE, 707 .parent = TYPE_X86_MACHINE, 708 .instance_size = sizeof(MicrovmMachineState), 709 .instance_init = microvm_machine_initfn, 710 .class_size = sizeof(MicrovmMachineClass), 711 .class_init = microvm_class_init, 712 .interfaces = (InterfaceInfo[]) { 713 { TYPE_HOTPLUG_HANDLER }, 714 { } 715 }, 716 }; 717 718 static void microvm_machine_init(void) 719 { 720 type_register_static(µvm_machine_info); 721 } 722 type_init(microvm_machine_init); 723