1 /*
2 * Copyright (c) 2018 Intel Corporation
3 * Copyright (c) 2019 Red Hat, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2 or later, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/error-report.h"
20 #include "qemu/cutils.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "qapi/visitor.h"
24 #include "qapi/qapi-visit-common.h"
25 #include "system/system.h"
26 #include "system/cpus.h"
27 #include "system/numa.h"
28 #include "system/reset.h"
29 #include "system/runstate.h"
30 #include "acpi-microvm.h"
31 #include "microvm-dt.h"
32
33 #include "hw/loader.h"
34 #include "hw/irq.h"
35 #include "hw/i386/kvm/clock.h"
36 #include "hw/i386/microvm.h"
37 #include "hw/i386/x86.h"
38 #include "target/i386/cpu.h"
39 #include "hw/intc/i8259.h"
40 #include "hw/timer/i8254.h"
41 #include "hw/rtc/mc146818rtc.h"
42 #include "hw/char/serial-isa.h"
43 #include "hw/display/ramfb.h"
44 #include "hw/i386/topology.h"
45 #include "hw/i386/e820_memory_layout.h"
46 #include "hw/i386/fw_cfg.h"
47 #include "hw/virtio/virtio-mmio.h"
48 #include "hw/acpi/acpi.h"
49 #include "hw/acpi/generic_event_device.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/usb/xhci.h"
52 #include "hw/vfio/types.h"
53
54 #include "elf.h"
55 #include "kvm/kvm_i386.h"
56 #include "hw/xen/start_info.h"
57
58 #define MICROVM_QBOOT_FILENAME "qboot.rom"
59 #define MICROVM_BIOS_FILENAME "bios-microvm.bin"
60
microvm_set_rtc(MicrovmMachineState * mms,MC146818RtcState * s)61 static void microvm_set_rtc(MicrovmMachineState *mms, MC146818RtcState *s)
62 {
63 X86MachineState *x86ms = X86_MACHINE(mms);
64 int val;
65
66 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
67 mc146818rtc_set_cmos_data(s, 0x15, val);
68 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
69 /* extended memory (next 64MiB) */
70 if (x86ms->below_4g_mem_size > 1 * MiB) {
71 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
72 } else {
73 val = 0;
74 }
75 if (val > 65535) {
76 val = 65535;
77 }
78 mc146818rtc_set_cmos_data(s, 0x17, val);
79 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
80 mc146818rtc_set_cmos_data(s, 0x30, val);
81 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
82 /* memory between 16MiB and 4GiB */
83 if (x86ms->below_4g_mem_size > 16 * MiB) {
84 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
85 } else {
86 val = 0;
87 }
88 if (val > 65535) {
89 val = 65535;
90 }
91 mc146818rtc_set_cmos_data(s, 0x34, val);
92 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
93 /* memory above 4GiB */
94 val = x86ms->above_4g_mem_size / 65536;
95 mc146818rtc_set_cmos_data(s, 0x5b, val);
96 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
97 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
98 }
99
create_gpex(MicrovmMachineState * mms)100 static void create_gpex(MicrovmMachineState *mms)
101 {
102 X86MachineState *x86ms = X86_MACHINE(mms);
103 MemoryRegion *mmio32_alias;
104 MemoryRegion *mmio64_alias;
105 MemoryRegion *mmio_reg;
106 MemoryRegion *ecam_alias;
107 MemoryRegion *ecam_reg;
108 DeviceState *dev;
109 int i;
110
111 dev = qdev_new(TYPE_GPEX_HOST);
112 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
113
114 /* Map only the first size_ecam bytes of ECAM space */
115 ecam_alias = g_new0(MemoryRegion, 1);
116 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
117 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
118 ecam_reg, 0, mms->gpex.ecam.size);
119 memory_region_add_subregion(get_system_memory(),
120 mms->gpex.ecam.base, ecam_alias);
121
122 /* Map the MMIO window into system address space so as to expose
123 * the section of PCI MMIO space which starts at the same base address
124 * (ie 1:1 mapping for that part of PCI MMIO space visible through
125 * the window).
126 */
127 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
128 if (mms->gpex.mmio32.size) {
129 mmio32_alias = g_new0(MemoryRegion, 1);
130 memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg,
131 mms->gpex.mmio32.base, mms->gpex.mmio32.size);
132 memory_region_add_subregion(get_system_memory(),
133 mms->gpex.mmio32.base, mmio32_alias);
134 }
135 if (mms->gpex.mmio64.size) {
136 mmio64_alias = g_new0(MemoryRegion, 1);
137 memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg,
138 mms->gpex.mmio64.base, mms->gpex.mmio64.size);
139 memory_region_add_subregion(get_system_memory(),
140 mms->gpex.mmio64.base, mmio64_alias);
141 }
142
143 for (i = 0; i < PCI_NUM_PINS; i++) {
144 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
145 x86ms->gsi[mms->gpex.irq + i]);
146 }
147 }
148
microvm_ioapics(MicrovmMachineState * mms)149 static int microvm_ioapics(MicrovmMachineState *mms)
150 {
151 if (!x86_machine_is_acpi_enabled(X86_MACHINE(mms))) {
152 return 1;
153 }
154 if (mms->ioapic2 == ON_OFF_AUTO_OFF) {
155 return 1;
156 }
157 return 2;
158 }
159
microvm_devices_init(MicrovmMachineState * mms)160 static void microvm_devices_init(MicrovmMachineState *mms)
161 {
162 const char *default_firmware;
163 X86MachineState *x86ms = X86_MACHINE(mms);
164 ISABus *isa_bus;
165 GSIState *gsi_state;
166 int ioapics;
167 int i;
168
169 /* Core components */
170 ioapics = microvm_ioapics(mms);
171 gsi_state = g_malloc0(sizeof(*gsi_state));
172 x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state,
173 IOAPIC_NUM_PINS * ioapics);
174
175 isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
176 &error_abort);
177 isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
178
179 ioapic_init_gsi(gsi_state, OBJECT(mms));
180 if (ioapics > 1) {
181 x86ms->ioapic2 = ioapic_init_secondary(gsi_state);
182 }
183
184 if (kvm_enabled()) {
185 kvmclock_create(true);
186 }
187
188 mms->virtio_irq_base = 5;
189 mms->virtio_num_transports = 8;
190 if (x86ms->ioapic2) {
191 mms->pcie_irq_base = 16; /* 16 -> 19 */
192 /* use second ioapic (24 -> 47) for virtio-mmio irq lines */
193 mms->virtio_irq_base = IO_APIC_SECONDARY_IRQBASE;
194 mms->virtio_num_transports = IOAPIC_NUM_PINS;
195 } else if (x86_machine_is_acpi_enabled(x86ms)) {
196 mms->pcie_irq_base = 12; /* 12 -> 15 */
197 mms->virtio_irq_base = 16; /* 16 -> 23 */
198 }
199
200 for (i = 0; i < mms->virtio_num_transports; i++) {
201 sysbus_create_simple("virtio-mmio",
202 VIRTIO_MMIO_BASE + i * 512,
203 x86ms->gsi[mms->virtio_irq_base + i]);
204 }
205
206 /* Optional and legacy devices */
207 if (x86_machine_is_acpi_enabled(x86ms)) {
208 DeviceState *dev = qdev_new(TYPE_ACPI_GED);
209 qdev_prop_set_uint32(dev, "ged-event", ACPI_GED_PWR_DOWN_EVT);
210 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
211 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, GED_MMIO_BASE);
212 /* sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, GED_MMIO_BASE_MEMHP); */
213 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, GED_MMIO_BASE_REGS);
214 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
215 x86ms->gsi[GED_MMIO_IRQ]);
216 x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
217 }
218
219 if (x86_machine_is_acpi_enabled(x86ms) && machine_usb(MACHINE(mms))) {
220 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
221 qdev_prop_set_uint32(dev, "intrs", 1);
222 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
223 qdev_prop_set_uint32(dev, "p2", 8);
224 qdev_prop_set_uint32(dev, "p3", 8);
225 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
226 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MICROVM_XHCI_BASE);
227 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
228 x86ms->gsi[MICROVM_XHCI_IRQ]);
229 }
230
231 if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) {
232 /* use topmost 25% of the address space available */
233 hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits;
234 if (phys_size > 0x1000000ll) {
235 mms->gpex.mmio64.size = phys_size / 4;
236 mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size;
237 }
238 mms->gpex.mmio32.base = PCIE_MMIO_BASE;
239 mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
240 mms->gpex.ecam.base = PCIE_ECAM_BASE;
241 mms->gpex.ecam.size = PCIE_ECAM_SIZE;
242 mms->gpex.irq = mms->pcie_irq_base;
243 create_gpex(mms);
244 x86ms->pci_irq_mask = ((1 << (mms->pcie_irq_base + 0)) |
245 (1 << (mms->pcie_irq_base + 1)) |
246 (1 << (mms->pcie_irq_base + 2)) |
247 (1 << (mms->pcie_irq_base + 3)));
248 } else {
249 x86ms->pci_irq_mask = 0;
250 }
251
252 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
253 qemu_irq *i8259;
254
255 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
256 for (i = 0; i < ISA_NUM_IRQS; i++) {
257 gsi_state->i8259_irq[i] = i8259[i];
258 }
259 g_free(i8259);
260 }
261
262 if (x86ms->pit == ON_OFF_AUTO_ON || x86ms->pit == ON_OFF_AUTO_AUTO) {
263 if (kvm_pit_in_kernel()) {
264 kvm_pit_init(isa_bus, 0x40);
265 } else {
266 i8254_pit_init(isa_bus, 0x40, 0, NULL);
267 }
268 }
269
270 if (mms->rtc == ON_OFF_AUTO_ON ||
271 (mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) {
272 microvm_set_rtc(mms, mc146818_rtc_init(isa_bus, 2000, NULL));
273 }
274
275 if (mms->isa_serial) {
276 serial_hds_isa_init(isa_bus, 0, 1);
277 }
278
279 default_firmware = x86_machine_is_acpi_enabled(x86ms)
280 ? MICROVM_BIOS_FILENAME
281 : MICROVM_QBOOT_FILENAME;
282 x86_bios_rom_init(x86ms, default_firmware, get_system_memory(), true);
283 }
284
microvm_memory_init(MicrovmMachineState * mms)285 static void microvm_memory_init(MicrovmMachineState *mms)
286 {
287 MicrovmMachineClass *mmc = MICROVM_MACHINE_GET_CLASS(mms);
288 MachineState *machine = MACHINE(mms);
289 X86MachineState *x86ms = X86_MACHINE(mms);
290 MemoryRegion *ram_below_4g, *ram_above_4g;
291 MemoryRegion *system_memory = get_system_memory();
292 FWCfgState *fw_cfg;
293 ram_addr_t lowmem = 0xc0000000; /* 3G */
294 int i;
295
296 if (machine->ram_size > lowmem) {
297 x86ms->above_4g_mem_size = machine->ram_size - lowmem;
298 x86ms->below_4g_mem_size = lowmem;
299 } else {
300 x86ms->above_4g_mem_size = 0;
301 x86ms->below_4g_mem_size = machine->ram_size;
302 }
303
304 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
305 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
306 0, x86ms->below_4g_mem_size);
307 memory_region_add_subregion(system_memory, 0, ram_below_4g);
308
309 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
310
311 if (x86ms->above_4g_mem_size > 0) {
312 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
313 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
314 machine->ram,
315 x86ms->below_4g_mem_size,
316 x86ms->above_4g_mem_size);
317 memory_region_add_subregion(system_memory, 0x100000000ULL,
318 ram_above_4g);
319 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
320 }
321
322 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
323 &address_space_memory);
324
325 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus);
326 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus);
327 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
328 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
329
330 rom_set_fw(fw_cfg);
331
332 if (machine->kernel_filename != NULL) {
333 mmc->x86_load_linux(x86ms, fw_cfg, 0, true);
334 }
335
336 if (mms->option_roms) {
337 for (i = 0; i < nb_option_roms; i++) {
338 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
339 }
340 }
341
342 x86ms->fw_cfg = fw_cfg;
343 x86ms->ioapic_as = &address_space_memory;
344 }
345
microvm_get_mmio_cmdline(gchar * name,uint32_t virtio_irq_base)346 static gchar *microvm_get_mmio_cmdline(gchar *name, uint32_t virtio_irq_base)
347 {
348 gchar *cmdline;
349 gchar *separator;
350 long int index;
351 int ret;
352
353 separator = g_strrstr(name, ".");
354 if (!separator) {
355 return NULL;
356 }
357
358 if (qemu_strtol(separator + 1, NULL, 10, &index) != 0) {
359 return NULL;
360 }
361
362 cmdline = g_malloc0(VIRTIO_CMDLINE_MAXLEN);
363 ret = g_snprintf(cmdline, VIRTIO_CMDLINE_MAXLEN,
364 " virtio_mmio.device=512@0x%lx:%ld",
365 VIRTIO_MMIO_BASE + index * 512,
366 virtio_irq_base + index);
367 if (ret < 0 || ret >= VIRTIO_CMDLINE_MAXLEN) {
368 g_free(cmdline);
369 return NULL;
370 }
371
372 return cmdline;
373 }
374
microvm_fix_kernel_cmdline(MachineState * machine)375 static void microvm_fix_kernel_cmdline(MachineState *machine)
376 {
377 X86MachineState *x86ms = X86_MACHINE(machine);
378 MicrovmMachineState *mms = MICROVM_MACHINE(machine);
379 BusState *bus;
380 BusChild *kid;
381 char *cmdline;
382
383 /*
384 * Find MMIO transports with attached devices, and add them to the kernel
385 * command line.
386 *
387 * Yes, this is a hack, but one that heavily improves the UX without
388 * introducing any significant issues.
389 */
390 cmdline = g_strdup(machine->kernel_cmdline);
391 bus = sysbus_get_default();
392 QTAILQ_FOREACH(kid, &bus->children, sibling) {
393 DeviceState *dev = kid->child;
394
395 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MMIO)) {
396 VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev));
397 VirtioBusState *mmio_virtio_bus = &mmio->bus;
398 BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
399
400 if (!QTAILQ_EMPTY(&mmio_bus->children)) {
401 gchar *mmio_cmdline = microvm_get_mmio_cmdline
402 (mmio_bus->name, mms->virtio_irq_base);
403 if (mmio_cmdline) {
404 char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL);
405 g_free(mmio_cmdline);
406 g_free(cmdline);
407 cmdline = newcmd;
408 }
409 }
410 }
411 }
412
413 fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1);
414 fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline);
415
416 g_free(cmdline);
417 }
418
microvm_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)419 static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev,
420 DeviceState *dev, Error **errp)
421 {
422 X86CPU *cpu = X86_CPU(dev);
423
424 cpu->host_phys_bits = true; /* need reliable phys-bits */
425 x86_cpu_pre_plug(hotplug_dev, dev, errp);
426 }
427
microvm_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)428 static void microvm_device_plug_cb(HotplugHandler *hotplug_dev,
429 DeviceState *dev, Error **errp)
430 {
431 x86_cpu_plug(hotplug_dev, dev, errp);
432 }
433
microvm_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)434 static void microvm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
435 DeviceState *dev, Error **errp)
436 {
437 error_setg(errp, "unplug not supported by microvm");
438 }
439
microvm_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)440 static void microvm_device_unplug_cb(HotplugHandler *hotplug_dev,
441 DeviceState *dev, Error **errp)
442 {
443 error_setg(errp, "unplug not supported by microvm");
444 }
445
microvm_get_hotplug_handler(MachineState * machine,DeviceState * dev)446 static HotplugHandler *microvm_get_hotplug_handler(MachineState *machine,
447 DeviceState *dev)
448 {
449 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
450 return HOTPLUG_HANDLER(machine);
451 }
452 return NULL;
453 }
454
microvm_machine_done(Notifier * notifier,void * data)455 static void microvm_machine_done(Notifier *notifier, void *data)
456 {
457 MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState,
458 machine_done);
459 X86MachineState *x86ms = X86_MACHINE(mms);
460
461 acpi_setup_microvm(mms);
462 dt_setup_microvm(mms);
463 fw_cfg_add_e820(x86ms->fw_cfg);
464 }
465
microvm_powerdown_req(Notifier * notifier,void * data)466 static void microvm_powerdown_req(Notifier *notifier, void *data)
467 {
468 MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState,
469 powerdown_req);
470 X86MachineState *x86ms = X86_MACHINE(mms);
471
472 if (x86ms->acpi_dev) {
473 Object *obj = OBJECT(x86ms->acpi_dev);
474 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(obj);
475 adevc->send_event(ACPI_DEVICE_IF(x86ms->acpi_dev),
476 ACPI_POWER_DOWN_STATUS);
477 }
478 }
479
microvm_machine_state_init(MachineState * machine)480 static void microvm_machine_state_init(MachineState *machine)
481 {
482 MicrovmMachineState *mms = MICROVM_MACHINE(machine);
483 X86MachineState *x86ms = X86_MACHINE(machine);
484
485 /* State */
486 mms->kernel_cmdline_fixed = false;
487
488 mms->machine_done.notify = microvm_machine_done;
489 qemu_add_machine_init_done_notifier(&mms->machine_done);
490 mms->powerdown_req.notify = microvm_powerdown_req;
491 qemu_register_powerdown_notifier(&mms->powerdown_req);
492
493 microvm_memory_init(mms);
494
495 x86_cpus_init(x86ms, CPU_VERSION_LATEST);
496
497 microvm_devices_init(mms);
498 }
499
microvm_machine_reset(MachineState * machine,ResetType type)500 static void microvm_machine_reset(MachineState *machine, ResetType type)
501 {
502 MicrovmMachineState *mms = MICROVM_MACHINE(machine);
503 CPUState *cs;
504 X86CPU *cpu;
505
506 if (!x86_machine_is_acpi_enabled(X86_MACHINE(machine)) &&
507 machine->kernel_filename != NULL &&
508 mms->auto_kernel_cmdline && !mms->kernel_cmdline_fixed) {
509 microvm_fix_kernel_cmdline(machine);
510 mms->kernel_cmdline_fixed = true;
511 }
512
513 qemu_devices_reset(type);
514
515 CPU_FOREACH(cs) {
516 cpu = X86_CPU(cs);
517
518 x86_cpu_after_reset(cpu);
519 }
520 }
521
microvm_machine_get_rtc(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)522 static void microvm_machine_get_rtc(Object *obj, Visitor *v, const char *name,
523 void *opaque, Error **errp)
524 {
525 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
526 OnOffAuto rtc = mms->rtc;
527
528 visit_type_OnOffAuto(v, name, &rtc, errp);
529 }
530
microvm_machine_set_rtc(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)531 static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name,
532 void *opaque, Error **errp)
533 {
534 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
535
536 visit_type_OnOffAuto(v, name, &mms->rtc, errp);
537 }
538
microvm_machine_get_pcie(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)539 static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name,
540 void *opaque, Error **errp)
541 {
542 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
543 OnOffAuto pcie = mms->pcie;
544
545 visit_type_OnOffAuto(v, name, &pcie, errp);
546 }
547
microvm_machine_set_pcie(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)548 static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name,
549 void *opaque, Error **errp)
550 {
551 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
552
553 visit_type_OnOffAuto(v, name, &mms->pcie, errp);
554 }
555
microvm_machine_get_ioapic2(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)556 static void microvm_machine_get_ioapic2(Object *obj, Visitor *v, const char *name,
557 void *opaque, Error **errp)
558 {
559 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
560 OnOffAuto ioapic2 = mms->ioapic2;
561
562 visit_type_OnOffAuto(v, name, &ioapic2, errp);
563 }
564
microvm_machine_set_ioapic2(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)565 static void microvm_machine_set_ioapic2(Object *obj, Visitor *v, const char *name,
566 void *opaque, Error **errp)
567 {
568 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
569
570 visit_type_OnOffAuto(v, name, &mms->ioapic2, errp);
571 }
572
microvm_machine_get_isa_serial(Object * obj,Error ** errp)573 static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
574 {
575 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
576
577 return mms->isa_serial;
578 }
579
microvm_machine_set_isa_serial(Object * obj,bool value,Error ** errp)580 static void microvm_machine_set_isa_serial(Object *obj, bool value,
581 Error **errp)
582 {
583 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
584
585 mms->isa_serial = value;
586 }
587
microvm_machine_get_option_roms(Object * obj,Error ** errp)588 static bool microvm_machine_get_option_roms(Object *obj, Error **errp)
589 {
590 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
591
592 return mms->option_roms;
593 }
594
microvm_machine_set_option_roms(Object * obj,bool value,Error ** errp)595 static void microvm_machine_set_option_roms(Object *obj, bool value,
596 Error **errp)
597 {
598 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
599
600 mms->option_roms = value;
601 }
602
microvm_machine_get_auto_kernel_cmdline(Object * obj,Error ** errp)603 static bool microvm_machine_get_auto_kernel_cmdline(Object *obj, Error **errp)
604 {
605 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
606
607 return mms->auto_kernel_cmdline;
608 }
609
microvm_machine_set_auto_kernel_cmdline(Object * obj,bool value,Error ** errp)610 static void microvm_machine_set_auto_kernel_cmdline(Object *obj, bool value,
611 Error **errp)
612 {
613 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
614
615 mms->auto_kernel_cmdline = value;
616 }
617
microvm_machine_initfn(Object * obj)618 static void microvm_machine_initfn(Object *obj)
619 {
620 MicrovmMachineState *mms = MICROVM_MACHINE(obj);
621
622 /* Configuration */
623 mms->rtc = ON_OFF_AUTO_AUTO;
624 mms->pcie = ON_OFF_AUTO_AUTO;
625 mms->ioapic2 = ON_OFF_AUTO_AUTO;
626 mms->isa_serial = true;
627 mms->option_roms = true;
628 mms->auto_kernel_cmdline = true;
629 }
630
631 GlobalProperty microvm_properties[] = {
632 /*
633 * pcie host bridge (gpex) on microvm has no io address window,
634 * so reserving io space is not going to work. Turn it off.
635 */
636 { "pcie-root-port", "io-reserve", "0" },
637 { TYPE_RAMFB_DEVICE, "use-legacy-x86-rom", "true" },
638 { TYPE_VFIO_PCI_NOHOTPLUG, "use-legacy-x86-rom", "true" },
639 };
640
microvm_class_init(ObjectClass * oc,const void * data)641 static void microvm_class_init(ObjectClass *oc, const void *data)
642 {
643 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
644 MicrovmMachineClass *mmc = MICROVM_MACHINE_CLASS(oc);
645 MachineClass *mc = MACHINE_CLASS(oc);
646 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
647
648 mmc->x86_load_linux = x86_load_linux;
649
650 mc->init = microvm_machine_state_init;
651
652 mc->family = "microvm_i386";
653 mc->desc = "microvm (i386)";
654 mc->units_per_default_bus = 1;
655 mc->no_floppy = 1;
656 mc->max_cpus = 288;
657 mc->has_hotpluggable_cpus = false;
658 mc->auto_enable_numa_with_memhp = false;
659 mc->auto_enable_numa_with_memdev = false;
660 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
661 mc->nvdimm_supported = false;
662 mc->default_ram_id = "microvm.ram";
663
664 /* Avoid relying too much on kernel components */
665 mc->default_kernel_irqchip_split = true;
666
667 /* Machine class handlers */
668 mc->reset = microvm_machine_reset;
669
670 /* hotplug (for cpu coldplug) */
671 mc->get_hotplug_handler = microvm_get_hotplug_handler;
672 hc->pre_plug = microvm_device_pre_plug_cb;
673 hc->plug = microvm_device_plug_cb;
674 hc->unplug_request = microvm_device_unplug_request_cb;
675 hc->unplug = microvm_device_unplug_cb;
676
677 x86mc->fwcfg_dma_enabled = true;
678
679 object_class_property_add(oc, MICROVM_MACHINE_RTC, "OnOffAuto",
680 microvm_machine_get_rtc,
681 microvm_machine_set_rtc,
682 NULL, NULL);
683 object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
684 "Enable MC146818 RTC");
685
686 object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto",
687 microvm_machine_get_pcie,
688 microvm_machine_set_pcie,
689 NULL, NULL);
690 object_class_property_set_description(oc, MICROVM_MACHINE_PCIE,
691 "Enable PCIe");
692
693 object_class_property_add(oc, MICROVM_MACHINE_IOAPIC2, "OnOffAuto",
694 microvm_machine_get_ioapic2,
695 microvm_machine_set_ioapic2,
696 NULL, NULL);
697 object_class_property_set_description(oc, MICROVM_MACHINE_IOAPIC2,
698 "Enable second IO-APIC");
699
700 object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
701 microvm_machine_get_isa_serial,
702 microvm_machine_set_isa_serial);
703 object_class_property_set_description(oc, MICROVM_MACHINE_ISA_SERIAL,
704 "Set off to disable the instantiation an ISA serial port");
705
706 object_class_property_add_bool(oc, MICROVM_MACHINE_OPTION_ROMS,
707 microvm_machine_get_option_roms,
708 microvm_machine_set_option_roms);
709 object_class_property_set_description(oc, MICROVM_MACHINE_OPTION_ROMS,
710 "Set off to disable loading option ROMs");
711
712 object_class_property_add_bool(oc, MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
713 microvm_machine_get_auto_kernel_cmdline,
714 microvm_machine_set_auto_kernel_cmdline);
715 object_class_property_set_description(oc,
716 MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
717 "Set off to disable adding virtio-mmio devices to the kernel cmdline");
718
719 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
720
721 compat_props_add(mc->compat_props, microvm_properties,
722 G_N_ELEMENTS(microvm_properties));
723 }
724
725 static const TypeInfo microvm_machine_info = {
726 .name = TYPE_MICROVM_MACHINE,
727 .parent = TYPE_X86_MACHINE,
728 .instance_size = sizeof(MicrovmMachineState),
729 .instance_init = microvm_machine_initfn,
730 .class_size = sizeof(MicrovmMachineClass),
731 .class_init = microvm_class_init,
732 .interfaces = (const InterfaceInfo[]) {
733 { TYPE_HOTPLUG_HANDLER },
734 { }
735 },
736 };
737
microvm_machine_init(void)738 static void microvm_machine_init(void)
739 {
740 type_register_static(µvm_machine_info);
741 }
742 type_init(microvm_machine_init);
743