1 /* 2 * TPR optimization for 32-bit Windows guests (XP and Server 2003) 3 * 4 * Copyright (C) 2007-2008 Qumranet Technologies 5 * Copyright (C) 2012 Jan Kiszka, Siemens AG 6 * 7 * This work is licensed under the terms of the GNU GPL version 2, or 8 * (at your option) any later version. See the COPYING file in the 9 * top-level directory. 10 */ 11 #include "qemu/osdep.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "sysemu/sysemu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/hw_accel.h" 17 #include "sysemu/kvm.h" 18 #include "hw/i386/apic_internal.h" 19 #include "hw/sysbus.h" 20 #include "tcg/tcg.h" 21 22 #define VAPIC_IO_PORT 0x7e 23 24 #define VAPIC_CPU_SHIFT 7 25 26 #define ROM_BLOCK_SIZE 512 27 #define ROM_BLOCK_MASK (~(ROM_BLOCK_SIZE - 1)) 28 29 typedef enum VAPICMode { 30 VAPIC_INACTIVE = 0, 31 VAPIC_ACTIVE = 1, 32 VAPIC_STANDBY = 2, 33 } VAPICMode; 34 35 typedef struct VAPICHandlers { 36 uint32_t set_tpr; 37 uint32_t set_tpr_eax; 38 uint32_t get_tpr[8]; 39 uint32_t get_tpr_stack; 40 } QEMU_PACKED VAPICHandlers; 41 42 typedef struct GuestROMState { 43 char signature[8]; 44 uint32_t vaddr; 45 uint32_t fixup_start; 46 uint32_t fixup_end; 47 uint32_t vapic_vaddr; 48 uint32_t vapic_size; 49 uint32_t vcpu_shift; 50 uint32_t real_tpr_addr; 51 VAPICHandlers up; 52 VAPICHandlers mp; 53 } QEMU_PACKED GuestROMState; 54 55 typedef struct VAPICROMState { 56 SysBusDevice busdev; 57 MemoryRegion io; 58 MemoryRegion rom; 59 uint32_t state; 60 uint32_t rom_state_paddr; 61 uint32_t rom_state_vaddr; 62 uint32_t vapic_paddr; 63 uint32_t real_tpr_addr; 64 GuestROMState rom_state; 65 size_t rom_size; 66 bool rom_mapped_writable; 67 VMChangeStateEntry *vmsentry; 68 } VAPICROMState; 69 70 #define TYPE_VAPIC "kvmvapic" 71 #define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC) 72 73 #define TPR_INSTR_ABS_MODRM 0x1 74 #define TPR_INSTR_MATCH_MODRM_REG 0x2 75 76 typedef struct TPRInstruction { 77 uint8_t opcode; 78 uint8_t modrm_reg; 79 unsigned int flags; 80 TPRAccess access; 81 size_t length; 82 off_t addr_offset; 83 } TPRInstruction; 84 85 /* must be sorted by length, shortest first */ 86 static const TPRInstruction tpr_instr[] = { 87 { /* mov abs to eax */ 88 .opcode = 0xa1, 89 .access = TPR_ACCESS_READ, 90 .length = 5, 91 .addr_offset = 1, 92 }, 93 { /* mov eax to abs */ 94 .opcode = 0xa3, 95 .access = TPR_ACCESS_WRITE, 96 .length = 5, 97 .addr_offset = 1, 98 }, 99 { /* mov r32 to r/m32 */ 100 .opcode = 0x89, 101 .flags = TPR_INSTR_ABS_MODRM, 102 .access = TPR_ACCESS_WRITE, 103 .length = 6, 104 .addr_offset = 2, 105 }, 106 { /* mov r/m32 to r32 */ 107 .opcode = 0x8b, 108 .flags = TPR_INSTR_ABS_MODRM, 109 .access = TPR_ACCESS_READ, 110 .length = 6, 111 .addr_offset = 2, 112 }, 113 { /* push r/m32 */ 114 .opcode = 0xff, 115 .modrm_reg = 6, 116 .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, 117 .access = TPR_ACCESS_READ, 118 .length = 6, 119 .addr_offset = 2, 120 }, 121 { /* mov imm32, r/m32 (c7/0) */ 122 .opcode = 0xc7, 123 .modrm_reg = 0, 124 .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG, 125 .access = TPR_ACCESS_WRITE, 126 .length = 10, 127 .addr_offset = 2, 128 }, 129 }; 130 131 static void read_guest_rom_state(VAPICROMState *s) 132 { 133 cpu_physical_memory_read(s->rom_state_paddr, &s->rom_state, 134 sizeof(GuestROMState)); 135 } 136 137 static void write_guest_rom_state(VAPICROMState *s) 138 { 139 cpu_physical_memory_write(s->rom_state_paddr, &s->rom_state, 140 sizeof(GuestROMState)); 141 } 142 143 static void update_guest_rom_state(VAPICROMState *s) 144 { 145 read_guest_rom_state(s); 146 147 s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr); 148 s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT); 149 150 write_guest_rom_state(s); 151 } 152 153 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) 154 { 155 CPUState *cs = CPU(x86_env_get_cpu(env)); 156 hwaddr paddr; 157 target_ulong addr; 158 159 if (s->state == VAPIC_ACTIVE) { 160 return 0; 161 } 162 /* 163 * If there is no prior TPR access instruction we could analyze (which is 164 * the case after resume from hibernation), we need to scan the possible 165 * virtual address space for the APIC mapping. 166 */ 167 for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) { 168 paddr = cpu_get_phys_page_debug(cs, addr); 169 if (paddr != APIC_DEFAULT_ADDRESS) { 170 continue; 171 } 172 s->real_tpr_addr = addr + 0x80; 173 update_guest_rom_state(s); 174 return 0; 175 } 176 return -1; 177 } 178 179 static uint8_t modrm_reg(uint8_t modrm) 180 { 181 return (modrm >> 3) & 7; 182 } 183 184 static bool is_abs_modrm(uint8_t modrm) 185 { 186 return (modrm & 0xc7) == 0x05; 187 } 188 189 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr) 190 { 191 return opcode[0] == instr->opcode && 192 (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) && 193 (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) || 194 modrm_reg(opcode[1]) == instr->modrm_reg); 195 } 196 197 static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu, 198 target_ulong *pip, TPRAccess access) 199 { 200 CPUState *cs = CPU(cpu); 201 const TPRInstruction *instr; 202 target_ulong ip = *pip; 203 uint8_t opcode[2]; 204 uint32_t real_tpr_addr; 205 int i; 206 207 if ((ip & 0xf0000000ULL) != 0x80000000ULL && 208 (ip & 0xf0000000ULL) != 0xe0000000ULL) { 209 return -1; 210 } 211 212 /* 213 * Early Windows 2003 SMP initialization contains a 214 * 215 * mov imm32, r/m32 216 * 217 * instruction that is patched by TPR optimization. The problem is that 218 * RSP, used by the patched instruction, is zero, so the guest gets a 219 * double fault and dies. 220 */ 221 if (cpu->env.regs[R_ESP] == 0) { 222 return -1; 223 } 224 225 if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 226 /* 227 * KVM without kernel-based TPR access reporting will pass an IP that 228 * points after the accessing instruction. So we need to look backward 229 * to find the reason. 230 */ 231 for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { 232 instr = &tpr_instr[i]; 233 if (instr->access != access) { 234 continue; 235 } 236 if (cpu_memory_rw_debug(cs, ip - instr->length, opcode, 237 sizeof(opcode), 0) < 0) { 238 return -1; 239 } 240 if (opcode_matches(opcode, instr)) { 241 ip -= instr->length; 242 goto instruction_ok; 243 } 244 } 245 return -1; 246 } else { 247 if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) { 248 return -1; 249 } 250 for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) { 251 instr = &tpr_instr[i]; 252 if (opcode_matches(opcode, instr)) { 253 goto instruction_ok; 254 } 255 } 256 return -1; 257 } 258 259 instruction_ok: 260 /* 261 * Grab the virtual TPR address from the instruction 262 * and update the cached values. 263 */ 264 if (cpu_memory_rw_debug(cs, ip + instr->addr_offset, 265 (void *)&real_tpr_addr, 266 sizeof(real_tpr_addr), 0) < 0) { 267 return -1; 268 } 269 real_tpr_addr = le32_to_cpu(real_tpr_addr); 270 if ((real_tpr_addr & 0xfff) != 0x80) { 271 return -1; 272 } 273 s->real_tpr_addr = real_tpr_addr; 274 update_guest_rom_state(s); 275 276 *pip = ip; 277 return 0; 278 } 279 280 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip) 281 { 282 CPUState *cs = CPU(x86_env_get_cpu(env)); 283 hwaddr paddr; 284 uint32_t rom_state_vaddr; 285 uint32_t pos, patch, offset; 286 287 /* nothing to do if already activated */ 288 if (s->state == VAPIC_ACTIVE) { 289 return 0; 290 } 291 292 /* bail out if ROM init code was not executed (missing ROM?) */ 293 if (s->state == VAPIC_INACTIVE) { 294 return -1; 295 } 296 297 /* find out virtual address of the ROM */ 298 rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000); 299 paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr); 300 if (paddr == -1) { 301 return -1; 302 } 303 paddr += rom_state_vaddr & ~TARGET_PAGE_MASK; 304 if (paddr != s->rom_state_paddr) { 305 return -1; 306 } 307 read_guest_rom_state(s); 308 if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) { 309 return -1; 310 } 311 s->rom_state_vaddr = rom_state_vaddr; 312 313 /* fixup addresses in ROM if needed */ 314 if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) { 315 return 0; 316 } 317 for (pos = le32_to_cpu(s->rom_state.fixup_start); 318 pos < le32_to_cpu(s->rom_state.fixup_end); 319 pos += 4) { 320 cpu_physical_memory_read(paddr + pos - s->rom_state.vaddr, 321 &offset, sizeof(offset)); 322 offset = le32_to_cpu(offset); 323 cpu_physical_memory_read(paddr + offset, &patch, sizeof(patch)); 324 patch = le32_to_cpu(patch); 325 patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr); 326 patch = cpu_to_le32(patch); 327 cpu_physical_memory_write(paddr + offset, &patch, sizeof(patch)); 328 } 329 read_guest_rom_state(s); 330 s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) - 331 le32_to_cpu(s->rom_state.vaddr); 332 333 return 0; 334 } 335 336 /* 337 * Tries to read the unique processor number from the Kernel Processor Control 338 * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR 339 * cannot be accessed or is considered invalid. This also ensures that we are 340 * not patching the wrong guest. 341 */ 342 static int get_kpcr_number(X86CPU *cpu) 343 { 344 CPUX86State *env = &cpu->env; 345 struct kpcr { 346 uint8_t fill1[0x1c]; 347 uint32_t self; 348 uint8_t fill2[0x31]; 349 uint8_t number; 350 } QEMU_PACKED kpcr; 351 352 if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base, 353 (void *)&kpcr, sizeof(kpcr), 0) < 0 || 354 kpcr.self != env->segs[R_FS].base) { 355 return -1; 356 } 357 return kpcr.number; 358 } 359 360 static int vapic_enable(VAPICROMState *s, X86CPU *cpu) 361 { 362 int cpu_number = get_kpcr_number(cpu); 363 hwaddr vapic_paddr; 364 static const uint8_t enabled = 1; 365 366 if (cpu_number < 0) { 367 return -1; 368 } 369 vapic_paddr = s->vapic_paddr + 370 (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT); 371 cpu_physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled), 372 &enabled, sizeof(enabled)); 373 apic_enable_vapic(cpu->apic_state, vapic_paddr); 374 375 s->state = VAPIC_ACTIVE; 376 377 return 0; 378 } 379 380 static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte) 381 { 382 cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1); 383 } 384 385 static void patch_call(X86CPU *cpu, target_ulong ip, uint32_t target) 386 { 387 uint32_t offset; 388 389 offset = cpu_to_le32(target - ip - 5); 390 patch_byte(cpu, ip, 0xe8); /* call near */ 391 cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1); 392 } 393 394 typedef struct PatchInfo { 395 VAPICHandlers *handler; 396 target_ulong ip; 397 } PatchInfo; 398 399 static void do_patch_instruction(CPUState *cs, run_on_cpu_data data) 400 { 401 X86CPU *x86_cpu = X86_CPU(cs); 402 PatchInfo *info = (PatchInfo *) data.host_ptr; 403 VAPICHandlers *handlers = info->handler; 404 target_ulong ip = info->ip; 405 uint8_t opcode[2]; 406 uint32_t imm32 = 0; 407 408 cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0); 409 410 switch (opcode[0]) { 411 case 0x89: /* mov r32 to r/m32 */ 412 patch_byte(x86_cpu, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */ 413 patch_call(x86_cpu, ip + 1, handlers->set_tpr); 414 break; 415 case 0x8b: /* mov r/m32 to r32 */ 416 patch_byte(x86_cpu, ip, 0x90); 417 patch_call(x86_cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]); 418 break; 419 case 0xa1: /* mov abs to eax */ 420 patch_call(x86_cpu, ip, handlers->get_tpr[0]); 421 break; 422 case 0xa3: /* mov eax to abs */ 423 patch_call(x86_cpu, ip, handlers->set_tpr_eax); 424 break; 425 case 0xc7: /* mov imm32, r/m32 (c7/0) */ 426 patch_byte(x86_cpu, ip, 0x68); /* push imm32 */ 427 cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0); 428 cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1); 429 patch_call(x86_cpu, ip + 5, handlers->set_tpr); 430 break; 431 case 0xff: /* push r/m32 */ 432 patch_byte(x86_cpu, ip, 0x50); /* push eax */ 433 patch_call(x86_cpu, ip + 1, handlers->get_tpr_stack); 434 break; 435 default: 436 abort(); 437 } 438 439 g_free(info); 440 } 441 442 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) 443 { 444 CPUState *cs = CPU(cpu); 445 VAPICHandlers *handlers; 446 PatchInfo *info; 447 448 if (smp_cpus == 1) { 449 handlers = &s->rom_state.up; 450 } else { 451 handlers = &s->rom_state.mp; 452 } 453 454 info = g_new(PatchInfo, 1); 455 info->handler = handlers; 456 info->ip = ip; 457 458 async_safe_run_on_cpu(cs, do_patch_instruction, RUN_ON_CPU_HOST_PTR(info)); 459 } 460 461 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip, 462 TPRAccess access) 463 { 464 VAPICROMState *s = VAPIC(dev); 465 X86CPU *cpu = X86_CPU(cs); 466 CPUX86State *env = &cpu->env; 467 468 cpu_synchronize_state(cs); 469 470 if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) { 471 if (s->state == VAPIC_ACTIVE) { 472 vapic_enable(s, cpu); 473 } 474 return; 475 } 476 if (update_rom_mapping(s, env, ip) < 0) { 477 return; 478 } 479 if (vapic_enable(s, cpu) < 0) { 480 return; 481 } 482 patch_instruction(s, cpu, ip); 483 } 484 485 typedef struct VAPICEnableTPRReporting { 486 DeviceState *apic; 487 bool enable; 488 } VAPICEnableTPRReporting; 489 490 static void vapic_do_enable_tpr_reporting(CPUState *cpu, run_on_cpu_data data) 491 { 492 VAPICEnableTPRReporting *info = data.host_ptr; 493 apic_enable_tpr_access_reporting(info->apic, info->enable); 494 } 495 496 static void vapic_enable_tpr_reporting(bool enable) 497 { 498 VAPICEnableTPRReporting info = { 499 .enable = enable, 500 }; 501 CPUState *cs; 502 X86CPU *cpu; 503 504 CPU_FOREACH(cs) { 505 cpu = X86_CPU(cs); 506 info.apic = cpu->apic_state; 507 run_on_cpu(cs, vapic_do_enable_tpr_reporting, RUN_ON_CPU_HOST_PTR(&info)); 508 } 509 } 510 511 static void vapic_reset(DeviceState *dev) 512 { 513 VAPICROMState *s = VAPIC(dev); 514 515 s->state = VAPIC_INACTIVE; 516 s->rom_state_paddr = 0; 517 vapic_enable_tpr_reporting(false); 518 } 519 520 /* 521 * Set the IRQ polling hypercalls to the supported variant: 522 * - vmcall if using KVM in-kernel irqchip 523 * - 32-bit VAPIC port write otherwise 524 */ 525 static int patch_hypercalls(VAPICROMState *s) 526 { 527 hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; 528 static const uint8_t vmcall_pattern[] = { /* vmcall */ 529 0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1 530 }; 531 static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */ 532 0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e 533 }; 534 uint8_t alternates[2]; 535 const uint8_t *pattern; 536 const uint8_t *patch; 537 off_t pos; 538 uint8_t *rom; 539 540 rom = g_malloc(s->rom_size); 541 cpu_physical_memory_read(rom_paddr, rom, s->rom_size); 542 543 for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) { 544 if (kvm_irqchip_in_kernel()) { 545 pattern = outl_pattern; 546 alternates[0] = outl_pattern[7]; 547 alternates[1] = outl_pattern[7]; 548 patch = &vmcall_pattern[5]; 549 } else { 550 pattern = vmcall_pattern; 551 alternates[0] = vmcall_pattern[7]; 552 alternates[1] = 0xd9; /* AMD's VMMCALL */ 553 patch = &outl_pattern[5]; 554 } 555 if (memcmp(rom + pos, pattern, 7) == 0 && 556 (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) { 557 cpu_physical_memory_write(rom_paddr + pos + 5, patch, 3); 558 /* 559 * Don't flush the tb here. Under ordinary conditions, the patched 560 * calls are miles away from the current IP. Under malicious 561 * conditions, the guest could trick us to crash. 562 */ 563 } 564 } 565 566 g_free(rom); 567 return 0; 568 } 569 570 /* 571 * For TCG mode or the time KVM honors read-only memory regions, we need to 572 * enable write access to the option ROM so that variables can be updated by 573 * the guest. 574 */ 575 static int vapic_map_rom_writable(VAPICROMState *s) 576 { 577 hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK; 578 MemoryRegionSection section; 579 MemoryRegion *as; 580 size_t rom_size; 581 uint8_t *ram; 582 583 as = sysbus_address_space(&s->busdev); 584 585 if (s->rom_mapped_writable) { 586 memory_region_del_subregion(as, &s->rom); 587 object_unparent(OBJECT(&s->rom)); 588 } 589 590 /* grab RAM memory region (region @rom_paddr may still be pc.rom) */ 591 section = memory_region_find(as, 0, 1); 592 593 /* read ROM size from RAM region */ 594 if (rom_paddr + 2 >= memory_region_size(section.mr)) { 595 return -1; 596 } 597 ram = memory_region_get_ram_ptr(section.mr); 598 rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE; 599 if (rom_size == 0) { 600 return -1; 601 } 602 s->rom_size = rom_size; 603 604 /* We need to round to avoid creating subpages 605 * from which we cannot run code. */ 606 rom_size += rom_paddr & ~TARGET_PAGE_MASK; 607 rom_paddr &= TARGET_PAGE_MASK; 608 rom_size = TARGET_PAGE_ALIGN(rom_size); 609 610 memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr, 611 rom_paddr, rom_size); 612 memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000); 613 s->rom_mapped_writable = true; 614 memory_region_unref(section.mr); 615 616 return 0; 617 } 618 619 static int vapic_prepare(VAPICROMState *s) 620 { 621 if (vapic_map_rom_writable(s) < 0) { 622 return -1; 623 } 624 625 if (patch_hypercalls(s) < 0) { 626 return -1; 627 } 628 629 vapic_enable_tpr_reporting(true); 630 631 return 0; 632 } 633 634 static void vapic_write(void *opaque, hwaddr addr, uint64_t data, 635 unsigned int size) 636 { 637 VAPICROMState *s = opaque; 638 X86CPU *cpu; 639 CPUX86State *env; 640 hwaddr rom_paddr; 641 642 if (!current_cpu) { 643 return; 644 } 645 646 cpu_synchronize_state(current_cpu); 647 cpu = X86_CPU(current_cpu); 648 env = &cpu->env; 649 650 /* 651 * The VAPIC supports two PIO-based hypercalls, both via port 0x7E. 652 * o 16-bit write access: 653 * Reports the option ROM initialization to the hypervisor. Written 654 * value is the offset of the state structure in the ROM. 655 * o 8-bit write access: 656 * Reactivates the VAPIC after a guest hibernation, i.e. after the 657 * option ROM content has been re-initialized by a guest power cycle. 658 * o 32-bit write access: 659 * Poll for pending IRQs, considering the current VAPIC state. 660 */ 661 switch (size) { 662 case 2: 663 if (s->state == VAPIC_INACTIVE) { 664 rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK; 665 s->rom_state_paddr = rom_paddr + data; 666 667 s->state = VAPIC_STANDBY; 668 } 669 if (vapic_prepare(s) < 0) { 670 s->state = VAPIC_INACTIVE; 671 s->rom_state_paddr = 0; 672 break; 673 } 674 break; 675 case 1: 676 if (kvm_enabled()) { 677 /* 678 * Disable triggering instruction in ROM by writing a NOP. 679 * 680 * We cannot do this in TCG mode as the reported IP is not 681 * accurate. 682 */ 683 pause_all_vcpus(); 684 patch_byte(cpu, env->eip - 2, 0x66); 685 patch_byte(cpu, env->eip - 1, 0x90); 686 resume_all_vcpus(); 687 } 688 689 if (s->state == VAPIC_ACTIVE) { 690 break; 691 } 692 if (update_rom_mapping(s, env, env->eip) < 0) { 693 break; 694 } 695 if (find_real_tpr_addr(s, env) < 0) { 696 break; 697 } 698 vapic_enable(s, cpu); 699 break; 700 default: 701 case 4: 702 if (!kvm_irqchip_in_kernel()) { 703 apic_poll_irq(cpu->apic_state); 704 } 705 break; 706 } 707 } 708 709 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) 710 { 711 return 0xffffffff; 712 } 713 714 static const MemoryRegionOps vapic_ops = { 715 .write = vapic_write, 716 .read = vapic_read, 717 .endianness = DEVICE_NATIVE_ENDIAN, 718 }; 719 720 static void vapic_realize(DeviceState *dev, Error **errp) 721 { 722 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 723 VAPICROMState *s = VAPIC(dev); 724 725 memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2); 726 sysbus_add_io(sbd, VAPIC_IO_PORT, &s->io); 727 sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2); 728 729 option_rom[nb_option_roms].name = "kvmvapic.bin"; 730 option_rom[nb_option_roms].bootindex = -1; 731 nb_option_roms++; 732 } 733 734 static void do_vapic_enable(CPUState *cs, run_on_cpu_data data) 735 { 736 VAPICROMState *s = data.host_ptr; 737 X86CPU *cpu = X86_CPU(cs); 738 739 static const uint8_t enabled = 1; 740 cpu_physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled), 741 &enabled, sizeof(enabled)); 742 apic_enable_vapic(cpu->apic_state, s->vapic_paddr); 743 s->state = VAPIC_ACTIVE; 744 } 745 746 static void kvmvapic_vm_state_change(void *opaque, int running, 747 RunState state) 748 { 749 VAPICROMState *s = opaque; 750 uint8_t *zero; 751 752 if (!running) { 753 return; 754 } 755 756 if (s->state == VAPIC_ACTIVE) { 757 if (smp_cpus == 1) { 758 run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s)); 759 } else { 760 zero = g_malloc0(s->rom_state.vapic_size); 761 cpu_physical_memory_write(s->vapic_paddr, zero, 762 s->rom_state.vapic_size); 763 g_free(zero); 764 } 765 } 766 767 qemu_del_vm_change_state_handler(s->vmsentry); 768 s->vmsentry = NULL; 769 } 770 771 static int vapic_post_load(void *opaque, int version_id) 772 { 773 VAPICROMState *s = opaque; 774 775 /* 776 * The old implementation of qemu-kvm did not provide the state 777 * VAPIC_STANDBY. Reconstruct it. 778 */ 779 if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) { 780 s->state = VAPIC_STANDBY; 781 } 782 783 if (s->state != VAPIC_INACTIVE) { 784 if (vapic_prepare(s) < 0) { 785 return -1; 786 } 787 } 788 789 if (!s->vmsentry) { 790 s->vmsentry = 791 qemu_add_vm_change_state_handler(kvmvapic_vm_state_change, s); 792 } 793 return 0; 794 } 795 796 static const VMStateDescription vmstate_handlers = { 797 .name = "kvmvapic-handlers", 798 .version_id = 1, 799 .minimum_version_id = 1, 800 .fields = (VMStateField[]) { 801 VMSTATE_UINT32(set_tpr, VAPICHandlers), 802 VMSTATE_UINT32(set_tpr_eax, VAPICHandlers), 803 VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8), 804 VMSTATE_UINT32(get_tpr_stack, VAPICHandlers), 805 VMSTATE_END_OF_LIST() 806 } 807 }; 808 809 static const VMStateDescription vmstate_guest_rom = { 810 .name = "kvmvapic-guest-rom", 811 .version_id = 1, 812 .minimum_version_id = 1, 813 .fields = (VMStateField[]) { 814 VMSTATE_UNUSED(8), /* signature */ 815 VMSTATE_UINT32(vaddr, GuestROMState), 816 VMSTATE_UINT32(fixup_start, GuestROMState), 817 VMSTATE_UINT32(fixup_end, GuestROMState), 818 VMSTATE_UINT32(vapic_vaddr, GuestROMState), 819 VMSTATE_UINT32(vapic_size, GuestROMState), 820 VMSTATE_UINT32(vcpu_shift, GuestROMState), 821 VMSTATE_UINT32(real_tpr_addr, GuestROMState), 822 VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers), 823 VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers), 824 VMSTATE_END_OF_LIST() 825 } 826 }; 827 828 static const VMStateDescription vmstate_vapic = { 829 .name = "kvm-tpr-opt", /* compatible with qemu-kvm VAPIC */ 830 .version_id = 1, 831 .minimum_version_id = 1, 832 .post_load = vapic_post_load, 833 .fields = (VMStateField[]) { 834 VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom, 835 GuestROMState), 836 VMSTATE_UINT32(state, VAPICROMState), 837 VMSTATE_UINT32(real_tpr_addr, VAPICROMState), 838 VMSTATE_UINT32(rom_state_vaddr, VAPICROMState), 839 VMSTATE_UINT32(vapic_paddr, VAPICROMState), 840 VMSTATE_UINT32(rom_state_paddr, VAPICROMState), 841 VMSTATE_END_OF_LIST() 842 } 843 }; 844 845 static void vapic_class_init(ObjectClass *klass, void *data) 846 { 847 DeviceClass *dc = DEVICE_CLASS(klass); 848 849 dc->reset = vapic_reset; 850 dc->vmsd = &vmstate_vapic; 851 dc->realize = vapic_realize; 852 } 853 854 static const TypeInfo vapic_type = { 855 .name = TYPE_VAPIC, 856 .parent = TYPE_SYS_BUS_DEVICE, 857 .instance_size = sizeof(VAPICROMState), 858 .class_init = vapic_class_init, 859 }; 860 861 static void vapic_register(void) 862 { 863 type_register_static(&vapic_type); 864 } 865 866 type_init(vapic_register); 867