1 /* 2 * KVM in-kernel APIC support 3 * 4 * Copyright (c) 2011 Siemens AG 5 * 6 * Authors: 7 * Jan Kiszka <jan.kiszka@siemens.com> 8 * 9 * This work is licensed under the terms of the GNU GPL version 2. 10 * See the COPYING file in the top-level directory. 11 */ 12 #include "qemu/osdep.h" 13 #include "qemu-common.h" 14 #include "cpu.h" 15 #include "hw/i386/apic_internal.h" 16 #include "hw/pci/msi.h" 17 #include "sysemu/kvm.h" 18 19 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, 20 int reg_id, uint32_t val) 21 { 22 *((uint32_t *)(kapic->regs + (reg_id << 4))) = val; 23 } 24 25 static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic, 26 int reg_id) 27 { 28 return *((uint32_t *)(kapic->regs + (reg_id << 4))); 29 } 30 31 static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) 32 { 33 int i; 34 35 memset(kapic, 0, sizeof(*kapic)); 36 kvm_apic_set_reg(kapic, 0x2, s->id << 24); 37 kvm_apic_set_reg(kapic, 0x8, s->tpr); 38 kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24); 39 kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff); 40 kvm_apic_set_reg(kapic, 0xf, s->spurious_vec); 41 for (i = 0; i < 8; i++) { 42 kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]); 43 kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]); 44 kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]); 45 } 46 kvm_apic_set_reg(kapic, 0x28, s->esr); 47 kvm_apic_set_reg(kapic, 0x30, s->icr[0]); 48 kvm_apic_set_reg(kapic, 0x31, s->icr[1]); 49 for (i = 0; i < APIC_LVT_NB; i++) { 50 kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]); 51 } 52 kvm_apic_set_reg(kapic, 0x38, s->initial_count); 53 kvm_apic_set_reg(kapic, 0x3e, s->divide_conf); 54 } 55 56 void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic) 57 { 58 APICCommonState *s = APIC_COMMON(dev); 59 int i, v; 60 61 s->id = kvm_apic_get_reg(kapic, 0x2) >> 24; 62 s->tpr = kvm_apic_get_reg(kapic, 0x8); 63 s->arb_id = kvm_apic_get_reg(kapic, 0x9); 64 s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24; 65 s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28; 66 s->spurious_vec = kvm_apic_get_reg(kapic, 0xf); 67 for (i = 0; i < 8; i++) { 68 s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i); 69 s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i); 70 s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i); 71 } 72 s->esr = kvm_apic_get_reg(kapic, 0x28); 73 s->icr[0] = kvm_apic_get_reg(kapic, 0x30); 74 s->icr[1] = kvm_apic_get_reg(kapic, 0x31); 75 for (i = 0; i < APIC_LVT_NB; i++) { 76 s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i); 77 } 78 s->initial_count = kvm_apic_get_reg(kapic, 0x38); 79 s->divide_conf = kvm_apic_get_reg(kapic, 0x3e); 80 81 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 82 s->count_shift = (v + 1) & 7; 83 84 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 85 apic_next_timer(s, s->initial_count_load_time); 86 } 87 88 static void kvm_apic_set_base(APICCommonState *s, uint64_t val) 89 { 90 s->apicbase = val; 91 } 92 93 static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val) 94 { 95 s->tpr = (val & 0x0f) << 4; 96 } 97 98 static uint8_t kvm_apic_get_tpr(APICCommonState *s) 99 { 100 return s->tpr >> 4; 101 } 102 103 static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable) 104 { 105 struct kvm_tpr_access_ctl ctl = { 106 .enabled = enable 107 }; 108 109 kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl); 110 } 111 112 static void kvm_apic_vapic_base_update(APICCommonState *s) 113 { 114 struct kvm_vapic_addr vapid_addr = { 115 .vapic_addr = s->vapic_paddr, 116 }; 117 int ret; 118 119 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr); 120 if (ret < 0) { 121 fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", 122 strerror(-ret)); 123 abort(); 124 } 125 } 126 127 static void kvm_apic_put(void *data) 128 { 129 APICCommonState *s = data; 130 struct kvm_lapic_state kapic; 131 int ret; 132 133 kvm_put_apic_state(s, &kapic); 134 135 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); 136 if (ret < 0) { 137 fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(ret)); 138 abort(); 139 } 140 } 141 142 static void kvm_apic_post_load(APICCommonState *s) 143 { 144 fprintf(stderr, "%s: Yeh\n", __func__); 145 run_on_cpu(CPU(s->cpu), kvm_apic_put, s); 146 } 147 148 static void do_inject_external_nmi(void *data) 149 { 150 APICCommonState *s = data; 151 CPUState *cpu = CPU(s->cpu); 152 uint32_t lvt; 153 int ret; 154 155 cpu_synchronize_state(cpu); 156 157 lvt = s->lvt[APIC_LVT_LINT1]; 158 if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) { 159 ret = kvm_vcpu_ioctl(cpu, KVM_NMI); 160 if (ret < 0) { 161 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", 162 strerror(-ret)); 163 } 164 } 165 } 166 167 static void kvm_apic_external_nmi(APICCommonState *s) 168 { 169 run_on_cpu(CPU(s->cpu), do_inject_external_nmi, s); 170 } 171 172 static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, 173 unsigned size) 174 { 175 return ~(uint64_t)0; 176 } 177 178 static void kvm_apic_mem_write(void *opaque, hwaddr addr, 179 uint64_t data, unsigned size) 180 { 181 MSIMessage msg = { .address = addr, .data = data }; 182 int ret; 183 184 ret = kvm_irqchip_send_msi(kvm_state, msg); 185 if (ret < 0) { 186 fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", 187 strerror(-ret)); 188 } 189 } 190 191 static const MemoryRegionOps kvm_apic_io_ops = { 192 .read = kvm_apic_mem_read, 193 .write = kvm_apic_mem_write, 194 .endianness = DEVICE_NATIVE_ENDIAN, 195 }; 196 197 static void kvm_apic_reset(APICCommonState *s) 198 { 199 /* Not used by KVM, which uses the CPU mp_state instead. */ 200 s->wait_for_sipi = 0; 201 202 run_on_cpu(CPU(s->cpu), kvm_apic_put, s); 203 } 204 205 static void kvm_apic_realize(DeviceState *dev, Error **errp) 206 { 207 APICCommonState *s = APIC_COMMON(dev); 208 209 memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s, 210 "kvm-apic-msi", APIC_SPACE_SIZE); 211 212 if (kvm_has_gsi_routing()) { 213 msi_nonbroken = true; 214 } 215 } 216 217 static void kvm_apic_unrealize(DeviceState *dev, Error **errp) 218 { 219 } 220 221 static void kvm_apic_class_init(ObjectClass *klass, void *data) 222 { 223 APICCommonClass *k = APIC_COMMON_CLASS(klass); 224 225 k->realize = kvm_apic_realize; 226 k->unrealize = kvm_apic_unrealize; 227 k->reset = kvm_apic_reset; 228 k->set_base = kvm_apic_set_base; 229 k->set_tpr = kvm_apic_set_tpr; 230 k->get_tpr = kvm_apic_get_tpr; 231 k->post_load = kvm_apic_post_load; 232 k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting; 233 k->vapic_base_update = kvm_apic_vapic_base_update; 234 k->external_nmi = kvm_apic_external_nmi; 235 } 236 237 static const TypeInfo kvm_apic_info = { 238 .name = "kvm-apic", 239 .parent = TYPE_APIC_COMMON, 240 .instance_size = sizeof(APICCommonState), 241 .class_init = kvm_apic_class_init, 242 }; 243 244 static void kvm_apic_register_types(void) 245 { 246 type_register_static(&kvm_apic_info); 247 } 248 249 type_init(kvm_apic_register_types) 250