1 /* 2 * KVM in-kernel APIC support 3 * 4 * Copyright (c) 2011 Siemens AG 5 * 6 * Authors: 7 * Jan Kiszka <jan.kiszka@siemens.com> 8 * 9 * This work is licensed under the terms of the GNU GPL version 2. 10 * See the COPYING file in the top-level directory. 11 */ 12 #include "qemu/osdep.h" 13 #include "qemu-common.h" 14 #include "cpu.h" 15 #include "hw/i386/apic_internal.h" 16 #include "hw/pci/msi.h" 17 #include "sysemu/hw_accel.h" 18 #include "sysemu/kvm.h" 19 #include "target/i386/kvm_i386.h" 20 21 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, 22 int reg_id, uint32_t val) 23 { 24 *((uint32_t *)(kapic->regs + (reg_id << 4))) = val; 25 } 26 27 static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic, 28 int reg_id) 29 { 30 return *((uint32_t *)(kapic->regs + (reg_id << 4))); 31 } 32 33 static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) 34 { 35 int i; 36 37 memset(kapic, 0, sizeof(*kapic)); 38 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { 39 kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id); 40 } else { 41 kvm_apic_set_reg(kapic, 0x2, s->id << 24); 42 } 43 kvm_apic_set_reg(kapic, 0x8, s->tpr); 44 kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24); 45 kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff); 46 kvm_apic_set_reg(kapic, 0xf, s->spurious_vec); 47 for (i = 0; i < 8; i++) { 48 kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]); 49 kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]); 50 kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]); 51 } 52 kvm_apic_set_reg(kapic, 0x28, s->esr); 53 kvm_apic_set_reg(kapic, 0x30, s->icr[0]); 54 kvm_apic_set_reg(kapic, 0x31, s->icr[1]); 55 for (i = 0; i < APIC_LVT_NB; i++) { 56 kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]); 57 } 58 kvm_apic_set_reg(kapic, 0x38, s->initial_count); 59 kvm_apic_set_reg(kapic, 0x3e, s->divide_conf); 60 } 61 62 void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic) 63 { 64 APICCommonState *s = APIC_COMMON(dev); 65 int i, v; 66 67 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { 68 assert(kvm_apic_get_reg(kapic, 0x2) == s->initial_apic_id); 69 } else { 70 s->id = kvm_apic_get_reg(kapic, 0x2) >> 24; 71 } 72 s->tpr = kvm_apic_get_reg(kapic, 0x8); 73 s->arb_id = kvm_apic_get_reg(kapic, 0x9); 74 s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24; 75 s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28; 76 s->spurious_vec = kvm_apic_get_reg(kapic, 0xf); 77 for (i = 0; i < 8; i++) { 78 s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i); 79 s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i); 80 s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i); 81 } 82 s->esr = kvm_apic_get_reg(kapic, 0x28); 83 s->icr[0] = kvm_apic_get_reg(kapic, 0x30); 84 s->icr[1] = kvm_apic_get_reg(kapic, 0x31); 85 for (i = 0; i < APIC_LVT_NB; i++) { 86 s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i); 87 } 88 s->initial_count = kvm_apic_get_reg(kapic, 0x38); 89 s->divide_conf = kvm_apic_get_reg(kapic, 0x3e); 90 91 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 92 s->count_shift = (v + 1) & 7; 93 94 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 95 apic_next_timer(s, s->initial_count_load_time); 96 } 97 98 static void kvm_apic_set_base(APICCommonState *s, uint64_t val) 99 { 100 s->apicbase = val; 101 } 102 103 static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val) 104 { 105 s->tpr = (val & 0x0f) << 4; 106 } 107 108 static uint8_t kvm_apic_get_tpr(APICCommonState *s) 109 { 110 return s->tpr >> 4; 111 } 112 113 static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable) 114 { 115 struct kvm_tpr_access_ctl ctl = { 116 .enabled = enable 117 }; 118 119 kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl); 120 } 121 122 static void kvm_apic_vapic_base_update(APICCommonState *s) 123 { 124 struct kvm_vapic_addr vapid_addr = { 125 .vapic_addr = s->vapic_paddr, 126 }; 127 int ret; 128 129 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr); 130 if (ret < 0) { 131 fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", 132 strerror(-ret)); 133 abort(); 134 } 135 } 136 137 static void kvm_apic_put(CPUState *cs, run_on_cpu_data data) 138 { 139 APICCommonState *s = data.host_ptr; 140 struct kvm_lapic_state kapic; 141 int ret; 142 143 kvm_put_apicbase(s->cpu, s->apicbase); 144 kvm_put_apic_state(s, &kapic); 145 146 ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); 147 if (ret < 0) { 148 fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(ret)); 149 abort(); 150 } 151 } 152 153 static void kvm_apic_post_load(APICCommonState *s) 154 { 155 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); 156 } 157 158 static void do_inject_external_nmi(CPUState *cpu, run_on_cpu_data data) 159 { 160 APICCommonState *s = data.host_ptr; 161 uint32_t lvt; 162 int ret; 163 164 cpu_synchronize_state(cpu); 165 166 lvt = s->lvt[APIC_LVT_LINT1]; 167 if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) { 168 ret = kvm_vcpu_ioctl(cpu, KVM_NMI); 169 if (ret < 0) { 170 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", 171 strerror(-ret)); 172 } 173 } 174 } 175 176 static void kvm_apic_external_nmi(APICCommonState *s) 177 { 178 run_on_cpu(CPU(s->cpu), do_inject_external_nmi, RUN_ON_CPU_HOST_PTR(s)); 179 } 180 181 static void kvm_send_msi(MSIMessage *msg) 182 { 183 int ret; 184 185 ret = kvm_irqchip_send_msi(kvm_state, *msg); 186 if (ret < 0) { 187 fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", 188 strerror(-ret)); 189 } 190 } 191 192 static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, 193 unsigned size) 194 { 195 return ~(uint64_t)0; 196 } 197 198 static void kvm_apic_mem_write(void *opaque, hwaddr addr, 199 uint64_t data, unsigned size) 200 { 201 MSIMessage msg = { .address = addr, .data = data }; 202 203 kvm_send_msi(&msg); 204 } 205 206 static const MemoryRegionOps kvm_apic_io_ops = { 207 .read = kvm_apic_mem_read, 208 .write = kvm_apic_mem_write, 209 .endianness = DEVICE_NATIVE_ENDIAN, 210 }; 211 212 static void kvm_apic_reset(APICCommonState *s) 213 { 214 /* Not used by KVM, which uses the CPU mp_state instead. */ 215 s->wait_for_sipi = 0; 216 217 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); 218 } 219 220 static void kvm_apic_realize(DeviceState *dev, Error **errp) 221 { 222 APICCommonState *s = APIC_COMMON(dev); 223 224 memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s, 225 "kvm-apic-msi", APIC_SPACE_SIZE); 226 227 if (kvm_has_gsi_routing()) { 228 msi_nonbroken = true; 229 } 230 } 231 232 static void kvm_apic_unrealize(DeviceState *dev, Error **errp) 233 { 234 } 235 236 static void kvm_apic_class_init(ObjectClass *klass, void *data) 237 { 238 APICCommonClass *k = APIC_COMMON_CLASS(klass); 239 240 k->realize = kvm_apic_realize; 241 k->unrealize = kvm_apic_unrealize; 242 k->reset = kvm_apic_reset; 243 k->set_base = kvm_apic_set_base; 244 k->set_tpr = kvm_apic_set_tpr; 245 k->get_tpr = kvm_apic_get_tpr; 246 k->post_load = kvm_apic_post_load; 247 k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting; 248 k->vapic_base_update = kvm_apic_vapic_base_update; 249 k->external_nmi = kvm_apic_external_nmi; 250 k->send_msi = kvm_send_msi; 251 } 252 253 static const TypeInfo kvm_apic_info = { 254 .name = "kvm-apic", 255 .parent = TYPE_APIC_COMMON, 256 .instance_size = sizeof(APICCommonState), 257 .class_init = kvm_apic_class_init, 258 }; 259 260 static void kvm_apic_register_types(void) 261 { 262 type_register_static(&kvm_apic_info); 263 } 264 265 type_init(kvm_apic_register_types) 266