1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/error-report.h" 24 #include "qemu/main-loop.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "intel_iommu_internal.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_bus.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/i386/pc.h" 32 #include "hw/i386/apic-msidef.h" 33 #include "hw/i386/x86-iommu.h" 34 #include "hw/pci-host/q35.h" 35 #include "sysemu/kvm.h" 36 #include "sysemu/dma.h" 37 #include "sysemu/sysemu.h" 38 #include "hw/i386/apic_internal.h" 39 #include "kvm/kvm_i386.h" 40 #include "migration/vmstate.h" 41 #include "trace.h" 42 43 /* context entry operations */ 44 #define VTD_CE_GET_RID2PASID(ce) \ 45 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK) 46 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \ 47 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) 48 49 /* pe operations */ 50 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) 51 #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) 52 #define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\ 53 if (ret_fr) { \ 54 ret_fr = -ret_fr; \ 55 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \ 56 trace_vtd_fault_disabled(); \ 57 } else { \ 58 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \ 59 } \ 60 goto error; \ 61 } \ 62 } 63 64 static void vtd_address_space_refresh_all(IntelIOMMUState *s); 65 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); 66 67 static void vtd_panic_require_caching_mode(void) 68 { 69 error_report("We need to set caching-mode=on for intel-iommu to enable " 70 "device assignment with IOMMU protection."); 71 exit(1); 72 } 73 74 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, 75 uint64_t wmask, uint64_t w1cmask) 76 { 77 stq_le_p(&s->csr[addr], val); 78 stq_le_p(&s->wmask[addr], wmask); 79 stq_le_p(&s->w1cmask[addr], w1cmask); 80 } 81 82 static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask) 83 { 84 stq_le_p(&s->womask[addr], mask); 85 } 86 87 static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val, 88 uint32_t wmask, uint32_t w1cmask) 89 { 90 stl_le_p(&s->csr[addr], val); 91 stl_le_p(&s->wmask[addr], wmask); 92 stl_le_p(&s->w1cmask[addr], w1cmask); 93 } 94 95 static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask) 96 { 97 stl_le_p(&s->womask[addr], mask); 98 } 99 100 /* "External" get/set operations */ 101 static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val) 102 { 103 uint64_t oldval = ldq_le_p(&s->csr[addr]); 104 uint64_t wmask = ldq_le_p(&s->wmask[addr]); 105 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); 106 stq_le_p(&s->csr[addr], 107 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); 108 } 109 110 static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val) 111 { 112 uint32_t oldval = ldl_le_p(&s->csr[addr]); 113 uint32_t wmask = ldl_le_p(&s->wmask[addr]); 114 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); 115 stl_le_p(&s->csr[addr], 116 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); 117 } 118 119 static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr) 120 { 121 uint64_t val = ldq_le_p(&s->csr[addr]); 122 uint64_t womask = ldq_le_p(&s->womask[addr]); 123 return val & ~womask; 124 } 125 126 static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr) 127 { 128 uint32_t val = ldl_le_p(&s->csr[addr]); 129 uint32_t womask = ldl_le_p(&s->womask[addr]); 130 return val & ~womask; 131 } 132 133 /* "Internal" get/set operations */ 134 static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr) 135 { 136 return ldq_le_p(&s->csr[addr]); 137 } 138 139 static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr) 140 { 141 return ldl_le_p(&s->csr[addr]); 142 } 143 144 static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val) 145 { 146 stq_le_p(&s->csr[addr], val); 147 } 148 149 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr, 150 uint32_t clear, uint32_t mask) 151 { 152 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; 153 stl_le_p(&s->csr[addr], new_val); 154 return new_val; 155 } 156 157 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr, 158 uint64_t clear, uint64_t mask) 159 { 160 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; 161 stq_le_p(&s->csr[addr], new_val); 162 return new_val; 163 } 164 165 static inline void vtd_iommu_lock(IntelIOMMUState *s) 166 { 167 qemu_mutex_lock(&s->iommu_lock); 168 } 169 170 static inline void vtd_iommu_unlock(IntelIOMMUState *s) 171 { 172 qemu_mutex_unlock(&s->iommu_lock); 173 } 174 175 static void vtd_update_scalable_state(IntelIOMMUState *s) 176 { 177 uint64_t val = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 178 179 if (s->scalable_mode) { 180 s->root_scalable = val & VTD_RTADDR_SMT; 181 } 182 } 183 184 /* Whether the address space needs to notify new mappings */ 185 static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as) 186 { 187 return as->notifier_flags & IOMMU_NOTIFIER_MAP; 188 } 189 190 /* GHashTable functions */ 191 static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2) 192 { 193 return *((const uint64_t *)v1) == *((const uint64_t *)v2); 194 } 195 196 static guint vtd_uint64_hash(gconstpointer v) 197 { 198 return (guint)*(const uint64_t *)v; 199 } 200 201 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, 202 gpointer user_data) 203 { 204 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; 205 uint16_t domain_id = *(uint16_t *)user_data; 206 return entry->domain_id == domain_id; 207 } 208 209 /* The shift of an addr for a certain level of paging structure */ 210 static inline uint32_t vtd_slpt_level_shift(uint32_t level) 211 { 212 assert(level != 0); 213 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS; 214 } 215 216 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level) 217 { 218 return ~((1ULL << vtd_slpt_level_shift(level)) - 1); 219 } 220 221 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value, 222 gpointer user_data) 223 { 224 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; 225 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; 226 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; 227 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; 228 return (entry->domain_id == info->domain_id) && 229 (((entry->gfn & info->mask) == gfn) || 230 (entry->gfn == gfn_tlb)); 231 } 232 233 /* Reset all the gen of VTDAddressSpace to zero and set the gen of 234 * IntelIOMMUState to 1. Must be called with IOMMU lock held. 235 */ 236 static void vtd_reset_context_cache_locked(IntelIOMMUState *s) 237 { 238 VTDAddressSpace *vtd_as; 239 VTDBus *vtd_bus; 240 GHashTableIter bus_it; 241 uint32_t devfn_it; 242 243 trace_vtd_context_cache_reset(); 244 245 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr); 246 247 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) { 248 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { 249 vtd_as = vtd_bus->dev_as[devfn_it]; 250 if (!vtd_as) { 251 continue; 252 } 253 vtd_as->context_cache_entry.context_cache_gen = 0; 254 } 255 } 256 s->context_cache_gen = 1; 257 } 258 259 /* Must be called with IOMMU lock held. */ 260 static void vtd_reset_iotlb_locked(IntelIOMMUState *s) 261 { 262 assert(s->iotlb); 263 g_hash_table_remove_all(s->iotlb); 264 } 265 266 static void vtd_reset_iotlb(IntelIOMMUState *s) 267 { 268 vtd_iommu_lock(s); 269 vtd_reset_iotlb_locked(s); 270 vtd_iommu_unlock(s); 271 } 272 273 static void vtd_reset_caches(IntelIOMMUState *s) 274 { 275 vtd_iommu_lock(s); 276 vtd_reset_iotlb_locked(s); 277 vtd_reset_context_cache_locked(s); 278 vtd_iommu_unlock(s); 279 } 280 281 static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id, 282 uint32_t level) 283 { 284 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) | 285 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT); 286 } 287 288 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) 289 { 290 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; 291 } 292 293 /* Must be called with IOMMU lock held */ 294 static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id, 295 hwaddr addr) 296 { 297 VTDIOTLBEntry *entry; 298 uint64_t key; 299 int level; 300 301 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { 302 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level), 303 source_id, level); 304 entry = g_hash_table_lookup(s->iotlb, &key); 305 if (entry) { 306 goto out; 307 } 308 } 309 310 out: 311 return entry; 312 } 313 314 /* Must be with IOMMU lock held */ 315 static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, 316 uint16_t domain_id, hwaddr addr, uint64_t slpte, 317 uint8_t access_flags, uint32_t level) 318 { 319 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry)); 320 uint64_t *key = g_malloc(sizeof(*key)); 321 uint64_t gfn = vtd_get_iotlb_gfn(addr, level); 322 323 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id); 324 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) { 325 trace_vtd_iotlb_reset("iotlb exceeds size limit"); 326 vtd_reset_iotlb_locked(s); 327 } 328 329 entry->gfn = gfn; 330 entry->domain_id = domain_id; 331 entry->slpte = slpte; 332 entry->access_flags = access_flags; 333 entry->mask = vtd_slpt_level_page_mask(level); 334 *key = vtd_get_iotlb_key(gfn, source_id, level); 335 g_hash_table_replace(s->iotlb, key, entry); 336 } 337 338 /* Given the reg addr of both the message data and address, generate an 339 * interrupt via MSI. 340 */ 341 static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg, 342 hwaddr mesg_data_reg) 343 { 344 MSIMessage msi; 345 346 assert(mesg_data_reg < DMAR_REG_SIZE); 347 assert(mesg_addr_reg < DMAR_REG_SIZE); 348 349 msi.address = vtd_get_long_raw(s, mesg_addr_reg); 350 msi.data = vtd_get_long_raw(s, mesg_data_reg); 351 352 trace_vtd_irq_generate(msi.address, msi.data); 353 354 apic_get_class()->send_msi(&msi); 355 } 356 357 /* Generate a fault event to software via MSI if conditions are met. 358 * Notice that the value of FSTS_REG being passed to it should be the one 359 * before any update. 360 */ 361 static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts) 362 { 363 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO || 364 pre_fsts & VTD_FSTS_IQE) { 365 error_report_once("There are previous interrupt conditions " 366 "to be serviced by software, fault event " 367 "is not generated"); 368 return; 369 } 370 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP); 371 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) { 372 error_report_once("Interrupt Mask set, irq is not generated"); 373 } else { 374 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); 375 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 376 } 377 } 378 379 /* Check if the Fault (F) field of the Fault Recording Register referenced by 380 * @index is Set. 381 */ 382 static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index) 383 { 384 /* Each reg is 128-bit */ 385 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 386 addr += 8; /* Access the high 64-bit half */ 387 388 assert(index < DMAR_FRCD_REG_NR); 389 390 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F; 391 } 392 393 /* Update the PPF field of Fault Status Register. 394 * Should be called whenever change the F field of any fault recording 395 * registers. 396 */ 397 static void vtd_update_fsts_ppf(IntelIOMMUState *s) 398 { 399 uint32_t i; 400 uint32_t ppf_mask = 0; 401 402 for (i = 0; i < DMAR_FRCD_REG_NR; i++) { 403 if (vtd_is_frcd_set(s, i)) { 404 ppf_mask = VTD_FSTS_PPF; 405 break; 406 } 407 } 408 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask); 409 trace_vtd_fsts_ppf(!!ppf_mask); 410 } 411 412 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index) 413 { 414 /* Each reg is 128-bit */ 415 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 416 addr += 8; /* Access the high 64-bit half */ 417 418 assert(index < DMAR_FRCD_REG_NR); 419 420 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F); 421 vtd_update_fsts_ppf(s); 422 } 423 424 /* Must not update F field now, should be done later */ 425 static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index, 426 uint16_t source_id, hwaddr addr, 427 VTDFaultReason fault, bool is_write) 428 { 429 uint64_t hi = 0, lo; 430 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 431 432 assert(index < DMAR_FRCD_REG_NR); 433 434 lo = VTD_FRCD_FI(addr); 435 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault); 436 if (!is_write) { 437 hi |= VTD_FRCD_T; 438 } 439 vtd_set_quad_raw(s, frcd_reg_addr, lo); 440 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi); 441 442 trace_vtd_frr_new(index, hi, lo); 443 } 444 445 /* Try to collapse multiple pending faults from the same requester */ 446 static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id) 447 { 448 uint32_t i; 449 uint64_t frcd_reg; 450 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */ 451 452 for (i = 0; i < DMAR_FRCD_REG_NR; i++) { 453 frcd_reg = vtd_get_quad_raw(s, addr); 454 if ((frcd_reg & VTD_FRCD_F) && 455 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) { 456 return true; 457 } 458 addr += 16; /* 128-bit for each */ 459 } 460 return false; 461 } 462 463 /* Log and report an DMAR (address translation) fault to software */ 464 static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id, 465 hwaddr addr, VTDFaultReason fault, 466 bool is_write) 467 { 468 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 469 470 assert(fault < VTD_FR_MAX); 471 472 if (fault == VTD_FR_RESERVED_ERR) { 473 /* This is not a normal fault reason case. Drop it. */ 474 return; 475 } 476 477 trace_vtd_dmar_fault(source_id, fault, addr, is_write); 478 479 if (fsts_reg & VTD_FSTS_PFO) { 480 error_report_once("New fault is not recorded due to " 481 "Primary Fault Overflow"); 482 return; 483 } 484 485 if (vtd_try_collapse_fault(s, source_id)) { 486 error_report_once("New fault is not recorded due to " 487 "compression of faults"); 488 return; 489 } 490 491 if (vtd_is_frcd_set(s, s->next_frcd_reg)) { 492 error_report_once("Next Fault Recording Reg is used, " 493 "new fault is not recorded, set PFO field"); 494 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO); 495 return; 496 } 497 498 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write); 499 500 if (fsts_reg & VTD_FSTS_PPF) { 501 error_report_once("There are pending faults already, " 502 "fault event is not generated"); 503 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); 504 s->next_frcd_reg++; 505 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { 506 s->next_frcd_reg = 0; 507 } 508 } else { 509 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK, 510 VTD_FSTS_FRI(s->next_frcd_reg)); 511 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */ 512 s->next_frcd_reg++; 513 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { 514 s->next_frcd_reg = 0; 515 } 516 /* This case actually cause the PPF to be Set. 517 * So generate fault event (interrupt). 518 */ 519 vtd_generate_fault_event(s, fsts_reg); 520 } 521 } 522 523 /* Handle Invalidation Queue Errors of queued invalidation interface error 524 * conditions. 525 */ 526 static void vtd_handle_inv_queue_error(IntelIOMMUState *s) 527 { 528 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 529 530 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE); 531 vtd_generate_fault_event(s, fsts_reg); 532 } 533 534 /* Set the IWC field and try to generate an invalidation completion interrupt */ 535 static void vtd_generate_completion_event(IntelIOMMUState *s) 536 { 537 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) { 538 trace_vtd_inv_desc_wait_irq("One pending, skip current"); 539 return; 540 } 541 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC); 542 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP); 543 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) { 544 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, " 545 "new event not generated"); 546 return; 547 } else { 548 /* Generate the interrupt event */ 549 trace_vtd_inv_desc_wait_irq("Generating complete event"); 550 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); 551 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 552 } 553 } 554 555 static inline bool vtd_root_entry_present(IntelIOMMUState *s, 556 VTDRootEntry *re, 557 uint8_t devfn) 558 { 559 if (s->root_scalable && devfn > UINT8_MAX / 2) { 560 return re->hi & VTD_ROOT_ENTRY_P; 561 } 562 563 return re->lo & VTD_ROOT_ENTRY_P; 564 } 565 566 static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index, 567 VTDRootEntry *re) 568 { 569 dma_addr_t addr; 570 571 addr = s->root + index * sizeof(*re); 572 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) { 573 re->lo = 0; 574 return -VTD_FR_ROOT_TABLE_INV; 575 } 576 re->lo = le64_to_cpu(re->lo); 577 re->hi = le64_to_cpu(re->hi); 578 return 0; 579 } 580 581 static inline bool vtd_ce_present(VTDContextEntry *context) 582 { 583 return context->lo & VTD_CONTEXT_ENTRY_P; 584 } 585 586 static int vtd_get_context_entry_from_root(IntelIOMMUState *s, 587 VTDRootEntry *re, 588 uint8_t index, 589 VTDContextEntry *ce) 590 { 591 dma_addr_t addr, ce_size; 592 593 /* we have checked that root entry is present */ 594 ce_size = s->root_scalable ? VTD_CTX_ENTRY_SCALABLE_SIZE : 595 VTD_CTX_ENTRY_LEGACY_SIZE; 596 597 if (s->root_scalable && index > UINT8_MAX / 2) { 598 index = index & (~VTD_DEVFN_CHECK_MASK); 599 addr = re->hi & VTD_ROOT_ENTRY_CTP; 600 } else { 601 addr = re->lo & VTD_ROOT_ENTRY_CTP; 602 } 603 604 addr = addr + index * ce_size; 605 if (dma_memory_read(&address_space_memory, addr, ce, ce_size)) { 606 return -VTD_FR_CONTEXT_TABLE_INV; 607 } 608 609 ce->lo = le64_to_cpu(ce->lo); 610 ce->hi = le64_to_cpu(ce->hi); 611 if (ce_size == VTD_CTX_ENTRY_SCALABLE_SIZE) { 612 ce->val[2] = le64_to_cpu(ce->val[2]); 613 ce->val[3] = le64_to_cpu(ce->val[3]); 614 } 615 return 0; 616 } 617 618 static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce) 619 { 620 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; 621 } 622 623 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw) 624 { 625 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw); 626 } 627 628 /* Whether the pte indicates the address of the page frame */ 629 static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level) 630 { 631 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK); 632 } 633 634 /* Get the content of a spte located in @base_addr[@index] */ 635 static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index) 636 { 637 uint64_t slpte; 638 639 assert(index < VTD_SL_PT_ENTRY_NR); 640 641 if (dma_memory_read(&address_space_memory, 642 base_addr + index * sizeof(slpte), &slpte, 643 sizeof(slpte))) { 644 slpte = (uint64_t)-1; 645 return slpte; 646 } 647 slpte = le64_to_cpu(slpte); 648 return slpte; 649 } 650 651 /* Given an iova and the level of paging structure, return the offset 652 * of current level. 653 */ 654 static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level) 655 { 656 return (iova >> vtd_slpt_level_shift(level)) & 657 ((1ULL << VTD_SL_LEVEL_BITS) - 1); 658 } 659 660 /* Check Capability Register to see if the @level of page-table is supported */ 661 static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level) 662 { 663 return VTD_CAP_SAGAW_MASK & s->cap & 664 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); 665 } 666 667 /* Return true if check passed, otherwise false */ 668 static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu, 669 VTDPASIDEntry *pe) 670 { 671 switch (VTD_PE_GET_TYPE(pe)) { 672 case VTD_SM_PASID_ENTRY_FLT: 673 case VTD_SM_PASID_ENTRY_SLT: 674 case VTD_SM_PASID_ENTRY_NESTED: 675 break; 676 case VTD_SM_PASID_ENTRY_PT: 677 if (!x86_iommu->pt_supported) { 678 return false; 679 } 680 break; 681 default: 682 /* Unknown type */ 683 return false; 684 } 685 return true; 686 } 687 688 static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) 689 { 690 return pdire->val & 1; 691 } 692 693 /** 694 * Caller of this function should check present bit if wants 695 * to use pdir entry for further usage except for fpd bit check. 696 */ 697 static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, 698 uint32_t pasid, 699 VTDPASIDDirEntry *pdire) 700 { 701 uint32_t index; 702 dma_addr_t addr, entry_size; 703 704 index = VTD_PASID_DIR_INDEX(pasid); 705 entry_size = VTD_PASID_DIR_ENTRY_SIZE; 706 addr = pasid_dir_base + index * entry_size; 707 if (dma_memory_read(&address_space_memory, addr, pdire, entry_size)) { 708 return -VTD_FR_PASID_TABLE_INV; 709 } 710 711 return 0; 712 } 713 714 static inline bool vtd_pe_present(VTDPASIDEntry *pe) 715 { 716 return pe->val[0] & VTD_PASID_ENTRY_P; 717 } 718 719 static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, 720 uint32_t pasid, 721 dma_addr_t addr, 722 VTDPASIDEntry *pe) 723 { 724 uint32_t index; 725 dma_addr_t entry_size; 726 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 727 728 index = VTD_PASID_TABLE_INDEX(pasid); 729 entry_size = VTD_PASID_ENTRY_SIZE; 730 addr = addr + index * entry_size; 731 if (dma_memory_read(&address_space_memory, addr, pe, entry_size)) { 732 return -VTD_FR_PASID_TABLE_INV; 733 } 734 735 /* Do translation type check */ 736 if (!vtd_pe_type_check(x86_iommu, pe)) { 737 return -VTD_FR_PASID_TABLE_INV; 738 } 739 740 if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { 741 return -VTD_FR_PASID_TABLE_INV; 742 } 743 744 return 0; 745 } 746 747 /** 748 * Caller of this function should check present bit if wants 749 * to use pasid entry for further usage except for fpd bit check. 750 */ 751 static int vtd_get_pe_from_pdire(IntelIOMMUState *s, 752 uint32_t pasid, 753 VTDPASIDDirEntry *pdire, 754 VTDPASIDEntry *pe) 755 { 756 dma_addr_t addr = pdire->val & VTD_PASID_TABLE_BASE_ADDR_MASK; 757 758 return vtd_get_pe_in_pasid_leaf_table(s, pasid, addr, pe); 759 } 760 761 /** 762 * This function gets a pasid entry from a specified pasid 763 * table (includes dir and leaf table) with a specified pasid. 764 * Sanity check should be done to ensure return a present 765 * pasid entry to caller. 766 */ 767 static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s, 768 dma_addr_t pasid_dir_base, 769 uint32_t pasid, 770 VTDPASIDEntry *pe) 771 { 772 int ret; 773 VTDPASIDDirEntry pdire; 774 775 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, 776 pasid, &pdire); 777 if (ret) { 778 return ret; 779 } 780 781 if (!vtd_pdire_present(&pdire)) { 782 return -VTD_FR_PASID_TABLE_INV; 783 } 784 785 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe); 786 if (ret) { 787 return ret; 788 } 789 790 if (!vtd_pe_present(pe)) { 791 return -VTD_FR_PASID_TABLE_INV; 792 } 793 794 return 0; 795 } 796 797 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, 798 VTDContextEntry *ce, 799 VTDPASIDEntry *pe) 800 { 801 uint32_t pasid; 802 dma_addr_t pasid_dir_base; 803 int ret = 0; 804 805 pasid = VTD_CE_GET_RID2PASID(ce); 806 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce); 807 ret = vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); 808 809 return ret; 810 } 811 812 static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, 813 VTDContextEntry *ce, 814 bool *pe_fpd_set) 815 { 816 int ret; 817 uint32_t pasid; 818 dma_addr_t pasid_dir_base; 819 VTDPASIDDirEntry pdire; 820 VTDPASIDEntry pe; 821 822 pasid = VTD_CE_GET_RID2PASID(ce); 823 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce); 824 825 /* 826 * No present bit check since fpd is meaningful even 827 * if the present bit is clear. 828 */ 829 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, pasid, &pdire); 830 if (ret) { 831 return ret; 832 } 833 834 if (pdire.val & VTD_PASID_DIR_FPD) { 835 *pe_fpd_set = true; 836 return 0; 837 } 838 839 if (!vtd_pdire_present(&pdire)) { 840 return -VTD_FR_PASID_TABLE_INV; 841 } 842 843 /* 844 * No present bit check since fpd is meaningful even 845 * if the present bit is clear. 846 */ 847 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, &pe); 848 if (ret) { 849 return ret; 850 } 851 852 if (pe.val[0] & VTD_PASID_ENTRY_FPD) { 853 *pe_fpd_set = true; 854 } 855 856 return 0; 857 } 858 859 /* Get the page-table level that hardware should use for the second-level 860 * page-table walk from the Address Width field of context-entry. 861 */ 862 static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce) 863 { 864 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW); 865 } 866 867 static uint32_t vtd_get_iova_level(IntelIOMMUState *s, 868 VTDContextEntry *ce) 869 { 870 VTDPASIDEntry pe; 871 872 if (s->root_scalable) { 873 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 874 return VTD_PE_GET_LEVEL(&pe); 875 } 876 877 return vtd_ce_get_level(ce); 878 } 879 880 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce) 881 { 882 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; 883 } 884 885 static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, 886 VTDContextEntry *ce) 887 { 888 VTDPASIDEntry pe; 889 890 if (s->root_scalable) { 891 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 892 return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; 893 } 894 895 return vtd_ce_get_agaw(ce); 896 } 897 898 static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce) 899 { 900 return ce->lo & VTD_CONTEXT_ENTRY_TT; 901 } 902 903 /* Only for Legacy Mode. Return true if check passed, otherwise false */ 904 static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu, 905 VTDContextEntry *ce) 906 { 907 switch (vtd_ce_get_type(ce)) { 908 case VTD_CONTEXT_TT_MULTI_LEVEL: 909 /* Always supported */ 910 break; 911 case VTD_CONTEXT_TT_DEV_IOTLB: 912 if (!x86_iommu->dt_supported) { 913 error_report_once("%s: DT specified but not supported", __func__); 914 return false; 915 } 916 break; 917 case VTD_CONTEXT_TT_PASS_THROUGH: 918 if (!x86_iommu->pt_supported) { 919 error_report_once("%s: PT specified but not supported", __func__); 920 return false; 921 } 922 break; 923 default: 924 /* Unknown type */ 925 error_report_once("%s: unknown ce type: %"PRIu32, __func__, 926 vtd_ce_get_type(ce)); 927 return false; 928 } 929 return true; 930 } 931 932 static inline uint64_t vtd_iova_limit(IntelIOMMUState *s, 933 VTDContextEntry *ce, uint8_t aw) 934 { 935 uint32_t ce_agaw = vtd_get_iova_agaw(s, ce); 936 return 1ULL << MIN(ce_agaw, aw); 937 } 938 939 /* Return true if IOVA passes range check, otherwise false. */ 940 static inline bool vtd_iova_range_check(IntelIOMMUState *s, 941 uint64_t iova, VTDContextEntry *ce, 942 uint8_t aw) 943 { 944 /* 945 * Check if @iova is above 2^X-1, where X is the minimum of MGAW 946 * in CAP_REG and AW in context-entry. 947 */ 948 return !(iova & ~(vtd_iova_limit(s, ce, aw) - 1)); 949 } 950 951 static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, 952 VTDContextEntry *ce) 953 { 954 VTDPASIDEntry pe; 955 956 if (s->root_scalable) { 957 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 958 return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; 959 } 960 961 return vtd_ce_get_slpt_base(ce); 962 } 963 964 /* 965 * Rsvd field masks for spte: 966 * vtd_spte_rsvd 4k pages 967 * vtd_spte_rsvd_large large pages 968 */ 969 static uint64_t vtd_spte_rsvd[5]; 970 static uint64_t vtd_spte_rsvd_large[5]; 971 972 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) 973 { 974 uint64_t rsvd_mask = vtd_spte_rsvd[level]; 975 976 if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) && 977 (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { 978 /* large page */ 979 rsvd_mask = vtd_spte_rsvd_large[level]; 980 } 981 982 return slpte & rsvd_mask; 983 } 984 985 /* Find the VTD address space associated with a given bus number */ 986 static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num) 987 { 988 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num]; 989 GHashTableIter iter; 990 991 if (vtd_bus) { 992 return vtd_bus; 993 } 994 995 /* 996 * Iterate over the registered buses to find the one which 997 * currently holds this bus number and update the bus_num 998 * lookup table. 999 */ 1000 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); 1001 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { 1002 if (pci_bus_num(vtd_bus->bus) == bus_num) { 1003 s->vtd_as_by_bus_num[bus_num] = vtd_bus; 1004 return vtd_bus; 1005 } 1006 } 1007 1008 return NULL; 1009 } 1010 1011 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level 1012 * of the translation, can be used for deciding the size of large page. 1013 */ 1014 static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce, 1015 uint64_t iova, bool is_write, 1016 uint64_t *slptep, uint32_t *slpte_level, 1017 bool *reads, bool *writes, uint8_t aw_bits) 1018 { 1019 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce); 1020 uint32_t level = vtd_get_iova_level(s, ce); 1021 uint32_t offset; 1022 uint64_t slpte; 1023 uint64_t access_right_check; 1024 1025 if (!vtd_iova_range_check(s, iova, ce, aw_bits)) { 1026 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ")", 1027 __func__, iova); 1028 return -VTD_FR_ADDR_BEYOND_MGAW; 1029 } 1030 1031 /* FIXME: what is the Atomics request here? */ 1032 access_right_check = is_write ? VTD_SL_W : VTD_SL_R; 1033 1034 while (true) { 1035 offset = vtd_iova_level_offset(iova, level); 1036 slpte = vtd_get_slpte(addr, offset); 1037 1038 if (slpte == (uint64_t)-1) { 1039 error_report_once("%s: detected read error on DMAR slpte " 1040 "(iova=0x%" PRIx64 ")", __func__, iova); 1041 if (level == vtd_get_iova_level(s, ce)) { 1042 /* Invalid programming of context-entry */ 1043 return -VTD_FR_CONTEXT_ENTRY_INV; 1044 } else { 1045 return -VTD_FR_PAGING_ENTRY_INV; 1046 } 1047 } 1048 *reads = (*reads) && (slpte & VTD_SL_R); 1049 *writes = (*writes) && (slpte & VTD_SL_W); 1050 if (!(slpte & access_right_check)) { 1051 error_report_once("%s: detected slpte permission error " 1052 "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", " 1053 "slpte=0x%" PRIx64 ", write=%d)", __func__, 1054 iova, level, slpte, is_write); 1055 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; 1056 } 1057 if (vtd_slpte_nonzero_rsvd(slpte, level)) { 1058 error_report_once("%s: detected splte reserve non-zero " 1059 "iova=0x%" PRIx64 ", level=0x%" PRIx32 1060 "slpte=0x%" PRIx64 ")", __func__, iova, 1061 level, slpte); 1062 return -VTD_FR_PAGING_ENTRY_RSVD; 1063 } 1064 1065 if (vtd_is_last_slpte(slpte, level)) { 1066 *slptep = slpte; 1067 *slpte_level = level; 1068 return 0; 1069 } 1070 addr = vtd_get_slpte_addr(slpte, aw_bits); 1071 level--; 1072 } 1073 } 1074 1075 typedef int (*vtd_page_walk_hook)(IOMMUTLBEvent *event, void *private); 1076 1077 /** 1078 * Constant information used during page walking 1079 * 1080 * @hook_fn: hook func to be called when detected page 1081 * @private: private data to be passed into hook func 1082 * @notify_unmap: whether we should notify invalid entries 1083 * @as: VT-d address space of the device 1084 * @aw: maximum address width 1085 * @domain: domain ID of the page walk 1086 */ 1087 typedef struct { 1088 VTDAddressSpace *as; 1089 vtd_page_walk_hook hook_fn; 1090 void *private; 1091 bool notify_unmap; 1092 uint8_t aw; 1093 uint16_t domain_id; 1094 } vtd_page_walk_info; 1095 1096 static int vtd_page_walk_one(IOMMUTLBEvent *event, vtd_page_walk_info *info) 1097 { 1098 VTDAddressSpace *as = info->as; 1099 vtd_page_walk_hook hook_fn = info->hook_fn; 1100 void *private = info->private; 1101 IOMMUTLBEntry *entry = &event->entry; 1102 DMAMap target = { 1103 .iova = entry->iova, 1104 .size = entry->addr_mask, 1105 .translated_addr = entry->translated_addr, 1106 .perm = entry->perm, 1107 }; 1108 DMAMap *mapped = iova_tree_find(as->iova_tree, &target); 1109 1110 if (event->type == IOMMU_NOTIFIER_UNMAP && !info->notify_unmap) { 1111 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask); 1112 return 0; 1113 } 1114 1115 assert(hook_fn); 1116 1117 /* Update local IOVA mapped ranges */ 1118 if (event->type == IOMMU_NOTIFIER_MAP) { 1119 if (mapped) { 1120 /* If it's exactly the same translation, skip */ 1121 if (!memcmp(mapped, &target, sizeof(target))) { 1122 trace_vtd_page_walk_one_skip_map(entry->iova, entry->addr_mask, 1123 entry->translated_addr); 1124 return 0; 1125 } else { 1126 /* 1127 * Translation changed. Normally this should not 1128 * happen, but it can happen when with buggy guest 1129 * OSes. Note that there will be a small window that 1130 * we don't have map at all. But that's the best 1131 * effort we can do. The ideal way to emulate this is 1132 * atomically modify the PTE to follow what has 1133 * changed, but we can't. One example is that vfio 1134 * driver only has VFIO_IOMMU_[UN]MAP_DMA but no 1135 * interface to modify a mapping (meanwhile it seems 1136 * meaningless to even provide one). Anyway, let's 1137 * mark this as a TODO in case one day we'll have 1138 * a better solution. 1139 */ 1140 IOMMUAccessFlags cache_perm = entry->perm; 1141 int ret; 1142 1143 /* Emulate an UNMAP */ 1144 event->type = IOMMU_NOTIFIER_UNMAP; 1145 entry->perm = IOMMU_NONE; 1146 trace_vtd_page_walk_one(info->domain_id, 1147 entry->iova, 1148 entry->translated_addr, 1149 entry->addr_mask, 1150 entry->perm); 1151 ret = hook_fn(event, private); 1152 if (ret) { 1153 return ret; 1154 } 1155 /* Drop any existing mapping */ 1156 iova_tree_remove(as->iova_tree, &target); 1157 /* Recover the correct type */ 1158 event->type = IOMMU_NOTIFIER_MAP; 1159 entry->perm = cache_perm; 1160 } 1161 } 1162 iova_tree_insert(as->iova_tree, &target); 1163 } else { 1164 if (!mapped) { 1165 /* Skip since we didn't map this range at all */ 1166 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask); 1167 return 0; 1168 } 1169 iova_tree_remove(as->iova_tree, &target); 1170 } 1171 1172 trace_vtd_page_walk_one(info->domain_id, entry->iova, 1173 entry->translated_addr, entry->addr_mask, 1174 entry->perm); 1175 return hook_fn(event, private); 1176 } 1177 1178 /** 1179 * vtd_page_walk_level - walk over specific level for IOVA range 1180 * 1181 * @addr: base GPA addr to start the walk 1182 * @start: IOVA range start address 1183 * @end: IOVA range end address (start <= addr < end) 1184 * @read: whether parent level has read permission 1185 * @write: whether parent level has write permission 1186 * @info: constant information for the page walk 1187 */ 1188 static int vtd_page_walk_level(dma_addr_t addr, uint64_t start, 1189 uint64_t end, uint32_t level, bool read, 1190 bool write, vtd_page_walk_info *info) 1191 { 1192 bool read_cur, write_cur, entry_valid; 1193 uint32_t offset; 1194 uint64_t slpte; 1195 uint64_t subpage_size, subpage_mask; 1196 IOMMUTLBEvent event; 1197 uint64_t iova = start; 1198 uint64_t iova_next; 1199 int ret = 0; 1200 1201 trace_vtd_page_walk_level(addr, level, start, end); 1202 1203 subpage_size = 1ULL << vtd_slpt_level_shift(level); 1204 subpage_mask = vtd_slpt_level_page_mask(level); 1205 1206 while (iova < end) { 1207 iova_next = (iova & subpage_mask) + subpage_size; 1208 1209 offset = vtd_iova_level_offset(iova, level); 1210 slpte = vtd_get_slpte(addr, offset); 1211 1212 if (slpte == (uint64_t)-1) { 1213 trace_vtd_page_walk_skip_read(iova, iova_next); 1214 goto next; 1215 } 1216 1217 if (vtd_slpte_nonzero_rsvd(slpte, level)) { 1218 trace_vtd_page_walk_skip_reserve(iova, iova_next); 1219 goto next; 1220 } 1221 1222 /* Permissions are stacked with parents' */ 1223 read_cur = read && (slpte & VTD_SL_R); 1224 write_cur = write && (slpte & VTD_SL_W); 1225 1226 /* 1227 * As long as we have either read/write permission, this is a 1228 * valid entry. The rule works for both page entries and page 1229 * table entries. 1230 */ 1231 entry_valid = read_cur | write_cur; 1232 1233 if (!vtd_is_last_slpte(slpte, level) && entry_valid) { 1234 /* 1235 * This is a valid PDE (or even bigger than PDE). We need 1236 * to walk one further level. 1237 */ 1238 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw), 1239 iova, MIN(iova_next, end), level - 1, 1240 read_cur, write_cur, info); 1241 } else { 1242 /* 1243 * This means we are either: 1244 * 1245 * (1) the real page entry (either 4K page, or huge page) 1246 * (2) the whole range is invalid 1247 * 1248 * In either case, we send an IOTLB notification down. 1249 */ 1250 event.entry.target_as = &address_space_memory; 1251 event.entry.iova = iova & subpage_mask; 1252 event.entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); 1253 event.entry.addr_mask = ~subpage_mask; 1254 /* NOTE: this is only meaningful if entry_valid == true */ 1255 event.entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw); 1256 event.type = event.entry.perm ? IOMMU_NOTIFIER_MAP : 1257 IOMMU_NOTIFIER_UNMAP; 1258 ret = vtd_page_walk_one(&event, info); 1259 } 1260 1261 if (ret < 0) { 1262 return ret; 1263 } 1264 1265 next: 1266 iova = iova_next; 1267 } 1268 1269 return 0; 1270 } 1271 1272 /** 1273 * vtd_page_walk - walk specific IOVA range, and call the hook 1274 * 1275 * @s: intel iommu state 1276 * @ce: context entry to walk upon 1277 * @start: IOVA address to start the walk 1278 * @end: IOVA range end address (start <= addr < end) 1279 * @info: page walking information struct 1280 */ 1281 static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce, 1282 uint64_t start, uint64_t end, 1283 vtd_page_walk_info *info) 1284 { 1285 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce); 1286 uint32_t level = vtd_get_iova_level(s, ce); 1287 1288 if (!vtd_iova_range_check(s, start, ce, info->aw)) { 1289 return -VTD_FR_ADDR_BEYOND_MGAW; 1290 } 1291 1292 if (!vtd_iova_range_check(s, end, ce, info->aw)) { 1293 /* Fix end so that it reaches the maximum */ 1294 end = vtd_iova_limit(s, ce, info->aw); 1295 } 1296 1297 return vtd_page_walk_level(addr, start, end, level, true, true, info); 1298 } 1299 1300 static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState *s, 1301 VTDRootEntry *re) 1302 { 1303 /* Legacy Mode reserved bits check */ 1304 if (!s->root_scalable && 1305 (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) 1306 goto rsvd_err; 1307 1308 /* Scalable Mode reserved bits check */ 1309 if (s->root_scalable && 1310 ((re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)) || 1311 (re->hi & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) 1312 goto rsvd_err; 1313 1314 return 0; 1315 1316 rsvd_err: 1317 error_report_once("%s: invalid root entry: hi=0x%"PRIx64 1318 ", lo=0x%"PRIx64, 1319 __func__, re->hi, re->lo); 1320 return -VTD_FR_ROOT_ENTRY_RSVD; 1321 } 1322 1323 static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState *s, 1324 VTDContextEntry *ce) 1325 { 1326 if (!s->root_scalable && 1327 (ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI || 1328 ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) { 1329 error_report_once("%s: invalid context entry: hi=%"PRIx64 1330 ", lo=%"PRIx64" (reserved nonzero)", 1331 __func__, ce->hi, ce->lo); 1332 return -VTD_FR_CONTEXT_ENTRY_RSVD; 1333 } 1334 1335 if (s->root_scalable && 1336 (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s->aw_bits) || 1337 ce->val[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 || 1338 ce->val[2] || 1339 ce->val[3])) { 1340 error_report_once("%s: invalid context entry: val[3]=%"PRIx64 1341 ", val[2]=%"PRIx64 1342 ", val[1]=%"PRIx64 1343 ", val[0]=%"PRIx64" (reserved nonzero)", 1344 __func__, ce->val[3], ce->val[2], 1345 ce->val[1], ce->val[0]); 1346 return -VTD_FR_CONTEXT_ENTRY_RSVD; 1347 } 1348 1349 return 0; 1350 } 1351 1352 static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, 1353 VTDContextEntry *ce) 1354 { 1355 VTDPASIDEntry pe; 1356 1357 /* 1358 * Make sure in Scalable Mode, a present context entry 1359 * has valid rid2pasid setting, which includes valid 1360 * rid2pasid field and corresponding pasid entry setting 1361 */ 1362 return vtd_ce_get_rid2pasid_entry(s, ce, &pe); 1363 } 1364 1365 /* Map a device to its corresponding domain (context-entry) */ 1366 static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, 1367 uint8_t devfn, VTDContextEntry *ce) 1368 { 1369 VTDRootEntry re; 1370 int ret_fr; 1371 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 1372 1373 ret_fr = vtd_get_root_entry(s, bus_num, &re); 1374 if (ret_fr) { 1375 return ret_fr; 1376 } 1377 1378 if (!vtd_root_entry_present(s, &re, devfn)) { 1379 /* Not error - it's okay we don't have root entry. */ 1380 trace_vtd_re_not_present(bus_num); 1381 return -VTD_FR_ROOT_ENTRY_P; 1382 } 1383 1384 ret_fr = vtd_root_entry_rsvd_bits_check(s, &re); 1385 if (ret_fr) { 1386 return ret_fr; 1387 } 1388 1389 ret_fr = vtd_get_context_entry_from_root(s, &re, devfn, ce); 1390 if (ret_fr) { 1391 return ret_fr; 1392 } 1393 1394 if (!vtd_ce_present(ce)) { 1395 /* Not error - it's okay we don't have context entry. */ 1396 trace_vtd_ce_not_present(bus_num, devfn); 1397 return -VTD_FR_CONTEXT_ENTRY_P; 1398 } 1399 1400 ret_fr = vtd_context_entry_rsvd_bits_check(s, ce); 1401 if (ret_fr) { 1402 return ret_fr; 1403 } 1404 1405 /* Check if the programming of context-entry is valid */ 1406 if (!s->root_scalable && 1407 !vtd_is_level_supported(s, vtd_ce_get_level(ce))) { 1408 error_report_once("%s: invalid context entry: hi=%"PRIx64 1409 ", lo=%"PRIx64" (level %d not supported)", 1410 __func__, ce->hi, ce->lo, 1411 vtd_ce_get_level(ce)); 1412 return -VTD_FR_CONTEXT_ENTRY_INV; 1413 } 1414 1415 if (!s->root_scalable) { 1416 /* Do translation type check */ 1417 if (!vtd_ce_type_check(x86_iommu, ce)) { 1418 /* Errors dumped in vtd_ce_type_check() */ 1419 return -VTD_FR_CONTEXT_ENTRY_INV; 1420 } 1421 } else { 1422 /* 1423 * Check if the programming of context-entry.rid2pasid 1424 * and corresponding pasid setting is valid, and thus 1425 * avoids to check pasid entry fetching result in future 1426 * helper function calling. 1427 */ 1428 ret_fr = vtd_ce_rid2pasid_check(s, ce); 1429 if (ret_fr) { 1430 return ret_fr; 1431 } 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int vtd_sync_shadow_page_hook(IOMMUTLBEvent *event, 1438 void *private) 1439 { 1440 memory_region_notify_iommu(private, 0, *event); 1441 return 0; 1442 } 1443 1444 static uint16_t vtd_get_domain_id(IntelIOMMUState *s, 1445 VTDContextEntry *ce) 1446 { 1447 VTDPASIDEntry pe; 1448 1449 if (s->root_scalable) { 1450 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 1451 return VTD_SM_PASID_ENTRY_DID(pe.val[1]); 1452 } 1453 1454 return VTD_CONTEXT_ENTRY_DID(ce->hi); 1455 } 1456 1457 static int vtd_sync_shadow_page_table_range(VTDAddressSpace *vtd_as, 1458 VTDContextEntry *ce, 1459 hwaddr addr, hwaddr size) 1460 { 1461 IntelIOMMUState *s = vtd_as->iommu_state; 1462 vtd_page_walk_info info = { 1463 .hook_fn = vtd_sync_shadow_page_hook, 1464 .private = (void *)&vtd_as->iommu, 1465 .notify_unmap = true, 1466 .aw = s->aw_bits, 1467 .as = vtd_as, 1468 .domain_id = vtd_get_domain_id(s, ce), 1469 }; 1470 1471 return vtd_page_walk(s, ce, addr, addr + size, &info); 1472 } 1473 1474 static int vtd_sync_shadow_page_table(VTDAddressSpace *vtd_as) 1475 { 1476 int ret; 1477 VTDContextEntry ce; 1478 IOMMUNotifier *n; 1479 1480 if (!(vtd_as->iommu.iommu_notify_flags & IOMMU_NOTIFIER_IOTLB_EVENTS)) { 1481 return 0; 1482 } 1483 1484 ret = vtd_dev_to_context_entry(vtd_as->iommu_state, 1485 pci_bus_num(vtd_as->bus), 1486 vtd_as->devfn, &ce); 1487 if (ret) { 1488 if (ret == -VTD_FR_CONTEXT_ENTRY_P) { 1489 /* 1490 * It's a valid scenario to have a context entry that is 1491 * not present. For example, when a device is removed 1492 * from an existing domain then the context entry will be 1493 * zeroed by the guest before it was put into another 1494 * domain. When this happens, instead of synchronizing 1495 * the shadow pages we should invalidate all existing 1496 * mappings and notify the backends. 1497 */ 1498 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) { 1499 vtd_address_space_unmap(vtd_as, n); 1500 } 1501 ret = 0; 1502 } 1503 return ret; 1504 } 1505 1506 return vtd_sync_shadow_page_table_range(vtd_as, &ce, 0, UINT64_MAX); 1507 } 1508 1509 /* 1510 * Check if specific device is configured to bypass address 1511 * translation for DMA requests. In Scalable Mode, bypass 1512 * 1st-level translation or 2nd-level translation, it depends 1513 * on PGTT setting. 1514 */ 1515 static bool vtd_dev_pt_enabled(VTDAddressSpace *as) 1516 { 1517 IntelIOMMUState *s; 1518 VTDContextEntry ce; 1519 VTDPASIDEntry pe; 1520 int ret; 1521 1522 assert(as); 1523 1524 s = as->iommu_state; 1525 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus), 1526 as->devfn, &ce); 1527 if (ret) { 1528 /* 1529 * Possibly failed to parse the context entry for some reason 1530 * (e.g., during init, or any guest configuration errors on 1531 * context entries). We should assume PT not enabled for 1532 * safety. 1533 */ 1534 return false; 1535 } 1536 1537 if (s->root_scalable) { 1538 ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe); 1539 if (ret) { 1540 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32, 1541 __func__, ret); 1542 return false; 1543 } 1544 return (VTD_PE_GET_TYPE(&pe) == VTD_SM_PASID_ENTRY_PT); 1545 } 1546 1547 return (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH); 1548 } 1549 1550 /* Return whether the device is using IOMMU translation. */ 1551 static bool vtd_switch_address_space(VTDAddressSpace *as) 1552 { 1553 bool use_iommu; 1554 /* Whether we need to take the BQL on our own */ 1555 bool take_bql = !qemu_mutex_iothread_locked(); 1556 1557 assert(as); 1558 1559 use_iommu = as->iommu_state->dmar_enabled && !vtd_dev_pt_enabled(as); 1560 1561 trace_vtd_switch_address_space(pci_bus_num(as->bus), 1562 VTD_PCI_SLOT(as->devfn), 1563 VTD_PCI_FUNC(as->devfn), 1564 use_iommu); 1565 1566 /* 1567 * It's possible that we reach here without BQL, e.g., when called 1568 * from vtd_pt_enable_fast_path(). However the memory APIs need 1569 * it. We'd better make sure we have had it already, or, take it. 1570 */ 1571 if (take_bql) { 1572 qemu_mutex_lock_iothread(); 1573 } 1574 1575 /* Turn off first then on the other */ 1576 if (use_iommu) { 1577 memory_region_set_enabled(&as->nodmar, false); 1578 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true); 1579 } else { 1580 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false); 1581 memory_region_set_enabled(&as->nodmar, true); 1582 } 1583 1584 if (take_bql) { 1585 qemu_mutex_unlock_iothread(); 1586 } 1587 1588 return use_iommu; 1589 } 1590 1591 static void vtd_switch_address_space_all(IntelIOMMUState *s) 1592 { 1593 GHashTableIter iter; 1594 VTDBus *vtd_bus; 1595 int i; 1596 1597 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); 1598 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { 1599 for (i = 0; i < PCI_DEVFN_MAX; i++) { 1600 if (!vtd_bus->dev_as[i]) { 1601 continue; 1602 } 1603 vtd_switch_address_space(vtd_bus->dev_as[i]); 1604 } 1605 } 1606 } 1607 1608 static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) 1609 { 1610 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); 1611 } 1612 1613 static const bool vtd_qualified_faults[] = { 1614 [VTD_FR_RESERVED] = false, 1615 [VTD_FR_ROOT_ENTRY_P] = false, 1616 [VTD_FR_CONTEXT_ENTRY_P] = true, 1617 [VTD_FR_CONTEXT_ENTRY_INV] = true, 1618 [VTD_FR_ADDR_BEYOND_MGAW] = true, 1619 [VTD_FR_WRITE] = true, 1620 [VTD_FR_READ] = true, 1621 [VTD_FR_PAGING_ENTRY_INV] = true, 1622 [VTD_FR_ROOT_TABLE_INV] = false, 1623 [VTD_FR_CONTEXT_TABLE_INV] = false, 1624 [VTD_FR_ROOT_ENTRY_RSVD] = false, 1625 [VTD_FR_PAGING_ENTRY_RSVD] = true, 1626 [VTD_FR_CONTEXT_ENTRY_TT] = true, 1627 [VTD_FR_PASID_TABLE_INV] = false, 1628 [VTD_FR_RESERVED_ERR] = false, 1629 [VTD_FR_MAX] = false, 1630 }; 1631 1632 /* To see if a fault condition is "qualified", which is reported to software 1633 * only if the FPD field in the context-entry used to process the faulting 1634 * request is 0. 1635 */ 1636 static inline bool vtd_is_qualified_fault(VTDFaultReason fault) 1637 { 1638 return vtd_qualified_faults[fault]; 1639 } 1640 1641 static inline bool vtd_is_interrupt_addr(hwaddr addr) 1642 { 1643 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST; 1644 } 1645 1646 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) 1647 { 1648 VTDBus *vtd_bus; 1649 VTDAddressSpace *vtd_as; 1650 bool success = false; 1651 1652 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id)); 1653 if (!vtd_bus) { 1654 goto out; 1655 } 1656 1657 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)]; 1658 if (!vtd_as) { 1659 goto out; 1660 } 1661 1662 if (vtd_switch_address_space(vtd_as) == false) { 1663 /* We switched off IOMMU region successfully. */ 1664 success = true; 1665 } 1666 1667 out: 1668 trace_vtd_pt_enable_fast_path(source_id, success); 1669 } 1670 1671 /* Map dev to context-entry then do a paging-structures walk to do a iommu 1672 * translation. 1673 * 1674 * Called from RCU critical section. 1675 * 1676 * @bus_num: The bus number 1677 * @devfn: The devfn, which is the combined of device and function number 1678 * @is_write: The access is a write operation 1679 * @entry: IOMMUTLBEntry that contain the addr to be translated and result 1680 * 1681 * Returns true if translation is successful, otherwise false. 1682 */ 1683 static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 1684 uint8_t devfn, hwaddr addr, bool is_write, 1685 IOMMUTLBEntry *entry) 1686 { 1687 IntelIOMMUState *s = vtd_as->iommu_state; 1688 VTDContextEntry ce; 1689 uint8_t bus_num = pci_bus_num(bus); 1690 VTDContextCacheEntry *cc_entry; 1691 uint64_t slpte, page_mask; 1692 uint32_t level; 1693 uint16_t source_id = vtd_make_source_id(bus_num, devfn); 1694 int ret_fr; 1695 bool is_fpd_set = false; 1696 bool reads = true; 1697 bool writes = true; 1698 uint8_t access_flags; 1699 VTDIOTLBEntry *iotlb_entry; 1700 1701 /* 1702 * We have standalone memory region for interrupt addresses, we 1703 * should never receive translation requests in this region. 1704 */ 1705 assert(!vtd_is_interrupt_addr(addr)); 1706 1707 vtd_iommu_lock(s); 1708 1709 cc_entry = &vtd_as->context_cache_entry; 1710 1711 /* Try to fetch slpte form IOTLB */ 1712 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr); 1713 if (iotlb_entry) { 1714 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, 1715 iotlb_entry->domain_id); 1716 slpte = iotlb_entry->slpte; 1717 access_flags = iotlb_entry->access_flags; 1718 page_mask = iotlb_entry->mask; 1719 goto out; 1720 } 1721 1722 /* Try to fetch context-entry from cache first */ 1723 if (cc_entry->context_cache_gen == s->context_cache_gen) { 1724 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi, 1725 cc_entry->context_entry.lo, 1726 cc_entry->context_cache_gen); 1727 ce = cc_entry->context_entry; 1728 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; 1729 if (!is_fpd_set && s->root_scalable) { 1730 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); 1731 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1732 } 1733 } else { 1734 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce); 1735 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; 1736 if (!ret_fr && !is_fpd_set && s->root_scalable) { 1737 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); 1738 } 1739 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1740 /* Update context-cache */ 1741 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo, 1742 cc_entry->context_cache_gen, 1743 s->context_cache_gen); 1744 cc_entry->context_entry = ce; 1745 cc_entry->context_cache_gen = s->context_cache_gen; 1746 } 1747 1748 /* 1749 * We don't need to translate for pass-through context entries. 1750 * Also, let's ignore IOTLB caching as well for PT devices. 1751 */ 1752 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) { 1753 entry->iova = addr & VTD_PAGE_MASK_4K; 1754 entry->translated_addr = entry->iova; 1755 entry->addr_mask = ~VTD_PAGE_MASK_4K; 1756 entry->perm = IOMMU_RW; 1757 trace_vtd_translate_pt(source_id, entry->iova); 1758 1759 /* 1760 * When this happens, it means firstly caching-mode is not 1761 * enabled, and this is the first passthrough translation for 1762 * the device. Let's enable the fast path for passthrough. 1763 * 1764 * When passthrough is disabled again for the device, we can 1765 * capture it via the context entry invalidation, then the 1766 * IOMMU region can be swapped back. 1767 */ 1768 vtd_pt_enable_fast_path(s, source_id); 1769 vtd_iommu_unlock(s); 1770 return true; 1771 } 1772 1773 ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, 1774 &reads, &writes, s->aw_bits); 1775 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1776 1777 page_mask = vtd_slpt_level_page_mask(level); 1778 access_flags = IOMMU_ACCESS_FLAG(reads, writes); 1779 vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce), addr, slpte, 1780 access_flags, level); 1781 out: 1782 vtd_iommu_unlock(s); 1783 entry->iova = addr & page_mask; 1784 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask; 1785 entry->addr_mask = ~page_mask; 1786 entry->perm = access_flags; 1787 return true; 1788 1789 error: 1790 vtd_iommu_unlock(s); 1791 entry->iova = 0; 1792 entry->translated_addr = 0; 1793 entry->addr_mask = 0; 1794 entry->perm = IOMMU_NONE; 1795 return false; 1796 } 1797 1798 static void vtd_root_table_setup(IntelIOMMUState *s) 1799 { 1800 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 1801 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits); 1802 1803 vtd_update_scalable_state(s); 1804 1805 trace_vtd_reg_dmar_root(s->root, s->root_scalable); 1806 } 1807 1808 static void vtd_iec_notify_all(IntelIOMMUState *s, bool global, 1809 uint32_t index, uint32_t mask) 1810 { 1811 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask); 1812 } 1813 1814 static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s) 1815 { 1816 uint64_t value = 0; 1817 value = vtd_get_quad_raw(s, DMAR_IRTA_REG); 1818 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1); 1819 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits); 1820 s->intr_eime = value & VTD_IRTA_EIME; 1821 1822 /* Notify global invalidation */ 1823 vtd_iec_notify_all(s, true, 0, 0); 1824 1825 trace_vtd_reg_ir_root(s->intr_root, s->intr_size); 1826 } 1827 1828 static void vtd_iommu_replay_all(IntelIOMMUState *s) 1829 { 1830 VTDAddressSpace *vtd_as; 1831 1832 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 1833 vtd_sync_shadow_page_table(vtd_as); 1834 } 1835 } 1836 1837 static void vtd_context_global_invalidate(IntelIOMMUState *s) 1838 { 1839 trace_vtd_inv_desc_cc_global(); 1840 /* Protects context cache */ 1841 vtd_iommu_lock(s); 1842 s->context_cache_gen++; 1843 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) { 1844 vtd_reset_context_cache_locked(s); 1845 } 1846 vtd_iommu_unlock(s); 1847 vtd_address_space_refresh_all(s); 1848 /* 1849 * From VT-d spec 6.5.2.1, a global context entry invalidation 1850 * should be followed by a IOTLB global invalidation, so we should 1851 * be safe even without this. Hoewever, let's replay the region as 1852 * well to be safer, and go back here when we need finer tunes for 1853 * VT-d emulation codes. 1854 */ 1855 vtd_iommu_replay_all(s); 1856 } 1857 1858 /* Do a context-cache device-selective invalidation. 1859 * @func_mask: FM field after shifting 1860 */ 1861 static void vtd_context_device_invalidate(IntelIOMMUState *s, 1862 uint16_t source_id, 1863 uint16_t func_mask) 1864 { 1865 uint16_t mask; 1866 VTDBus *vtd_bus; 1867 VTDAddressSpace *vtd_as; 1868 uint8_t bus_n, devfn; 1869 uint16_t devfn_it; 1870 1871 trace_vtd_inv_desc_cc_devices(source_id, func_mask); 1872 1873 switch (func_mask & 3) { 1874 case 0: 1875 mask = 0; /* No bits in the SID field masked */ 1876 break; 1877 case 1: 1878 mask = 4; /* Mask bit 2 in the SID field */ 1879 break; 1880 case 2: 1881 mask = 6; /* Mask bit 2:1 in the SID field */ 1882 break; 1883 case 3: 1884 mask = 7; /* Mask bit 2:0 in the SID field */ 1885 break; 1886 default: 1887 g_assert_not_reached(); 1888 } 1889 mask = ~mask; 1890 1891 bus_n = VTD_SID_TO_BUS(source_id); 1892 vtd_bus = vtd_find_as_from_bus_num(s, bus_n); 1893 if (vtd_bus) { 1894 devfn = VTD_SID_TO_DEVFN(source_id); 1895 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { 1896 vtd_as = vtd_bus->dev_as[devfn_it]; 1897 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) { 1898 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it), 1899 VTD_PCI_FUNC(devfn_it)); 1900 vtd_iommu_lock(s); 1901 vtd_as->context_cache_entry.context_cache_gen = 0; 1902 vtd_iommu_unlock(s); 1903 /* 1904 * Do switch address space when needed, in case if the 1905 * device passthrough bit is switched. 1906 */ 1907 vtd_switch_address_space(vtd_as); 1908 /* 1909 * So a device is moving out of (or moving into) a 1910 * domain, resync the shadow page table. 1911 * This won't bring bad even if we have no such 1912 * notifier registered - the IOMMU notification 1913 * framework will skip MAP notifications if that 1914 * happened. 1915 */ 1916 vtd_sync_shadow_page_table(vtd_as); 1917 } 1918 } 1919 } 1920 } 1921 1922 /* Context-cache invalidation 1923 * Returns the Context Actual Invalidation Granularity. 1924 * @val: the content of the CCMD_REG 1925 */ 1926 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val) 1927 { 1928 uint64_t caig; 1929 uint64_t type = val & VTD_CCMD_CIRG_MASK; 1930 1931 switch (type) { 1932 case VTD_CCMD_DOMAIN_INVL: 1933 /* Fall through */ 1934 case VTD_CCMD_GLOBAL_INVL: 1935 caig = VTD_CCMD_GLOBAL_INVL_A; 1936 vtd_context_global_invalidate(s); 1937 break; 1938 1939 case VTD_CCMD_DEVICE_INVL: 1940 caig = VTD_CCMD_DEVICE_INVL_A; 1941 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val)); 1942 break; 1943 1944 default: 1945 error_report_once("%s: invalid context: 0x%" PRIx64, 1946 __func__, val); 1947 caig = 0; 1948 } 1949 return caig; 1950 } 1951 1952 static void vtd_iotlb_global_invalidate(IntelIOMMUState *s) 1953 { 1954 trace_vtd_inv_desc_iotlb_global(); 1955 vtd_reset_iotlb(s); 1956 vtd_iommu_replay_all(s); 1957 } 1958 1959 static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id) 1960 { 1961 VTDContextEntry ce; 1962 VTDAddressSpace *vtd_as; 1963 1964 trace_vtd_inv_desc_iotlb_domain(domain_id); 1965 1966 vtd_iommu_lock(s); 1967 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain, 1968 &domain_id); 1969 vtd_iommu_unlock(s); 1970 1971 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 1972 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), 1973 vtd_as->devfn, &ce) && 1974 domain_id == vtd_get_domain_id(s, &ce)) { 1975 vtd_sync_shadow_page_table(vtd_as); 1976 } 1977 } 1978 } 1979 1980 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, 1981 uint16_t domain_id, hwaddr addr, 1982 uint8_t am) 1983 { 1984 VTDAddressSpace *vtd_as; 1985 VTDContextEntry ce; 1986 int ret; 1987 hwaddr size = (1 << am) * VTD_PAGE_SIZE; 1988 1989 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) { 1990 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), 1991 vtd_as->devfn, &ce); 1992 if (!ret && domain_id == vtd_get_domain_id(s, &ce)) { 1993 if (vtd_as_has_map_notifier(vtd_as)) { 1994 /* 1995 * As long as we have MAP notifications registered in 1996 * any of our IOMMU notifiers, we need to sync the 1997 * shadow page table. 1998 */ 1999 vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size); 2000 } else { 2001 /* 2002 * For UNMAP-only notifiers, we don't need to walk the 2003 * page tables. We just deliver the PSI down to 2004 * invalidate caches. 2005 */ 2006 IOMMUTLBEvent event = { 2007 .type = IOMMU_NOTIFIER_UNMAP, 2008 .entry = { 2009 .target_as = &address_space_memory, 2010 .iova = addr, 2011 .translated_addr = 0, 2012 .addr_mask = size - 1, 2013 .perm = IOMMU_NONE, 2014 }, 2015 }; 2016 memory_region_notify_iommu(&vtd_as->iommu, 0, event); 2017 } 2018 } 2019 } 2020 } 2021 2022 static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id, 2023 hwaddr addr, uint8_t am) 2024 { 2025 VTDIOTLBPageInvInfo info; 2026 2027 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am); 2028 2029 assert(am <= VTD_MAMV); 2030 info.domain_id = domain_id; 2031 info.addr = addr; 2032 info.mask = ~((1 << am) - 1); 2033 vtd_iommu_lock(s); 2034 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info); 2035 vtd_iommu_unlock(s); 2036 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am); 2037 } 2038 2039 /* Flush IOTLB 2040 * Returns the IOTLB Actual Invalidation Granularity. 2041 * @val: the content of the IOTLB_REG 2042 */ 2043 static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val) 2044 { 2045 uint64_t iaig; 2046 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK; 2047 uint16_t domain_id; 2048 hwaddr addr; 2049 uint8_t am; 2050 2051 switch (type) { 2052 case VTD_TLB_GLOBAL_FLUSH: 2053 iaig = VTD_TLB_GLOBAL_FLUSH_A; 2054 vtd_iotlb_global_invalidate(s); 2055 break; 2056 2057 case VTD_TLB_DSI_FLUSH: 2058 domain_id = VTD_TLB_DID(val); 2059 iaig = VTD_TLB_DSI_FLUSH_A; 2060 vtd_iotlb_domain_invalidate(s, domain_id); 2061 break; 2062 2063 case VTD_TLB_PSI_FLUSH: 2064 domain_id = VTD_TLB_DID(val); 2065 addr = vtd_get_quad_raw(s, DMAR_IVA_REG); 2066 am = VTD_IVA_AM(addr); 2067 addr = VTD_IVA_ADDR(addr); 2068 if (am > VTD_MAMV) { 2069 error_report_once("%s: address mask overflow: 0x%" PRIx64, 2070 __func__, vtd_get_quad_raw(s, DMAR_IVA_REG)); 2071 iaig = 0; 2072 break; 2073 } 2074 iaig = VTD_TLB_PSI_FLUSH_A; 2075 vtd_iotlb_page_invalidate(s, domain_id, addr, am); 2076 break; 2077 2078 default: 2079 error_report_once("%s: invalid granularity: 0x%" PRIx64, 2080 __func__, val); 2081 iaig = 0; 2082 } 2083 return iaig; 2084 } 2085 2086 static void vtd_fetch_inv_desc(IntelIOMMUState *s); 2087 2088 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s) 2089 { 2090 return s->qi_enabled && (s->iq_tail == s->iq_head) && 2091 (s->iq_last_desc_type == VTD_INV_DESC_WAIT); 2092 } 2093 2094 static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en) 2095 { 2096 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG); 2097 2098 trace_vtd_inv_qi_enable(en); 2099 2100 if (en) { 2101 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits); 2102 /* 2^(x+8) entries */ 2103 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8 - (s->iq_dw ? 1 : 0)); 2104 s->qi_enabled = true; 2105 trace_vtd_inv_qi_setup(s->iq, s->iq_size); 2106 /* Ok - report back to driver */ 2107 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES); 2108 2109 if (s->iq_tail != 0) { 2110 /* 2111 * This is a spec violation but Windows guests are known to set up 2112 * Queued Invalidation this way so we allow the write and process 2113 * Invalidation Descriptors right away. 2114 */ 2115 trace_vtd_warn_invalid_qi_tail(s->iq_tail); 2116 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { 2117 vtd_fetch_inv_desc(s); 2118 } 2119 } 2120 } else { 2121 if (vtd_queued_inv_disable_check(s)) { 2122 /* disable Queued Invalidation */ 2123 vtd_set_quad_raw(s, DMAR_IQH_REG, 0); 2124 s->iq_head = 0; 2125 s->qi_enabled = false; 2126 /* Ok - report back to driver */ 2127 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0); 2128 } else { 2129 error_report_once("%s: detected improper state when disable QI " 2130 "(head=0x%x, tail=0x%x, last_type=%d)", 2131 __func__, 2132 s->iq_head, s->iq_tail, s->iq_last_desc_type); 2133 } 2134 } 2135 } 2136 2137 /* Set Root Table Pointer */ 2138 static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) 2139 { 2140 vtd_root_table_setup(s); 2141 /* Ok - report back to driver */ 2142 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); 2143 vtd_reset_caches(s); 2144 vtd_address_space_refresh_all(s); 2145 } 2146 2147 /* Set Interrupt Remap Table Pointer */ 2148 static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s) 2149 { 2150 vtd_interrupt_remap_table_setup(s); 2151 /* Ok - report back to driver */ 2152 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS); 2153 } 2154 2155 /* Handle Translation Enable/Disable */ 2156 static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en) 2157 { 2158 if (s->dmar_enabled == en) { 2159 return; 2160 } 2161 2162 trace_vtd_dmar_enable(en); 2163 2164 if (en) { 2165 s->dmar_enabled = true; 2166 /* Ok - report back to driver */ 2167 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES); 2168 } else { 2169 s->dmar_enabled = false; 2170 2171 /* Clear the index of Fault Recording Register */ 2172 s->next_frcd_reg = 0; 2173 /* Ok - report back to driver */ 2174 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0); 2175 } 2176 2177 vtd_reset_caches(s); 2178 vtd_address_space_refresh_all(s); 2179 } 2180 2181 /* Handle Interrupt Remap Enable/Disable */ 2182 static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en) 2183 { 2184 trace_vtd_ir_enable(en); 2185 2186 if (en) { 2187 s->intr_enabled = true; 2188 /* Ok - report back to driver */ 2189 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES); 2190 } else { 2191 s->intr_enabled = false; 2192 /* Ok - report back to driver */ 2193 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0); 2194 } 2195 } 2196 2197 /* Handle write to Global Command Register */ 2198 static void vtd_handle_gcmd_write(IntelIOMMUState *s) 2199 { 2200 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG); 2201 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG); 2202 uint32_t changed = status ^ val; 2203 2204 trace_vtd_reg_write_gcmd(status, val); 2205 if (changed & VTD_GCMD_TE) { 2206 /* Translation enable/disable */ 2207 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE); 2208 } 2209 if (val & VTD_GCMD_SRTP) { 2210 /* Set/update the root-table pointer */ 2211 vtd_handle_gcmd_srtp(s); 2212 } 2213 if (changed & VTD_GCMD_QIE) { 2214 /* Queued Invalidation Enable */ 2215 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE); 2216 } 2217 if (val & VTD_GCMD_SIRTP) { 2218 /* Set/update the interrupt remapping root-table pointer */ 2219 vtd_handle_gcmd_sirtp(s); 2220 } 2221 if (changed & VTD_GCMD_IRE) { 2222 /* Interrupt remap enable/disable */ 2223 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE); 2224 } 2225 } 2226 2227 /* Handle write to Context Command Register */ 2228 static void vtd_handle_ccmd_write(IntelIOMMUState *s) 2229 { 2230 uint64_t ret; 2231 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG); 2232 2233 /* Context-cache invalidation request */ 2234 if (val & VTD_CCMD_ICC) { 2235 if (s->qi_enabled) { 2236 error_report_once("Queued Invalidation enabled, " 2237 "should not use register-based invalidation"); 2238 return; 2239 } 2240 ret = vtd_context_cache_invalidate(s, val); 2241 /* Invalidation completed. Change something to show */ 2242 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL); 2243 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK, 2244 ret); 2245 } 2246 } 2247 2248 /* Handle write to IOTLB Invalidation Register */ 2249 static void vtd_handle_iotlb_write(IntelIOMMUState *s) 2250 { 2251 uint64_t ret; 2252 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG); 2253 2254 /* IOTLB invalidation request */ 2255 if (val & VTD_TLB_IVT) { 2256 if (s->qi_enabled) { 2257 error_report_once("Queued Invalidation enabled, " 2258 "should not use register-based invalidation"); 2259 return; 2260 } 2261 ret = vtd_iotlb_flush(s, val); 2262 /* Invalidation completed. Change something to show */ 2263 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL); 2264 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, 2265 VTD_TLB_FLUSH_GRANU_MASK_A, ret); 2266 } 2267 } 2268 2269 /* Fetch an Invalidation Descriptor from the Invalidation Queue */ 2270 static bool vtd_get_inv_desc(IntelIOMMUState *s, 2271 VTDInvDesc *inv_desc) 2272 { 2273 dma_addr_t base_addr = s->iq; 2274 uint32_t offset = s->iq_head; 2275 uint32_t dw = s->iq_dw ? 32 : 16; 2276 dma_addr_t addr = base_addr + offset * dw; 2277 2278 if (dma_memory_read(&address_space_memory, addr, inv_desc, dw)) { 2279 error_report_once("Read INV DESC failed."); 2280 return false; 2281 } 2282 inv_desc->lo = le64_to_cpu(inv_desc->lo); 2283 inv_desc->hi = le64_to_cpu(inv_desc->hi); 2284 if (dw == 32) { 2285 inv_desc->val[2] = le64_to_cpu(inv_desc->val[2]); 2286 inv_desc->val[3] = le64_to_cpu(inv_desc->val[3]); 2287 } 2288 return true; 2289 } 2290 2291 static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) 2292 { 2293 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) || 2294 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) { 2295 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 2296 " (reserved nonzero)", __func__, inv_desc->hi, 2297 inv_desc->lo); 2298 return false; 2299 } 2300 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) { 2301 /* Status Write */ 2302 uint32_t status_data = (uint32_t)(inv_desc->lo >> 2303 VTD_INV_DESC_WAIT_DATA_SHIFT); 2304 2305 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF)); 2306 2307 /* FIXME: need to be masked with HAW? */ 2308 dma_addr_t status_addr = inv_desc->hi; 2309 trace_vtd_inv_desc_wait_sw(status_addr, status_data); 2310 status_data = cpu_to_le32(status_data); 2311 if (dma_memory_write(&address_space_memory, status_addr, &status_data, 2312 sizeof(status_data))) { 2313 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo); 2314 return false; 2315 } 2316 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) { 2317 /* Interrupt flag */ 2318 vtd_generate_completion_event(s); 2319 } else { 2320 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 2321 " (unknown type)", __func__, inv_desc->hi, 2322 inv_desc->lo); 2323 return false; 2324 } 2325 return true; 2326 } 2327 2328 static bool vtd_process_context_cache_desc(IntelIOMMUState *s, 2329 VTDInvDesc *inv_desc) 2330 { 2331 uint16_t sid, fmask; 2332 2333 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) { 2334 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 2335 " (reserved nonzero)", __func__, inv_desc->hi, 2336 inv_desc->lo); 2337 return false; 2338 } 2339 switch (inv_desc->lo & VTD_INV_DESC_CC_G) { 2340 case VTD_INV_DESC_CC_DOMAIN: 2341 trace_vtd_inv_desc_cc_domain( 2342 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo)); 2343 /* Fall through */ 2344 case VTD_INV_DESC_CC_GLOBAL: 2345 vtd_context_global_invalidate(s); 2346 break; 2347 2348 case VTD_INV_DESC_CC_DEVICE: 2349 sid = VTD_INV_DESC_CC_SID(inv_desc->lo); 2350 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo); 2351 vtd_context_device_invalidate(s, sid, fmask); 2352 break; 2353 2354 default: 2355 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 2356 " (invalid type)", __func__, inv_desc->hi, 2357 inv_desc->lo); 2358 return false; 2359 } 2360 return true; 2361 } 2362 2363 static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) 2364 { 2365 uint16_t domain_id; 2366 uint8_t am; 2367 hwaddr addr; 2368 2369 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) || 2370 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) { 2371 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2372 ", lo=0x%"PRIx64" (reserved bits unzero)", 2373 __func__, inv_desc->hi, inv_desc->lo); 2374 return false; 2375 } 2376 2377 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) { 2378 case VTD_INV_DESC_IOTLB_GLOBAL: 2379 vtd_iotlb_global_invalidate(s); 2380 break; 2381 2382 case VTD_INV_DESC_IOTLB_DOMAIN: 2383 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo); 2384 vtd_iotlb_domain_invalidate(s, domain_id); 2385 break; 2386 2387 case VTD_INV_DESC_IOTLB_PAGE: 2388 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo); 2389 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi); 2390 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi); 2391 if (am > VTD_MAMV) { 2392 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2393 ", lo=0x%"PRIx64" (am=%u > VTD_MAMV=%u)", 2394 __func__, inv_desc->hi, inv_desc->lo, 2395 am, (unsigned)VTD_MAMV); 2396 return false; 2397 } 2398 vtd_iotlb_page_invalidate(s, domain_id, addr, am); 2399 break; 2400 2401 default: 2402 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2403 ", lo=0x%"PRIx64" (type mismatch: 0x%llx)", 2404 __func__, inv_desc->hi, inv_desc->lo, 2405 inv_desc->lo & VTD_INV_DESC_IOTLB_G); 2406 return false; 2407 } 2408 return true; 2409 } 2410 2411 static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, 2412 VTDInvDesc *inv_desc) 2413 { 2414 trace_vtd_inv_desc_iec(inv_desc->iec.granularity, 2415 inv_desc->iec.index, 2416 inv_desc->iec.index_mask); 2417 2418 vtd_iec_notify_all(s, !inv_desc->iec.granularity, 2419 inv_desc->iec.index, 2420 inv_desc->iec.index_mask); 2421 return true; 2422 } 2423 2424 static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, 2425 VTDInvDesc *inv_desc) 2426 { 2427 VTDAddressSpace *vtd_dev_as; 2428 IOMMUTLBEvent event; 2429 struct VTDBus *vtd_bus; 2430 hwaddr addr; 2431 uint64_t sz; 2432 uint16_t sid; 2433 uint8_t devfn; 2434 bool size; 2435 uint8_t bus_num; 2436 2437 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi); 2438 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo); 2439 devfn = sid & 0xff; 2440 bus_num = sid >> 8; 2441 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi); 2442 2443 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) || 2444 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) { 2445 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64 2446 ", lo=%"PRIx64" (reserved nonzero)", __func__, 2447 inv_desc->hi, inv_desc->lo); 2448 return false; 2449 } 2450 2451 vtd_bus = vtd_find_as_from_bus_num(s, bus_num); 2452 if (!vtd_bus) { 2453 goto done; 2454 } 2455 2456 vtd_dev_as = vtd_bus->dev_as[devfn]; 2457 if (!vtd_dev_as) { 2458 goto done; 2459 } 2460 2461 /* According to ATS spec table 2.4: 2462 * S = 0, bits 15:12 = xxxx range size: 4K 2463 * S = 1, bits 15:12 = xxx0 range size: 8K 2464 * S = 1, bits 15:12 = xx01 range size: 16K 2465 * S = 1, bits 15:12 = x011 range size: 32K 2466 * S = 1, bits 15:12 = 0111 range size: 64K 2467 * ... 2468 */ 2469 if (size) { 2470 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT); 2471 addr &= ~(sz - 1); 2472 } else { 2473 sz = VTD_PAGE_SIZE; 2474 } 2475 2476 event.type = IOMMU_NOTIFIER_DEVIOTLB_UNMAP; 2477 event.entry.target_as = &vtd_dev_as->as; 2478 event.entry.addr_mask = sz - 1; 2479 event.entry.iova = addr; 2480 event.entry.perm = IOMMU_NONE; 2481 event.entry.translated_addr = 0; 2482 memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); 2483 2484 done: 2485 return true; 2486 } 2487 2488 static bool vtd_process_inv_desc(IntelIOMMUState *s) 2489 { 2490 VTDInvDesc inv_desc; 2491 uint8_t desc_type; 2492 2493 trace_vtd_inv_qi_head(s->iq_head); 2494 if (!vtd_get_inv_desc(s, &inv_desc)) { 2495 s->iq_last_desc_type = VTD_INV_DESC_NONE; 2496 return false; 2497 } 2498 2499 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE; 2500 /* FIXME: should update at first or at last? */ 2501 s->iq_last_desc_type = desc_type; 2502 2503 switch (desc_type) { 2504 case VTD_INV_DESC_CC: 2505 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo); 2506 if (!vtd_process_context_cache_desc(s, &inv_desc)) { 2507 return false; 2508 } 2509 break; 2510 2511 case VTD_INV_DESC_IOTLB: 2512 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo); 2513 if (!vtd_process_iotlb_desc(s, &inv_desc)) { 2514 return false; 2515 } 2516 break; 2517 2518 /* 2519 * TODO: the entity of below two cases will be implemented in future series. 2520 * To make guest (which integrates scalable mode support patch set in 2521 * iommu driver) work, just return true is enough so far. 2522 */ 2523 case VTD_INV_DESC_PC: 2524 break; 2525 2526 case VTD_INV_DESC_PIOTLB: 2527 break; 2528 2529 case VTD_INV_DESC_WAIT: 2530 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo); 2531 if (!vtd_process_wait_desc(s, &inv_desc)) { 2532 return false; 2533 } 2534 break; 2535 2536 case VTD_INV_DESC_IEC: 2537 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo); 2538 if (!vtd_process_inv_iec_desc(s, &inv_desc)) { 2539 return false; 2540 } 2541 break; 2542 2543 case VTD_INV_DESC_DEVICE: 2544 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo); 2545 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) { 2546 return false; 2547 } 2548 break; 2549 2550 default: 2551 error_report_once("%s: invalid inv desc: hi=%"PRIx64", lo=%"PRIx64 2552 " (unknown type)", __func__, inv_desc.hi, 2553 inv_desc.lo); 2554 return false; 2555 } 2556 s->iq_head++; 2557 if (s->iq_head == s->iq_size) { 2558 s->iq_head = 0; 2559 } 2560 return true; 2561 } 2562 2563 /* Try to fetch and process more Invalidation Descriptors */ 2564 static void vtd_fetch_inv_desc(IntelIOMMUState *s) 2565 { 2566 int qi_shift; 2567 2568 /* Refer to 10.4.23 of VT-d spec 3.0 */ 2569 qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4; 2570 2571 trace_vtd_inv_qi_fetch(); 2572 2573 if (s->iq_tail >= s->iq_size) { 2574 /* Detects an invalid Tail pointer */ 2575 error_report_once("%s: detected invalid QI tail " 2576 "(tail=0x%x, size=0x%x)", 2577 __func__, s->iq_tail, s->iq_size); 2578 vtd_handle_inv_queue_error(s); 2579 return; 2580 } 2581 while (s->iq_head != s->iq_tail) { 2582 if (!vtd_process_inv_desc(s)) { 2583 /* Invalidation Queue Errors */ 2584 vtd_handle_inv_queue_error(s); 2585 break; 2586 } 2587 /* Must update the IQH_REG in time */ 2588 vtd_set_quad_raw(s, DMAR_IQH_REG, 2589 (((uint64_t)(s->iq_head)) << qi_shift) & 2590 VTD_IQH_QH_MASK); 2591 } 2592 } 2593 2594 /* Handle write to Invalidation Queue Tail Register */ 2595 static void vtd_handle_iqt_write(IntelIOMMUState *s) 2596 { 2597 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG); 2598 2599 if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) { 2600 error_report_once("%s: RSV bit is set: val=0x%"PRIx64, 2601 __func__, val); 2602 return; 2603 } 2604 s->iq_tail = VTD_IQT_QT(s->iq_dw, val); 2605 trace_vtd_inv_qi_tail(s->iq_tail); 2606 2607 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { 2608 /* Process Invalidation Queue here */ 2609 vtd_fetch_inv_desc(s); 2610 } 2611 } 2612 2613 static void vtd_handle_fsts_write(IntelIOMMUState *s) 2614 { 2615 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 2616 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); 2617 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE; 2618 2619 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) { 2620 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 2621 trace_vtd_fsts_clear_ip(); 2622 } 2623 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation 2624 * Descriptors if there are any when Queued Invalidation is enabled? 2625 */ 2626 } 2627 2628 static void vtd_handle_fectl_write(IntelIOMMUState *s) 2629 { 2630 uint32_t fectl_reg; 2631 /* FIXME: when software clears the IM field, check the IP field. But do we 2632 * need to compare the old value and the new value to conclude that 2633 * software clears the IM field? Or just check if the IM field is zero? 2634 */ 2635 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); 2636 2637 trace_vtd_reg_write_fectl(fectl_reg); 2638 2639 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) { 2640 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); 2641 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 2642 } 2643 } 2644 2645 static void vtd_handle_ics_write(IntelIOMMUState *s) 2646 { 2647 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG); 2648 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); 2649 2650 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) { 2651 trace_vtd_reg_ics_clear_ip(); 2652 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 2653 } 2654 } 2655 2656 static void vtd_handle_iectl_write(IntelIOMMUState *s) 2657 { 2658 uint32_t iectl_reg; 2659 /* FIXME: when software clears the IM field, check the IP field. But do we 2660 * need to compare the old value and the new value to conclude that 2661 * software clears the IM field? Or just check if the IM field is zero? 2662 */ 2663 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); 2664 2665 trace_vtd_reg_write_iectl(iectl_reg); 2666 2667 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) { 2668 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); 2669 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 2670 } 2671 } 2672 2673 static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size) 2674 { 2675 IntelIOMMUState *s = opaque; 2676 uint64_t val; 2677 2678 trace_vtd_reg_read(addr, size); 2679 2680 if (addr + size > DMAR_REG_SIZE) { 2681 error_report_once("%s: MMIO over range: addr=0x%" PRIx64 2682 " size=0x%x", __func__, addr, size); 2683 return (uint64_t)-1; 2684 } 2685 2686 switch (addr) { 2687 /* Root Table Address Register, 64-bit */ 2688 case DMAR_RTADDR_REG: 2689 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 2690 if (size == 4) { 2691 val = val & ((1ULL << 32) - 1); 2692 } 2693 break; 2694 2695 case DMAR_RTADDR_REG_HI: 2696 assert(size == 4); 2697 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32; 2698 break; 2699 2700 /* Invalidation Queue Address Register, 64-bit */ 2701 case DMAR_IQA_REG: 2702 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS); 2703 if (size == 4) { 2704 val = val & ((1ULL << 32) - 1); 2705 } 2706 break; 2707 2708 case DMAR_IQA_REG_HI: 2709 assert(size == 4); 2710 val = s->iq >> 32; 2711 break; 2712 2713 default: 2714 if (size == 4) { 2715 val = vtd_get_long(s, addr); 2716 } else { 2717 val = vtd_get_quad(s, addr); 2718 } 2719 } 2720 2721 return val; 2722 } 2723 2724 static void vtd_mem_write(void *opaque, hwaddr addr, 2725 uint64_t val, unsigned size) 2726 { 2727 IntelIOMMUState *s = opaque; 2728 2729 trace_vtd_reg_write(addr, size, val); 2730 2731 if (addr + size > DMAR_REG_SIZE) { 2732 error_report_once("%s: MMIO over range: addr=0x%" PRIx64 2733 " size=0x%x", __func__, addr, size); 2734 return; 2735 } 2736 2737 switch (addr) { 2738 /* Global Command Register, 32-bit */ 2739 case DMAR_GCMD_REG: 2740 vtd_set_long(s, addr, val); 2741 vtd_handle_gcmd_write(s); 2742 break; 2743 2744 /* Context Command Register, 64-bit */ 2745 case DMAR_CCMD_REG: 2746 if (size == 4) { 2747 vtd_set_long(s, addr, val); 2748 } else { 2749 vtd_set_quad(s, addr, val); 2750 vtd_handle_ccmd_write(s); 2751 } 2752 break; 2753 2754 case DMAR_CCMD_REG_HI: 2755 assert(size == 4); 2756 vtd_set_long(s, addr, val); 2757 vtd_handle_ccmd_write(s); 2758 break; 2759 2760 /* IOTLB Invalidation Register, 64-bit */ 2761 case DMAR_IOTLB_REG: 2762 if (size == 4) { 2763 vtd_set_long(s, addr, val); 2764 } else { 2765 vtd_set_quad(s, addr, val); 2766 vtd_handle_iotlb_write(s); 2767 } 2768 break; 2769 2770 case DMAR_IOTLB_REG_HI: 2771 assert(size == 4); 2772 vtd_set_long(s, addr, val); 2773 vtd_handle_iotlb_write(s); 2774 break; 2775 2776 /* Invalidate Address Register, 64-bit */ 2777 case DMAR_IVA_REG: 2778 if (size == 4) { 2779 vtd_set_long(s, addr, val); 2780 } else { 2781 vtd_set_quad(s, addr, val); 2782 } 2783 break; 2784 2785 case DMAR_IVA_REG_HI: 2786 assert(size == 4); 2787 vtd_set_long(s, addr, val); 2788 break; 2789 2790 /* Fault Status Register, 32-bit */ 2791 case DMAR_FSTS_REG: 2792 assert(size == 4); 2793 vtd_set_long(s, addr, val); 2794 vtd_handle_fsts_write(s); 2795 break; 2796 2797 /* Fault Event Control Register, 32-bit */ 2798 case DMAR_FECTL_REG: 2799 assert(size == 4); 2800 vtd_set_long(s, addr, val); 2801 vtd_handle_fectl_write(s); 2802 break; 2803 2804 /* Fault Event Data Register, 32-bit */ 2805 case DMAR_FEDATA_REG: 2806 assert(size == 4); 2807 vtd_set_long(s, addr, val); 2808 break; 2809 2810 /* Fault Event Address Register, 32-bit */ 2811 case DMAR_FEADDR_REG: 2812 if (size == 4) { 2813 vtd_set_long(s, addr, val); 2814 } else { 2815 /* 2816 * While the register is 32-bit only, some guests (Xen...) write to 2817 * it with 64-bit. 2818 */ 2819 vtd_set_quad(s, addr, val); 2820 } 2821 break; 2822 2823 /* Fault Event Upper Address Register, 32-bit */ 2824 case DMAR_FEUADDR_REG: 2825 assert(size == 4); 2826 vtd_set_long(s, addr, val); 2827 break; 2828 2829 /* Protected Memory Enable Register, 32-bit */ 2830 case DMAR_PMEN_REG: 2831 assert(size == 4); 2832 vtd_set_long(s, addr, val); 2833 break; 2834 2835 /* Root Table Address Register, 64-bit */ 2836 case DMAR_RTADDR_REG: 2837 if (size == 4) { 2838 vtd_set_long(s, addr, val); 2839 } else { 2840 vtd_set_quad(s, addr, val); 2841 } 2842 break; 2843 2844 case DMAR_RTADDR_REG_HI: 2845 assert(size == 4); 2846 vtd_set_long(s, addr, val); 2847 break; 2848 2849 /* Invalidation Queue Tail Register, 64-bit */ 2850 case DMAR_IQT_REG: 2851 if (size == 4) { 2852 vtd_set_long(s, addr, val); 2853 } else { 2854 vtd_set_quad(s, addr, val); 2855 } 2856 vtd_handle_iqt_write(s); 2857 break; 2858 2859 case DMAR_IQT_REG_HI: 2860 assert(size == 4); 2861 vtd_set_long(s, addr, val); 2862 /* 19:63 of IQT_REG is RsvdZ, do nothing here */ 2863 break; 2864 2865 /* Invalidation Queue Address Register, 64-bit */ 2866 case DMAR_IQA_REG: 2867 if (size == 4) { 2868 vtd_set_long(s, addr, val); 2869 } else { 2870 vtd_set_quad(s, addr, val); 2871 } 2872 if (s->ecap & VTD_ECAP_SMTS && 2873 val & VTD_IQA_DW_MASK) { 2874 s->iq_dw = true; 2875 } else { 2876 s->iq_dw = false; 2877 } 2878 break; 2879 2880 case DMAR_IQA_REG_HI: 2881 assert(size == 4); 2882 vtd_set_long(s, addr, val); 2883 break; 2884 2885 /* Invalidation Completion Status Register, 32-bit */ 2886 case DMAR_ICS_REG: 2887 assert(size == 4); 2888 vtd_set_long(s, addr, val); 2889 vtd_handle_ics_write(s); 2890 break; 2891 2892 /* Invalidation Event Control Register, 32-bit */ 2893 case DMAR_IECTL_REG: 2894 assert(size == 4); 2895 vtd_set_long(s, addr, val); 2896 vtd_handle_iectl_write(s); 2897 break; 2898 2899 /* Invalidation Event Data Register, 32-bit */ 2900 case DMAR_IEDATA_REG: 2901 assert(size == 4); 2902 vtd_set_long(s, addr, val); 2903 break; 2904 2905 /* Invalidation Event Address Register, 32-bit */ 2906 case DMAR_IEADDR_REG: 2907 assert(size == 4); 2908 vtd_set_long(s, addr, val); 2909 break; 2910 2911 /* Invalidation Event Upper Address Register, 32-bit */ 2912 case DMAR_IEUADDR_REG: 2913 assert(size == 4); 2914 vtd_set_long(s, addr, val); 2915 break; 2916 2917 /* Fault Recording Registers, 128-bit */ 2918 case DMAR_FRCD_REG_0_0: 2919 if (size == 4) { 2920 vtd_set_long(s, addr, val); 2921 } else { 2922 vtd_set_quad(s, addr, val); 2923 } 2924 break; 2925 2926 case DMAR_FRCD_REG_0_1: 2927 assert(size == 4); 2928 vtd_set_long(s, addr, val); 2929 break; 2930 2931 case DMAR_FRCD_REG_0_2: 2932 if (size == 4) { 2933 vtd_set_long(s, addr, val); 2934 } else { 2935 vtd_set_quad(s, addr, val); 2936 /* May clear bit 127 (Fault), update PPF */ 2937 vtd_update_fsts_ppf(s); 2938 } 2939 break; 2940 2941 case DMAR_FRCD_REG_0_3: 2942 assert(size == 4); 2943 vtd_set_long(s, addr, val); 2944 /* May clear bit 127 (Fault), update PPF */ 2945 vtd_update_fsts_ppf(s); 2946 break; 2947 2948 case DMAR_IRTA_REG: 2949 if (size == 4) { 2950 vtd_set_long(s, addr, val); 2951 } else { 2952 vtd_set_quad(s, addr, val); 2953 } 2954 break; 2955 2956 case DMAR_IRTA_REG_HI: 2957 assert(size == 4); 2958 vtd_set_long(s, addr, val); 2959 break; 2960 2961 default: 2962 if (size == 4) { 2963 vtd_set_long(s, addr, val); 2964 } else { 2965 vtd_set_quad(s, addr, val); 2966 } 2967 } 2968 } 2969 2970 static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr, 2971 IOMMUAccessFlags flag, int iommu_idx) 2972 { 2973 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); 2974 IntelIOMMUState *s = vtd_as->iommu_state; 2975 IOMMUTLBEntry iotlb = { 2976 /* We'll fill in the rest later. */ 2977 .target_as = &address_space_memory, 2978 }; 2979 bool success; 2980 2981 if (likely(s->dmar_enabled)) { 2982 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, 2983 addr, flag & IOMMU_WO, &iotlb); 2984 } else { 2985 /* DMAR disabled, passthrough, use 4k-page*/ 2986 iotlb.iova = addr & VTD_PAGE_MASK_4K; 2987 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K; 2988 iotlb.addr_mask = ~VTD_PAGE_MASK_4K; 2989 iotlb.perm = IOMMU_RW; 2990 success = true; 2991 } 2992 2993 if (likely(success)) { 2994 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus), 2995 VTD_PCI_SLOT(vtd_as->devfn), 2996 VTD_PCI_FUNC(vtd_as->devfn), 2997 iotlb.iova, iotlb.translated_addr, 2998 iotlb.addr_mask); 2999 } else { 3000 error_report_once("%s: detected translation failure " 3001 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64 ")", 3002 __func__, pci_bus_num(vtd_as->bus), 3003 VTD_PCI_SLOT(vtd_as->devfn), 3004 VTD_PCI_FUNC(vtd_as->devfn), 3005 addr); 3006 } 3007 3008 return iotlb; 3009 } 3010 3011 static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu, 3012 IOMMUNotifierFlag old, 3013 IOMMUNotifierFlag new, 3014 Error **errp) 3015 { 3016 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); 3017 IntelIOMMUState *s = vtd_as->iommu_state; 3018 3019 /* Update per-address-space notifier flags */ 3020 vtd_as->notifier_flags = new; 3021 3022 if (old == IOMMU_NOTIFIER_NONE) { 3023 QLIST_INSERT_HEAD(&s->vtd_as_with_notifiers, vtd_as, next); 3024 } else if (new == IOMMU_NOTIFIER_NONE) { 3025 QLIST_REMOVE(vtd_as, next); 3026 } 3027 return 0; 3028 } 3029 3030 static int vtd_post_load(void *opaque, int version_id) 3031 { 3032 IntelIOMMUState *iommu = opaque; 3033 3034 /* 3035 * Memory regions are dynamically turned on/off depending on 3036 * context entry configurations from the guest. After migration, 3037 * we need to make sure the memory regions are still correct. 3038 */ 3039 vtd_switch_address_space_all(iommu); 3040 3041 /* 3042 * We don't need to migrate the root_scalable because we can 3043 * simply do the calculation after the loading is complete. We 3044 * can actually do similar things with root, dmar_enabled, etc. 3045 * however since we've had them already so we'd better keep them 3046 * for compatibility of migration. 3047 */ 3048 vtd_update_scalable_state(iommu); 3049 3050 return 0; 3051 } 3052 3053 static const VMStateDescription vtd_vmstate = { 3054 .name = "iommu-intel", 3055 .version_id = 1, 3056 .minimum_version_id = 1, 3057 .priority = MIG_PRI_IOMMU, 3058 .post_load = vtd_post_load, 3059 .fields = (VMStateField[]) { 3060 VMSTATE_UINT64(root, IntelIOMMUState), 3061 VMSTATE_UINT64(intr_root, IntelIOMMUState), 3062 VMSTATE_UINT64(iq, IntelIOMMUState), 3063 VMSTATE_UINT32(intr_size, IntelIOMMUState), 3064 VMSTATE_UINT16(iq_head, IntelIOMMUState), 3065 VMSTATE_UINT16(iq_tail, IntelIOMMUState), 3066 VMSTATE_UINT16(iq_size, IntelIOMMUState), 3067 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState), 3068 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE), 3069 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState), 3070 VMSTATE_UNUSED(1), /* bool root_extended is obsolete by VT-d */ 3071 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState), 3072 VMSTATE_BOOL(qi_enabled, IntelIOMMUState), 3073 VMSTATE_BOOL(intr_enabled, IntelIOMMUState), 3074 VMSTATE_BOOL(intr_eime, IntelIOMMUState), 3075 VMSTATE_END_OF_LIST() 3076 } 3077 }; 3078 3079 static const MemoryRegionOps vtd_mem_ops = { 3080 .read = vtd_mem_read, 3081 .write = vtd_mem_write, 3082 .endianness = DEVICE_LITTLE_ENDIAN, 3083 .impl = { 3084 .min_access_size = 4, 3085 .max_access_size = 8, 3086 }, 3087 .valid = { 3088 .min_access_size = 4, 3089 .max_access_size = 8, 3090 }, 3091 }; 3092 3093 static Property vtd_properties[] = { 3094 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), 3095 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim, 3096 ON_OFF_AUTO_AUTO), 3097 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), 3098 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, 3099 VTD_HOST_ADDRESS_WIDTH), 3100 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), 3101 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE), 3102 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), 3103 DEFINE_PROP_END_OF_LIST(), 3104 }; 3105 3106 /* Read IRTE entry with specific index */ 3107 static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index, 3108 VTD_IR_TableEntry *entry, uint16_t sid) 3109 { 3110 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \ 3111 {0xffff, 0xfffb, 0xfff9, 0xfff8}; 3112 dma_addr_t addr = 0x00; 3113 uint16_t mask, source_id; 3114 uint8_t bus, bus_max, bus_min; 3115 3116 if (index >= iommu->intr_size) { 3117 error_report_once("%s: index too large: ind=0x%x", 3118 __func__, index); 3119 return -VTD_FR_IR_INDEX_OVER; 3120 } 3121 3122 addr = iommu->intr_root + index * sizeof(*entry); 3123 if (dma_memory_read(&address_space_memory, addr, entry, 3124 sizeof(*entry))) { 3125 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64, 3126 __func__, index, addr); 3127 return -VTD_FR_IR_ROOT_INVAL; 3128 } 3129 3130 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]), 3131 le64_to_cpu(entry->data[0])); 3132 3133 if (!entry->irte.present) { 3134 error_report_once("%s: detected non-present IRTE " 3135 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")", 3136 __func__, index, le64_to_cpu(entry->data[1]), 3137 le64_to_cpu(entry->data[0])); 3138 return -VTD_FR_IR_ENTRY_P; 3139 } 3140 3141 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 || 3142 entry->irte.__reserved_2) { 3143 error_report_once("%s: detected non-zero reserved IRTE " 3144 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")", 3145 __func__, index, le64_to_cpu(entry->data[1]), 3146 le64_to_cpu(entry->data[0])); 3147 return -VTD_FR_IR_IRTE_RSVD; 3148 } 3149 3150 if (sid != X86_IOMMU_SID_INVALID) { 3151 /* Validate IRTE SID */ 3152 source_id = le32_to_cpu(entry->irte.source_id); 3153 switch (entry->irte.sid_vtype) { 3154 case VTD_SVT_NONE: 3155 break; 3156 3157 case VTD_SVT_ALL: 3158 mask = vtd_svt_mask[entry->irte.sid_q]; 3159 if ((source_id & mask) != (sid & mask)) { 3160 error_report_once("%s: invalid IRTE SID " 3161 "(index=%u, sid=%u, source_id=%u)", 3162 __func__, index, sid, source_id); 3163 return -VTD_FR_IR_SID_ERR; 3164 } 3165 break; 3166 3167 case VTD_SVT_BUS: 3168 bus_max = source_id >> 8; 3169 bus_min = source_id & 0xff; 3170 bus = sid >> 8; 3171 if (bus > bus_max || bus < bus_min) { 3172 error_report_once("%s: invalid SVT_BUS " 3173 "(index=%u, bus=%u, min=%u, max=%u)", 3174 __func__, index, bus, bus_min, bus_max); 3175 return -VTD_FR_IR_SID_ERR; 3176 } 3177 break; 3178 3179 default: 3180 error_report_once("%s: detected invalid IRTE SVT " 3181 "(index=%u, type=%d)", __func__, 3182 index, entry->irte.sid_vtype); 3183 /* Take this as verification failure. */ 3184 return -VTD_FR_IR_SID_ERR; 3185 } 3186 } 3187 3188 return 0; 3189 } 3190 3191 /* Fetch IRQ information of specific IR index */ 3192 static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, 3193 X86IOMMUIrq *irq, uint16_t sid) 3194 { 3195 VTD_IR_TableEntry irte = {}; 3196 int ret = 0; 3197 3198 ret = vtd_irte_get(iommu, index, &irte, sid); 3199 if (ret) { 3200 return ret; 3201 } 3202 3203 irq->trigger_mode = irte.irte.trigger_mode; 3204 irq->vector = irte.irte.vector; 3205 irq->delivery_mode = irte.irte.delivery_mode; 3206 irq->dest = le32_to_cpu(irte.irte.dest_id); 3207 if (!iommu->intr_eime) { 3208 #define VTD_IR_APIC_DEST_MASK (0xff00ULL) 3209 #define VTD_IR_APIC_DEST_SHIFT (8) 3210 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >> 3211 VTD_IR_APIC_DEST_SHIFT; 3212 } 3213 irq->dest_mode = irte.irte.dest_mode; 3214 irq->redir_hint = irte.irte.redir_hint; 3215 3216 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector, 3217 irq->delivery_mode, irq->dest, irq->dest_mode); 3218 3219 return 0; 3220 } 3221 3222 /* Interrupt remapping for MSI/MSI-X entry */ 3223 static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, 3224 MSIMessage *origin, 3225 MSIMessage *translated, 3226 uint16_t sid) 3227 { 3228 int ret = 0; 3229 VTD_IR_MSIAddress addr; 3230 uint16_t index; 3231 X86IOMMUIrq irq = {}; 3232 3233 assert(origin && translated); 3234 3235 trace_vtd_ir_remap_msi_req(origin->address, origin->data); 3236 3237 if (!iommu || !iommu->intr_enabled) { 3238 memcpy(translated, origin, sizeof(*origin)); 3239 goto out; 3240 } 3241 3242 if (origin->address & VTD_MSI_ADDR_HI_MASK) { 3243 error_report_once("%s: MSI address high 32 bits non-zero detected: " 3244 "address=0x%" PRIx64, __func__, origin->address); 3245 return -VTD_FR_IR_REQ_RSVD; 3246 } 3247 3248 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK; 3249 if (addr.addr.__head != 0xfee) { 3250 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32, 3251 __func__, addr.data); 3252 return -VTD_FR_IR_REQ_RSVD; 3253 } 3254 3255 /* This is compatible mode. */ 3256 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) { 3257 memcpy(translated, origin, sizeof(*origin)); 3258 goto out; 3259 } 3260 3261 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l); 3262 3263 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff) 3264 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000) 3265 3266 if (addr.addr.sub_valid) { 3267 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */ 3268 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE; 3269 } 3270 3271 ret = vtd_remap_irq_get(iommu, index, &irq, sid); 3272 if (ret) { 3273 return ret; 3274 } 3275 3276 if (addr.addr.sub_valid) { 3277 trace_vtd_ir_remap_type("MSI"); 3278 if (origin->data & VTD_IR_MSI_DATA_RESERVED) { 3279 error_report_once("%s: invalid IR MSI " 3280 "(sid=%u, address=0x%" PRIx64 3281 ", data=0x%" PRIx32 ")", 3282 __func__, sid, origin->address, origin->data); 3283 return -VTD_FR_IR_REQ_RSVD; 3284 } 3285 } else { 3286 uint8_t vector = origin->data & 0xff; 3287 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 3288 3289 trace_vtd_ir_remap_type("IOAPIC"); 3290 /* IOAPIC entry vector should be aligned with IRTE vector 3291 * (see vt-d spec 5.1.5.1). */ 3292 if (vector != irq.vector) { 3293 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector); 3294 } 3295 3296 /* The Trigger Mode field must match the Trigger Mode in the IRTE. 3297 * (see vt-d spec 5.1.5.1). */ 3298 if (trigger_mode != irq.trigger_mode) { 3299 trace_vtd_warn_ir_trigger(sid, index, trigger_mode, 3300 irq.trigger_mode); 3301 } 3302 } 3303 3304 /* 3305 * We'd better keep the last two bits, assuming that guest OS 3306 * might modify it. Keep it does not hurt after all. 3307 */ 3308 irq.msi_addr_last_bits = addr.addr.__not_care; 3309 3310 /* Translate X86IOMMUIrq to MSI message */ 3311 x86_iommu_irq_to_msi_message(&irq, translated); 3312 3313 out: 3314 trace_vtd_ir_remap_msi(origin->address, origin->data, 3315 translated->address, translated->data); 3316 return 0; 3317 } 3318 3319 static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src, 3320 MSIMessage *dst, uint16_t sid) 3321 { 3322 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), 3323 src, dst, sid); 3324 } 3325 3326 static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr, 3327 uint64_t *data, unsigned size, 3328 MemTxAttrs attrs) 3329 { 3330 return MEMTX_OK; 3331 } 3332 3333 static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, 3334 uint64_t value, unsigned size, 3335 MemTxAttrs attrs) 3336 { 3337 int ret = 0; 3338 MSIMessage from = {}, to = {}; 3339 uint16_t sid = X86_IOMMU_SID_INVALID; 3340 3341 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; 3342 from.data = (uint32_t) value; 3343 3344 if (!attrs.unspecified) { 3345 /* We have explicit Source ID */ 3346 sid = attrs.requester_id; 3347 } 3348 3349 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid); 3350 if (ret) { 3351 /* TODO: report error */ 3352 /* Drop this interrupt */ 3353 return MEMTX_ERROR; 3354 } 3355 3356 apic_get_class()->send_msi(&to); 3357 3358 return MEMTX_OK; 3359 } 3360 3361 static const MemoryRegionOps vtd_mem_ir_ops = { 3362 .read_with_attrs = vtd_mem_ir_read, 3363 .write_with_attrs = vtd_mem_ir_write, 3364 .endianness = DEVICE_LITTLE_ENDIAN, 3365 .impl = { 3366 .min_access_size = 4, 3367 .max_access_size = 4, 3368 }, 3369 .valid = { 3370 .min_access_size = 4, 3371 .max_access_size = 4, 3372 }, 3373 }; 3374 3375 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) 3376 { 3377 uintptr_t key = (uintptr_t)bus; 3378 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key); 3379 VTDAddressSpace *vtd_dev_as; 3380 char name[128]; 3381 3382 if (!vtd_bus) { 3383 uintptr_t *new_key = g_malloc(sizeof(*new_key)); 3384 *new_key = (uintptr_t)bus; 3385 /* No corresponding free() */ 3386 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \ 3387 PCI_DEVFN_MAX); 3388 vtd_bus->bus = bus; 3389 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); 3390 } 3391 3392 vtd_dev_as = vtd_bus->dev_as[devfn]; 3393 3394 if (!vtd_dev_as) { 3395 snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), 3396 PCI_FUNC(devfn)); 3397 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace)); 3398 3399 vtd_dev_as->bus = bus; 3400 vtd_dev_as->devfn = (uint8_t)devfn; 3401 vtd_dev_as->iommu_state = s; 3402 vtd_dev_as->context_cache_entry.context_cache_gen = 0; 3403 vtd_dev_as->iova_tree = iova_tree_new(); 3404 3405 memory_region_init(&vtd_dev_as->root, OBJECT(s), name, UINT64_MAX); 3406 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, "vtd-root"); 3407 3408 /* 3409 * Build the DMAR-disabled container with aliases to the 3410 * shared MRs. Note that aliasing to a shared memory region 3411 * could help the memory API to detect same FlatViews so we 3412 * can have devices to share the same FlatView when DMAR is 3413 * disabled (either by not providing "intel_iommu=on" or with 3414 * "iommu=pt"). It will greatly reduce the total number of 3415 * FlatViews of the system hence VM runs faster. 3416 */ 3417 memory_region_init_alias(&vtd_dev_as->nodmar, OBJECT(s), 3418 "vtd-nodmar", &s->mr_nodmar, 0, 3419 memory_region_size(&s->mr_nodmar)); 3420 3421 /* 3422 * Build the per-device DMAR-enabled container. 3423 * 3424 * TODO: currently we have per-device IOMMU memory region only 3425 * because we have per-device IOMMU notifiers for devices. If 3426 * one day we can abstract the IOMMU notifiers out of the 3427 * memory regions then we can also share the same memory 3428 * region here just like what we've done above with the nodmar 3429 * region. 3430 */ 3431 strcat(name, "-dmar"); 3432 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu), 3433 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s), 3434 name, UINT64_MAX); 3435 memory_region_init_alias(&vtd_dev_as->iommu_ir, OBJECT(s), "vtd-ir", 3436 &s->mr_ir, 0, memory_region_size(&s->mr_ir)); 3437 memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as->iommu), 3438 VTD_INTERRUPT_ADDR_FIRST, 3439 &vtd_dev_as->iommu_ir, 1); 3440 3441 /* 3442 * Hook both the containers under the root container, we 3443 * switch between DMAR & noDMAR by enable/disable 3444 * corresponding sub-containers 3445 */ 3446 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, 3447 MEMORY_REGION(&vtd_dev_as->iommu), 3448 0); 3449 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, 3450 &vtd_dev_as->nodmar, 0); 3451 3452 vtd_switch_address_space(vtd_dev_as); 3453 } 3454 return vtd_dev_as; 3455 } 3456 3457 /* Unmap the whole range in the notifier's scope. */ 3458 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) 3459 { 3460 hwaddr size, remain; 3461 hwaddr start = n->start; 3462 hwaddr end = n->end; 3463 IntelIOMMUState *s = as->iommu_state; 3464 DMAMap map; 3465 3466 /* 3467 * Note: all the codes in this function has a assumption that IOVA 3468 * bits are no more than VTD_MGAW bits (which is restricted by 3469 * VT-d spec), otherwise we need to consider overflow of 64 bits. 3470 */ 3471 3472 if (end > VTD_ADDRESS_SIZE(s->aw_bits) - 1) { 3473 /* 3474 * Don't need to unmap regions that is bigger than the whole 3475 * VT-d supported address space size 3476 */ 3477 end = VTD_ADDRESS_SIZE(s->aw_bits) - 1; 3478 } 3479 3480 assert(start <= end); 3481 size = remain = end - start + 1; 3482 3483 while (remain >= VTD_PAGE_SIZE) { 3484 IOMMUTLBEvent event; 3485 uint64_t mask = dma_aligned_pow2_mask(start, end, s->aw_bits); 3486 uint64_t size = mask + 1; 3487 3488 assert(size); 3489 3490 event.type = IOMMU_NOTIFIER_UNMAP; 3491 event.entry.iova = start; 3492 event.entry.addr_mask = mask; 3493 event.entry.target_as = &address_space_memory; 3494 event.entry.perm = IOMMU_NONE; 3495 /* This field is meaningless for unmap */ 3496 event.entry.translated_addr = 0; 3497 3498 memory_region_notify_iommu_one(n, &event); 3499 3500 start += size; 3501 remain -= size; 3502 } 3503 3504 assert(!remain); 3505 3506 trace_vtd_as_unmap_whole(pci_bus_num(as->bus), 3507 VTD_PCI_SLOT(as->devfn), 3508 VTD_PCI_FUNC(as->devfn), 3509 n->start, size); 3510 3511 map.iova = n->start; 3512 map.size = size; 3513 iova_tree_remove(as->iova_tree, &map); 3514 } 3515 3516 static void vtd_address_space_unmap_all(IntelIOMMUState *s) 3517 { 3518 VTDAddressSpace *vtd_as; 3519 IOMMUNotifier *n; 3520 3521 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 3522 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) { 3523 vtd_address_space_unmap(vtd_as, n); 3524 } 3525 } 3526 } 3527 3528 static void vtd_address_space_refresh_all(IntelIOMMUState *s) 3529 { 3530 vtd_address_space_unmap_all(s); 3531 vtd_switch_address_space_all(s); 3532 } 3533 3534 static int vtd_replay_hook(IOMMUTLBEvent *event, void *private) 3535 { 3536 memory_region_notify_iommu_one(private, event); 3537 return 0; 3538 } 3539 3540 static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) 3541 { 3542 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu); 3543 IntelIOMMUState *s = vtd_as->iommu_state; 3544 uint8_t bus_n = pci_bus_num(vtd_as->bus); 3545 VTDContextEntry ce; 3546 3547 /* 3548 * The replay can be triggered by either a invalidation or a newly 3549 * created entry. No matter what, we release existing mappings 3550 * (it means flushing caches for UNMAP-only registers). 3551 */ 3552 vtd_address_space_unmap(vtd_as, n); 3553 3554 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) { 3555 trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" : 3556 "legacy mode", 3557 bus_n, PCI_SLOT(vtd_as->devfn), 3558 PCI_FUNC(vtd_as->devfn), 3559 vtd_get_domain_id(s, &ce), 3560 ce.hi, ce.lo); 3561 if (vtd_as_has_map_notifier(vtd_as)) { 3562 /* This is required only for MAP typed notifiers */ 3563 vtd_page_walk_info info = { 3564 .hook_fn = vtd_replay_hook, 3565 .private = (void *)n, 3566 .notify_unmap = false, 3567 .aw = s->aw_bits, 3568 .as = vtd_as, 3569 .domain_id = vtd_get_domain_id(s, &ce), 3570 }; 3571 3572 vtd_page_walk(s, &ce, 0, ~0ULL, &info); 3573 } 3574 } else { 3575 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn), 3576 PCI_FUNC(vtd_as->devfn)); 3577 } 3578 3579 return; 3580 } 3581 3582 /* Do the initialization. It will also be called when reset, so pay 3583 * attention when adding new initialization stuff. 3584 */ 3585 static void vtd_init(IntelIOMMUState *s) 3586 { 3587 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 3588 3589 memset(s->csr, 0, DMAR_REG_SIZE); 3590 memset(s->wmask, 0, DMAR_REG_SIZE); 3591 memset(s->w1cmask, 0, DMAR_REG_SIZE); 3592 memset(s->womask, 0, DMAR_REG_SIZE); 3593 3594 s->root = 0; 3595 s->root_scalable = false; 3596 s->dmar_enabled = false; 3597 s->intr_enabled = false; 3598 s->iq_head = 0; 3599 s->iq_tail = 0; 3600 s->iq = 0; 3601 s->iq_size = 0; 3602 s->qi_enabled = false; 3603 s->iq_last_desc_type = VTD_INV_DESC_NONE; 3604 s->iq_dw = false; 3605 s->next_frcd_reg = 0; 3606 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | 3607 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | 3608 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits); 3609 if (s->dma_drain) { 3610 s->cap |= VTD_CAP_DRAIN; 3611 } 3612 if (s->aw_bits == VTD_HOST_AW_48BIT) { 3613 s->cap |= VTD_CAP_SAGAW_48bit; 3614 } 3615 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; 3616 3617 /* 3618 * Rsvd field masks for spte 3619 */ 3620 vtd_spte_rsvd[0] = ~0ULL; 3621 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, 3622 x86_iommu->dt_supported); 3623 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); 3624 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); 3625 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); 3626 3627 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, 3628 x86_iommu->dt_supported); 3629 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, 3630 x86_iommu->dt_supported); 3631 3632 if (x86_iommu_ir_supported(x86_iommu)) { 3633 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; 3634 if (s->intr_eim == ON_OFF_AUTO_ON) { 3635 s->ecap |= VTD_ECAP_EIM; 3636 } 3637 assert(s->intr_eim != ON_OFF_AUTO_AUTO); 3638 } 3639 3640 if (x86_iommu->dt_supported) { 3641 s->ecap |= VTD_ECAP_DT; 3642 } 3643 3644 if (x86_iommu->pt_supported) { 3645 s->ecap |= VTD_ECAP_PT; 3646 } 3647 3648 if (s->caching_mode) { 3649 s->cap |= VTD_CAP_CM; 3650 } 3651 3652 /* TODO: read cap/ecap from host to decide which cap to be exposed. */ 3653 if (s->scalable_mode) { 3654 s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; 3655 } 3656 3657 vtd_reset_caches(s); 3658 3659 /* Define registers with default values and bit semantics */ 3660 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0); 3661 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0); 3662 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0); 3663 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0); 3664 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL); 3665 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0); 3666 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffffc00ULL, 0); 3667 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0); 3668 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL); 3669 3670 /* Advanced Fault Logging not supported */ 3671 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL); 3672 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0); 3673 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0); 3674 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0); 3675 3676 /* Treated as RsvdZ when EIM in ECAP_REG is not supported 3677 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0); 3678 */ 3679 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0); 3680 3681 /* Treated as RO for implementations that PLMR and PHMR fields reported 3682 * as Clear in the CAP_REG. 3683 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0); 3684 */ 3685 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0); 3686 3687 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0); 3688 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0); 3689 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff807ULL, 0); 3690 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL); 3691 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0); 3692 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0); 3693 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0); 3694 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */ 3695 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0); 3696 3697 /* IOTLB registers */ 3698 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0); 3699 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0); 3700 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL); 3701 3702 /* Fault Recording Registers, 128-bit */ 3703 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0); 3704 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL); 3705 3706 /* 3707 * Interrupt remapping registers. 3708 */ 3709 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0); 3710 } 3711 3712 /* Should not reset address_spaces when reset because devices will still use 3713 * the address space they got at first (won't ask the bus again). 3714 */ 3715 static void vtd_reset(DeviceState *dev) 3716 { 3717 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); 3718 3719 vtd_init(s); 3720 vtd_address_space_refresh_all(s); 3721 } 3722 3723 static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 3724 { 3725 IntelIOMMUState *s = opaque; 3726 VTDAddressSpace *vtd_as; 3727 3728 assert(0 <= devfn && devfn < PCI_DEVFN_MAX); 3729 3730 vtd_as = vtd_find_add_as(s, bus, devfn); 3731 return &vtd_as->as; 3732 } 3733 3734 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) 3735 { 3736 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 3737 3738 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu_ir_supported(x86_iommu)) { 3739 error_setg(errp, "eim=on cannot be selected without intremap=on"); 3740 return false; 3741 } 3742 3743 if (s->intr_eim == ON_OFF_AUTO_AUTO) { 3744 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim) 3745 && x86_iommu_ir_supported(x86_iommu) ? 3746 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 3747 } 3748 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) { 3749 if (!kvm_irqchip_in_kernel()) { 3750 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split"); 3751 return false; 3752 } 3753 if (!kvm_enable_x2apic()) { 3754 error_setg(errp, "eim=on requires support on the KVM side" 3755 "(X2APIC_API, first shipped in v4.7)"); 3756 return false; 3757 } 3758 } 3759 3760 /* Currently only address widths supported are 39 and 48 bits */ 3761 if ((s->aw_bits != VTD_HOST_AW_39BIT) && 3762 (s->aw_bits != VTD_HOST_AW_48BIT)) { 3763 error_setg(errp, "Supported values for aw-bits are: %d, %d", 3764 VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); 3765 return false; 3766 } 3767 3768 if (s->scalable_mode && !s->dma_drain) { 3769 error_setg(errp, "Need to set dma_drain for scalable mode"); 3770 return false; 3771 } 3772 3773 return true; 3774 } 3775 3776 static int vtd_machine_done_notify_one(Object *child, void *unused) 3777 { 3778 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 3779 3780 /* 3781 * We hard-coded here because vfio-pci is the only special case 3782 * here. Let's be more elegant in the future when we can, but so 3783 * far there seems to be no better way. 3784 */ 3785 if (object_dynamic_cast(child, "vfio-pci") && !iommu->caching_mode) { 3786 vtd_panic_require_caching_mode(); 3787 } 3788 3789 return 0; 3790 } 3791 3792 static void vtd_machine_done_hook(Notifier *notifier, void *unused) 3793 { 3794 object_child_foreach_recursive(object_get_root(), 3795 vtd_machine_done_notify_one, NULL); 3796 } 3797 3798 static Notifier vtd_machine_done_notify = { 3799 .notify = vtd_machine_done_hook, 3800 }; 3801 3802 static void vtd_realize(DeviceState *dev, Error **errp) 3803 { 3804 MachineState *ms = MACHINE(qdev_get_machine()); 3805 PCMachineState *pcms = PC_MACHINE(ms); 3806 X86MachineState *x86ms = X86_MACHINE(ms); 3807 PCIBus *bus = pcms->bus; 3808 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); 3809 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); 3810 3811 x86_iommu->type = TYPE_INTEL; 3812 3813 if (!vtd_decide_config(s, errp)) { 3814 return; 3815 } 3816 3817 QLIST_INIT(&s->vtd_as_with_notifiers); 3818 qemu_mutex_init(&s->iommu_lock); 3819 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num)); 3820 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s, 3821 "intel_iommu", DMAR_REG_SIZE); 3822 3823 /* Create the shared memory regions by all devices */ 3824 memory_region_init(&s->mr_nodmar, OBJECT(s), "vtd-nodmar", 3825 UINT64_MAX); 3826 memory_region_init_io(&s->mr_ir, OBJECT(s), &vtd_mem_ir_ops, 3827 s, "vtd-ir", VTD_INTERRUPT_ADDR_SIZE); 3828 memory_region_init_alias(&s->mr_sys_alias, OBJECT(s), 3829 "vtd-sys-alias", get_system_memory(), 0, 3830 memory_region_size(get_system_memory())); 3831 memory_region_add_subregion_overlap(&s->mr_nodmar, 0, 3832 &s->mr_sys_alias, 0); 3833 memory_region_add_subregion_overlap(&s->mr_nodmar, 3834 VTD_INTERRUPT_ADDR_FIRST, 3835 &s->mr_ir, 1); 3836 3837 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem); 3838 /* No corresponding destroy */ 3839 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, 3840 g_free, g_free); 3841 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, 3842 g_free, g_free); 3843 vtd_init(s); 3844 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 3845 pci_setup_iommu(bus, vtd_host_dma_iommu, dev); 3846 /* Pseudo address space under root PCI bus. */ 3847 x86ms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC); 3848 qemu_add_machine_init_done_notifier(&vtd_machine_done_notify); 3849 } 3850 3851 static void vtd_class_init(ObjectClass *klass, void *data) 3852 { 3853 DeviceClass *dc = DEVICE_CLASS(klass); 3854 X86IOMMUClass *x86_class = X86_IOMMU_DEVICE_CLASS(klass); 3855 3856 dc->reset = vtd_reset; 3857 dc->vmsd = &vtd_vmstate; 3858 device_class_set_props(dc, vtd_properties); 3859 dc->hotpluggable = false; 3860 x86_class->realize = vtd_realize; 3861 x86_class->int_remap = vtd_int_remap; 3862 /* Supported by the pc-q35-* machine types */ 3863 dc->user_creatable = true; 3864 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3865 dc->desc = "Intel IOMMU (VT-d) DMA Remapping device"; 3866 } 3867 3868 static const TypeInfo vtd_info = { 3869 .name = TYPE_INTEL_IOMMU_DEVICE, 3870 .parent = TYPE_X86_IOMMU_DEVICE, 3871 .instance_size = sizeof(IntelIOMMUState), 3872 .class_init = vtd_class_init, 3873 }; 3874 3875 static void vtd_iommu_memory_region_class_init(ObjectClass *klass, 3876 void *data) 3877 { 3878 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 3879 3880 imrc->translate = vtd_iommu_translate; 3881 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed; 3882 imrc->replay = vtd_iommu_replay; 3883 } 3884 3885 static const TypeInfo vtd_iommu_memory_region_info = { 3886 .parent = TYPE_IOMMU_MEMORY_REGION, 3887 .name = TYPE_INTEL_IOMMU_MEMORY_REGION, 3888 .class_init = vtd_iommu_memory_region_class_init, 3889 }; 3890 3891 static void vtd_register_types(void) 3892 { 3893 type_register_static(&vtd_info); 3894 type_register_static(&vtd_iommu_memory_region_info); 3895 } 3896 3897 type_init(vtd_register_types) 3898