xref: /openbmc/qemu/hw/i386/intel_iommu.c (revision cb135f59b8059c3a372652377ef92fa4a49ad550)
1 /*
2  * QEMU emulation of an Intel IOMMU (VT-d)
3  *   (DMA Remapping device)
4  *
5  * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6  * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12 
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17 
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "exec/address-spaces.h"
25 #include "intel_iommu_internal.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/i386/pc.h"
29 #include "hw/boards.h"
30 #include "hw/i386/x86-iommu.h"
31 #include "hw/pci-host/q35.h"
32 
33 /*#define DEBUG_INTEL_IOMMU*/
34 #ifdef DEBUG_INTEL_IOMMU
35 enum {
36     DEBUG_GENERAL, DEBUG_CSR, DEBUG_INV, DEBUG_MMU, DEBUG_FLOG,
37     DEBUG_CACHE, DEBUG_IR,
38 };
39 #define VTD_DBGBIT(x)   (1 << DEBUG_##x)
40 static int vtd_dbgflags = VTD_DBGBIT(GENERAL) | VTD_DBGBIT(CSR);
41 
42 #define VTD_DPRINTF(what, fmt, ...) do { \
43     if (vtd_dbgflags & VTD_DBGBIT(what)) { \
44         fprintf(stderr, "(vtd)%s: " fmt "\n", __func__, \
45                 ## __VA_ARGS__); } \
46     } while (0)
47 #else
48 #define VTD_DPRINTF(what, fmt, ...) do {} while (0)
49 #endif
50 
51 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
52                             uint64_t wmask, uint64_t w1cmask)
53 {
54     stq_le_p(&s->csr[addr], val);
55     stq_le_p(&s->wmask[addr], wmask);
56     stq_le_p(&s->w1cmask[addr], w1cmask);
57 }
58 
59 static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
60 {
61     stq_le_p(&s->womask[addr], mask);
62 }
63 
64 static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
65                             uint32_t wmask, uint32_t w1cmask)
66 {
67     stl_le_p(&s->csr[addr], val);
68     stl_le_p(&s->wmask[addr], wmask);
69     stl_le_p(&s->w1cmask[addr], w1cmask);
70 }
71 
72 static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
73 {
74     stl_le_p(&s->womask[addr], mask);
75 }
76 
77 /* "External" get/set operations */
78 static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
79 {
80     uint64_t oldval = ldq_le_p(&s->csr[addr]);
81     uint64_t wmask = ldq_le_p(&s->wmask[addr]);
82     uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
83     stq_le_p(&s->csr[addr],
84              ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
85 }
86 
87 static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
88 {
89     uint32_t oldval = ldl_le_p(&s->csr[addr]);
90     uint32_t wmask = ldl_le_p(&s->wmask[addr]);
91     uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
92     stl_le_p(&s->csr[addr],
93              ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
94 }
95 
96 static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
97 {
98     uint64_t val = ldq_le_p(&s->csr[addr]);
99     uint64_t womask = ldq_le_p(&s->womask[addr]);
100     return val & ~womask;
101 }
102 
103 static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
104 {
105     uint32_t val = ldl_le_p(&s->csr[addr]);
106     uint32_t womask = ldl_le_p(&s->womask[addr]);
107     return val & ~womask;
108 }
109 
110 /* "Internal" get/set operations */
111 static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
112 {
113     return ldq_le_p(&s->csr[addr]);
114 }
115 
116 static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
117 {
118     return ldl_le_p(&s->csr[addr]);
119 }
120 
121 static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
122 {
123     stq_le_p(&s->csr[addr], val);
124 }
125 
126 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
127                                         uint32_t clear, uint32_t mask)
128 {
129     uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
130     stl_le_p(&s->csr[addr], new_val);
131     return new_val;
132 }
133 
134 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
135                                         uint64_t clear, uint64_t mask)
136 {
137     uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
138     stq_le_p(&s->csr[addr], new_val);
139     return new_val;
140 }
141 
142 /* GHashTable functions */
143 static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
144 {
145     return *((const uint64_t *)v1) == *((const uint64_t *)v2);
146 }
147 
148 static guint vtd_uint64_hash(gconstpointer v)
149 {
150     return (guint)*(const uint64_t *)v;
151 }
152 
153 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
154                                           gpointer user_data)
155 {
156     VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
157     uint16_t domain_id = *(uint16_t *)user_data;
158     return entry->domain_id == domain_id;
159 }
160 
161 /* The shift of an addr for a certain level of paging structure */
162 static inline uint32_t vtd_slpt_level_shift(uint32_t level)
163 {
164     return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
165 }
166 
167 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
168 {
169     return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
170 }
171 
172 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
173                                         gpointer user_data)
174 {
175     VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
176     VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
177     uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
178     uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
179     return (entry->domain_id == info->domain_id) &&
180             (((entry->gfn & info->mask) == gfn) ||
181              (entry->gfn == gfn_tlb));
182 }
183 
184 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
185  * IntelIOMMUState to 1.
186  */
187 static void vtd_reset_context_cache(IntelIOMMUState *s)
188 {
189     VTDAddressSpace *vtd_as;
190     VTDBus *vtd_bus;
191     GHashTableIter bus_it;
192     uint32_t devfn_it;
193 
194     g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
195 
196     VTD_DPRINTF(CACHE, "global context_cache_gen=1");
197     while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
198         for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
199             vtd_as = vtd_bus->dev_as[devfn_it];
200             if (!vtd_as) {
201                 continue;
202             }
203             vtd_as->context_cache_entry.context_cache_gen = 0;
204         }
205     }
206     s->context_cache_gen = 1;
207 }
208 
209 static void vtd_reset_iotlb(IntelIOMMUState *s)
210 {
211     assert(s->iotlb);
212     g_hash_table_remove_all(s->iotlb);
213 }
214 
215 static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint8_t source_id,
216                                   uint32_t level)
217 {
218     return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
219            ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
220 }
221 
222 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
223 {
224     return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
225 }
226 
227 static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
228                                        hwaddr addr)
229 {
230     VTDIOTLBEntry *entry;
231     uint64_t key;
232     int level;
233 
234     for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
235         key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
236                                 source_id, level);
237         entry = g_hash_table_lookup(s->iotlb, &key);
238         if (entry) {
239             goto out;
240         }
241     }
242 
243 out:
244     return entry;
245 }
246 
247 static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
248                              uint16_t domain_id, hwaddr addr, uint64_t slpte,
249                              bool read_flags, bool write_flags,
250                              uint32_t level)
251 {
252     VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
253     uint64_t *key = g_malloc(sizeof(*key));
254     uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
255 
256     VTD_DPRINTF(CACHE, "update iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64
257                 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr, slpte,
258                 domain_id);
259     if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
260         VTD_DPRINTF(CACHE, "iotlb exceeds size limit, forced to reset");
261         vtd_reset_iotlb(s);
262     }
263 
264     entry->gfn = gfn;
265     entry->domain_id = domain_id;
266     entry->slpte = slpte;
267     entry->read_flags = read_flags;
268     entry->write_flags = write_flags;
269     entry->mask = vtd_slpt_level_page_mask(level);
270     *key = vtd_get_iotlb_key(gfn, source_id, level);
271     g_hash_table_replace(s->iotlb, key, entry);
272 }
273 
274 /* Given the reg addr of both the message data and address, generate an
275  * interrupt via MSI.
276  */
277 static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
278                                    hwaddr mesg_data_reg)
279 {
280     hwaddr addr;
281     uint32_t data;
282 
283     assert(mesg_data_reg < DMAR_REG_SIZE);
284     assert(mesg_addr_reg < DMAR_REG_SIZE);
285 
286     addr = vtd_get_long_raw(s, mesg_addr_reg);
287     data = vtd_get_long_raw(s, mesg_data_reg);
288 
289     VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, addr, data);
290     address_space_stl_le(&address_space_memory, addr, data,
291                          MEMTXATTRS_UNSPECIFIED, NULL);
292 }
293 
294 /* Generate a fault event to software via MSI if conditions are met.
295  * Notice that the value of FSTS_REG being passed to it should be the one
296  * before any update.
297  */
298 static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
299 {
300     if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
301         pre_fsts & VTD_FSTS_IQE) {
302         VTD_DPRINTF(FLOG, "there are previous interrupt conditions "
303                     "to be serviced by software, fault event is not generated "
304                     "(FSTS_REG 0x%"PRIx32 ")", pre_fsts);
305         return;
306     }
307     vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
308     if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
309         VTD_DPRINTF(FLOG, "Interrupt Mask set, fault event is not generated");
310     } else {
311         vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
312         vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
313     }
314 }
315 
316 /* Check if the Fault (F) field of the Fault Recording Register referenced by
317  * @index is Set.
318  */
319 static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
320 {
321     /* Each reg is 128-bit */
322     hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
323     addr += 8; /* Access the high 64-bit half */
324 
325     assert(index < DMAR_FRCD_REG_NR);
326 
327     return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
328 }
329 
330 /* Update the PPF field of Fault Status Register.
331  * Should be called whenever change the F field of any fault recording
332  * registers.
333  */
334 static void vtd_update_fsts_ppf(IntelIOMMUState *s)
335 {
336     uint32_t i;
337     uint32_t ppf_mask = 0;
338 
339     for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
340         if (vtd_is_frcd_set(s, i)) {
341             ppf_mask = VTD_FSTS_PPF;
342             break;
343         }
344     }
345     vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
346     VTD_DPRINTF(FLOG, "set PPF of FSTS_REG to %d", ppf_mask ? 1 : 0);
347 }
348 
349 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
350 {
351     /* Each reg is 128-bit */
352     hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
353     addr += 8; /* Access the high 64-bit half */
354 
355     assert(index < DMAR_FRCD_REG_NR);
356 
357     vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
358     vtd_update_fsts_ppf(s);
359 }
360 
361 /* Must not update F field now, should be done later */
362 static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
363                             uint16_t source_id, hwaddr addr,
364                             VTDFaultReason fault, bool is_write)
365 {
366     uint64_t hi = 0, lo;
367     hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
368 
369     assert(index < DMAR_FRCD_REG_NR);
370 
371     lo = VTD_FRCD_FI(addr);
372     hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
373     if (!is_write) {
374         hi |= VTD_FRCD_T;
375     }
376     vtd_set_quad_raw(s, frcd_reg_addr, lo);
377     vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
378     VTD_DPRINTF(FLOG, "record to FRCD_REG #%"PRIu16 ": hi 0x%"PRIx64
379                 ", lo 0x%"PRIx64, index, hi, lo);
380 }
381 
382 /* Try to collapse multiple pending faults from the same requester */
383 static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
384 {
385     uint32_t i;
386     uint64_t frcd_reg;
387     hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
388 
389     for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
390         frcd_reg = vtd_get_quad_raw(s, addr);
391         VTD_DPRINTF(FLOG, "frcd_reg #%d 0x%"PRIx64, i, frcd_reg);
392         if ((frcd_reg & VTD_FRCD_F) &&
393             ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
394             return true;
395         }
396         addr += 16; /* 128-bit for each */
397     }
398     return false;
399 }
400 
401 /* Log and report an DMAR (address translation) fault to software */
402 static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
403                                   hwaddr addr, VTDFaultReason fault,
404                                   bool is_write)
405 {
406     uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
407 
408     assert(fault < VTD_FR_MAX);
409 
410     if (fault == VTD_FR_RESERVED_ERR) {
411         /* This is not a normal fault reason case. Drop it. */
412         return;
413     }
414     VTD_DPRINTF(FLOG, "sid 0x%"PRIx16 ", fault %d, addr 0x%"PRIx64
415                 ", is_write %d", source_id, fault, addr, is_write);
416     if (fsts_reg & VTD_FSTS_PFO) {
417         VTD_DPRINTF(FLOG, "new fault is not recorded due to "
418                     "Primary Fault Overflow");
419         return;
420     }
421     if (vtd_try_collapse_fault(s, source_id)) {
422         VTD_DPRINTF(FLOG, "new fault is not recorded due to "
423                     "compression of faults");
424         return;
425     }
426     if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
427         VTD_DPRINTF(FLOG, "Primary Fault Overflow and "
428                     "new fault is not recorded, set PFO field");
429         vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
430         return;
431     }
432 
433     vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
434 
435     if (fsts_reg & VTD_FSTS_PPF) {
436         VTD_DPRINTF(FLOG, "there are pending faults already, "
437                     "fault event is not generated");
438         vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
439         s->next_frcd_reg++;
440         if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
441             s->next_frcd_reg = 0;
442         }
443     } else {
444         vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
445                                 VTD_FSTS_FRI(s->next_frcd_reg));
446         vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
447         s->next_frcd_reg++;
448         if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
449             s->next_frcd_reg = 0;
450         }
451         /* This case actually cause the PPF to be Set.
452          * So generate fault event (interrupt).
453          */
454          vtd_generate_fault_event(s, fsts_reg);
455     }
456 }
457 
458 /* Handle Invalidation Queue Errors of queued invalidation interface error
459  * conditions.
460  */
461 static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
462 {
463     uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
464 
465     vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
466     vtd_generate_fault_event(s, fsts_reg);
467 }
468 
469 /* Set the IWC field and try to generate an invalidation completion interrupt */
470 static void vtd_generate_completion_event(IntelIOMMUState *s)
471 {
472     VTD_DPRINTF(INV, "completes an invalidation wait command with "
473                 "Interrupt Flag");
474     if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
475         VTD_DPRINTF(INV, "there is a previous interrupt condition to be "
476                     "serviced by software, "
477                     "new invalidation event is not generated");
478         return;
479     }
480     vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
481     vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
482     if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
483         VTD_DPRINTF(INV, "IM filed in IECTL_REG is set, new invalidation "
484                     "event is not generated");
485         return;
486     } else {
487         /* Generate the interrupt event */
488         vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
489         vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
490     }
491 }
492 
493 static inline bool vtd_root_entry_present(VTDRootEntry *root)
494 {
495     return root->val & VTD_ROOT_ENTRY_P;
496 }
497 
498 static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
499                               VTDRootEntry *re)
500 {
501     dma_addr_t addr;
502 
503     addr = s->root + index * sizeof(*re);
504     if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
505         VTD_DPRINTF(GENERAL, "error: fail to access root-entry at 0x%"PRIx64
506                     " + %"PRIu8, s->root, index);
507         re->val = 0;
508         return -VTD_FR_ROOT_TABLE_INV;
509     }
510     re->val = le64_to_cpu(re->val);
511     return 0;
512 }
513 
514 static inline bool vtd_context_entry_present(VTDContextEntry *context)
515 {
516     return context->lo & VTD_CONTEXT_ENTRY_P;
517 }
518 
519 static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
520                                            VTDContextEntry *ce)
521 {
522     dma_addr_t addr;
523 
524     if (!vtd_root_entry_present(root)) {
525         VTD_DPRINTF(GENERAL, "error: root-entry is not present");
526         return -VTD_FR_ROOT_ENTRY_P;
527     }
528     addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
529     if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
530         VTD_DPRINTF(GENERAL, "error: fail to access context-entry at 0x%"PRIx64
531                     " + %"PRIu8,
532                     (uint64_t)(root->val & VTD_ROOT_ENTRY_CTP), index);
533         return -VTD_FR_CONTEXT_TABLE_INV;
534     }
535     ce->lo = le64_to_cpu(ce->lo);
536     ce->hi = le64_to_cpu(ce->hi);
537     return 0;
538 }
539 
540 static inline dma_addr_t vtd_get_slpt_base_from_context(VTDContextEntry *ce)
541 {
542     return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
543 }
544 
545 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte)
546 {
547     return slpte & VTD_SL_PT_BASE_ADDR_MASK;
548 }
549 
550 /* Whether the pte indicates the address of the page frame */
551 static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
552 {
553     return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
554 }
555 
556 /* Get the content of a spte located in @base_addr[@index] */
557 static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
558 {
559     uint64_t slpte;
560 
561     assert(index < VTD_SL_PT_ENTRY_NR);
562 
563     if (dma_memory_read(&address_space_memory,
564                         base_addr + index * sizeof(slpte), &slpte,
565                         sizeof(slpte))) {
566         slpte = (uint64_t)-1;
567         return slpte;
568     }
569     slpte = le64_to_cpu(slpte);
570     return slpte;
571 }
572 
573 /* Given a gpa and the level of paging structure, return the offset of current
574  * level.
575  */
576 static inline uint32_t vtd_gpa_level_offset(uint64_t gpa, uint32_t level)
577 {
578     return (gpa >> vtd_slpt_level_shift(level)) &
579             ((1ULL << VTD_SL_LEVEL_BITS) - 1);
580 }
581 
582 /* Check Capability Register to see if the @level of page-table is supported */
583 static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
584 {
585     return VTD_CAP_SAGAW_MASK & s->cap &
586            (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
587 }
588 
589 /* Get the page-table level that hardware should use for the second-level
590  * page-table walk from the Address Width field of context-entry.
591  */
592 static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *ce)
593 {
594     return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
595 }
596 
597 static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce)
598 {
599     return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
600 }
601 
602 static const uint64_t vtd_paging_entry_rsvd_field[] = {
603     [0] = ~0ULL,
604     /* For not large page */
605     [1] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
606     [2] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
607     [3] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
608     [4] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
609     /* For large page */
610     [5] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
611     [6] = 0x1ff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
612     [7] = 0x3ffff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
613     [8] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
614 };
615 
616 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
617 {
618     if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
619         /* Maybe large page */
620         return slpte & vtd_paging_entry_rsvd_field[level + 4];
621     } else {
622         return slpte & vtd_paging_entry_rsvd_field[level];
623     }
624 }
625 
626 /* Given the @gpa, get relevant @slptep. @slpte_level will be the last level
627  * of the translation, can be used for deciding the size of large page.
628  */
629 static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64_t gpa, bool is_write,
630                             uint64_t *slptep, uint32_t *slpte_level,
631                             bool *reads, bool *writes)
632 {
633     dma_addr_t addr = vtd_get_slpt_base_from_context(ce);
634     uint32_t level = vtd_get_level_from_context_entry(ce);
635     uint32_t offset;
636     uint64_t slpte;
637     uint32_t ce_agaw = vtd_get_agaw_from_context_entry(ce);
638     uint64_t access_right_check;
639 
640     /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP_REG
641      * and AW in context-entry.
642      */
643     if (gpa & ~((1ULL << MIN(ce_agaw, VTD_MGAW)) - 1)) {
644         VTD_DPRINTF(GENERAL, "error: gpa 0x%"PRIx64 " exceeds limits", gpa);
645         return -VTD_FR_ADDR_BEYOND_MGAW;
646     }
647 
648     /* FIXME: what is the Atomics request here? */
649     access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
650 
651     while (true) {
652         offset = vtd_gpa_level_offset(gpa, level);
653         slpte = vtd_get_slpte(addr, offset);
654 
655         if (slpte == (uint64_t)-1) {
656             VTD_DPRINTF(GENERAL, "error: fail to access second-level paging "
657                         "entry at level %"PRIu32 " for gpa 0x%"PRIx64,
658                         level, gpa);
659             if (level == vtd_get_level_from_context_entry(ce)) {
660                 /* Invalid programming of context-entry */
661                 return -VTD_FR_CONTEXT_ENTRY_INV;
662             } else {
663                 return -VTD_FR_PAGING_ENTRY_INV;
664             }
665         }
666         *reads = (*reads) && (slpte & VTD_SL_R);
667         *writes = (*writes) && (slpte & VTD_SL_W);
668         if (!(slpte & access_right_check)) {
669             VTD_DPRINTF(GENERAL, "error: lack of %s permission for "
670                         "gpa 0x%"PRIx64 " slpte 0x%"PRIx64,
671                         (is_write ? "write" : "read"), gpa, slpte);
672             return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
673         }
674         if (vtd_slpte_nonzero_rsvd(slpte, level)) {
675             VTD_DPRINTF(GENERAL, "error: non-zero reserved field in second "
676                         "level paging entry level %"PRIu32 " slpte 0x%"PRIx64,
677                         level, slpte);
678             return -VTD_FR_PAGING_ENTRY_RSVD;
679         }
680 
681         if (vtd_is_last_slpte(slpte, level)) {
682             *slptep = slpte;
683             *slpte_level = level;
684             return 0;
685         }
686         addr = vtd_get_slpte_addr(slpte);
687         level--;
688     }
689 }
690 
691 /* Map a device to its corresponding domain (context-entry) */
692 static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
693                                     uint8_t devfn, VTDContextEntry *ce)
694 {
695     VTDRootEntry re;
696     int ret_fr;
697 
698     ret_fr = vtd_get_root_entry(s, bus_num, &re);
699     if (ret_fr) {
700         return ret_fr;
701     }
702 
703     if (!vtd_root_entry_present(&re)) {
704         VTD_DPRINTF(GENERAL, "error: root-entry #%"PRIu8 " is not present",
705                     bus_num);
706         return -VTD_FR_ROOT_ENTRY_P;
707     } else if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) {
708         VTD_DPRINTF(GENERAL, "error: non-zero reserved field in root-entry "
709                     "hi 0x%"PRIx64 " lo 0x%"PRIx64, re.rsvd, re.val);
710         return -VTD_FR_ROOT_ENTRY_RSVD;
711     }
712 
713     ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
714     if (ret_fr) {
715         return ret_fr;
716     }
717 
718     if (!vtd_context_entry_present(ce)) {
719         VTD_DPRINTF(GENERAL,
720                     "error: context-entry #%"PRIu8 "(bus #%"PRIu8 ") "
721                     "is not present", devfn, bus_num);
722         return -VTD_FR_CONTEXT_ENTRY_P;
723     } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
724                (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) {
725         VTD_DPRINTF(GENERAL,
726                     "error: non-zero reserved field in context-entry "
727                     "hi 0x%"PRIx64 " lo 0x%"PRIx64, ce->hi, ce->lo);
728         return -VTD_FR_CONTEXT_ENTRY_RSVD;
729     }
730     /* Check if the programming of context-entry is valid */
731     if (!vtd_is_level_supported(s, vtd_get_level_from_context_entry(ce))) {
732         VTD_DPRINTF(GENERAL, "error: unsupported Address Width value in "
733                     "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,
734                     ce->hi, ce->lo);
735         return -VTD_FR_CONTEXT_ENTRY_INV;
736     } else if (ce->lo & VTD_CONTEXT_ENTRY_TT) {
737         VTD_DPRINTF(GENERAL, "error: unsupported Translation Type in "
738                     "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,
739                     ce->hi, ce->lo);
740         return -VTD_FR_CONTEXT_ENTRY_INV;
741     }
742     return 0;
743 }
744 
745 static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
746 {
747     return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
748 }
749 
750 static const bool vtd_qualified_faults[] = {
751     [VTD_FR_RESERVED] = false,
752     [VTD_FR_ROOT_ENTRY_P] = false,
753     [VTD_FR_CONTEXT_ENTRY_P] = true,
754     [VTD_FR_CONTEXT_ENTRY_INV] = true,
755     [VTD_FR_ADDR_BEYOND_MGAW] = true,
756     [VTD_FR_WRITE] = true,
757     [VTD_FR_READ] = true,
758     [VTD_FR_PAGING_ENTRY_INV] = true,
759     [VTD_FR_ROOT_TABLE_INV] = false,
760     [VTD_FR_CONTEXT_TABLE_INV] = false,
761     [VTD_FR_ROOT_ENTRY_RSVD] = false,
762     [VTD_FR_PAGING_ENTRY_RSVD] = true,
763     [VTD_FR_CONTEXT_ENTRY_TT] = true,
764     [VTD_FR_RESERVED_ERR] = false,
765     [VTD_FR_MAX] = false,
766 };
767 
768 /* To see if a fault condition is "qualified", which is reported to software
769  * only if the FPD field in the context-entry used to process the faulting
770  * request is 0.
771  */
772 static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
773 {
774     return vtd_qualified_faults[fault];
775 }
776 
777 static inline bool vtd_is_interrupt_addr(hwaddr addr)
778 {
779     return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
780 }
781 
782 /* Map dev to context-entry then do a paging-structures walk to do a iommu
783  * translation.
784  *
785  * Called from RCU critical section.
786  *
787  * @bus_num: The bus number
788  * @devfn: The devfn, which is the  combined of device and function number
789  * @is_write: The access is a write operation
790  * @entry: IOMMUTLBEntry that contain the addr to be translated and result
791  */
792 static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
793                                    uint8_t devfn, hwaddr addr, bool is_write,
794                                    IOMMUTLBEntry *entry)
795 {
796     IntelIOMMUState *s = vtd_as->iommu_state;
797     VTDContextEntry ce;
798     uint8_t bus_num = pci_bus_num(bus);
799     VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
800     uint64_t slpte, page_mask;
801     uint32_t level;
802     uint16_t source_id = vtd_make_source_id(bus_num, devfn);
803     int ret_fr;
804     bool is_fpd_set = false;
805     bool reads = true;
806     bool writes = true;
807     VTDIOTLBEntry *iotlb_entry;
808 
809     /* Check if the request is in interrupt address range */
810     if (vtd_is_interrupt_addr(addr)) {
811         if (is_write) {
812             /* FIXME: since we don't know the length of the access here, we
813              * treat Non-DWORD length write requests without PASID as
814              * interrupt requests, too. Withoud interrupt remapping support,
815              * we just use 1:1 mapping.
816              */
817             VTD_DPRINTF(MMU, "write request to interrupt address "
818                         "gpa 0x%"PRIx64, addr);
819             entry->iova = addr & VTD_PAGE_MASK_4K;
820             entry->translated_addr = addr & VTD_PAGE_MASK_4K;
821             entry->addr_mask = ~VTD_PAGE_MASK_4K;
822             entry->perm = IOMMU_WO;
823             return;
824         } else {
825             VTD_DPRINTF(GENERAL, "error: read request from interrupt address "
826                         "gpa 0x%"PRIx64, addr);
827             vtd_report_dmar_fault(s, source_id, addr, VTD_FR_READ, is_write);
828             return;
829         }
830     }
831     /* Try to fetch slpte form IOTLB */
832     iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
833     if (iotlb_entry) {
834         VTD_DPRINTF(CACHE, "hit iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64
835                     " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr,
836                     iotlb_entry->slpte, iotlb_entry->domain_id);
837         slpte = iotlb_entry->slpte;
838         reads = iotlb_entry->read_flags;
839         writes = iotlb_entry->write_flags;
840         page_mask = iotlb_entry->mask;
841         goto out;
842     }
843     /* Try to fetch context-entry from cache first */
844     if (cc_entry->context_cache_gen == s->context_cache_gen) {
845         VTD_DPRINTF(CACHE, "hit context-cache bus %d devfn %d "
846                     "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 ")",
847                     bus_num, devfn, cc_entry->context_entry.hi,
848                     cc_entry->context_entry.lo, cc_entry->context_cache_gen);
849         ce = cc_entry->context_entry;
850         is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
851     } else {
852         ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
853         is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
854         if (ret_fr) {
855             ret_fr = -ret_fr;
856             if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
857                 VTD_DPRINTF(FLOG, "fault processing is disabled for DMA "
858                             "requests through this context-entry "
859                             "(with FPD Set)");
860             } else {
861                 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
862             }
863             return;
864         }
865         /* Update context-cache */
866         VTD_DPRINTF(CACHE, "update context-cache bus %d devfn %d "
867                     "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 "->%"PRIu32 ")",
868                     bus_num, devfn, ce.hi, ce.lo,
869                     cc_entry->context_cache_gen, s->context_cache_gen);
870         cc_entry->context_entry = ce;
871         cc_entry->context_cache_gen = s->context_cache_gen;
872     }
873 
874     ret_fr = vtd_gpa_to_slpte(&ce, addr, is_write, &slpte, &level,
875                               &reads, &writes);
876     if (ret_fr) {
877         ret_fr = -ret_fr;
878         if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
879             VTD_DPRINTF(FLOG, "fault processing is disabled for DMA requests "
880                         "through this context-entry (with FPD Set)");
881         } else {
882             vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
883         }
884         return;
885     }
886 
887     page_mask = vtd_slpt_level_page_mask(level);
888     vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
889                      reads, writes, level);
890 out:
891     entry->iova = addr & page_mask;
892     entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
893     entry->addr_mask = ~page_mask;
894     entry->perm = (writes ? 2 : 0) + (reads ? 1 : 0);
895 }
896 
897 static void vtd_root_table_setup(IntelIOMMUState *s)
898 {
899     s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
900     s->root_extended = s->root & VTD_RTADDR_RTT;
901     s->root &= VTD_RTADDR_ADDR_MASK;
902 
903     VTD_DPRINTF(CSR, "root_table addr 0x%"PRIx64 " %s", s->root,
904                 (s->root_extended ? "(extended)" : ""));
905 }
906 
907 static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
908 {
909     uint64_t value = 0;
910     value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
911     s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
912     s->intr_root = value & VTD_IRTA_ADDR_MASK;
913 
914     /* TODO: invalidate interrupt entry cache */
915 
916     VTD_DPRINTF(CSR, "int remap table addr 0x%"PRIx64 " size %"PRIu32,
917                 s->intr_root, s->intr_size);
918 }
919 
920 static void vtd_context_global_invalidate(IntelIOMMUState *s)
921 {
922     s->context_cache_gen++;
923     if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
924         vtd_reset_context_cache(s);
925     }
926 }
927 
928 
929 /* Find the VTD address space currently associated with a given bus number,
930  */
931 static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
932 {
933     VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
934     if (!vtd_bus) {
935         /* Iterate over the registered buses to find the one
936          * which currently hold this bus number, and update the bus_num lookup table:
937          */
938         GHashTableIter iter;
939 
940         g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
941         while (g_hash_table_iter_next (&iter, NULL, (void**)&vtd_bus)) {
942             if (pci_bus_num(vtd_bus->bus) == bus_num) {
943                 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
944                 return vtd_bus;
945             }
946         }
947     }
948     return vtd_bus;
949 }
950 
951 /* Do a context-cache device-selective invalidation.
952  * @func_mask: FM field after shifting
953  */
954 static void vtd_context_device_invalidate(IntelIOMMUState *s,
955                                           uint16_t source_id,
956                                           uint16_t func_mask)
957 {
958     uint16_t mask;
959     VTDBus *vtd_bus;
960     VTDAddressSpace *vtd_as;
961     uint16_t devfn;
962     uint16_t devfn_it;
963 
964     switch (func_mask & 3) {
965     case 0:
966         mask = 0;   /* No bits in the SID field masked */
967         break;
968     case 1:
969         mask = 4;   /* Mask bit 2 in the SID field */
970         break;
971     case 2:
972         mask = 6;   /* Mask bit 2:1 in the SID field */
973         break;
974     case 3:
975         mask = 7;   /* Mask bit 2:0 in the SID field */
976         break;
977     }
978     VTD_DPRINTF(INV, "device-selective invalidation source 0x%"PRIx16
979                     " mask %"PRIu16, source_id, mask);
980     vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
981     if (vtd_bus) {
982         devfn = VTD_SID_TO_DEVFN(source_id);
983         for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
984             vtd_as = vtd_bus->dev_as[devfn_it];
985             if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
986                 VTD_DPRINTF(INV, "invalidate context-cahce of devfn 0x%"PRIx16,
987                             devfn_it);
988                 vtd_as->context_cache_entry.context_cache_gen = 0;
989             }
990         }
991     }
992 }
993 
994 /* Context-cache invalidation
995  * Returns the Context Actual Invalidation Granularity.
996  * @val: the content of the CCMD_REG
997  */
998 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
999 {
1000     uint64_t caig;
1001     uint64_t type = val & VTD_CCMD_CIRG_MASK;
1002 
1003     switch (type) {
1004     case VTD_CCMD_DOMAIN_INVL:
1005         VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1006                     (uint16_t)VTD_CCMD_DID(val));
1007         /* Fall through */
1008     case VTD_CCMD_GLOBAL_INVL:
1009         VTD_DPRINTF(INV, "global invalidation");
1010         caig = VTD_CCMD_GLOBAL_INVL_A;
1011         vtd_context_global_invalidate(s);
1012         break;
1013 
1014     case VTD_CCMD_DEVICE_INVL:
1015         caig = VTD_CCMD_DEVICE_INVL_A;
1016         vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1017         break;
1018 
1019     default:
1020         VTD_DPRINTF(GENERAL, "error: invalid granularity");
1021         caig = 0;
1022     }
1023     return caig;
1024 }
1025 
1026 static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1027 {
1028     vtd_reset_iotlb(s);
1029 }
1030 
1031 static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1032 {
1033     g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1034                                 &domain_id);
1035 }
1036 
1037 static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1038                                       hwaddr addr, uint8_t am)
1039 {
1040     VTDIOTLBPageInvInfo info;
1041 
1042     assert(am <= VTD_MAMV);
1043     info.domain_id = domain_id;
1044     info.addr = addr;
1045     info.mask = ~((1 << am) - 1);
1046     g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
1047 }
1048 
1049 /* Flush IOTLB
1050  * Returns the IOTLB Actual Invalidation Granularity.
1051  * @val: the content of the IOTLB_REG
1052  */
1053 static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1054 {
1055     uint64_t iaig;
1056     uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
1057     uint16_t domain_id;
1058     hwaddr addr;
1059     uint8_t am;
1060 
1061     switch (type) {
1062     case VTD_TLB_GLOBAL_FLUSH:
1063         VTD_DPRINTF(INV, "global invalidation");
1064         iaig = VTD_TLB_GLOBAL_FLUSH_A;
1065         vtd_iotlb_global_invalidate(s);
1066         break;
1067 
1068     case VTD_TLB_DSI_FLUSH:
1069         domain_id = VTD_TLB_DID(val);
1070         VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1071                     domain_id);
1072         iaig = VTD_TLB_DSI_FLUSH_A;
1073         vtd_iotlb_domain_invalidate(s, domain_id);
1074         break;
1075 
1076     case VTD_TLB_PSI_FLUSH:
1077         domain_id = VTD_TLB_DID(val);
1078         addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1079         am = VTD_IVA_AM(addr);
1080         addr = VTD_IVA_ADDR(addr);
1081         VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1082                     " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1083         if (am > VTD_MAMV) {
1084             VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1085                         "%"PRIu8, (uint8_t)VTD_MAMV);
1086             iaig = 0;
1087             break;
1088         }
1089         iaig = VTD_TLB_PSI_FLUSH_A;
1090         vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1091         break;
1092 
1093     default:
1094         VTD_DPRINTF(GENERAL, "error: invalid granularity");
1095         iaig = 0;
1096     }
1097     return iaig;
1098 }
1099 
1100 static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s)
1101 {
1102     return s->iq_tail == 0;
1103 }
1104 
1105 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1106 {
1107     return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1108            (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1109 }
1110 
1111 static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1112 {
1113     uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1114 
1115     VTD_DPRINTF(INV, "Queued Invalidation Enable %s", (en ? "on" : "off"));
1116     if (en) {
1117         if (vtd_queued_inv_enable_check(s)) {
1118             s->iq = iqa_val & VTD_IQA_IQA_MASK;
1119             /* 2^(x+8) entries */
1120             s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1121             s->qi_enabled = true;
1122             VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val);
1123             VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d",
1124                         s->iq, s->iq_size);
1125             /* Ok - report back to driver */
1126             vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1127         } else {
1128             VTD_DPRINTF(GENERAL, "error: can't enable Queued Invalidation: "
1129                         "tail %"PRIu16, s->iq_tail);
1130         }
1131     } else {
1132         if (vtd_queued_inv_disable_check(s)) {
1133             /* disable Queued Invalidation */
1134             vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1135             s->iq_head = 0;
1136             s->qi_enabled = false;
1137             /* Ok - report back to driver */
1138             vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1139         } else {
1140             VTD_DPRINTF(GENERAL, "error: can't disable Queued Invalidation: "
1141                         "head %"PRIu16 ", tail %"PRIu16
1142                         ", last_descriptor %"PRIu8,
1143                         s->iq_head, s->iq_tail, s->iq_last_desc_type);
1144         }
1145     }
1146 }
1147 
1148 /* Set Root Table Pointer */
1149 static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1150 {
1151     VTD_DPRINTF(CSR, "set Root Table Pointer");
1152 
1153     vtd_root_table_setup(s);
1154     /* Ok - report back to driver */
1155     vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1156 }
1157 
1158 /* Set Interrupt Remap Table Pointer */
1159 static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1160 {
1161     VTD_DPRINTF(CSR, "set Interrupt Remap Table Pointer");
1162 
1163     vtd_interrupt_remap_table_setup(s);
1164     /* Ok - report back to driver */
1165     vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1166 }
1167 
1168 /* Handle Translation Enable/Disable */
1169 static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1170 {
1171     VTD_DPRINTF(CSR, "Translation Enable %s", (en ? "on" : "off"));
1172 
1173     if (en) {
1174         s->dmar_enabled = true;
1175         /* Ok - report back to driver */
1176         vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1177     } else {
1178         s->dmar_enabled = false;
1179 
1180         /* Clear the index of Fault Recording Register */
1181         s->next_frcd_reg = 0;
1182         /* Ok - report back to driver */
1183         vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1184     }
1185 }
1186 
1187 /* Handle Interrupt Remap Enable/Disable */
1188 static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1189 {
1190     VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
1191 
1192     if (en) {
1193         s->intr_enabled = true;
1194         /* Ok - report back to driver */
1195         vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1196     } else {
1197         s->intr_enabled = false;
1198         /* Ok - report back to driver */
1199         vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1200     }
1201 }
1202 
1203 /* Handle write to Global Command Register */
1204 static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1205 {
1206     uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1207     uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1208     uint32_t changed = status ^ val;
1209 
1210     VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status);
1211     if (changed & VTD_GCMD_TE) {
1212         /* Translation enable/disable */
1213         vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1214     }
1215     if (val & VTD_GCMD_SRTP) {
1216         /* Set/update the root-table pointer */
1217         vtd_handle_gcmd_srtp(s);
1218     }
1219     if (changed & VTD_GCMD_QIE) {
1220         /* Queued Invalidation Enable */
1221         vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1222     }
1223     if (val & VTD_GCMD_SIRTP) {
1224         /* Set/update the interrupt remapping root-table pointer */
1225         vtd_handle_gcmd_sirtp(s);
1226     }
1227     if (changed & VTD_GCMD_IRE) {
1228         /* Interrupt remap enable/disable */
1229         vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1230     }
1231 }
1232 
1233 /* Handle write to Context Command Register */
1234 static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1235 {
1236     uint64_t ret;
1237     uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1238 
1239     /* Context-cache invalidation request */
1240     if (val & VTD_CCMD_ICC) {
1241         if (s->qi_enabled) {
1242             VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1243                         "should not use register-based invalidation");
1244             return;
1245         }
1246         ret = vtd_context_cache_invalidate(s, val);
1247         /* Invalidation completed. Change something to show */
1248         vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1249         ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1250                                       ret);
1251         VTD_DPRINTF(INV, "CCMD_REG write-back val: 0x%"PRIx64, ret);
1252     }
1253 }
1254 
1255 /* Handle write to IOTLB Invalidation Register */
1256 static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1257 {
1258     uint64_t ret;
1259     uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1260 
1261     /* IOTLB invalidation request */
1262     if (val & VTD_TLB_IVT) {
1263         if (s->qi_enabled) {
1264             VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1265                         "should not use register-based invalidation");
1266             return;
1267         }
1268         ret = vtd_iotlb_flush(s, val);
1269         /* Invalidation completed. Change something to show */
1270         vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1271         ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1272                                       VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1273         VTD_DPRINTF(INV, "IOTLB_REG write-back val: 0x%"PRIx64, ret);
1274     }
1275 }
1276 
1277 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
1278 static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1279                              VTDInvDesc *inv_desc)
1280 {
1281     dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1282     if (dma_memory_read(&address_space_memory, addr, inv_desc,
1283         sizeof(*inv_desc))) {
1284         VTD_DPRINTF(GENERAL, "error: fail to fetch Invalidation Descriptor "
1285                     "base_addr 0x%"PRIx64 " offset %"PRIu32, base_addr, offset);
1286         inv_desc->lo = 0;
1287         inv_desc->hi = 0;
1288 
1289         return false;
1290     }
1291     inv_desc->lo = le64_to_cpu(inv_desc->lo);
1292     inv_desc->hi = le64_to_cpu(inv_desc->hi);
1293     return true;
1294 }
1295 
1296 static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1297 {
1298     if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1299         (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
1300         VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Invalidation "
1301                     "Wait Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1302                     inv_desc->hi, inv_desc->lo);
1303         return false;
1304     }
1305     if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1306         /* Status Write */
1307         uint32_t status_data = (uint32_t)(inv_desc->lo >>
1308                                VTD_INV_DESC_WAIT_DATA_SHIFT);
1309 
1310         assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1311 
1312         /* FIXME: need to be masked with HAW? */
1313         dma_addr_t status_addr = inv_desc->hi;
1314         VTD_DPRINTF(INV, "status data 0x%x, status addr 0x%"PRIx64,
1315                     status_data, status_addr);
1316         status_data = cpu_to_le32(status_data);
1317         if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1318                              sizeof(status_data))) {
1319             VTD_DPRINTF(GENERAL, "error: fail to perform a coherent write");
1320             return false;
1321         }
1322     } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1323         /* Interrupt flag */
1324         VTD_DPRINTF(INV, "Invalidation Wait Descriptor interrupt completion");
1325         vtd_generate_completion_event(s);
1326     } else {
1327         VTD_DPRINTF(GENERAL, "error: invalid Invalidation Wait Descriptor: "
1328                     "hi 0x%"PRIx64 " lo 0x%"PRIx64, inv_desc->hi, inv_desc->lo);
1329         return false;
1330     }
1331     return true;
1332 }
1333 
1334 static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1335                                            VTDInvDesc *inv_desc)
1336 {
1337     if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
1338         VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Context-cache "
1339                     "Invalidate Descriptor");
1340         return false;
1341     }
1342     switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1343     case VTD_INV_DESC_CC_DOMAIN:
1344         VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1345                     (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
1346         /* Fall through */
1347     case VTD_INV_DESC_CC_GLOBAL:
1348         VTD_DPRINTF(INV, "global invalidation");
1349         vtd_context_global_invalidate(s);
1350         break;
1351 
1352     case VTD_INV_DESC_CC_DEVICE:
1353         vtd_context_device_invalidate(s, VTD_INV_DESC_CC_SID(inv_desc->lo),
1354                                       VTD_INV_DESC_CC_FM(inv_desc->lo));
1355         break;
1356 
1357     default:
1358         VTD_DPRINTF(GENERAL, "error: invalid granularity in Context-cache "
1359                     "Invalidate Descriptor hi 0x%"PRIx64  " lo 0x%"PRIx64,
1360                     inv_desc->hi, inv_desc->lo);
1361         return false;
1362     }
1363     return true;
1364 }
1365 
1366 static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1367 {
1368     uint16_t domain_id;
1369     uint8_t am;
1370     hwaddr addr;
1371 
1372     if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1373         (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
1374         VTD_DPRINTF(GENERAL, "error: non-zero reserved field in IOTLB "
1375                     "Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1376                     inv_desc->hi, inv_desc->lo);
1377         return false;
1378     }
1379 
1380     switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1381     case VTD_INV_DESC_IOTLB_GLOBAL:
1382         VTD_DPRINTF(INV, "global invalidation");
1383         vtd_iotlb_global_invalidate(s);
1384         break;
1385 
1386     case VTD_INV_DESC_IOTLB_DOMAIN:
1387         domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1388         VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1389                     domain_id);
1390         vtd_iotlb_domain_invalidate(s, domain_id);
1391         break;
1392 
1393     case VTD_INV_DESC_IOTLB_PAGE:
1394         domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1395         addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1396         am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
1397         VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1398                     " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1399         if (am > VTD_MAMV) {
1400             VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1401                         "%"PRIu8, (uint8_t)VTD_MAMV);
1402             return false;
1403         }
1404         vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1405         break;
1406 
1407     default:
1408         VTD_DPRINTF(GENERAL, "error: invalid granularity in IOTLB Invalidate "
1409                     "Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1410                     inv_desc->hi, inv_desc->lo);
1411         return false;
1412     }
1413     return true;
1414 }
1415 
1416 static bool vtd_process_inv_desc(IntelIOMMUState *s)
1417 {
1418     VTDInvDesc inv_desc;
1419     uint8_t desc_type;
1420 
1421     VTD_DPRINTF(INV, "iq head %"PRIu16, s->iq_head);
1422     if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1423         s->iq_last_desc_type = VTD_INV_DESC_NONE;
1424         return false;
1425     }
1426     desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1427     /* FIXME: should update at first or at last? */
1428     s->iq_last_desc_type = desc_type;
1429 
1430     switch (desc_type) {
1431     case VTD_INV_DESC_CC:
1432         VTD_DPRINTF(INV, "Context-cache Invalidate Descriptor hi 0x%"PRIx64
1433                     " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1434         if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1435             return false;
1436         }
1437         break;
1438 
1439     case VTD_INV_DESC_IOTLB:
1440         VTD_DPRINTF(INV, "IOTLB Invalidate Descriptor hi 0x%"PRIx64
1441                     " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1442         if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1443             return false;
1444         }
1445         break;
1446 
1447     case VTD_INV_DESC_WAIT:
1448         VTD_DPRINTF(INV, "Invalidation Wait Descriptor hi 0x%"PRIx64
1449                     " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1450         if (!vtd_process_wait_desc(s, &inv_desc)) {
1451             return false;
1452         }
1453         break;
1454 
1455     case VTD_INV_DESC_IEC:
1456         VTD_DPRINTF(INV, "Interrupt Entry Cache Invalidation "
1457                     "not implemented yet");
1458         /*
1459          * Since currently we do not cache interrupt entries, we can
1460          * just mark this descriptor as "good" and move on.
1461          */
1462         break;
1463 
1464     default:
1465         VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type "
1466                     "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8,
1467                     inv_desc.hi, inv_desc.lo, desc_type);
1468         return false;
1469     }
1470     s->iq_head++;
1471     if (s->iq_head == s->iq_size) {
1472         s->iq_head = 0;
1473     }
1474     return true;
1475 }
1476 
1477 /* Try to fetch and process more Invalidation Descriptors */
1478 static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1479 {
1480     VTD_DPRINTF(INV, "fetch Invalidation Descriptors");
1481     if (s->iq_tail >= s->iq_size) {
1482         /* Detects an invalid Tail pointer */
1483         VTD_DPRINTF(GENERAL, "error: iq_tail is %"PRIu16
1484                     " while iq_size is %"PRIu16, s->iq_tail, s->iq_size);
1485         vtd_handle_inv_queue_error(s);
1486         return;
1487     }
1488     while (s->iq_head != s->iq_tail) {
1489         if (!vtd_process_inv_desc(s)) {
1490             /* Invalidation Queue Errors */
1491             vtd_handle_inv_queue_error(s);
1492             break;
1493         }
1494         /* Must update the IQH_REG in time */
1495         vtd_set_quad_raw(s, DMAR_IQH_REG,
1496                          (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
1497                          VTD_IQH_QH_MASK);
1498     }
1499 }
1500 
1501 /* Handle write to Invalidation Queue Tail Register */
1502 static void vtd_handle_iqt_write(IntelIOMMUState *s)
1503 {
1504     uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
1505 
1506     s->iq_tail = VTD_IQT_QT(val);
1507     VTD_DPRINTF(INV, "set iq tail %"PRIu16, s->iq_tail);
1508     if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1509         /* Process Invalidation Queue here */
1510         vtd_fetch_inv_desc(s);
1511     }
1512 }
1513 
1514 static void vtd_handle_fsts_write(IntelIOMMUState *s)
1515 {
1516     uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
1517     uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1518     uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
1519 
1520     if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
1521         vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1522         VTD_DPRINTF(FLOG, "all pending interrupt conditions serviced, clear "
1523                     "IP field of FECTL_REG");
1524     }
1525     /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1526      * Descriptors if there are any when Queued Invalidation is enabled?
1527      */
1528 }
1529 
1530 static void vtd_handle_fectl_write(IntelIOMMUState *s)
1531 {
1532     uint32_t fectl_reg;
1533     /* FIXME: when software clears the IM field, check the IP field. But do we
1534      * need to compare the old value and the new value to conclude that
1535      * software clears the IM field? Or just check if the IM field is zero?
1536      */
1537     fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1538     if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
1539         vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
1540         vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1541         VTD_DPRINTF(FLOG, "IM field is cleared, generate "
1542                     "fault event interrupt");
1543     }
1544 }
1545 
1546 static void vtd_handle_ics_write(IntelIOMMUState *s)
1547 {
1548     uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
1549     uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1550 
1551     if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
1552         vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1553         VTD_DPRINTF(INV, "pending completion interrupt condition serviced, "
1554                     "clear IP field of IECTL_REG");
1555     }
1556 }
1557 
1558 static void vtd_handle_iectl_write(IntelIOMMUState *s)
1559 {
1560     uint32_t iectl_reg;
1561     /* FIXME: when software clears the IM field, check the IP field. But do we
1562      * need to compare the old value and the new value to conclude that
1563      * software clears the IM field? Or just check if the IM field is zero?
1564      */
1565     iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1566     if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
1567         vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
1568         vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1569         VTD_DPRINTF(INV, "IM field is cleared, generate "
1570                     "invalidation event interrupt");
1571     }
1572 }
1573 
1574 static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
1575 {
1576     IntelIOMMUState *s = opaque;
1577     uint64_t val;
1578 
1579     if (addr + size > DMAR_REG_SIZE) {
1580         VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1581                     ", got 0x%"PRIx64 " %d",
1582                     (uint64_t)DMAR_REG_SIZE, addr, size);
1583         return (uint64_t)-1;
1584     }
1585 
1586     switch (addr) {
1587     /* Root Table Address Register, 64-bit */
1588     case DMAR_RTADDR_REG:
1589         if (size == 4) {
1590             val = s->root & ((1ULL << 32) - 1);
1591         } else {
1592             val = s->root;
1593         }
1594         break;
1595 
1596     case DMAR_RTADDR_REG_HI:
1597         assert(size == 4);
1598         val = s->root >> 32;
1599         break;
1600 
1601     /* Invalidation Queue Address Register, 64-bit */
1602     case DMAR_IQA_REG:
1603         val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
1604         if (size == 4) {
1605             val = val & ((1ULL << 32) - 1);
1606         }
1607         break;
1608 
1609     case DMAR_IQA_REG_HI:
1610         assert(size == 4);
1611         val = s->iq >> 32;
1612         break;
1613 
1614     default:
1615         if (size == 4) {
1616             val = vtd_get_long(s, addr);
1617         } else {
1618             val = vtd_get_quad(s, addr);
1619         }
1620     }
1621     VTD_DPRINTF(CSR, "addr 0x%"PRIx64 " size %d val 0x%"PRIx64,
1622                 addr, size, val);
1623     return val;
1624 }
1625 
1626 static void vtd_mem_write(void *opaque, hwaddr addr,
1627                           uint64_t val, unsigned size)
1628 {
1629     IntelIOMMUState *s = opaque;
1630 
1631     if (addr + size > DMAR_REG_SIZE) {
1632         VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1633                     ", got 0x%"PRIx64 " %d",
1634                     (uint64_t)DMAR_REG_SIZE, addr, size);
1635         return;
1636     }
1637 
1638     switch (addr) {
1639     /* Global Command Register, 32-bit */
1640     case DMAR_GCMD_REG:
1641         VTD_DPRINTF(CSR, "DMAR_GCMD_REG write addr 0x%"PRIx64
1642                     ", size %d, val 0x%"PRIx64, addr, size, val);
1643         vtd_set_long(s, addr, val);
1644         vtd_handle_gcmd_write(s);
1645         break;
1646 
1647     /* Context Command Register, 64-bit */
1648     case DMAR_CCMD_REG:
1649         VTD_DPRINTF(CSR, "DMAR_CCMD_REG write addr 0x%"PRIx64
1650                     ", size %d, val 0x%"PRIx64, addr, size, val);
1651         if (size == 4) {
1652             vtd_set_long(s, addr, val);
1653         } else {
1654             vtd_set_quad(s, addr, val);
1655             vtd_handle_ccmd_write(s);
1656         }
1657         break;
1658 
1659     case DMAR_CCMD_REG_HI:
1660         VTD_DPRINTF(CSR, "DMAR_CCMD_REG_HI write addr 0x%"PRIx64
1661                     ", size %d, val 0x%"PRIx64, addr, size, val);
1662         assert(size == 4);
1663         vtd_set_long(s, addr, val);
1664         vtd_handle_ccmd_write(s);
1665         break;
1666 
1667     /* IOTLB Invalidation Register, 64-bit */
1668     case DMAR_IOTLB_REG:
1669         VTD_DPRINTF(INV, "DMAR_IOTLB_REG write addr 0x%"PRIx64
1670                     ", size %d, val 0x%"PRIx64, addr, size, val);
1671         if (size == 4) {
1672             vtd_set_long(s, addr, val);
1673         } else {
1674             vtd_set_quad(s, addr, val);
1675             vtd_handle_iotlb_write(s);
1676         }
1677         break;
1678 
1679     case DMAR_IOTLB_REG_HI:
1680         VTD_DPRINTF(INV, "DMAR_IOTLB_REG_HI write addr 0x%"PRIx64
1681                     ", size %d, val 0x%"PRIx64, addr, size, val);
1682         assert(size == 4);
1683         vtd_set_long(s, addr, val);
1684         vtd_handle_iotlb_write(s);
1685         break;
1686 
1687     /* Invalidate Address Register, 64-bit */
1688     case DMAR_IVA_REG:
1689         VTD_DPRINTF(INV, "DMAR_IVA_REG write addr 0x%"PRIx64
1690                     ", size %d, val 0x%"PRIx64, addr, size, val);
1691         if (size == 4) {
1692             vtd_set_long(s, addr, val);
1693         } else {
1694             vtd_set_quad(s, addr, val);
1695         }
1696         break;
1697 
1698     case DMAR_IVA_REG_HI:
1699         VTD_DPRINTF(INV, "DMAR_IVA_REG_HI write addr 0x%"PRIx64
1700                     ", size %d, val 0x%"PRIx64, addr, size, val);
1701         assert(size == 4);
1702         vtd_set_long(s, addr, val);
1703         break;
1704 
1705     /* Fault Status Register, 32-bit */
1706     case DMAR_FSTS_REG:
1707         VTD_DPRINTF(FLOG, "DMAR_FSTS_REG write addr 0x%"PRIx64
1708                     ", size %d, val 0x%"PRIx64, addr, size, val);
1709         assert(size == 4);
1710         vtd_set_long(s, addr, val);
1711         vtd_handle_fsts_write(s);
1712         break;
1713 
1714     /* Fault Event Control Register, 32-bit */
1715     case DMAR_FECTL_REG:
1716         VTD_DPRINTF(FLOG, "DMAR_FECTL_REG write addr 0x%"PRIx64
1717                     ", size %d, val 0x%"PRIx64, addr, size, val);
1718         assert(size == 4);
1719         vtd_set_long(s, addr, val);
1720         vtd_handle_fectl_write(s);
1721         break;
1722 
1723     /* Fault Event Data Register, 32-bit */
1724     case DMAR_FEDATA_REG:
1725         VTD_DPRINTF(FLOG, "DMAR_FEDATA_REG write addr 0x%"PRIx64
1726                     ", size %d, val 0x%"PRIx64, addr, size, val);
1727         assert(size == 4);
1728         vtd_set_long(s, addr, val);
1729         break;
1730 
1731     /* Fault Event Address Register, 32-bit */
1732     case DMAR_FEADDR_REG:
1733         VTD_DPRINTF(FLOG, "DMAR_FEADDR_REG write addr 0x%"PRIx64
1734                     ", size %d, val 0x%"PRIx64, addr, size, val);
1735         assert(size == 4);
1736         vtd_set_long(s, addr, val);
1737         break;
1738 
1739     /* Fault Event Upper Address Register, 32-bit */
1740     case DMAR_FEUADDR_REG:
1741         VTD_DPRINTF(FLOG, "DMAR_FEUADDR_REG write addr 0x%"PRIx64
1742                     ", size %d, val 0x%"PRIx64, addr, size, val);
1743         assert(size == 4);
1744         vtd_set_long(s, addr, val);
1745         break;
1746 
1747     /* Protected Memory Enable Register, 32-bit */
1748     case DMAR_PMEN_REG:
1749         VTD_DPRINTF(CSR, "DMAR_PMEN_REG write addr 0x%"PRIx64
1750                     ", size %d, val 0x%"PRIx64, addr, size, val);
1751         assert(size == 4);
1752         vtd_set_long(s, addr, val);
1753         break;
1754 
1755     /* Root Table Address Register, 64-bit */
1756     case DMAR_RTADDR_REG:
1757         VTD_DPRINTF(CSR, "DMAR_RTADDR_REG write addr 0x%"PRIx64
1758                     ", size %d, val 0x%"PRIx64, addr, size, val);
1759         if (size == 4) {
1760             vtd_set_long(s, addr, val);
1761         } else {
1762             vtd_set_quad(s, addr, val);
1763         }
1764         break;
1765 
1766     case DMAR_RTADDR_REG_HI:
1767         VTD_DPRINTF(CSR, "DMAR_RTADDR_REG_HI write addr 0x%"PRIx64
1768                     ", size %d, val 0x%"PRIx64, addr, size, val);
1769         assert(size == 4);
1770         vtd_set_long(s, addr, val);
1771         break;
1772 
1773     /* Invalidation Queue Tail Register, 64-bit */
1774     case DMAR_IQT_REG:
1775         VTD_DPRINTF(INV, "DMAR_IQT_REG write addr 0x%"PRIx64
1776                     ", size %d, val 0x%"PRIx64, addr, size, val);
1777         if (size == 4) {
1778             vtd_set_long(s, addr, val);
1779         } else {
1780             vtd_set_quad(s, addr, val);
1781         }
1782         vtd_handle_iqt_write(s);
1783         break;
1784 
1785     case DMAR_IQT_REG_HI:
1786         VTD_DPRINTF(INV, "DMAR_IQT_REG_HI write addr 0x%"PRIx64
1787                     ", size %d, val 0x%"PRIx64, addr, size, val);
1788         assert(size == 4);
1789         vtd_set_long(s, addr, val);
1790         /* 19:63 of IQT_REG is RsvdZ, do nothing here */
1791         break;
1792 
1793     /* Invalidation Queue Address Register, 64-bit */
1794     case DMAR_IQA_REG:
1795         VTD_DPRINTF(INV, "DMAR_IQA_REG write addr 0x%"PRIx64
1796                     ", size %d, val 0x%"PRIx64, addr, size, val);
1797         if (size == 4) {
1798             vtd_set_long(s, addr, val);
1799         } else {
1800             vtd_set_quad(s, addr, val);
1801         }
1802         break;
1803 
1804     case DMAR_IQA_REG_HI:
1805         VTD_DPRINTF(INV, "DMAR_IQA_REG_HI write addr 0x%"PRIx64
1806                     ", size %d, val 0x%"PRIx64, addr, size, val);
1807         assert(size == 4);
1808         vtd_set_long(s, addr, val);
1809         break;
1810 
1811     /* Invalidation Completion Status Register, 32-bit */
1812     case DMAR_ICS_REG:
1813         VTD_DPRINTF(INV, "DMAR_ICS_REG write addr 0x%"PRIx64
1814                     ", size %d, val 0x%"PRIx64, addr, size, val);
1815         assert(size == 4);
1816         vtd_set_long(s, addr, val);
1817         vtd_handle_ics_write(s);
1818         break;
1819 
1820     /* Invalidation Event Control Register, 32-bit */
1821     case DMAR_IECTL_REG:
1822         VTD_DPRINTF(INV, "DMAR_IECTL_REG write addr 0x%"PRIx64
1823                     ", size %d, val 0x%"PRIx64, addr, size, val);
1824         assert(size == 4);
1825         vtd_set_long(s, addr, val);
1826         vtd_handle_iectl_write(s);
1827         break;
1828 
1829     /* Invalidation Event Data Register, 32-bit */
1830     case DMAR_IEDATA_REG:
1831         VTD_DPRINTF(INV, "DMAR_IEDATA_REG write addr 0x%"PRIx64
1832                     ", size %d, val 0x%"PRIx64, addr, size, val);
1833         assert(size == 4);
1834         vtd_set_long(s, addr, val);
1835         break;
1836 
1837     /* Invalidation Event Address Register, 32-bit */
1838     case DMAR_IEADDR_REG:
1839         VTD_DPRINTF(INV, "DMAR_IEADDR_REG write addr 0x%"PRIx64
1840                     ", size %d, val 0x%"PRIx64, addr, size, val);
1841         assert(size == 4);
1842         vtd_set_long(s, addr, val);
1843         break;
1844 
1845     /* Invalidation Event Upper Address Register, 32-bit */
1846     case DMAR_IEUADDR_REG:
1847         VTD_DPRINTF(INV, "DMAR_IEUADDR_REG write addr 0x%"PRIx64
1848                     ", size %d, val 0x%"PRIx64, addr, size, val);
1849         assert(size == 4);
1850         vtd_set_long(s, addr, val);
1851         break;
1852 
1853     /* Fault Recording Registers, 128-bit */
1854     case DMAR_FRCD_REG_0_0:
1855         VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_0 write addr 0x%"PRIx64
1856                     ", size %d, val 0x%"PRIx64, addr, size, val);
1857         if (size == 4) {
1858             vtd_set_long(s, addr, val);
1859         } else {
1860             vtd_set_quad(s, addr, val);
1861         }
1862         break;
1863 
1864     case DMAR_FRCD_REG_0_1:
1865         VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_1 write addr 0x%"PRIx64
1866                     ", size %d, val 0x%"PRIx64, addr, size, val);
1867         assert(size == 4);
1868         vtd_set_long(s, addr, val);
1869         break;
1870 
1871     case DMAR_FRCD_REG_0_2:
1872         VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_2 write addr 0x%"PRIx64
1873                     ", size %d, val 0x%"PRIx64, addr, size, val);
1874         if (size == 4) {
1875             vtd_set_long(s, addr, val);
1876         } else {
1877             vtd_set_quad(s, addr, val);
1878             /* May clear bit 127 (Fault), update PPF */
1879             vtd_update_fsts_ppf(s);
1880         }
1881         break;
1882 
1883     case DMAR_FRCD_REG_0_3:
1884         VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_3 write addr 0x%"PRIx64
1885                     ", size %d, val 0x%"PRIx64, addr, size, val);
1886         assert(size == 4);
1887         vtd_set_long(s, addr, val);
1888         /* May clear bit 127 (Fault), update PPF */
1889         vtd_update_fsts_ppf(s);
1890         break;
1891 
1892     case DMAR_IRTA_REG:
1893         VTD_DPRINTF(IR, "DMAR_IRTA_REG write addr 0x%"PRIx64
1894                     ", size %d, val 0x%"PRIx64, addr, size, val);
1895         if (size == 4) {
1896             vtd_set_long(s, addr, val);
1897         } else {
1898             vtd_set_quad(s, addr, val);
1899         }
1900         break;
1901 
1902     case DMAR_IRTA_REG_HI:
1903         VTD_DPRINTF(IR, "DMAR_IRTA_REG_HI write addr 0x%"PRIx64
1904                     ", size %d, val 0x%"PRIx64, addr, size, val);
1905         assert(size == 4);
1906         vtd_set_long(s, addr, val);
1907         break;
1908 
1909     default:
1910         VTD_DPRINTF(GENERAL, "error: unhandled reg write addr 0x%"PRIx64
1911                     ", size %d, val 0x%"PRIx64, addr, size, val);
1912         if (size == 4) {
1913             vtd_set_long(s, addr, val);
1914         } else {
1915             vtd_set_quad(s, addr, val);
1916         }
1917     }
1918 }
1919 
1920 static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr,
1921                                          bool is_write)
1922 {
1923     VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
1924     IntelIOMMUState *s = vtd_as->iommu_state;
1925     IOMMUTLBEntry ret = {
1926         .target_as = &address_space_memory,
1927         .iova = addr,
1928         .translated_addr = 0,
1929         .addr_mask = ~(hwaddr)0,
1930         .perm = IOMMU_NONE,
1931     };
1932 
1933     if (!s->dmar_enabled) {
1934         /* DMAR disabled, passthrough, use 4k-page*/
1935         ret.iova = addr & VTD_PAGE_MASK_4K;
1936         ret.translated_addr = addr & VTD_PAGE_MASK_4K;
1937         ret.addr_mask = ~VTD_PAGE_MASK_4K;
1938         ret.perm = IOMMU_RW;
1939         return ret;
1940     }
1941 
1942     vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr,
1943                            is_write, &ret);
1944     VTD_DPRINTF(MMU,
1945                 "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8
1946                 " gpa 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bus),
1947                 VTD_PCI_SLOT(vtd_as->devfn), VTD_PCI_FUNC(vtd_as->devfn),
1948                 vtd_as->devfn, addr, ret.translated_addr);
1949     return ret;
1950 }
1951 
1952 static void vtd_iommu_notify_started(MemoryRegion *iommu)
1953 {
1954     VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
1955 
1956     hw_error("Device at bus %s addr %02x.%d requires iommu notifier which "
1957              "is currently not supported by intel-iommu emulation",
1958              vtd_as->bus->qbus.name, PCI_SLOT(vtd_as->devfn),
1959              PCI_FUNC(vtd_as->devfn));
1960 }
1961 
1962 static const VMStateDescription vtd_vmstate = {
1963     .name = "iommu-intel",
1964     .unmigratable = 1,
1965 };
1966 
1967 static const MemoryRegionOps vtd_mem_ops = {
1968     .read = vtd_mem_read,
1969     .write = vtd_mem_write,
1970     .endianness = DEVICE_LITTLE_ENDIAN,
1971     .impl = {
1972         .min_access_size = 4,
1973         .max_access_size = 8,
1974     },
1975     .valid = {
1976         .min_access_size = 4,
1977         .max_access_size = 8,
1978     },
1979 };
1980 
1981 static Property vtd_properties[] = {
1982     DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
1983     DEFINE_PROP_END_OF_LIST(),
1984 };
1985 
1986 /* Read IRTE entry with specific index */
1987 static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
1988                         VTD_IRTE *entry)
1989 {
1990     dma_addr_t addr = 0x00;
1991 
1992     addr = iommu->intr_root + index * sizeof(*entry);
1993     if (dma_memory_read(&address_space_memory, addr, entry,
1994                         sizeof(*entry))) {
1995         VTD_DPRINTF(GENERAL, "error: fail to access IR root at 0x%"PRIx64
1996                     " + %"PRIu16, iommu->intr_root, index);
1997         return -VTD_FR_IR_ROOT_INVAL;
1998     }
1999 
2000     if (!entry->present) {
2001         VTD_DPRINTF(GENERAL, "error: present flag not set in IRTE"
2002                     " entry index %u value 0x%"PRIx64 " 0x%"PRIx64,
2003                     index, le64_to_cpu(entry->data[1]),
2004                     le64_to_cpu(entry->data[0]));
2005         return -VTD_FR_IR_ENTRY_P;
2006     }
2007 
2008     if (entry->__reserved_0 || entry->__reserved_1 || \
2009         entry->__reserved_2) {
2010         VTD_DPRINTF(GENERAL, "error: IRTE entry index %"PRIu16
2011                     " reserved fields non-zero: 0x%"PRIx64 " 0x%"PRIx64,
2012                     index, le64_to_cpu(entry->data[1]),
2013                     le64_to_cpu(entry->data[0]));
2014         return -VTD_FR_IR_IRTE_RSVD;
2015     }
2016 
2017     /*
2018      * TODO: Check Source-ID corresponds to SVT (Source Validation
2019      * Type) bits
2020      */
2021 
2022     return 0;
2023 }
2024 
2025 /* Fetch IRQ information of specific IR index */
2026 static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, VTDIrq *irq)
2027 {
2028     VTD_IRTE irte = {};
2029     int ret = 0;
2030 
2031     ret = vtd_irte_get(iommu, index, &irte);
2032     if (ret) {
2033         return ret;
2034     }
2035 
2036     irq->trigger_mode = irte.trigger_mode;
2037     irq->vector = irte.vector;
2038     irq->delivery_mode = irte.delivery_mode;
2039     /* Not support EIM yet: please refer to vt-d 9.10 DST bits */
2040 #define  VTD_IR_APIC_DEST_MASK         (0xff00ULL)
2041 #define  VTD_IR_APIC_DEST_SHIFT        (8)
2042     irq->dest = (le32_to_cpu(irte.dest_id) & VTD_IR_APIC_DEST_MASK) >> \
2043         VTD_IR_APIC_DEST_SHIFT;
2044     irq->dest_mode = irte.dest_mode;
2045     irq->redir_hint = irte.redir_hint;
2046 
2047     VTD_DPRINTF(IR, "remapping interrupt index %d: trig:%u,vec:%u,"
2048                 "deliver:%u,dest:%u,dest_mode:%u", index,
2049                 irq->trigger_mode, irq->vector, irq->delivery_mode,
2050                 irq->dest, irq->dest_mode);
2051 
2052     return 0;
2053 }
2054 
2055 /* Generate one MSI message from VTDIrq info */
2056 static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2057 {
2058     VTD_MSIMessage msg = {};
2059 
2060     /* Generate address bits */
2061     msg.dest_mode = irq->dest_mode;
2062     msg.redir_hint = irq->redir_hint;
2063     msg.dest = irq->dest;
2064     msg.__addr_head = cpu_to_le32(0xfee);
2065     /* Keep this from original MSI address bits */
2066     msg.__not_used = irq->msi_addr_last_bits;
2067 
2068     /* Generate data bits */
2069     msg.vector = irq->vector;
2070     msg.delivery_mode = irq->delivery_mode;
2071     msg.level = 1;
2072     msg.trigger_mode = irq->trigger_mode;
2073 
2074     msg_out->address = msg.msi_addr;
2075     msg_out->data = msg.msi_data;
2076 }
2077 
2078 /* Interrupt remapping for MSI/MSI-X entry */
2079 static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2080                                    MSIMessage *origin,
2081                                    MSIMessage *translated)
2082 {
2083     int ret = 0;
2084     VTD_IR_MSIAddress addr;
2085     uint16_t index;
2086     VTDIrq irq = {};
2087 
2088     assert(origin && translated);
2089 
2090     if (!iommu || !iommu->intr_enabled) {
2091         goto do_not_translate;
2092     }
2093 
2094     if (origin->address & VTD_MSI_ADDR_HI_MASK) {
2095         VTD_DPRINTF(GENERAL, "error: MSI addr high 32 bits nonzero"
2096                     " during interrupt remapping: 0x%"PRIx32,
2097                     (uint32_t)((origin->address & VTD_MSI_ADDR_HI_MASK) >> \
2098                     VTD_MSI_ADDR_HI_SHIFT));
2099         return -VTD_FR_IR_REQ_RSVD;
2100     }
2101 
2102     addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
2103     if (le16_to_cpu(addr.__head) != 0xfee) {
2104         VTD_DPRINTF(GENERAL, "error: MSI addr low 32 bits invalid: "
2105                     "0x%"PRIx32, addr.data);
2106         return -VTD_FR_IR_REQ_RSVD;
2107     }
2108 
2109     /* This is compatible mode. */
2110     if (addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
2111         goto do_not_translate;
2112     }
2113 
2114     index = addr.index_h << 15 | le16_to_cpu(addr.index_l);
2115 
2116 #define  VTD_IR_MSI_DATA_SUBHANDLE       (0x0000ffff)
2117 #define  VTD_IR_MSI_DATA_RESERVED        (0xffff0000)
2118 
2119     if (addr.sub_valid) {
2120         /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2121         index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2122     }
2123 
2124     ret = vtd_remap_irq_get(iommu, index, &irq);
2125     if (ret) {
2126         return ret;
2127     }
2128 
2129     if (addr.sub_valid) {
2130         VTD_DPRINTF(IR, "received MSI interrupt");
2131         if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
2132             VTD_DPRINTF(GENERAL, "error: MSI data bits non-zero for "
2133                         "interrupt remappable entry: 0x%"PRIx32,
2134                         origin->data);
2135             return -VTD_FR_IR_REQ_RSVD;
2136         }
2137     } else {
2138         uint8_t vector = origin->data & 0xff;
2139         VTD_DPRINTF(IR, "received IOAPIC interrupt");
2140         /* IOAPIC entry vector should be aligned with IRTE vector
2141          * (see vt-d spec 5.1.5.1). */
2142         if (vector != irq.vector) {
2143             VTD_DPRINTF(GENERAL, "IOAPIC vector inconsistent: "
2144                         "entry: %d, IRTE: %d, index: %d",
2145                         vector, irq.vector, index);
2146         }
2147     }
2148 
2149     /*
2150      * We'd better keep the last two bits, assuming that guest OS
2151      * might modify it. Keep it does not hurt after all.
2152      */
2153     irq.msi_addr_last_bits = addr.__not_care;
2154 
2155     /* Translate VTDIrq to MSI message */
2156     vtd_generate_msi_message(&irq, translated);
2157 
2158     VTD_DPRINTF(IR, "mapping MSI 0x%"PRIx64":0x%"PRIx32 " -> "
2159                 "0x%"PRIx64":0x%"PRIx32, origin->address, origin->data,
2160                 translated->address, translated->data);
2161     return 0;
2162 
2163 do_not_translate:
2164     memcpy(translated, origin, sizeof(*origin));
2165     return 0;
2166 }
2167 
2168 static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2169                                    uint64_t *data, unsigned size,
2170                                    MemTxAttrs attrs)
2171 {
2172     return MEMTX_OK;
2173 }
2174 
2175 static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2176                                     uint64_t value, unsigned size,
2177                                     MemTxAttrs attrs)
2178 {
2179     int ret = 0;
2180     MSIMessage from = {}, to = {};
2181 
2182     from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2183     from.data = (uint32_t) value;
2184 
2185     ret = vtd_interrupt_remap_msi(opaque, &from, &to);
2186     if (ret) {
2187         /* TODO: report error */
2188         VTD_DPRINTF(GENERAL, "int remap fail for addr 0x%"PRIx64
2189                     " data 0x%"PRIx32, from.address, from.data);
2190         /* Drop this interrupt */
2191         return MEMTX_ERROR;
2192     }
2193 
2194     VTD_DPRINTF(IR, "delivering MSI 0x%"PRIx64":0x%"PRIx32
2195                 " for device sid 0x%04x",
2196                 to.address, to.data, sid);
2197 
2198     if (dma_memory_write(&address_space_memory, to.address,
2199                          &to.data, size)) {
2200         VTD_DPRINTF(GENERAL, "error: fail to write 0x%"PRIx64
2201                     " value 0x%"PRIx32, to.address, to.data);
2202     }
2203 
2204     return MEMTX_OK;
2205 }
2206 
2207 static const MemoryRegionOps vtd_mem_ir_ops = {
2208     .read_with_attrs = vtd_mem_ir_read,
2209     .write_with_attrs = vtd_mem_ir_write,
2210     .endianness = DEVICE_LITTLE_ENDIAN,
2211     .impl = {
2212         .min_access_size = 4,
2213         .max_access_size = 4,
2214     },
2215     .valid = {
2216         .min_access_size = 4,
2217         .max_access_size = 4,
2218     },
2219 };
2220 
2221 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2222 {
2223     uintptr_t key = (uintptr_t)bus;
2224     VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2225     VTDAddressSpace *vtd_dev_as;
2226 
2227     if (!vtd_bus) {
2228         /* No corresponding free() */
2229         vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
2230                             X86_IOMMU_PCI_DEVFN_MAX);
2231         vtd_bus->bus = bus;
2232         key = (uintptr_t)bus;
2233         g_hash_table_insert(s->vtd_as_by_busptr, &key, vtd_bus);
2234     }
2235 
2236     vtd_dev_as = vtd_bus->dev_as[devfn];
2237 
2238     if (!vtd_dev_as) {
2239         vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2240 
2241         vtd_dev_as->bus = bus;
2242         vtd_dev_as->devfn = (uint8_t)devfn;
2243         vtd_dev_as->iommu_state = s;
2244         vtd_dev_as->context_cache_entry.context_cache_gen = 0;
2245         memory_region_init_iommu(&vtd_dev_as->iommu, OBJECT(s),
2246                                  &s->iommu_ops, "intel_iommu", UINT64_MAX);
2247         memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2248                               &vtd_mem_ir_ops, s, "intel_iommu_ir",
2249                               VTD_INTERRUPT_ADDR_SIZE);
2250         memory_region_add_subregion(&vtd_dev_as->iommu, VTD_INTERRUPT_ADDR_FIRST,
2251                                     &vtd_dev_as->iommu_ir);
2252         address_space_init(&vtd_dev_as->as,
2253                            &vtd_dev_as->iommu, "intel_iommu");
2254     }
2255     return vtd_dev_as;
2256 }
2257 
2258 /* Do the initialization. It will also be called when reset, so pay
2259  * attention when adding new initialization stuff.
2260  */
2261 static void vtd_init(IntelIOMMUState *s)
2262 {
2263     X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2264 
2265     memset(s->csr, 0, DMAR_REG_SIZE);
2266     memset(s->wmask, 0, DMAR_REG_SIZE);
2267     memset(s->w1cmask, 0, DMAR_REG_SIZE);
2268     memset(s->womask, 0, DMAR_REG_SIZE);
2269 
2270     s->iommu_ops.translate = vtd_iommu_translate;
2271     s->iommu_ops.notify_started = vtd_iommu_notify_started;
2272     s->root = 0;
2273     s->root_extended = false;
2274     s->dmar_enabled = false;
2275     s->iq_head = 0;
2276     s->iq_tail = 0;
2277     s->iq = 0;
2278     s->iq_size = 0;
2279     s->qi_enabled = false;
2280     s->iq_last_desc_type = VTD_INV_DESC_NONE;
2281     s->next_frcd_reg = 0;
2282     s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MGAW |
2283              VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
2284     s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
2285 
2286     if (x86_iommu->intr_supported) {
2287         s->ecap |= VTD_ECAP_IR;
2288     }
2289 
2290     vtd_reset_context_cache(s);
2291     vtd_reset_iotlb(s);
2292 
2293     /* Define registers with default values and bit semantics */
2294     vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
2295     vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
2296     vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
2297     vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
2298     vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
2299     vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
2300     vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
2301     vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
2302     vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
2303 
2304     /* Advanced Fault Logging not supported */
2305     vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
2306     vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2307     vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
2308     vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
2309 
2310     /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2311      * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2312      */
2313     vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
2314 
2315     /* Treated as RO for implementations that PLMR and PHMR fields reported
2316      * as Clear in the CAP_REG.
2317      * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2318      */
2319     vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
2320 
2321     vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
2322     vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
2323     vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
2324     vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
2325     vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2326     vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
2327     vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
2328     /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2329     vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
2330 
2331     /* IOTLB registers */
2332     vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
2333     vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
2334     vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
2335 
2336     /* Fault Recording Registers, 128-bit */
2337     vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
2338     vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
2339 
2340     /*
2341      * Interrupt remapping registers, not support extended interrupt
2342      * mode for now.
2343      */
2344     vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff00fULL, 0);
2345 }
2346 
2347 /* Should not reset address_spaces when reset because devices will still use
2348  * the address space they got at first (won't ask the bus again).
2349  */
2350 static void vtd_reset(DeviceState *dev)
2351 {
2352     IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2353 
2354     VTD_DPRINTF(GENERAL, "");
2355     vtd_init(s);
2356 }
2357 
2358 static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
2359 {
2360     IntelIOMMUState *s = opaque;
2361     VTDAddressSpace *vtd_as;
2362 
2363     assert(0 <= devfn && devfn <= X86_IOMMU_PCI_DEVFN_MAX);
2364 
2365     vtd_as = vtd_find_add_as(s, bus, devfn);
2366     return &vtd_as->as;
2367 }
2368 
2369 static void vtd_realize(DeviceState *dev, Error **errp)
2370 {
2371     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2372     PCIBus *bus = pcms->bus;
2373     IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2374 
2375     VTD_DPRINTF(GENERAL, "");
2376     memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
2377     memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
2378                           "intel_iommu", DMAR_REG_SIZE);
2379     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
2380     /* No corresponding destroy */
2381     s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
2382                                      g_free, g_free);
2383     s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
2384                                               g_free, g_free);
2385     vtd_init(s);
2386     sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
2387     pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
2388     /* Pseudo address space under root PCI bus. */
2389     pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
2390 }
2391 
2392 static void vtd_class_init(ObjectClass *klass, void *data)
2393 {
2394     DeviceClass *dc = DEVICE_CLASS(klass);
2395     X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
2396 
2397     dc->reset = vtd_reset;
2398     dc->vmsd = &vtd_vmstate;
2399     dc->props = vtd_properties;
2400     dc->hotpluggable = false;
2401     x86_class->realize = vtd_realize;
2402 }
2403 
2404 static const TypeInfo vtd_info = {
2405     .name          = TYPE_INTEL_IOMMU_DEVICE,
2406     .parent        = TYPE_X86_IOMMU_DEVICE,
2407     .instance_size = sizeof(IntelIOMMUState),
2408     .class_init    = vtd_class_init,
2409 };
2410 
2411 static void vtd_register_types(void)
2412 {
2413     VTD_DPRINTF(GENERAL, "");
2414     type_register_static(&vtd_info);
2415 }
2416 
2417 type_init(vtd_register_types)
2418