1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/error-report.h" 24 #include "qemu/main-loop.h" 25 #include "qapi/error.h" 26 #include "hw/sysbus.h" 27 #include "exec/address-spaces.h" 28 #include "intel_iommu_internal.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/i386/pc.h" 33 #include "hw/i386/apic-msidef.h" 34 #include "hw/boards.h" 35 #include "hw/i386/x86-iommu.h" 36 #include "hw/pci-host/q35.h" 37 #include "sysemu/kvm.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/i386/apic_internal.h" 40 #include "kvm_i386.h" 41 #include "migration/vmstate.h" 42 #include "trace.h" 43 44 /* context entry operations */ 45 #define VTD_CE_GET_RID2PASID(ce) \ 46 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK) 47 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \ 48 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) 49 50 /* pe operations */ 51 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) 52 #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) 53 #define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\ 54 if (ret_fr) { \ 55 ret_fr = -ret_fr; \ 56 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \ 57 trace_vtd_fault_disabled(); \ 58 } else { \ 59 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \ 60 } \ 61 goto error; \ 62 } \ 63 } 64 65 static void vtd_address_space_refresh_all(IntelIOMMUState *s); 66 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); 67 68 static void vtd_panic_require_caching_mode(void) 69 { 70 error_report("We need to set caching-mode=on for intel-iommu to enable " 71 "device assignment with IOMMU protection."); 72 exit(1); 73 } 74 75 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, 76 uint64_t wmask, uint64_t w1cmask) 77 { 78 stq_le_p(&s->csr[addr], val); 79 stq_le_p(&s->wmask[addr], wmask); 80 stq_le_p(&s->w1cmask[addr], w1cmask); 81 } 82 83 static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask) 84 { 85 stq_le_p(&s->womask[addr], mask); 86 } 87 88 static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val, 89 uint32_t wmask, uint32_t w1cmask) 90 { 91 stl_le_p(&s->csr[addr], val); 92 stl_le_p(&s->wmask[addr], wmask); 93 stl_le_p(&s->w1cmask[addr], w1cmask); 94 } 95 96 static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask) 97 { 98 stl_le_p(&s->womask[addr], mask); 99 } 100 101 /* "External" get/set operations */ 102 static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val) 103 { 104 uint64_t oldval = ldq_le_p(&s->csr[addr]); 105 uint64_t wmask = ldq_le_p(&s->wmask[addr]); 106 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); 107 stq_le_p(&s->csr[addr], 108 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); 109 } 110 111 static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val) 112 { 113 uint32_t oldval = ldl_le_p(&s->csr[addr]); 114 uint32_t wmask = ldl_le_p(&s->wmask[addr]); 115 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); 116 stl_le_p(&s->csr[addr], 117 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); 118 } 119 120 static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr) 121 { 122 uint64_t val = ldq_le_p(&s->csr[addr]); 123 uint64_t womask = ldq_le_p(&s->womask[addr]); 124 return val & ~womask; 125 } 126 127 static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr) 128 { 129 uint32_t val = ldl_le_p(&s->csr[addr]); 130 uint32_t womask = ldl_le_p(&s->womask[addr]); 131 return val & ~womask; 132 } 133 134 /* "Internal" get/set operations */ 135 static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr) 136 { 137 return ldq_le_p(&s->csr[addr]); 138 } 139 140 static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr) 141 { 142 return ldl_le_p(&s->csr[addr]); 143 } 144 145 static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val) 146 { 147 stq_le_p(&s->csr[addr], val); 148 } 149 150 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr, 151 uint32_t clear, uint32_t mask) 152 { 153 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; 154 stl_le_p(&s->csr[addr], new_val); 155 return new_val; 156 } 157 158 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr, 159 uint64_t clear, uint64_t mask) 160 { 161 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; 162 stq_le_p(&s->csr[addr], new_val); 163 return new_val; 164 } 165 166 static inline void vtd_iommu_lock(IntelIOMMUState *s) 167 { 168 qemu_mutex_lock(&s->iommu_lock); 169 } 170 171 static inline void vtd_iommu_unlock(IntelIOMMUState *s) 172 { 173 qemu_mutex_unlock(&s->iommu_lock); 174 } 175 176 static void vtd_update_scalable_state(IntelIOMMUState *s) 177 { 178 uint64_t val = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 179 180 if (s->scalable_mode) { 181 s->root_scalable = val & VTD_RTADDR_SMT; 182 } 183 } 184 185 /* Whether the address space needs to notify new mappings */ 186 static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as) 187 { 188 return as->notifier_flags & IOMMU_NOTIFIER_MAP; 189 } 190 191 /* GHashTable functions */ 192 static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2) 193 { 194 return *((const uint64_t *)v1) == *((const uint64_t *)v2); 195 } 196 197 static guint vtd_uint64_hash(gconstpointer v) 198 { 199 return (guint)*(const uint64_t *)v; 200 } 201 202 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, 203 gpointer user_data) 204 { 205 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; 206 uint16_t domain_id = *(uint16_t *)user_data; 207 return entry->domain_id == domain_id; 208 } 209 210 /* The shift of an addr for a certain level of paging structure */ 211 static inline uint32_t vtd_slpt_level_shift(uint32_t level) 212 { 213 assert(level != 0); 214 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS; 215 } 216 217 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level) 218 { 219 return ~((1ULL << vtd_slpt_level_shift(level)) - 1); 220 } 221 222 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value, 223 gpointer user_data) 224 { 225 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value; 226 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data; 227 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; 228 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; 229 return (entry->domain_id == info->domain_id) && 230 (((entry->gfn & info->mask) == gfn) || 231 (entry->gfn == gfn_tlb)); 232 } 233 234 /* Reset all the gen of VTDAddressSpace to zero and set the gen of 235 * IntelIOMMUState to 1. Must be called with IOMMU lock held. 236 */ 237 static void vtd_reset_context_cache_locked(IntelIOMMUState *s) 238 { 239 VTDAddressSpace *vtd_as; 240 VTDBus *vtd_bus; 241 GHashTableIter bus_it; 242 uint32_t devfn_it; 243 244 trace_vtd_context_cache_reset(); 245 246 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr); 247 248 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) { 249 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { 250 vtd_as = vtd_bus->dev_as[devfn_it]; 251 if (!vtd_as) { 252 continue; 253 } 254 vtd_as->context_cache_entry.context_cache_gen = 0; 255 } 256 } 257 s->context_cache_gen = 1; 258 } 259 260 /* Must be called with IOMMU lock held. */ 261 static void vtd_reset_iotlb_locked(IntelIOMMUState *s) 262 { 263 assert(s->iotlb); 264 g_hash_table_remove_all(s->iotlb); 265 } 266 267 static void vtd_reset_iotlb(IntelIOMMUState *s) 268 { 269 vtd_iommu_lock(s); 270 vtd_reset_iotlb_locked(s); 271 vtd_iommu_unlock(s); 272 } 273 274 static void vtd_reset_caches(IntelIOMMUState *s) 275 { 276 vtd_iommu_lock(s); 277 vtd_reset_iotlb_locked(s); 278 vtd_reset_context_cache_locked(s); 279 vtd_iommu_unlock(s); 280 } 281 282 static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id, 283 uint32_t level) 284 { 285 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) | 286 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT); 287 } 288 289 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) 290 { 291 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; 292 } 293 294 /* Must be called with IOMMU lock held */ 295 static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id, 296 hwaddr addr) 297 { 298 VTDIOTLBEntry *entry; 299 uint64_t key; 300 int level; 301 302 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { 303 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level), 304 source_id, level); 305 entry = g_hash_table_lookup(s->iotlb, &key); 306 if (entry) { 307 goto out; 308 } 309 } 310 311 out: 312 return entry; 313 } 314 315 /* Must be with IOMMU lock held */ 316 static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, 317 uint16_t domain_id, hwaddr addr, uint64_t slpte, 318 uint8_t access_flags, uint32_t level) 319 { 320 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry)); 321 uint64_t *key = g_malloc(sizeof(*key)); 322 uint64_t gfn = vtd_get_iotlb_gfn(addr, level); 323 324 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id); 325 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) { 326 trace_vtd_iotlb_reset("iotlb exceeds size limit"); 327 vtd_reset_iotlb_locked(s); 328 } 329 330 entry->gfn = gfn; 331 entry->domain_id = domain_id; 332 entry->slpte = slpte; 333 entry->access_flags = access_flags; 334 entry->mask = vtd_slpt_level_page_mask(level); 335 *key = vtd_get_iotlb_key(gfn, source_id, level); 336 g_hash_table_replace(s->iotlb, key, entry); 337 } 338 339 /* Given the reg addr of both the message data and address, generate an 340 * interrupt via MSI. 341 */ 342 static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg, 343 hwaddr mesg_data_reg) 344 { 345 MSIMessage msi; 346 347 assert(mesg_data_reg < DMAR_REG_SIZE); 348 assert(mesg_addr_reg < DMAR_REG_SIZE); 349 350 msi.address = vtd_get_long_raw(s, mesg_addr_reg); 351 msi.data = vtd_get_long_raw(s, mesg_data_reg); 352 353 trace_vtd_irq_generate(msi.address, msi.data); 354 355 apic_get_class()->send_msi(&msi); 356 } 357 358 /* Generate a fault event to software via MSI if conditions are met. 359 * Notice that the value of FSTS_REG being passed to it should be the one 360 * before any update. 361 */ 362 static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts) 363 { 364 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO || 365 pre_fsts & VTD_FSTS_IQE) { 366 error_report_once("There are previous interrupt conditions " 367 "to be serviced by software, fault event " 368 "is not generated"); 369 return; 370 } 371 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP); 372 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) { 373 error_report_once("Interrupt Mask set, irq is not generated"); 374 } else { 375 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); 376 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 377 } 378 } 379 380 /* Check if the Fault (F) field of the Fault Recording Register referenced by 381 * @index is Set. 382 */ 383 static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index) 384 { 385 /* Each reg is 128-bit */ 386 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 387 addr += 8; /* Access the high 64-bit half */ 388 389 assert(index < DMAR_FRCD_REG_NR); 390 391 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F; 392 } 393 394 /* Update the PPF field of Fault Status Register. 395 * Should be called whenever change the F field of any fault recording 396 * registers. 397 */ 398 static void vtd_update_fsts_ppf(IntelIOMMUState *s) 399 { 400 uint32_t i; 401 uint32_t ppf_mask = 0; 402 403 for (i = 0; i < DMAR_FRCD_REG_NR; i++) { 404 if (vtd_is_frcd_set(s, i)) { 405 ppf_mask = VTD_FSTS_PPF; 406 break; 407 } 408 } 409 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask); 410 trace_vtd_fsts_ppf(!!ppf_mask); 411 } 412 413 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index) 414 { 415 /* Each reg is 128-bit */ 416 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 417 addr += 8; /* Access the high 64-bit half */ 418 419 assert(index < DMAR_FRCD_REG_NR); 420 421 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F); 422 vtd_update_fsts_ppf(s); 423 } 424 425 /* Must not update F field now, should be done later */ 426 static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index, 427 uint16_t source_id, hwaddr addr, 428 VTDFaultReason fault, bool is_write) 429 { 430 uint64_t hi = 0, lo; 431 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4); 432 433 assert(index < DMAR_FRCD_REG_NR); 434 435 lo = VTD_FRCD_FI(addr); 436 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault); 437 if (!is_write) { 438 hi |= VTD_FRCD_T; 439 } 440 vtd_set_quad_raw(s, frcd_reg_addr, lo); 441 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi); 442 443 trace_vtd_frr_new(index, hi, lo); 444 } 445 446 /* Try to collapse multiple pending faults from the same requester */ 447 static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id) 448 { 449 uint32_t i; 450 uint64_t frcd_reg; 451 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */ 452 453 for (i = 0; i < DMAR_FRCD_REG_NR; i++) { 454 frcd_reg = vtd_get_quad_raw(s, addr); 455 if ((frcd_reg & VTD_FRCD_F) && 456 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) { 457 return true; 458 } 459 addr += 16; /* 128-bit for each */ 460 } 461 return false; 462 } 463 464 /* Log and report an DMAR (address translation) fault to software */ 465 static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id, 466 hwaddr addr, VTDFaultReason fault, 467 bool is_write) 468 { 469 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 470 471 assert(fault < VTD_FR_MAX); 472 473 if (fault == VTD_FR_RESERVED_ERR) { 474 /* This is not a normal fault reason case. Drop it. */ 475 return; 476 } 477 478 trace_vtd_dmar_fault(source_id, fault, addr, is_write); 479 480 if (fsts_reg & VTD_FSTS_PFO) { 481 error_report_once("New fault is not recorded due to " 482 "Primary Fault Overflow"); 483 return; 484 } 485 486 if (vtd_try_collapse_fault(s, source_id)) { 487 error_report_once("New fault is not recorded due to " 488 "compression of faults"); 489 return; 490 } 491 492 if (vtd_is_frcd_set(s, s->next_frcd_reg)) { 493 error_report_once("Next Fault Recording Reg is used, " 494 "new fault is not recorded, set PFO field"); 495 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO); 496 return; 497 } 498 499 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write); 500 501 if (fsts_reg & VTD_FSTS_PPF) { 502 error_report_once("There are pending faults already, " 503 "fault event is not generated"); 504 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); 505 s->next_frcd_reg++; 506 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { 507 s->next_frcd_reg = 0; 508 } 509 } else { 510 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK, 511 VTD_FSTS_FRI(s->next_frcd_reg)); 512 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */ 513 s->next_frcd_reg++; 514 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) { 515 s->next_frcd_reg = 0; 516 } 517 /* This case actually cause the PPF to be Set. 518 * So generate fault event (interrupt). 519 */ 520 vtd_generate_fault_event(s, fsts_reg); 521 } 522 } 523 524 /* Handle Invalidation Queue Errors of queued invalidation interface error 525 * conditions. 526 */ 527 static void vtd_handle_inv_queue_error(IntelIOMMUState *s) 528 { 529 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 530 531 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE); 532 vtd_generate_fault_event(s, fsts_reg); 533 } 534 535 /* Set the IWC field and try to generate an invalidation completion interrupt */ 536 static void vtd_generate_completion_event(IntelIOMMUState *s) 537 { 538 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) { 539 trace_vtd_inv_desc_wait_irq("One pending, skip current"); 540 return; 541 } 542 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC); 543 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP); 544 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) { 545 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, " 546 "new event not generated"); 547 return; 548 } else { 549 /* Generate the interrupt event */ 550 trace_vtd_inv_desc_wait_irq("Generating complete event"); 551 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); 552 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 553 } 554 } 555 556 static inline bool vtd_root_entry_present(IntelIOMMUState *s, 557 VTDRootEntry *re, 558 uint8_t devfn) 559 { 560 if (s->root_scalable && devfn > UINT8_MAX / 2) { 561 return re->hi & VTD_ROOT_ENTRY_P; 562 } 563 564 return re->lo & VTD_ROOT_ENTRY_P; 565 } 566 567 static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index, 568 VTDRootEntry *re) 569 { 570 dma_addr_t addr; 571 572 addr = s->root + index * sizeof(*re); 573 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) { 574 re->lo = 0; 575 return -VTD_FR_ROOT_TABLE_INV; 576 } 577 re->lo = le64_to_cpu(re->lo); 578 re->hi = le64_to_cpu(re->hi); 579 return 0; 580 } 581 582 static inline bool vtd_ce_present(VTDContextEntry *context) 583 { 584 return context->lo & VTD_CONTEXT_ENTRY_P; 585 } 586 587 static int vtd_get_context_entry_from_root(IntelIOMMUState *s, 588 VTDRootEntry *re, 589 uint8_t index, 590 VTDContextEntry *ce) 591 { 592 dma_addr_t addr, ce_size; 593 594 /* we have checked that root entry is present */ 595 ce_size = s->root_scalable ? VTD_CTX_ENTRY_SCALABLE_SIZE : 596 VTD_CTX_ENTRY_LEGACY_SIZE; 597 598 if (s->root_scalable && index > UINT8_MAX / 2) { 599 index = index & (~VTD_DEVFN_CHECK_MASK); 600 addr = re->hi & VTD_ROOT_ENTRY_CTP; 601 } else { 602 addr = re->lo & VTD_ROOT_ENTRY_CTP; 603 } 604 605 addr = addr + index * ce_size; 606 if (dma_memory_read(&address_space_memory, addr, ce, ce_size)) { 607 return -VTD_FR_CONTEXT_TABLE_INV; 608 } 609 610 ce->lo = le64_to_cpu(ce->lo); 611 ce->hi = le64_to_cpu(ce->hi); 612 if (ce_size == VTD_CTX_ENTRY_SCALABLE_SIZE) { 613 ce->val[2] = le64_to_cpu(ce->val[2]); 614 ce->val[3] = le64_to_cpu(ce->val[3]); 615 } 616 return 0; 617 } 618 619 static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce) 620 { 621 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; 622 } 623 624 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw) 625 { 626 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw); 627 } 628 629 /* Whether the pte indicates the address of the page frame */ 630 static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level) 631 { 632 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK); 633 } 634 635 /* Get the content of a spte located in @base_addr[@index] */ 636 static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index) 637 { 638 uint64_t slpte; 639 640 assert(index < VTD_SL_PT_ENTRY_NR); 641 642 if (dma_memory_read(&address_space_memory, 643 base_addr + index * sizeof(slpte), &slpte, 644 sizeof(slpte))) { 645 slpte = (uint64_t)-1; 646 return slpte; 647 } 648 slpte = le64_to_cpu(slpte); 649 return slpte; 650 } 651 652 /* Given an iova and the level of paging structure, return the offset 653 * of current level. 654 */ 655 static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level) 656 { 657 return (iova >> vtd_slpt_level_shift(level)) & 658 ((1ULL << VTD_SL_LEVEL_BITS) - 1); 659 } 660 661 /* Check Capability Register to see if the @level of page-table is supported */ 662 static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level) 663 { 664 return VTD_CAP_SAGAW_MASK & s->cap & 665 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); 666 } 667 668 /* Return true if check passed, otherwise false */ 669 static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu, 670 VTDPASIDEntry *pe) 671 { 672 switch (VTD_PE_GET_TYPE(pe)) { 673 case VTD_SM_PASID_ENTRY_FLT: 674 case VTD_SM_PASID_ENTRY_SLT: 675 case VTD_SM_PASID_ENTRY_NESTED: 676 break; 677 case VTD_SM_PASID_ENTRY_PT: 678 if (!x86_iommu->pt_supported) { 679 return false; 680 } 681 break; 682 default: 683 /* Unknwon type */ 684 return false; 685 } 686 return true; 687 } 688 689 static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) 690 { 691 return pdire->val & 1; 692 } 693 694 /** 695 * Caller of this function should check present bit if wants 696 * to use pdir entry for futher usage except for fpd bit check. 697 */ 698 static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, 699 uint32_t pasid, 700 VTDPASIDDirEntry *pdire) 701 { 702 uint32_t index; 703 dma_addr_t addr, entry_size; 704 705 index = VTD_PASID_DIR_INDEX(pasid); 706 entry_size = VTD_PASID_DIR_ENTRY_SIZE; 707 addr = pasid_dir_base + index * entry_size; 708 if (dma_memory_read(&address_space_memory, addr, pdire, entry_size)) { 709 return -VTD_FR_PASID_TABLE_INV; 710 } 711 712 return 0; 713 } 714 715 static inline bool vtd_pe_present(VTDPASIDEntry *pe) 716 { 717 return pe->val[0] & VTD_PASID_ENTRY_P; 718 } 719 720 static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, 721 uint32_t pasid, 722 dma_addr_t addr, 723 VTDPASIDEntry *pe) 724 { 725 uint32_t index; 726 dma_addr_t entry_size; 727 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 728 729 index = VTD_PASID_TABLE_INDEX(pasid); 730 entry_size = VTD_PASID_ENTRY_SIZE; 731 addr = addr + index * entry_size; 732 if (dma_memory_read(&address_space_memory, addr, pe, entry_size)) { 733 return -VTD_FR_PASID_TABLE_INV; 734 } 735 736 /* Do translation type check */ 737 if (!vtd_pe_type_check(x86_iommu, pe)) { 738 return -VTD_FR_PASID_TABLE_INV; 739 } 740 741 if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { 742 return -VTD_FR_PASID_TABLE_INV; 743 } 744 745 return 0; 746 } 747 748 /** 749 * Caller of this function should check present bit if wants 750 * to use pasid entry for futher usage except for fpd bit check. 751 */ 752 static int vtd_get_pe_from_pdire(IntelIOMMUState *s, 753 uint32_t pasid, 754 VTDPASIDDirEntry *pdire, 755 VTDPASIDEntry *pe) 756 { 757 dma_addr_t addr = pdire->val & VTD_PASID_TABLE_BASE_ADDR_MASK; 758 759 return vtd_get_pe_in_pasid_leaf_table(s, pasid, addr, pe); 760 } 761 762 /** 763 * This function gets a pasid entry from a specified pasid 764 * table (includes dir and leaf table) with a specified pasid. 765 * Sanity check should be done to ensure return a present 766 * pasid entry to caller. 767 */ 768 static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s, 769 dma_addr_t pasid_dir_base, 770 uint32_t pasid, 771 VTDPASIDEntry *pe) 772 { 773 int ret; 774 VTDPASIDDirEntry pdire; 775 776 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, 777 pasid, &pdire); 778 if (ret) { 779 return ret; 780 } 781 782 if (!vtd_pdire_present(&pdire)) { 783 return -VTD_FR_PASID_TABLE_INV; 784 } 785 786 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe); 787 if (ret) { 788 return ret; 789 } 790 791 if (!vtd_pe_present(pe)) { 792 return -VTD_FR_PASID_TABLE_INV; 793 } 794 795 return 0; 796 } 797 798 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, 799 VTDContextEntry *ce, 800 VTDPASIDEntry *pe) 801 { 802 uint32_t pasid; 803 dma_addr_t pasid_dir_base; 804 int ret = 0; 805 806 pasid = VTD_CE_GET_RID2PASID(ce); 807 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce); 808 ret = vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); 809 810 return ret; 811 } 812 813 static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, 814 VTDContextEntry *ce, 815 bool *pe_fpd_set) 816 { 817 int ret; 818 uint32_t pasid; 819 dma_addr_t pasid_dir_base; 820 VTDPASIDDirEntry pdire; 821 VTDPASIDEntry pe; 822 823 pasid = VTD_CE_GET_RID2PASID(ce); 824 pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce); 825 826 /* 827 * No present bit check since fpd is meaningful even 828 * if the present bit is clear. 829 */ 830 ret = vtd_get_pdire_from_pdir_table(pasid_dir_base, pasid, &pdire); 831 if (ret) { 832 return ret; 833 } 834 835 if (pdire.val & VTD_PASID_DIR_FPD) { 836 *pe_fpd_set = true; 837 return 0; 838 } 839 840 if (!vtd_pdire_present(&pdire)) { 841 return -VTD_FR_PASID_TABLE_INV; 842 } 843 844 /* 845 * No present bit check since fpd is meaningful even 846 * if the present bit is clear. 847 */ 848 ret = vtd_get_pe_from_pdire(s, pasid, &pdire, &pe); 849 if (ret) { 850 return ret; 851 } 852 853 if (pe.val[0] & VTD_PASID_ENTRY_FPD) { 854 *pe_fpd_set = true; 855 } 856 857 return 0; 858 } 859 860 /* Get the page-table level that hardware should use for the second-level 861 * page-table walk from the Address Width field of context-entry. 862 */ 863 static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce) 864 { 865 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW); 866 } 867 868 static uint32_t vtd_get_iova_level(IntelIOMMUState *s, 869 VTDContextEntry *ce) 870 { 871 VTDPASIDEntry pe; 872 873 if (s->root_scalable) { 874 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 875 return VTD_PE_GET_LEVEL(&pe); 876 } 877 878 return vtd_ce_get_level(ce); 879 } 880 881 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce) 882 { 883 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9; 884 } 885 886 static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, 887 VTDContextEntry *ce) 888 { 889 VTDPASIDEntry pe; 890 891 if (s->root_scalable) { 892 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 893 return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; 894 } 895 896 return vtd_ce_get_agaw(ce); 897 } 898 899 static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce) 900 { 901 return ce->lo & VTD_CONTEXT_ENTRY_TT; 902 } 903 904 /* Only for Legacy Mode. Return true if check passed, otherwise false */ 905 static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu, 906 VTDContextEntry *ce) 907 { 908 switch (vtd_ce_get_type(ce)) { 909 case VTD_CONTEXT_TT_MULTI_LEVEL: 910 /* Always supported */ 911 break; 912 case VTD_CONTEXT_TT_DEV_IOTLB: 913 if (!x86_iommu->dt_supported) { 914 error_report_once("%s: DT specified but not supported", __func__); 915 return false; 916 } 917 break; 918 case VTD_CONTEXT_TT_PASS_THROUGH: 919 if (!x86_iommu->pt_supported) { 920 error_report_once("%s: PT specified but not supported", __func__); 921 return false; 922 } 923 break; 924 default: 925 /* Unknown type */ 926 error_report_once("%s: unknown ce type: %"PRIu32, __func__, 927 vtd_ce_get_type(ce)); 928 return false; 929 } 930 return true; 931 } 932 933 static inline uint64_t vtd_iova_limit(IntelIOMMUState *s, 934 VTDContextEntry *ce, uint8_t aw) 935 { 936 uint32_t ce_agaw = vtd_get_iova_agaw(s, ce); 937 return 1ULL << MIN(ce_agaw, aw); 938 } 939 940 /* Return true if IOVA passes range check, otherwise false. */ 941 static inline bool vtd_iova_range_check(IntelIOMMUState *s, 942 uint64_t iova, VTDContextEntry *ce, 943 uint8_t aw) 944 { 945 /* 946 * Check if @iova is above 2^X-1, where X is the minimum of MGAW 947 * in CAP_REG and AW in context-entry. 948 */ 949 return !(iova & ~(vtd_iova_limit(s, ce, aw) - 1)); 950 } 951 952 static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, 953 VTDContextEntry *ce) 954 { 955 VTDPASIDEntry pe; 956 957 if (s->root_scalable) { 958 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 959 return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; 960 } 961 962 return vtd_ce_get_slpt_base(ce); 963 } 964 965 /* 966 * Rsvd field masks for spte: 967 * vtd_spte_rsvd 4k pages 968 * vtd_spte_rsvd_large large pages 969 */ 970 static uint64_t vtd_spte_rsvd[5]; 971 static uint64_t vtd_spte_rsvd_large[5]; 972 973 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) 974 { 975 uint64_t rsvd_mask = vtd_spte_rsvd[level]; 976 977 if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) && 978 (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { 979 /* large page */ 980 rsvd_mask = vtd_spte_rsvd_large[level]; 981 } 982 983 return slpte & rsvd_mask; 984 } 985 986 /* Find the VTD address space associated with a given bus number */ 987 static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num) 988 { 989 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num]; 990 GHashTableIter iter; 991 992 if (vtd_bus) { 993 return vtd_bus; 994 } 995 996 /* 997 * Iterate over the registered buses to find the one which 998 * currently holds this bus number and update the bus_num 999 * lookup table. 1000 */ 1001 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); 1002 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { 1003 if (pci_bus_num(vtd_bus->bus) == bus_num) { 1004 s->vtd_as_by_bus_num[bus_num] = vtd_bus; 1005 return vtd_bus; 1006 } 1007 } 1008 1009 return NULL; 1010 } 1011 1012 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level 1013 * of the translation, can be used for deciding the size of large page. 1014 */ 1015 static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce, 1016 uint64_t iova, bool is_write, 1017 uint64_t *slptep, uint32_t *slpte_level, 1018 bool *reads, bool *writes, uint8_t aw_bits) 1019 { 1020 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce); 1021 uint32_t level = vtd_get_iova_level(s, ce); 1022 uint32_t offset; 1023 uint64_t slpte; 1024 uint64_t access_right_check; 1025 1026 if (!vtd_iova_range_check(s, iova, ce, aw_bits)) { 1027 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ")", 1028 __func__, iova); 1029 return -VTD_FR_ADDR_BEYOND_MGAW; 1030 } 1031 1032 /* FIXME: what is the Atomics request here? */ 1033 access_right_check = is_write ? VTD_SL_W : VTD_SL_R; 1034 1035 while (true) { 1036 offset = vtd_iova_level_offset(iova, level); 1037 slpte = vtd_get_slpte(addr, offset); 1038 1039 if (slpte == (uint64_t)-1) { 1040 error_report_once("%s: detected read error on DMAR slpte " 1041 "(iova=0x%" PRIx64 ")", __func__, iova); 1042 if (level == vtd_get_iova_level(s, ce)) { 1043 /* Invalid programming of context-entry */ 1044 return -VTD_FR_CONTEXT_ENTRY_INV; 1045 } else { 1046 return -VTD_FR_PAGING_ENTRY_INV; 1047 } 1048 } 1049 *reads = (*reads) && (slpte & VTD_SL_R); 1050 *writes = (*writes) && (slpte & VTD_SL_W); 1051 if (!(slpte & access_right_check)) { 1052 error_report_once("%s: detected slpte permission error " 1053 "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", " 1054 "slpte=0x%" PRIx64 ", write=%d)", __func__, 1055 iova, level, slpte, is_write); 1056 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; 1057 } 1058 if (vtd_slpte_nonzero_rsvd(slpte, level)) { 1059 error_report_once("%s: detected splte reserve non-zero " 1060 "iova=0x%" PRIx64 ", level=0x%" PRIx32 1061 "slpte=0x%" PRIx64 ")", __func__, iova, 1062 level, slpte); 1063 return -VTD_FR_PAGING_ENTRY_RSVD; 1064 } 1065 1066 if (vtd_is_last_slpte(slpte, level)) { 1067 *slptep = slpte; 1068 *slpte_level = level; 1069 return 0; 1070 } 1071 addr = vtd_get_slpte_addr(slpte, aw_bits); 1072 level--; 1073 } 1074 } 1075 1076 typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private); 1077 1078 /** 1079 * Constant information used during page walking 1080 * 1081 * @hook_fn: hook func to be called when detected page 1082 * @private: private data to be passed into hook func 1083 * @notify_unmap: whether we should notify invalid entries 1084 * @as: VT-d address space of the device 1085 * @aw: maximum address width 1086 * @domain: domain ID of the page walk 1087 */ 1088 typedef struct { 1089 VTDAddressSpace *as; 1090 vtd_page_walk_hook hook_fn; 1091 void *private; 1092 bool notify_unmap; 1093 uint8_t aw; 1094 uint16_t domain_id; 1095 } vtd_page_walk_info; 1096 1097 static int vtd_page_walk_one(IOMMUTLBEntry *entry, vtd_page_walk_info *info) 1098 { 1099 VTDAddressSpace *as = info->as; 1100 vtd_page_walk_hook hook_fn = info->hook_fn; 1101 void *private = info->private; 1102 DMAMap target = { 1103 .iova = entry->iova, 1104 .size = entry->addr_mask, 1105 .translated_addr = entry->translated_addr, 1106 .perm = entry->perm, 1107 }; 1108 DMAMap *mapped = iova_tree_find(as->iova_tree, &target); 1109 1110 if (entry->perm == IOMMU_NONE && !info->notify_unmap) { 1111 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask); 1112 return 0; 1113 } 1114 1115 assert(hook_fn); 1116 1117 /* Update local IOVA mapped ranges */ 1118 if (entry->perm) { 1119 if (mapped) { 1120 /* If it's exactly the same translation, skip */ 1121 if (!memcmp(mapped, &target, sizeof(target))) { 1122 trace_vtd_page_walk_one_skip_map(entry->iova, entry->addr_mask, 1123 entry->translated_addr); 1124 return 0; 1125 } else { 1126 /* 1127 * Translation changed. Normally this should not 1128 * happen, but it can happen when with buggy guest 1129 * OSes. Note that there will be a small window that 1130 * we don't have map at all. But that's the best 1131 * effort we can do. The ideal way to emulate this is 1132 * atomically modify the PTE to follow what has 1133 * changed, but we can't. One example is that vfio 1134 * driver only has VFIO_IOMMU_[UN]MAP_DMA but no 1135 * interface to modify a mapping (meanwhile it seems 1136 * meaningless to even provide one). Anyway, let's 1137 * mark this as a TODO in case one day we'll have 1138 * a better solution. 1139 */ 1140 IOMMUAccessFlags cache_perm = entry->perm; 1141 int ret; 1142 1143 /* Emulate an UNMAP */ 1144 entry->perm = IOMMU_NONE; 1145 trace_vtd_page_walk_one(info->domain_id, 1146 entry->iova, 1147 entry->translated_addr, 1148 entry->addr_mask, 1149 entry->perm); 1150 ret = hook_fn(entry, private); 1151 if (ret) { 1152 return ret; 1153 } 1154 /* Drop any existing mapping */ 1155 iova_tree_remove(as->iova_tree, &target); 1156 /* Recover the correct permission */ 1157 entry->perm = cache_perm; 1158 } 1159 } 1160 iova_tree_insert(as->iova_tree, &target); 1161 } else { 1162 if (!mapped) { 1163 /* Skip since we didn't map this range at all */ 1164 trace_vtd_page_walk_one_skip_unmap(entry->iova, entry->addr_mask); 1165 return 0; 1166 } 1167 iova_tree_remove(as->iova_tree, &target); 1168 } 1169 1170 trace_vtd_page_walk_one(info->domain_id, entry->iova, 1171 entry->translated_addr, entry->addr_mask, 1172 entry->perm); 1173 return hook_fn(entry, private); 1174 } 1175 1176 /** 1177 * vtd_page_walk_level - walk over specific level for IOVA range 1178 * 1179 * @addr: base GPA addr to start the walk 1180 * @start: IOVA range start address 1181 * @end: IOVA range end address (start <= addr < end) 1182 * @read: whether parent level has read permission 1183 * @write: whether parent level has write permission 1184 * @info: constant information for the page walk 1185 */ 1186 static int vtd_page_walk_level(dma_addr_t addr, uint64_t start, 1187 uint64_t end, uint32_t level, bool read, 1188 bool write, vtd_page_walk_info *info) 1189 { 1190 bool read_cur, write_cur, entry_valid; 1191 uint32_t offset; 1192 uint64_t slpte; 1193 uint64_t subpage_size, subpage_mask; 1194 IOMMUTLBEntry entry; 1195 uint64_t iova = start; 1196 uint64_t iova_next; 1197 int ret = 0; 1198 1199 trace_vtd_page_walk_level(addr, level, start, end); 1200 1201 subpage_size = 1ULL << vtd_slpt_level_shift(level); 1202 subpage_mask = vtd_slpt_level_page_mask(level); 1203 1204 while (iova < end) { 1205 iova_next = (iova & subpage_mask) + subpage_size; 1206 1207 offset = vtd_iova_level_offset(iova, level); 1208 slpte = vtd_get_slpte(addr, offset); 1209 1210 if (slpte == (uint64_t)-1) { 1211 trace_vtd_page_walk_skip_read(iova, iova_next); 1212 goto next; 1213 } 1214 1215 if (vtd_slpte_nonzero_rsvd(slpte, level)) { 1216 trace_vtd_page_walk_skip_reserve(iova, iova_next); 1217 goto next; 1218 } 1219 1220 /* Permissions are stacked with parents' */ 1221 read_cur = read && (slpte & VTD_SL_R); 1222 write_cur = write && (slpte & VTD_SL_W); 1223 1224 /* 1225 * As long as we have either read/write permission, this is a 1226 * valid entry. The rule works for both page entries and page 1227 * table entries. 1228 */ 1229 entry_valid = read_cur | write_cur; 1230 1231 if (!vtd_is_last_slpte(slpte, level) && entry_valid) { 1232 /* 1233 * This is a valid PDE (or even bigger than PDE). We need 1234 * to walk one further level. 1235 */ 1236 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw), 1237 iova, MIN(iova_next, end), level - 1, 1238 read_cur, write_cur, info); 1239 } else { 1240 /* 1241 * This means we are either: 1242 * 1243 * (1) the real page entry (either 4K page, or huge page) 1244 * (2) the whole range is invalid 1245 * 1246 * In either case, we send an IOTLB notification down. 1247 */ 1248 entry.target_as = &address_space_memory; 1249 entry.iova = iova & subpage_mask; 1250 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur); 1251 entry.addr_mask = ~subpage_mask; 1252 /* NOTE: this is only meaningful if entry_valid == true */ 1253 entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw); 1254 ret = vtd_page_walk_one(&entry, info); 1255 } 1256 1257 if (ret < 0) { 1258 return ret; 1259 } 1260 1261 next: 1262 iova = iova_next; 1263 } 1264 1265 return 0; 1266 } 1267 1268 /** 1269 * vtd_page_walk - walk specific IOVA range, and call the hook 1270 * 1271 * @s: intel iommu state 1272 * @ce: context entry to walk upon 1273 * @start: IOVA address to start the walk 1274 * @end: IOVA range end address (start <= addr < end) 1275 * @info: page walking information struct 1276 */ 1277 static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce, 1278 uint64_t start, uint64_t end, 1279 vtd_page_walk_info *info) 1280 { 1281 dma_addr_t addr = vtd_get_iova_pgtbl_base(s, ce); 1282 uint32_t level = vtd_get_iova_level(s, ce); 1283 1284 if (!vtd_iova_range_check(s, start, ce, info->aw)) { 1285 return -VTD_FR_ADDR_BEYOND_MGAW; 1286 } 1287 1288 if (!vtd_iova_range_check(s, end, ce, info->aw)) { 1289 /* Fix end so that it reaches the maximum */ 1290 end = vtd_iova_limit(s, ce, info->aw); 1291 } 1292 1293 return vtd_page_walk_level(addr, start, end, level, true, true, info); 1294 } 1295 1296 static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState *s, 1297 VTDRootEntry *re) 1298 { 1299 /* Legacy Mode reserved bits check */ 1300 if (!s->root_scalable && 1301 (re->hi || (re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) 1302 goto rsvd_err; 1303 1304 /* Scalable Mode reserved bits check */ 1305 if (s->root_scalable && 1306 ((re->lo & VTD_ROOT_ENTRY_RSVD(s->aw_bits)) || 1307 (re->hi & VTD_ROOT_ENTRY_RSVD(s->aw_bits)))) 1308 goto rsvd_err; 1309 1310 return 0; 1311 1312 rsvd_err: 1313 error_report_once("%s: invalid root entry: hi=0x%"PRIx64 1314 ", lo=0x%"PRIx64, 1315 __func__, re->hi, re->lo); 1316 return -VTD_FR_ROOT_ENTRY_RSVD; 1317 } 1318 1319 static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState *s, 1320 VTDContextEntry *ce) 1321 { 1322 if (!s->root_scalable && 1323 (ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI || 1324 ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) { 1325 error_report_once("%s: invalid context entry: hi=%"PRIx64 1326 ", lo=%"PRIx64" (reserved nonzero)", 1327 __func__, ce->hi, ce->lo); 1328 return -VTD_FR_CONTEXT_ENTRY_RSVD; 1329 } 1330 1331 if (s->root_scalable && 1332 (ce->val[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s->aw_bits) || 1333 ce->val[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 || 1334 ce->val[2] || 1335 ce->val[3])) { 1336 error_report_once("%s: invalid context entry: val[3]=%"PRIx64 1337 ", val[2]=%"PRIx64 1338 ", val[1]=%"PRIx64 1339 ", val[0]=%"PRIx64" (reserved nonzero)", 1340 __func__, ce->val[3], ce->val[2], 1341 ce->val[1], ce->val[0]); 1342 return -VTD_FR_CONTEXT_ENTRY_RSVD; 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, 1349 VTDContextEntry *ce) 1350 { 1351 VTDPASIDEntry pe; 1352 1353 /* 1354 * Make sure in Scalable Mode, a present context entry 1355 * has valid rid2pasid setting, which includes valid 1356 * rid2pasid field and corresponding pasid entry setting 1357 */ 1358 return vtd_ce_get_rid2pasid_entry(s, ce, &pe); 1359 } 1360 1361 /* Map a device to its corresponding domain (context-entry) */ 1362 static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, 1363 uint8_t devfn, VTDContextEntry *ce) 1364 { 1365 VTDRootEntry re; 1366 int ret_fr; 1367 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 1368 1369 ret_fr = vtd_get_root_entry(s, bus_num, &re); 1370 if (ret_fr) { 1371 return ret_fr; 1372 } 1373 1374 if (!vtd_root_entry_present(s, &re, devfn)) { 1375 /* Not error - it's okay we don't have root entry. */ 1376 trace_vtd_re_not_present(bus_num); 1377 return -VTD_FR_ROOT_ENTRY_P; 1378 } 1379 1380 ret_fr = vtd_root_entry_rsvd_bits_check(s, &re); 1381 if (ret_fr) { 1382 return ret_fr; 1383 } 1384 1385 ret_fr = vtd_get_context_entry_from_root(s, &re, devfn, ce); 1386 if (ret_fr) { 1387 return ret_fr; 1388 } 1389 1390 if (!vtd_ce_present(ce)) { 1391 /* Not error - it's okay we don't have context entry. */ 1392 trace_vtd_ce_not_present(bus_num, devfn); 1393 return -VTD_FR_CONTEXT_ENTRY_P; 1394 } 1395 1396 ret_fr = vtd_context_entry_rsvd_bits_check(s, ce); 1397 if (ret_fr) { 1398 return ret_fr; 1399 } 1400 1401 /* Check if the programming of context-entry is valid */ 1402 if (!s->root_scalable && 1403 !vtd_is_level_supported(s, vtd_ce_get_level(ce))) { 1404 error_report_once("%s: invalid context entry: hi=%"PRIx64 1405 ", lo=%"PRIx64" (level %d not supported)", 1406 __func__, ce->hi, ce->lo, 1407 vtd_ce_get_level(ce)); 1408 return -VTD_FR_CONTEXT_ENTRY_INV; 1409 } 1410 1411 if (!s->root_scalable) { 1412 /* Do translation type check */ 1413 if (!vtd_ce_type_check(x86_iommu, ce)) { 1414 /* Errors dumped in vtd_ce_type_check() */ 1415 return -VTD_FR_CONTEXT_ENTRY_INV; 1416 } 1417 } else { 1418 /* 1419 * Check if the programming of context-entry.rid2pasid 1420 * and corresponding pasid setting is valid, and thus 1421 * avoids to check pasid entry fetching result in future 1422 * helper function calling. 1423 */ 1424 ret_fr = vtd_ce_rid2pasid_check(s, ce); 1425 if (ret_fr) { 1426 return ret_fr; 1427 } 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int vtd_sync_shadow_page_hook(IOMMUTLBEntry *entry, 1434 void *private) 1435 { 1436 memory_region_notify_iommu((IOMMUMemoryRegion *)private, 0, *entry); 1437 return 0; 1438 } 1439 1440 static uint16_t vtd_get_domain_id(IntelIOMMUState *s, 1441 VTDContextEntry *ce) 1442 { 1443 VTDPASIDEntry pe; 1444 1445 if (s->root_scalable) { 1446 vtd_ce_get_rid2pasid_entry(s, ce, &pe); 1447 return VTD_SM_PASID_ENTRY_DID(pe.val[1]); 1448 } 1449 1450 return VTD_CONTEXT_ENTRY_DID(ce->hi); 1451 } 1452 1453 static int vtd_sync_shadow_page_table_range(VTDAddressSpace *vtd_as, 1454 VTDContextEntry *ce, 1455 hwaddr addr, hwaddr size) 1456 { 1457 IntelIOMMUState *s = vtd_as->iommu_state; 1458 vtd_page_walk_info info = { 1459 .hook_fn = vtd_sync_shadow_page_hook, 1460 .private = (void *)&vtd_as->iommu, 1461 .notify_unmap = true, 1462 .aw = s->aw_bits, 1463 .as = vtd_as, 1464 .domain_id = vtd_get_domain_id(s, ce), 1465 }; 1466 1467 return vtd_page_walk(s, ce, addr, addr + size, &info); 1468 } 1469 1470 static int vtd_sync_shadow_page_table(VTDAddressSpace *vtd_as) 1471 { 1472 int ret; 1473 VTDContextEntry ce; 1474 IOMMUNotifier *n; 1475 1476 ret = vtd_dev_to_context_entry(vtd_as->iommu_state, 1477 pci_bus_num(vtd_as->bus), 1478 vtd_as->devfn, &ce); 1479 if (ret) { 1480 if (ret == -VTD_FR_CONTEXT_ENTRY_P) { 1481 /* 1482 * It's a valid scenario to have a context entry that is 1483 * not present. For example, when a device is removed 1484 * from an existing domain then the context entry will be 1485 * zeroed by the guest before it was put into another 1486 * domain. When this happens, instead of synchronizing 1487 * the shadow pages we should invalidate all existing 1488 * mappings and notify the backends. 1489 */ 1490 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) { 1491 vtd_address_space_unmap(vtd_as, n); 1492 } 1493 ret = 0; 1494 } 1495 return ret; 1496 } 1497 1498 return vtd_sync_shadow_page_table_range(vtd_as, &ce, 0, UINT64_MAX); 1499 } 1500 1501 /* 1502 * Check if specific device is configed to bypass address 1503 * translation for DMA requests. In Scalable Mode, bypass 1504 * 1st-level translation or 2nd-level translation, it depends 1505 * on PGTT setting. 1506 */ 1507 static bool vtd_dev_pt_enabled(VTDAddressSpace *as) 1508 { 1509 IntelIOMMUState *s; 1510 VTDContextEntry ce; 1511 VTDPASIDEntry pe; 1512 int ret; 1513 1514 assert(as); 1515 1516 s = as->iommu_state; 1517 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus), 1518 as->devfn, &ce); 1519 if (ret) { 1520 /* 1521 * Possibly failed to parse the context entry for some reason 1522 * (e.g., during init, or any guest configuration errors on 1523 * context entries). We should assume PT not enabled for 1524 * safety. 1525 */ 1526 return false; 1527 } 1528 1529 if (s->root_scalable) { 1530 ret = vtd_ce_get_rid2pasid_entry(s, &ce, &pe); 1531 if (ret) { 1532 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32, 1533 __func__, ret); 1534 return false; 1535 } 1536 return (VTD_PE_GET_TYPE(&pe) == VTD_SM_PASID_ENTRY_PT); 1537 } 1538 1539 return (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH); 1540 } 1541 1542 /* Return whether the device is using IOMMU translation. */ 1543 static bool vtd_switch_address_space(VTDAddressSpace *as) 1544 { 1545 bool use_iommu; 1546 /* Whether we need to take the BQL on our own */ 1547 bool take_bql = !qemu_mutex_iothread_locked(); 1548 1549 assert(as); 1550 1551 use_iommu = as->iommu_state->dmar_enabled && !vtd_dev_pt_enabled(as); 1552 1553 trace_vtd_switch_address_space(pci_bus_num(as->bus), 1554 VTD_PCI_SLOT(as->devfn), 1555 VTD_PCI_FUNC(as->devfn), 1556 use_iommu); 1557 1558 /* 1559 * It's possible that we reach here without BQL, e.g., when called 1560 * from vtd_pt_enable_fast_path(). However the memory APIs need 1561 * it. We'd better make sure we have had it already, or, take it. 1562 */ 1563 if (take_bql) { 1564 qemu_mutex_lock_iothread(); 1565 } 1566 1567 /* Turn off first then on the other */ 1568 if (use_iommu) { 1569 memory_region_set_enabled(&as->nodmar, false); 1570 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true); 1571 } else { 1572 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false); 1573 memory_region_set_enabled(&as->nodmar, true); 1574 } 1575 1576 if (take_bql) { 1577 qemu_mutex_unlock_iothread(); 1578 } 1579 1580 return use_iommu; 1581 } 1582 1583 static void vtd_switch_address_space_all(IntelIOMMUState *s) 1584 { 1585 GHashTableIter iter; 1586 VTDBus *vtd_bus; 1587 int i; 1588 1589 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); 1590 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { 1591 for (i = 0; i < PCI_DEVFN_MAX; i++) { 1592 if (!vtd_bus->dev_as[i]) { 1593 continue; 1594 } 1595 vtd_switch_address_space(vtd_bus->dev_as[i]); 1596 } 1597 } 1598 } 1599 1600 static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) 1601 { 1602 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); 1603 } 1604 1605 static const bool vtd_qualified_faults[] = { 1606 [VTD_FR_RESERVED] = false, 1607 [VTD_FR_ROOT_ENTRY_P] = false, 1608 [VTD_FR_CONTEXT_ENTRY_P] = true, 1609 [VTD_FR_CONTEXT_ENTRY_INV] = true, 1610 [VTD_FR_ADDR_BEYOND_MGAW] = true, 1611 [VTD_FR_WRITE] = true, 1612 [VTD_FR_READ] = true, 1613 [VTD_FR_PAGING_ENTRY_INV] = true, 1614 [VTD_FR_ROOT_TABLE_INV] = false, 1615 [VTD_FR_CONTEXT_TABLE_INV] = false, 1616 [VTD_FR_ROOT_ENTRY_RSVD] = false, 1617 [VTD_FR_PAGING_ENTRY_RSVD] = true, 1618 [VTD_FR_CONTEXT_ENTRY_TT] = true, 1619 [VTD_FR_PASID_TABLE_INV] = false, 1620 [VTD_FR_RESERVED_ERR] = false, 1621 [VTD_FR_MAX] = false, 1622 }; 1623 1624 /* To see if a fault condition is "qualified", which is reported to software 1625 * only if the FPD field in the context-entry used to process the faulting 1626 * request is 0. 1627 */ 1628 static inline bool vtd_is_qualified_fault(VTDFaultReason fault) 1629 { 1630 return vtd_qualified_faults[fault]; 1631 } 1632 1633 static inline bool vtd_is_interrupt_addr(hwaddr addr) 1634 { 1635 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST; 1636 } 1637 1638 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) 1639 { 1640 VTDBus *vtd_bus; 1641 VTDAddressSpace *vtd_as; 1642 bool success = false; 1643 1644 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id)); 1645 if (!vtd_bus) { 1646 goto out; 1647 } 1648 1649 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)]; 1650 if (!vtd_as) { 1651 goto out; 1652 } 1653 1654 if (vtd_switch_address_space(vtd_as) == false) { 1655 /* We switched off IOMMU region successfully. */ 1656 success = true; 1657 } 1658 1659 out: 1660 trace_vtd_pt_enable_fast_path(source_id, success); 1661 } 1662 1663 /* Map dev to context-entry then do a paging-structures walk to do a iommu 1664 * translation. 1665 * 1666 * Called from RCU critical section. 1667 * 1668 * @bus_num: The bus number 1669 * @devfn: The devfn, which is the combined of device and function number 1670 * @is_write: The access is a write operation 1671 * @entry: IOMMUTLBEntry that contain the addr to be translated and result 1672 * 1673 * Returns true if translation is successful, otherwise false. 1674 */ 1675 static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 1676 uint8_t devfn, hwaddr addr, bool is_write, 1677 IOMMUTLBEntry *entry) 1678 { 1679 IntelIOMMUState *s = vtd_as->iommu_state; 1680 VTDContextEntry ce; 1681 uint8_t bus_num = pci_bus_num(bus); 1682 VTDContextCacheEntry *cc_entry; 1683 uint64_t slpte, page_mask; 1684 uint32_t level; 1685 uint16_t source_id = vtd_make_source_id(bus_num, devfn); 1686 int ret_fr; 1687 bool is_fpd_set = false; 1688 bool reads = true; 1689 bool writes = true; 1690 uint8_t access_flags; 1691 VTDIOTLBEntry *iotlb_entry; 1692 1693 /* 1694 * We have standalone memory region for interrupt addresses, we 1695 * should never receive translation requests in this region. 1696 */ 1697 assert(!vtd_is_interrupt_addr(addr)); 1698 1699 vtd_iommu_lock(s); 1700 1701 cc_entry = &vtd_as->context_cache_entry; 1702 1703 /* Try to fetch slpte form IOTLB */ 1704 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr); 1705 if (iotlb_entry) { 1706 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, 1707 iotlb_entry->domain_id); 1708 slpte = iotlb_entry->slpte; 1709 access_flags = iotlb_entry->access_flags; 1710 page_mask = iotlb_entry->mask; 1711 goto out; 1712 } 1713 1714 /* Try to fetch context-entry from cache first */ 1715 if (cc_entry->context_cache_gen == s->context_cache_gen) { 1716 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi, 1717 cc_entry->context_entry.lo, 1718 cc_entry->context_cache_gen); 1719 ce = cc_entry->context_entry; 1720 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; 1721 if (!is_fpd_set && s->root_scalable) { 1722 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); 1723 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1724 } 1725 } else { 1726 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce); 1727 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; 1728 if (!ret_fr && !is_fpd_set && s->root_scalable) { 1729 ret_fr = vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); 1730 } 1731 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1732 /* Update context-cache */ 1733 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo, 1734 cc_entry->context_cache_gen, 1735 s->context_cache_gen); 1736 cc_entry->context_entry = ce; 1737 cc_entry->context_cache_gen = s->context_cache_gen; 1738 } 1739 1740 /* 1741 * We don't need to translate for pass-through context entries. 1742 * Also, let's ignore IOTLB caching as well for PT devices. 1743 */ 1744 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) { 1745 entry->iova = addr & VTD_PAGE_MASK_4K; 1746 entry->translated_addr = entry->iova; 1747 entry->addr_mask = ~VTD_PAGE_MASK_4K; 1748 entry->perm = IOMMU_RW; 1749 trace_vtd_translate_pt(source_id, entry->iova); 1750 1751 /* 1752 * When this happens, it means firstly caching-mode is not 1753 * enabled, and this is the first passthrough translation for 1754 * the device. Let's enable the fast path for passthrough. 1755 * 1756 * When passthrough is disabled again for the device, we can 1757 * capture it via the context entry invalidation, then the 1758 * IOMMU region can be swapped back. 1759 */ 1760 vtd_pt_enable_fast_path(s, source_id); 1761 vtd_iommu_unlock(s); 1762 return true; 1763 } 1764 1765 ret_fr = vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, 1766 &reads, &writes, s->aw_bits); 1767 VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); 1768 1769 page_mask = vtd_slpt_level_page_mask(level); 1770 access_flags = IOMMU_ACCESS_FLAG(reads, writes); 1771 vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce), addr, slpte, 1772 access_flags, level); 1773 out: 1774 vtd_iommu_unlock(s); 1775 entry->iova = addr & page_mask; 1776 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask; 1777 entry->addr_mask = ~page_mask; 1778 entry->perm = access_flags; 1779 return true; 1780 1781 error: 1782 vtd_iommu_unlock(s); 1783 entry->iova = 0; 1784 entry->translated_addr = 0; 1785 entry->addr_mask = 0; 1786 entry->perm = IOMMU_NONE; 1787 return false; 1788 } 1789 1790 static void vtd_root_table_setup(IntelIOMMUState *s) 1791 { 1792 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 1793 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits); 1794 1795 vtd_update_scalable_state(s); 1796 1797 trace_vtd_reg_dmar_root(s->root, s->root_scalable); 1798 } 1799 1800 static void vtd_iec_notify_all(IntelIOMMUState *s, bool global, 1801 uint32_t index, uint32_t mask) 1802 { 1803 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask); 1804 } 1805 1806 static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s) 1807 { 1808 uint64_t value = 0; 1809 value = vtd_get_quad_raw(s, DMAR_IRTA_REG); 1810 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1); 1811 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits); 1812 s->intr_eime = value & VTD_IRTA_EIME; 1813 1814 /* Notify global invalidation */ 1815 vtd_iec_notify_all(s, true, 0, 0); 1816 1817 trace_vtd_reg_ir_root(s->intr_root, s->intr_size); 1818 } 1819 1820 static void vtd_iommu_replay_all(IntelIOMMUState *s) 1821 { 1822 VTDAddressSpace *vtd_as; 1823 1824 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 1825 vtd_sync_shadow_page_table(vtd_as); 1826 } 1827 } 1828 1829 static void vtd_context_global_invalidate(IntelIOMMUState *s) 1830 { 1831 trace_vtd_inv_desc_cc_global(); 1832 /* Protects context cache */ 1833 vtd_iommu_lock(s); 1834 s->context_cache_gen++; 1835 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) { 1836 vtd_reset_context_cache_locked(s); 1837 } 1838 vtd_iommu_unlock(s); 1839 vtd_address_space_refresh_all(s); 1840 /* 1841 * From VT-d spec 6.5.2.1, a global context entry invalidation 1842 * should be followed by a IOTLB global invalidation, so we should 1843 * be safe even without this. Hoewever, let's replay the region as 1844 * well to be safer, and go back here when we need finer tunes for 1845 * VT-d emulation codes. 1846 */ 1847 vtd_iommu_replay_all(s); 1848 } 1849 1850 /* Do a context-cache device-selective invalidation. 1851 * @func_mask: FM field after shifting 1852 */ 1853 static void vtd_context_device_invalidate(IntelIOMMUState *s, 1854 uint16_t source_id, 1855 uint16_t func_mask) 1856 { 1857 uint16_t mask; 1858 VTDBus *vtd_bus; 1859 VTDAddressSpace *vtd_as; 1860 uint8_t bus_n, devfn; 1861 uint16_t devfn_it; 1862 1863 trace_vtd_inv_desc_cc_devices(source_id, func_mask); 1864 1865 switch (func_mask & 3) { 1866 case 0: 1867 mask = 0; /* No bits in the SID field masked */ 1868 break; 1869 case 1: 1870 mask = 4; /* Mask bit 2 in the SID field */ 1871 break; 1872 case 2: 1873 mask = 6; /* Mask bit 2:1 in the SID field */ 1874 break; 1875 case 3: 1876 mask = 7; /* Mask bit 2:0 in the SID field */ 1877 break; 1878 } 1879 mask = ~mask; 1880 1881 bus_n = VTD_SID_TO_BUS(source_id); 1882 vtd_bus = vtd_find_as_from_bus_num(s, bus_n); 1883 if (vtd_bus) { 1884 devfn = VTD_SID_TO_DEVFN(source_id); 1885 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { 1886 vtd_as = vtd_bus->dev_as[devfn_it]; 1887 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) { 1888 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it), 1889 VTD_PCI_FUNC(devfn_it)); 1890 vtd_iommu_lock(s); 1891 vtd_as->context_cache_entry.context_cache_gen = 0; 1892 vtd_iommu_unlock(s); 1893 /* 1894 * Do switch address space when needed, in case if the 1895 * device passthrough bit is switched. 1896 */ 1897 vtd_switch_address_space(vtd_as); 1898 /* 1899 * So a device is moving out of (or moving into) a 1900 * domain, resync the shadow page table. 1901 * This won't bring bad even if we have no such 1902 * notifier registered - the IOMMU notification 1903 * framework will skip MAP notifications if that 1904 * happened. 1905 */ 1906 vtd_sync_shadow_page_table(vtd_as); 1907 } 1908 } 1909 } 1910 } 1911 1912 /* Context-cache invalidation 1913 * Returns the Context Actual Invalidation Granularity. 1914 * @val: the content of the CCMD_REG 1915 */ 1916 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val) 1917 { 1918 uint64_t caig; 1919 uint64_t type = val & VTD_CCMD_CIRG_MASK; 1920 1921 switch (type) { 1922 case VTD_CCMD_DOMAIN_INVL: 1923 /* Fall through */ 1924 case VTD_CCMD_GLOBAL_INVL: 1925 caig = VTD_CCMD_GLOBAL_INVL_A; 1926 vtd_context_global_invalidate(s); 1927 break; 1928 1929 case VTD_CCMD_DEVICE_INVL: 1930 caig = VTD_CCMD_DEVICE_INVL_A; 1931 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val)); 1932 break; 1933 1934 default: 1935 error_report_once("%s: invalid context: 0x%" PRIx64, 1936 __func__, val); 1937 caig = 0; 1938 } 1939 return caig; 1940 } 1941 1942 static void vtd_iotlb_global_invalidate(IntelIOMMUState *s) 1943 { 1944 trace_vtd_inv_desc_iotlb_global(); 1945 vtd_reset_iotlb(s); 1946 vtd_iommu_replay_all(s); 1947 } 1948 1949 static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id) 1950 { 1951 VTDContextEntry ce; 1952 VTDAddressSpace *vtd_as; 1953 1954 trace_vtd_inv_desc_iotlb_domain(domain_id); 1955 1956 vtd_iommu_lock(s); 1957 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain, 1958 &domain_id); 1959 vtd_iommu_unlock(s); 1960 1961 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 1962 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), 1963 vtd_as->devfn, &ce) && 1964 domain_id == vtd_get_domain_id(s, &ce)) { 1965 vtd_sync_shadow_page_table(vtd_as); 1966 } 1967 } 1968 } 1969 1970 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, 1971 uint16_t domain_id, hwaddr addr, 1972 uint8_t am) 1973 { 1974 VTDAddressSpace *vtd_as; 1975 VTDContextEntry ce; 1976 int ret; 1977 hwaddr size = (1 << am) * VTD_PAGE_SIZE; 1978 1979 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) { 1980 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), 1981 vtd_as->devfn, &ce); 1982 if (!ret && domain_id == vtd_get_domain_id(s, &ce)) { 1983 if (vtd_as_has_map_notifier(vtd_as)) { 1984 /* 1985 * As long as we have MAP notifications registered in 1986 * any of our IOMMU notifiers, we need to sync the 1987 * shadow page table. 1988 */ 1989 vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size); 1990 } else { 1991 /* 1992 * For UNMAP-only notifiers, we don't need to walk the 1993 * page tables. We just deliver the PSI down to 1994 * invalidate caches. 1995 */ 1996 IOMMUTLBEntry entry = { 1997 .target_as = &address_space_memory, 1998 .iova = addr, 1999 .translated_addr = 0, 2000 .addr_mask = size - 1, 2001 .perm = IOMMU_NONE, 2002 }; 2003 memory_region_notify_iommu(&vtd_as->iommu, 0, entry); 2004 } 2005 } 2006 } 2007 } 2008 2009 static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id, 2010 hwaddr addr, uint8_t am) 2011 { 2012 VTDIOTLBPageInvInfo info; 2013 2014 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am); 2015 2016 assert(am <= VTD_MAMV); 2017 info.domain_id = domain_id; 2018 info.addr = addr; 2019 info.mask = ~((1 << am) - 1); 2020 vtd_iommu_lock(s); 2021 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info); 2022 vtd_iommu_unlock(s); 2023 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am); 2024 } 2025 2026 /* Flush IOTLB 2027 * Returns the IOTLB Actual Invalidation Granularity. 2028 * @val: the content of the IOTLB_REG 2029 */ 2030 static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val) 2031 { 2032 uint64_t iaig; 2033 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK; 2034 uint16_t domain_id; 2035 hwaddr addr; 2036 uint8_t am; 2037 2038 switch (type) { 2039 case VTD_TLB_GLOBAL_FLUSH: 2040 iaig = VTD_TLB_GLOBAL_FLUSH_A; 2041 vtd_iotlb_global_invalidate(s); 2042 break; 2043 2044 case VTD_TLB_DSI_FLUSH: 2045 domain_id = VTD_TLB_DID(val); 2046 iaig = VTD_TLB_DSI_FLUSH_A; 2047 vtd_iotlb_domain_invalidate(s, domain_id); 2048 break; 2049 2050 case VTD_TLB_PSI_FLUSH: 2051 domain_id = VTD_TLB_DID(val); 2052 addr = vtd_get_quad_raw(s, DMAR_IVA_REG); 2053 am = VTD_IVA_AM(addr); 2054 addr = VTD_IVA_ADDR(addr); 2055 if (am > VTD_MAMV) { 2056 error_report_once("%s: address mask overflow: 0x%" PRIx64, 2057 __func__, vtd_get_quad_raw(s, DMAR_IVA_REG)); 2058 iaig = 0; 2059 break; 2060 } 2061 iaig = VTD_TLB_PSI_FLUSH_A; 2062 vtd_iotlb_page_invalidate(s, domain_id, addr, am); 2063 break; 2064 2065 default: 2066 error_report_once("%s: invalid granularity: 0x%" PRIx64, 2067 __func__, val); 2068 iaig = 0; 2069 } 2070 return iaig; 2071 } 2072 2073 static void vtd_fetch_inv_desc(IntelIOMMUState *s); 2074 2075 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s) 2076 { 2077 return s->qi_enabled && (s->iq_tail == s->iq_head) && 2078 (s->iq_last_desc_type == VTD_INV_DESC_WAIT); 2079 } 2080 2081 static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en) 2082 { 2083 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG); 2084 2085 trace_vtd_inv_qi_enable(en); 2086 2087 if (en) { 2088 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits); 2089 /* 2^(x+8) entries */ 2090 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8 - (s->iq_dw ? 1 : 0)); 2091 s->qi_enabled = true; 2092 trace_vtd_inv_qi_setup(s->iq, s->iq_size); 2093 /* Ok - report back to driver */ 2094 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES); 2095 2096 if (s->iq_tail != 0) { 2097 /* 2098 * This is a spec violation but Windows guests are known to set up 2099 * Queued Invalidation this way so we allow the write and process 2100 * Invalidation Descriptors right away. 2101 */ 2102 trace_vtd_warn_invalid_qi_tail(s->iq_tail); 2103 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { 2104 vtd_fetch_inv_desc(s); 2105 } 2106 } 2107 } else { 2108 if (vtd_queued_inv_disable_check(s)) { 2109 /* disable Queued Invalidation */ 2110 vtd_set_quad_raw(s, DMAR_IQH_REG, 0); 2111 s->iq_head = 0; 2112 s->qi_enabled = false; 2113 /* Ok - report back to driver */ 2114 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0); 2115 } else { 2116 error_report_once("%s: detected improper state when disable QI " 2117 "(head=0x%x, tail=0x%x, last_type=%d)", 2118 __func__, 2119 s->iq_head, s->iq_tail, s->iq_last_desc_type); 2120 } 2121 } 2122 } 2123 2124 /* Set Root Table Pointer */ 2125 static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) 2126 { 2127 vtd_root_table_setup(s); 2128 /* Ok - report back to driver */ 2129 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); 2130 vtd_reset_caches(s); 2131 vtd_address_space_refresh_all(s); 2132 } 2133 2134 /* Set Interrupt Remap Table Pointer */ 2135 static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s) 2136 { 2137 vtd_interrupt_remap_table_setup(s); 2138 /* Ok - report back to driver */ 2139 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS); 2140 } 2141 2142 /* Handle Translation Enable/Disable */ 2143 static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en) 2144 { 2145 if (s->dmar_enabled == en) { 2146 return; 2147 } 2148 2149 trace_vtd_dmar_enable(en); 2150 2151 if (en) { 2152 s->dmar_enabled = true; 2153 /* Ok - report back to driver */ 2154 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES); 2155 } else { 2156 s->dmar_enabled = false; 2157 2158 /* Clear the index of Fault Recording Register */ 2159 s->next_frcd_reg = 0; 2160 /* Ok - report back to driver */ 2161 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0); 2162 } 2163 2164 vtd_reset_caches(s); 2165 vtd_address_space_refresh_all(s); 2166 } 2167 2168 /* Handle Interrupt Remap Enable/Disable */ 2169 static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en) 2170 { 2171 trace_vtd_ir_enable(en); 2172 2173 if (en) { 2174 s->intr_enabled = true; 2175 /* Ok - report back to driver */ 2176 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES); 2177 } else { 2178 s->intr_enabled = false; 2179 /* Ok - report back to driver */ 2180 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0); 2181 } 2182 } 2183 2184 /* Handle write to Global Command Register */ 2185 static void vtd_handle_gcmd_write(IntelIOMMUState *s) 2186 { 2187 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG); 2188 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG); 2189 uint32_t changed = status ^ val; 2190 2191 trace_vtd_reg_write_gcmd(status, val); 2192 if (changed & VTD_GCMD_TE) { 2193 /* Translation enable/disable */ 2194 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE); 2195 } 2196 if (val & VTD_GCMD_SRTP) { 2197 /* Set/update the root-table pointer */ 2198 vtd_handle_gcmd_srtp(s); 2199 } 2200 if (changed & VTD_GCMD_QIE) { 2201 /* Queued Invalidation Enable */ 2202 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE); 2203 } 2204 if (val & VTD_GCMD_SIRTP) { 2205 /* Set/update the interrupt remapping root-table pointer */ 2206 vtd_handle_gcmd_sirtp(s); 2207 } 2208 if (changed & VTD_GCMD_IRE) { 2209 /* Interrupt remap enable/disable */ 2210 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE); 2211 } 2212 } 2213 2214 /* Handle write to Context Command Register */ 2215 static void vtd_handle_ccmd_write(IntelIOMMUState *s) 2216 { 2217 uint64_t ret; 2218 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG); 2219 2220 /* Context-cache invalidation request */ 2221 if (val & VTD_CCMD_ICC) { 2222 if (s->qi_enabled) { 2223 error_report_once("Queued Invalidation enabled, " 2224 "should not use register-based invalidation"); 2225 return; 2226 } 2227 ret = vtd_context_cache_invalidate(s, val); 2228 /* Invalidation completed. Change something to show */ 2229 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL); 2230 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK, 2231 ret); 2232 } 2233 } 2234 2235 /* Handle write to IOTLB Invalidation Register */ 2236 static void vtd_handle_iotlb_write(IntelIOMMUState *s) 2237 { 2238 uint64_t ret; 2239 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG); 2240 2241 /* IOTLB invalidation request */ 2242 if (val & VTD_TLB_IVT) { 2243 if (s->qi_enabled) { 2244 error_report_once("Queued Invalidation enabled, " 2245 "should not use register-based invalidation"); 2246 return; 2247 } 2248 ret = vtd_iotlb_flush(s, val); 2249 /* Invalidation completed. Change something to show */ 2250 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL); 2251 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, 2252 VTD_TLB_FLUSH_GRANU_MASK_A, ret); 2253 } 2254 } 2255 2256 /* Fetch an Invalidation Descriptor from the Invalidation Queue */ 2257 static bool vtd_get_inv_desc(IntelIOMMUState *s, 2258 VTDInvDesc *inv_desc) 2259 { 2260 dma_addr_t base_addr = s->iq; 2261 uint32_t offset = s->iq_head; 2262 uint32_t dw = s->iq_dw ? 32 : 16; 2263 dma_addr_t addr = base_addr + offset * dw; 2264 2265 if (dma_memory_read(&address_space_memory, addr, inv_desc, dw)) { 2266 error_report_once("Read INV DESC failed."); 2267 return false; 2268 } 2269 inv_desc->lo = le64_to_cpu(inv_desc->lo); 2270 inv_desc->hi = le64_to_cpu(inv_desc->hi); 2271 if (dw == 32) { 2272 inv_desc->val[2] = le64_to_cpu(inv_desc->val[2]); 2273 inv_desc->val[3] = le64_to_cpu(inv_desc->val[3]); 2274 } 2275 return true; 2276 } 2277 2278 static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) 2279 { 2280 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) || 2281 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) { 2282 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 2283 " (reserved nonzero)", __func__, inv_desc->hi, 2284 inv_desc->lo); 2285 return false; 2286 } 2287 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) { 2288 /* Status Write */ 2289 uint32_t status_data = (uint32_t)(inv_desc->lo >> 2290 VTD_INV_DESC_WAIT_DATA_SHIFT); 2291 2292 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF)); 2293 2294 /* FIXME: need to be masked with HAW? */ 2295 dma_addr_t status_addr = inv_desc->hi; 2296 trace_vtd_inv_desc_wait_sw(status_addr, status_data); 2297 status_data = cpu_to_le32(status_data); 2298 if (dma_memory_write(&address_space_memory, status_addr, &status_data, 2299 sizeof(status_data))) { 2300 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo); 2301 return false; 2302 } 2303 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) { 2304 /* Interrupt flag */ 2305 vtd_generate_completion_event(s); 2306 } else { 2307 error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 2308 " (unknown type)", __func__, inv_desc->hi, 2309 inv_desc->lo); 2310 return false; 2311 } 2312 return true; 2313 } 2314 2315 static bool vtd_process_context_cache_desc(IntelIOMMUState *s, 2316 VTDInvDesc *inv_desc) 2317 { 2318 uint16_t sid, fmask; 2319 2320 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) { 2321 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 2322 " (reserved nonzero)", __func__, inv_desc->hi, 2323 inv_desc->lo); 2324 return false; 2325 } 2326 switch (inv_desc->lo & VTD_INV_DESC_CC_G) { 2327 case VTD_INV_DESC_CC_DOMAIN: 2328 trace_vtd_inv_desc_cc_domain( 2329 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo)); 2330 /* Fall through */ 2331 case VTD_INV_DESC_CC_GLOBAL: 2332 vtd_context_global_invalidate(s); 2333 break; 2334 2335 case VTD_INV_DESC_CC_DEVICE: 2336 sid = VTD_INV_DESC_CC_SID(inv_desc->lo); 2337 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo); 2338 vtd_context_device_invalidate(s, sid, fmask); 2339 break; 2340 2341 default: 2342 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 2343 " (invalid type)", __func__, inv_desc->hi, 2344 inv_desc->lo); 2345 return false; 2346 } 2347 return true; 2348 } 2349 2350 static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) 2351 { 2352 uint16_t domain_id; 2353 uint8_t am; 2354 hwaddr addr; 2355 2356 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) || 2357 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) { 2358 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2359 ", lo=0x%"PRIx64" (reserved bits unzero)\n", 2360 __func__, inv_desc->hi, inv_desc->lo); 2361 return false; 2362 } 2363 2364 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) { 2365 case VTD_INV_DESC_IOTLB_GLOBAL: 2366 vtd_iotlb_global_invalidate(s); 2367 break; 2368 2369 case VTD_INV_DESC_IOTLB_DOMAIN: 2370 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo); 2371 vtd_iotlb_domain_invalidate(s, domain_id); 2372 break; 2373 2374 case VTD_INV_DESC_IOTLB_PAGE: 2375 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo); 2376 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi); 2377 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi); 2378 if (am > VTD_MAMV) { 2379 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2380 ", lo=0x%"PRIx64" (am=%u > VTD_MAMV=%u)\n", 2381 __func__, inv_desc->hi, inv_desc->lo, 2382 am, (unsigned)VTD_MAMV); 2383 return false; 2384 } 2385 vtd_iotlb_page_invalidate(s, domain_id, addr, am); 2386 break; 2387 2388 default: 2389 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64 2390 ", lo=0x%"PRIx64" (type mismatch: 0x%llx)\n", 2391 __func__, inv_desc->hi, inv_desc->lo, 2392 inv_desc->lo & VTD_INV_DESC_IOTLB_G); 2393 return false; 2394 } 2395 return true; 2396 } 2397 2398 static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, 2399 VTDInvDesc *inv_desc) 2400 { 2401 trace_vtd_inv_desc_iec(inv_desc->iec.granularity, 2402 inv_desc->iec.index, 2403 inv_desc->iec.index_mask); 2404 2405 vtd_iec_notify_all(s, !inv_desc->iec.granularity, 2406 inv_desc->iec.index, 2407 inv_desc->iec.index_mask); 2408 return true; 2409 } 2410 2411 static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, 2412 VTDInvDesc *inv_desc) 2413 { 2414 VTDAddressSpace *vtd_dev_as; 2415 IOMMUTLBEntry entry; 2416 struct VTDBus *vtd_bus; 2417 hwaddr addr; 2418 uint64_t sz; 2419 uint16_t sid; 2420 uint8_t devfn; 2421 bool size; 2422 uint8_t bus_num; 2423 2424 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi); 2425 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo); 2426 devfn = sid & 0xff; 2427 bus_num = sid >> 8; 2428 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi); 2429 2430 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) || 2431 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) { 2432 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64 2433 ", lo=%"PRIx64" (reserved nonzero)", __func__, 2434 inv_desc->hi, inv_desc->lo); 2435 return false; 2436 } 2437 2438 vtd_bus = vtd_find_as_from_bus_num(s, bus_num); 2439 if (!vtd_bus) { 2440 goto done; 2441 } 2442 2443 vtd_dev_as = vtd_bus->dev_as[devfn]; 2444 if (!vtd_dev_as) { 2445 goto done; 2446 } 2447 2448 /* According to ATS spec table 2.4: 2449 * S = 0, bits 15:12 = xxxx range size: 4K 2450 * S = 1, bits 15:12 = xxx0 range size: 8K 2451 * S = 1, bits 15:12 = xx01 range size: 16K 2452 * S = 1, bits 15:12 = x011 range size: 32K 2453 * S = 1, bits 15:12 = 0111 range size: 64K 2454 * ... 2455 */ 2456 if (size) { 2457 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT); 2458 addr &= ~(sz - 1); 2459 } else { 2460 sz = VTD_PAGE_SIZE; 2461 } 2462 2463 entry.target_as = &vtd_dev_as->as; 2464 entry.addr_mask = sz - 1; 2465 entry.iova = addr; 2466 entry.perm = IOMMU_NONE; 2467 entry.translated_addr = 0; 2468 memory_region_notify_iommu(&vtd_dev_as->iommu, 0, entry); 2469 2470 done: 2471 return true; 2472 } 2473 2474 static bool vtd_process_inv_desc(IntelIOMMUState *s) 2475 { 2476 VTDInvDesc inv_desc; 2477 uint8_t desc_type; 2478 2479 trace_vtd_inv_qi_head(s->iq_head); 2480 if (!vtd_get_inv_desc(s, &inv_desc)) { 2481 s->iq_last_desc_type = VTD_INV_DESC_NONE; 2482 return false; 2483 } 2484 2485 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE; 2486 /* FIXME: should update at first or at last? */ 2487 s->iq_last_desc_type = desc_type; 2488 2489 switch (desc_type) { 2490 case VTD_INV_DESC_CC: 2491 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo); 2492 if (!vtd_process_context_cache_desc(s, &inv_desc)) { 2493 return false; 2494 } 2495 break; 2496 2497 case VTD_INV_DESC_IOTLB: 2498 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo); 2499 if (!vtd_process_iotlb_desc(s, &inv_desc)) { 2500 return false; 2501 } 2502 break; 2503 2504 /* 2505 * TODO: the entity of below two cases will be implemented in future series. 2506 * To make guest (which integrates scalable mode support patch set in 2507 * iommu driver) work, just return true is enough so far. 2508 */ 2509 case VTD_INV_DESC_PC: 2510 break; 2511 2512 case VTD_INV_DESC_PIOTLB: 2513 break; 2514 2515 case VTD_INV_DESC_WAIT: 2516 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo); 2517 if (!vtd_process_wait_desc(s, &inv_desc)) { 2518 return false; 2519 } 2520 break; 2521 2522 case VTD_INV_DESC_IEC: 2523 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo); 2524 if (!vtd_process_inv_iec_desc(s, &inv_desc)) { 2525 return false; 2526 } 2527 break; 2528 2529 case VTD_INV_DESC_DEVICE: 2530 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo); 2531 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) { 2532 return false; 2533 } 2534 break; 2535 2536 default: 2537 error_report_once("%s: invalid inv desc: hi=%"PRIx64", lo=%"PRIx64 2538 " (unknown type)", __func__, inv_desc.hi, 2539 inv_desc.lo); 2540 return false; 2541 } 2542 s->iq_head++; 2543 if (s->iq_head == s->iq_size) { 2544 s->iq_head = 0; 2545 } 2546 return true; 2547 } 2548 2549 /* Try to fetch and process more Invalidation Descriptors */ 2550 static void vtd_fetch_inv_desc(IntelIOMMUState *s) 2551 { 2552 trace_vtd_inv_qi_fetch(); 2553 2554 if (s->iq_tail >= s->iq_size) { 2555 /* Detects an invalid Tail pointer */ 2556 error_report_once("%s: detected invalid QI tail " 2557 "(tail=0x%x, size=0x%x)", 2558 __func__, s->iq_tail, s->iq_size); 2559 vtd_handle_inv_queue_error(s); 2560 return; 2561 } 2562 while (s->iq_head != s->iq_tail) { 2563 if (!vtd_process_inv_desc(s)) { 2564 /* Invalidation Queue Errors */ 2565 vtd_handle_inv_queue_error(s); 2566 break; 2567 } 2568 /* Must update the IQH_REG in time */ 2569 vtd_set_quad_raw(s, DMAR_IQH_REG, 2570 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) & 2571 VTD_IQH_QH_MASK); 2572 } 2573 } 2574 2575 /* Handle write to Invalidation Queue Tail Register */ 2576 static void vtd_handle_iqt_write(IntelIOMMUState *s) 2577 { 2578 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG); 2579 2580 if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) { 2581 error_report_once("%s: RSV bit is set: val=0x%"PRIx64, 2582 __func__, val); 2583 return; 2584 } 2585 s->iq_tail = VTD_IQT_QT(s->iq_dw, val); 2586 trace_vtd_inv_qi_tail(s->iq_tail); 2587 2588 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) { 2589 /* Process Invalidation Queue here */ 2590 vtd_fetch_inv_desc(s); 2591 } 2592 } 2593 2594 static void vtd_handle_fsts_write(IntelIOMMUState *s) 2595 { 2596 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG); 2597 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); 2598 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE; 2599 2600 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) { 2601 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 2602 trace_vtd_fsts_clear_ip(); 2603 } 2604 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation 2605 * Descriptors if there are any when Queued Invalidation is enabled? 2606 */ 2607 } 2608 2609 static void vtd_handle_fectl_write(IntelIOMMUState *s) 2610 { 2611 uint32_t fectl_reg; 2612 /* FIXME: when software clears the IM field, check the IP field. But do we 2613 * need to compare the old value and the new value to conclude that 2614 * software clears the IM field? Or just check if the IM field is zero? 2615 */ 2616 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG); 2617 2618 trace_vtd_reg_write_fectl(fectl_reg); 2619 2620 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) { 2621 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG); 2622 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0); 2623 } 2624 } 2625 2626 static void vtd_handle_ics_write(IntelIOMMUState *s) 2627 { 2628 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG); 2629 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); 2630 2631 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) { 2632 trace_vtd_reg_ics_clear_ip(); 2633 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 2634 } 2635 } 2636 2637 static void vtd_handle_iectl_write(IntelIOMMUState *s) 2638 { 2639 uint32_t iectl_reg; 2640 /* FIXME: when software clears the IM field, check the IP field. But do we 2641 * need to compare the old value and the new value to conclude that 2642 * software clears the IM field? Or just check if the IM field is zero? 2643 */ 2644 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG); 2645 2646 trace_vtd_reg_write_iectl(iectl_reg); 2647 2648 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) { 2649 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG); 2650 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0); 2651 } 2652 } 2653 2654 static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size) 2655 { 2656 IntelIOMMUState *s = opaque; 2657 uint64_t val; 2658 2659 trace_vtd_reg_read(addr, size); 2660 2661 if (addr + size > DMAR_REG_SIZE) { 2662 error_report_once("%s: MMIO over range: addr=0x%" PRIx64 2663 " size=0x%u", __func__, addr, size); 2664 return (uint64_t)-1; 2665 } 2666 2667 switch (addr) { 2668 /* Root Table Address Register, 64-bit */ 2669 case DMAR_RTADDR_REG: 2670 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG); 2671 if (size == 4) { 2672 val = val & ((1ULL << 32) - 1); 2673 } 2674 break; 2675 2676 case DMAR_RTADDR_REG_HI: 2677 assert(size == 4); 2678 val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32; 2679 break; 2680 2681 /* Invalidation Queue Address Register, 64-bit */ 2682 case DMAR_IQA_REG: 2683 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS); 2684 if (size == 4) { 2685 val = val & ((1ULL << 32) - 1); 2686 } 2687 break; 2688 2689 case DMAR_IQA_REG_HI: 2690 assert(size == 4); 2691 val = s->iq >> 32; 2692 break; 2693 2694 default: 2695 if (size == 4) { 2696 val = vtd_get_long(s, addr); 2697 } else { 2698 val = vtd_get_quad(s, addr); 2699 } 2700 } 2701 2702 return val; 2703 } 2704 2705 static void vtd_mem_write(void *opaque, hwaddr addr, 2706 uint64_t val, unsigned size) 2707 { 2708 IntelIOMMUState *s = opaque; 2709 2710 trace_vtd_reg_write(addr, size, val); 2711 2712 if (addr + size > DMAR_REG_SIZE) { 2713 error_report_once("%s: MMIO over range: addr=0x%" PRIx64 2714 " size=0x%u", __func__, addr, size); 2715 return; 2716 } 2717 2718 switch (addr) { 2719 /* Global Command Register, 32-bit */ 2720 case DMAR_GCMD_REG: 2721 vtd_set_long(s, addr, val); 2722 vtd_handle_gcmd_write(s); 2723 break; 2724 2725 /* Context Command Register, 64-bit */ 2726 case DMAR_CCMD_REG: 2727 if (size == 4) { 2728 vtd_set_long(s, addr, val); 2729 } else { 2730 vtd_set_quad(s, addr, val); 2731 vtd_handle_ccmd_write(s); 2732 } 2733 break; 2734 2735 case DMAR_CCMD_REG_HI: 2736 assert(size == 4); 2737 vtd_set_long(s, addr, val); 2738 vtd_handle_ccmd_write(s); 2739 break; 2740 2741 /* IOTLB Invalidation Register, 64-bit */ 2742 case DMAR_IOTLB_REG: 2743 if (size == 4) { 2744 vtd_set_long(s, addr, val); 2745 } else { 2746 vtd_set_quad(s, addr, val); 2747 vtd_handle_iotlb_write(s); 2748 } 2749 break; 2750 2751 case DMAR_IOTLB_REG_HI: 2752 assert(size == 4); 2753 vtd_set_long(s, addr, val); 2754 vtd_handle_iotlb_write(s); 2755 break; 2756 2757 /* Invalidate Address Register, 64-bit */ 2758 case DMAR_IVA_REG: 2759 if (size == 4) { 2760 vtd_set_long(s, addr, val); 2761 } else { 2762 vtd_set_quad(s, addr, val); 2763 } 2764 break; 2765 2766 case DMAR_IVA_REG_HI: 2767 assert(size == 4); 2768 vtd_set_long(s, addr, val); 2769 break; 2770 2771 /* Fault Status Register, 32-bit */ 2772 case DMAR_FSTS_REG: 2773 assert(size == 4); 2774 vtd_set_long(s, addr, val); 2775 vtd_handle_fsts_write(s); 2776 break; 2777 2778 /* Fault Event Control Register, 32-bit */ 2779 case DMAR_FECTL_REG: 2780 assert(size == 4); 2781 vtd_set_long(s, addr, val); 2782 vtd_handle_fectl_write(s); 2783 break; 2784 2785 /* Fault Event Data Register, 32-bit */ 2786 case DMAR_FEDATA_REG: 2787 assert(size == 4); 2788 vtd_set_long(s, addr, val); 2789 break; 2790 2791 /* Fault Event Address Register, 32-bit */ 2792 case DMAR_FEADDR_REG: 2793 if (size == 4) { 2794 vtd_set_long(s, addr, val); 2795 } else { 2796 /* 2797 * While the register is 32-bit only, some guests (Xen...) write to 2798 * it with 64-bit. 2799 */ 2800 vtd_set_quad(s, addr, val); 2801 } 2802 break; 2803 2804 /* Fault Event Upper Address Register, 32-bit */ 2805 case DMAR_FEUADDR_REG: 2806 assert(size == 4); 2807 vtd_set_long(s, addr, val); 2808 break; 2809 2810 /* Protected Memory Enable Register, 32-bit */ 2811 case DMAR_PMEN_REG: 2812 assert(size == 4); 2813 vtd_set_long(s, addr, val); 2814 break; 2815 2816 /* Root Table Address Register, 64-bit */ 2817 case DMAR_RTADDR_REG: 2818 if (size == 4) { 2819 vtd_set_long(s, addr, val); 2820 } else { 2821 vtd_set_quad(s, addr, val); 2822 } 2823 break; 2824 2825 case DMAR_RTADDR_REG_HI: 2826 assert(size == 4); 2827 vtd_set_long(s, addr, val); 2828 break; 2829 2830 /* Invalidation Queue Tail Register, 64-bit */ 2831 case DMAR_IQT_REG: 2832 if (size == 4) { 2833 vtd_set_long(s, addr, val); 2834 } else { 2835 vtd_set_quad(s, addr, val); 2836 } 2837 vtd_handle_iqt_write(s); 2838 break; 2839 2840 case DMAR_IQT_REG_HI: 2841 assert(size == 4); 2842 vtd_set_long(s, addr, val); 2843 /* 19:63 of IQT_REG is RsvdZ, do nothing here */ 2844 break; 2845 2846 /* Invalidation Queue Address Register, 64-bit */ 2847 case DMAR_IQA_REG: 2848 if (size == 4) { 2849 vtd_set_long(s, addr, val); 2850 } else { 2851 vtd_set_quad(s, addr, val); 2852 } 2853 if (s->ecap & VTD_ECAP_SMTS && 2854 val & VTD_IQA_DW_MASK) { 2855 s->iq_dw = true; 2856 } else { 2857 s->iq_dw = false; 2858 } 2859 break; 2860 2861 case DMAR_IQA_REG_HI: 2862 assert(size == 4); 2863 vtd_set_long(s, addr, val); 2864 break; 2865 2866 /* Invalidation Completion Status Register, 32-bit */ 2867 case DMAR_ICS_REG: 2868 assert(size == 4); 2869 vtd_set_long(s, addr, val); 2870 vtd_handle_ics_write(s); 2871 break; 2872 2873 /* Invalidation Event Control Register, 32-bit */ 2874 case DMAR_IECTL_REG: 2875 assert(size == 4); 2876 vtd_set_long(s, addr, val); 2877 vtd_handle_iectl_write(s); 2878 break; 2879 2880 /* Invalidation Event Data Register, 32-bit */ 2881 case DMAR_IEDATA_REG: 2882 assert(size == 4); 2883 vtd_set_long(s, addr, val); 2884 break; 2885 2886 /* Invalidation Event Address Register, 32-bit */ 2887 case DMAR_IEADDR_REG: 2888 assert(size == 4); 2889 vtd_set_long(s, addr, val); 2890 break; 2891 2892 /* Invalidation Event Upper Address Register, 32-bit */ 2893 case DMAR_IEUADDR_REG: 2894 assert(size == 4); 2895 vtd_set_long(s, addr, val); 2896 break; 2897 2898 /* Fault Recording Registers, 128-bit */ 2899 case DMAR_FRCD_REG_0_0: 2900 if (size == 4) { 2901 vtd_set_long(s, addr, val); 2902 } else { 2903 vtd_set_quad(s, addr, val); 2904 } 2905 break; 2906 2907 case DMAR_FRCD_REG_0_1: 2908 assert(size == 4); 2909 vtd_set_long(s, addr, val); 2910 break; 2911 2912 case DMAR_FRCD_REG_0_2: 2913 if (size == 4) { 2914 vtd_set_long(s, addr, val); 2915 } else { 2916 vtd_set_quad(s, addr, val); 2917 /* May clear bit 127 (Fault), update PPF */ 2918 vtd_update_fsts_ppf(s); 2919 } 2920 break; 2921 2922 case DMAR_FRCD_REG_0_3: 2923 assert(size == 4); 2924 vtd_set_long(s, addr, val); 2925 /* May clear bit 127 (Fault), update PPF */ 2926 vtd_update_fsts_ppf(s); 2927 break; 2928 2929 case DMAR_IRTA_REG: 2930 if (size == 4) { 2931 vtd_set_long(s, addr, val); 2932 } else { 2933 vtd_set_quad(s, addr, val); 2934 } 2935 break; 2936 2937 case DMAR_IRTA_REG_HI: 2938 assert(size == 4); 2939 vtd_set_long(s, addr, val); 2940 break; 2941 2942 default: 2943 if (size == 4) { 2944 vtd_set_long(s, addr, val); 2945 } else { 2946 vtd_set_quad(s, addr, val); 2947 } 2948 } 2949 } 2950 2951 static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr, 2952 IOMMUAccessFlags flag, int iommu_idx) 2953 { 2954 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); 2955 IntelIOMMUState *s = vtd_as->iommu_state; 2956 IOMMUTLBEntry iotlb = { 2957 /* We'll fill in the rest later. */ 2958 .target_as = &address_space_memory, 2959 }; 2960 bool success; 2961 2962 if (likely(s->dmar_enabled)) { 2963 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, 2964 addr, flag & IOMMU_WO, &iotlb); 2965 } else { 2966 /* DMAR disabled, passthrough, use 4k-page*/ 2967 iotlb.iova = addr & VTD_PAGE_MASK_4K; 2968 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K; 2969 iotlb.addr_mask = ~VTD_PAGE_MASK_4K; 2970 iotlb.perm = IOMMU_RW; 2971 success = true; 2972 } 2973 2974 if (likely(success)) { 2975 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus), 2976 VTD_PCI_SLOT(vtd_as->devfn), 2977 VTD_PCI_FUNC(vtd_as->devfn), 2978 iotlb.iova, iotlb.translated_addr, 2979 iotlb.addr_mask); 2980 } else { 2981 error_report_once("%s: detected translation failure " 2982 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64 ")", 2983 __func__, pci_bus_num(vtd_as->bus), 2984 VTD_PCI_SLOT(vtd_as->devfn), 2985 VTD_PCI_FUNC(vtd_as->devfn), 2986 addr); 2987 } 2988 2989 return iotlb; 2990 } 2991 2992 static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu, 2993 IOMMUNotifierFlag old, 2994 IOMMUNotifierFlag new, 2995 Error **errp) 2996 { 2997 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); 2998 IntelIOMMUState *s = vtd_as->iommu_state; 2999 3000 /* Update per-address-space notifier flags */ 3001 vtd_as->notifier_flags = new; 3002 3003 if (old == IOMMU_NOTIFIER_NONE) { 3004 QLIST_INSERT_HEAD(&s->vtd_as_with_notifiers, vtd_as, next); 3005 } else if (new == IOMMU_NOTIFIER_NONE) { 3006 QLIST_REMOVE(vtd_as, next); 3007 } 3008 return 0; 3009 } 3010 3011 static int vtd_post_load(void *opaque, int version_id) 3012 { 3013 IntelIOMMUState *iommu = opaque; 3014 3015 /* 3016 * Memory regions are dynamically turned on/off depending on 3017 * context entry configurations from the guest. After migration, 3018 * we need to make sure the memory regions are still correct. 3019 */ 3020 vtd_switch_address_space_all(iommu); 3021 3022 /* 3023 * We don't need to migrate the root_scalable because we can 3024 * simply do the calculation after the loading is complete. We 3025 * can actually do similar things with root, dmar_enabled, etc. 3026 * however since we've had them already so we'd better keep them 3027 * for compatibility of migration. 3028 */ 3029 vtd_update_scalable_state(iommu); 3030 3031 return 0; 3032 } 3033 3034 static const VMStateDescription vtd_vmstate = { 3035 .name = "iommu-intel", 3036 .version_id = 1, 3037 .minimum_version_id = 1, 3038 .priority = MIG_PRI_IOMMU, 3039 .post_load = vtd_post_load, 3040 .fields = (VMStateField[]) { 3041 VMSTATE_UINT64(root, IntelIOMMUState), 3042 VMSTATE_UINT64(intr_root, IntelIOMMUState), 3043 VMSTATE_UINT64(iq, IntelIOMMUState), 3044 VMSTATE_UINT32(intr_size, IntelIOMMUState), 3045 VMSTATE_UINT16(iq_head, IntelIOMMUState), 3046 VMSTATE_UINT16(iq_tail, IntelIOMMUState), 3047 VMSTATE_UINT16(iq_size, IntelIOMMUState), 3048 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState), 3049 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE), 3050 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState), 3051 VMSTATE_UNUSED(1), /* bool root_extended is obsolete by VT-d */ 3052 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState), 3053 VMSTATE_BOOL(qi_enabled, IntelIOMMUState), 3054 VMSTATE_BOOL(intr_enabled, IntelIOMMUState), 3055 VMSTATE_BOOL(intr_eime, IntelIOMMUState), 3056 VMSTATE_END_OF_LIST() 3057 } 3058 }; 3059 3060 static const MemoryRegionOps vtd_mem_ops = { 3061 .read = vtd_mem_read, 3062 .write = vtd_mem_write, 3063 .endianness = DEVICE_LITTLE_ENDIAN, 3064 .impl = { 3065 .min_access_size = 4, 3066 .max_access_size = 8, 3067 }, 3068 .valid = { 3069 .min_access_size = 4, 3070 .max_access_size = 8, 3071 }, 3072 }; 3073 3074 static Property vtd_properties[] = { 3075 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), 3076 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim, 3077 ON_OFF_AUTO_AUTO), 3078 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), 3079 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits, 3080 VTD_HOST_ADDRESS_WIDTH), 3081 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), 3082 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE), 3083 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), 3084 DEFINE_PROP_END_OF_LIST(), 3085 }; 3086 3087 /* Read IRTE entry with specific index */ 3088 static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index, 3089 VTD_IR_TableEntry *entry, uint16_t sid) 3090 { 3091 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \ 3092 {0xffff, 0xfffb, 0xfff9, 0xfff8}; 3093 dma_addr_t addr = 0x00; 3094 uint16_t mask, source_id; 3095 uint8_t bus, bus_max, bus_min; 3096 3097 addr = iommu->intr_root + index * sizeof(*entry); 3098 if (dma_memory_read(&address_space_memory, addr, entry, 3099 sizeof(*entry))) { 3100 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64, 3101 __func__, index, addr); 3102 return -VTD_FR_IR_ROOT_INVAL; 3103 } 3104 3105 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]), 3106 le64_to_cpu(entry->data[0])); 3107 3108 if (!entry->irte.present) { 3109 error_report_once("%s: detected non-present IRTE " 3110 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")", 3111 __func__, index, le64_to_cpu(entry->data[1]), 3112 le64_to_cpu(entry->data[0])); 3113 return -VTD_FR_IR_ENTRY_P; 3114 } 3115 3116 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 || 3117 entry->irte.__reserved_2) { 3118 error_report_once("%s: detected non-zero reserved IRTE " 3119 "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")", 3120 __func__, index, le64_to_cpu(entry->data[1]), 3121 le64_to_cpu(entry->data[0])); 3122 return -VTD_FR_IR_IRTE_RSVD; 3123 } 3124 3125 if (sid != X86_IOMMU_SID_INVALID) { 3126 /* Validate IRTE SID */ 3127 source_id = le32_to_cpu(entry->irte.source_id); 3128 switch (entry->irte.sid_vtype) { 3129 case VTD_SVT_NONE: 3130 break; 3131 3132 case VTD_SVT_ALL: 3133 mask = vtd_svt_mask[entry->irte.sid_q]; 3134 if ((source_id & mask) != (sid & mask)) { 3135 error_report_once("%s: invalid IRTE SID " 3136 "(index=%u, sid=%u, source_id=%u)", 3137 __func__, index, sid, source_id); 3138 return -VTD_FR_IR_SID_ERR; 3139 } 3140 break; 3141 3142 case VTD_SVT_BUS: 3143 bus_max = source_id >> 8; 3144 bus_min = source_id & 0xff; 3145 bus = sid >> 8; 3146 if (bus > bus_max || bus < bus_min) { 3147 error_report_once("%s: invalid SVT_BUS " 3148 "(index=%u, bus=%u, min=%u, max=%u)", 3149 __func__, index, bus, bus_min, bus_max); 3150 return -VTD_FR_IR_SID_ERR; 3151 } 3152 break; 3153 3154 default: 3155 error_report_once("%s: detected invalid IRTE SVT " 3156 "(index=%u, type=%d)", __func__, 3157 index, entry->irte.sid_vtype); 3158 /* Take this as verification failure. */ 3159 return -VTD_FR_IR_SID_ERR; 3160 break; 3161 } 3162 } 3163 3164 return 0; 3165 } 3166 3167 /* Fetch IRQ information of specific IR index */ 3168 static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, 3169 X86IOMMUIrq *irq, uint16_t sid) 3170 { 3171 VTD_IR_TableEntry irte = {}; 3172 int ret = 0; 3173 3174 ret = vtd_irte_get(iommu, index, &irte, sid); 3175 if (ret) { 3176 return ret; 3177 } 3178 3179 irq->trigger_mode = irte.irte.trigger_mode; 3180 irq->vector = irte.irte.vector; 3181 irq->delivery_mode = irte.irte.delivery_mode; 3182 irq->dest = le32_to_cpu(irte.irte.dest_id); 3183 if (!iommu->intr_eime) { 3184 #define VTD_IR_APIC_DEST_MASK (0xff00ULL) 3185 #define VTD_IR_APIC_DEST_SHIFT (8) 3186 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >> 3187 VTD_IR_APIC_DEST_SHIFT; 3188 } 3189 irq->dest_mode = irte.irte.dest_mode; 3190 irq->redir_hint = irte.irte.redir_hint; 3191 3192 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector, 3193 irq->delivery_mode, irq->dest, irq->dest_mode); 3194 3195 return 0; 3196 } 3197 3198 /* Interrupt remapping for MSI/MSI-X entry */ 3199 static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu, 3200 MSIMessage *origin, 3201 MSIMessage *translated, 3202 uint16_t sid) 3203 { 3204 int ret = 0; 3205 VTD_IR_MSIAddress addr; 3206 uint16_t index; 3207 X86IOMMUIrq irq = {}; 3208 3209 assert(origin && translated); 3210 3211 trace_vtd_ir_remap_msi_req(origin->address, origin->data); 3212 3213 if (!iommu || !iommu->intr_enabled) { 3214 memcpy(translated, origin, sizeof(*origin)); 3215 goto out; 3216 } 3217 3218 if (origin->address & VTD_MSI_ADDR_HI_MASK) { 3219 error_report_once("%s: MSI address high 32 bits non-zero detected: " 3220 "address=0x%" PRIx64, __func__, origin->address); 3221 return -VTD_FR_IR_REQ_RSVD; 3222 } 3223 3224 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK; 3225 if (addr.addr.__head != 0xfee) { 3226 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32, 3227 __func__, addr.data); 3228 return -VTD_FR_IR_REQ_RSVD; 3229 } 3230 3231 /* This is compatible mode. */ 3232 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) { 3233 memcpy(translated, origin, sizeof(*origin)); 3234 goto out; 3235 } 3236 3237 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l); 3238 3239 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff) 3240 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000) 3241 3242 if (addr.addr.sub_valid) { 3243 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */ 3244 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE; 3245 } 3246 3247 ret = vtd_remap_irq_get(iommu, index, &irq, sid); 3248 if (ret) { 3249 return ret; 3250 } 3251 3252 if (addr.addr.sub_valid) { 3253 trace_vtd_ir_remap_type("MSI"); 3254 if (origin->data & VTD_IR_MSI_DATA_RESERVED) { 3255 error_report_once("%s: invalid IR MSI " 3256 "(sid=%u, address=0x%" PRIx64 3257 ", data=0x%" PRIx32 ")", 3258 __func__, sid, origin->address, origin->data); 3259 return -VTD_FR_IR_REQ_RSVD; 3260 } 3261 } else { 3262 uint8_t vector = origin->data & 0xff; 3263 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 3264 3265 trace_vtd_ir_remap_type("IOAPIC"); 3266 /* IOAPIC entry vector should be aligned with IRTE vector 3267 * (see vt-d spec 5.1.5.1). */ 3268 if (vector != irq.vector) { 3269 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector); 3270 } 3271 3272 /* The Trigger Mode field must match the Trigger Mode in the IRTE. 3273 * (see vt-d spec 5.1.5.1). */ 3274 if (trigger_mode != irq.trigger_mode) { 3275 trace_vtd_warn_ir_trigger(sid, index, trigger_mode, 3276 irq.trigger_mode); 3277 } 3278 } 3279 3280 /* 3281 * We'd better keep the last two bits, assuming that guest OS 3282 * might modify it. Keep it does not hurt after all. 3283 */ 3284 irq.msi_addr_last_bits = addr.addr.__not_care; 3285 3286 /* Translate X86IOMMUIrq to MSI message */ 3287 x86_iommu_irq_to_msi_message(&irq, translated); 3288 3289 out: 3290 trace_vtd_ir_remap_msi(origin->address, origin->data, 3291 translated->address, translated->data); 3292 return 0; 3293 } 3294 3295 static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src, 3296 MSIMessage *dst, uint16_t sid) 3297 { 3298 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), 3299 src, dst, sid); 3300 } 3301 3302 static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr, 3303 uint64_t *data, unsigned size, 3304 MemTxAttrs attrs) 3305 { 3306 return MEMTX_OK; 3307 } 3308 3309 static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, 3310 uint64_t value, unsigned size, 3311 MemTxAttrs attrs) 3312 { 3313 int ret = 0; 3314 MSIMessage from = {}, to = {}; 3315 uint16_t sid = X86_IOMMU_SID_INVALID; 3316 3317 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; 3318 from.data = (uint32_t) value; 3319 3320 if (!attrs.unspecified) { 3321 /* We have explicit Source ID */ 3322 sid = attrs.requester_id; 3323 } 3324 3325 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid); 3326 if (ret) { 3327 /* TODO: report error */ 3328 /* Drop this interrupt */ 3329 return MEMTX_ERROR; 3330 } 3331 3332 apic_get_class()->send_msi(&to); 3333 3334 return MEMTX_OK; 3335 } 3336 3337 static const MemoryRegionOps vtd_mem_ir_ops = { 3338 .read_with_attrs = vtd_mem_ir_read, 3339 .write_with_attrs = vtd_mem_ir_write, 3340 .endianness = DEVICE_LITTLE_ENDIAN, 3341 .impl = { 3342 .min_access_size = 4, 3343 .max_access_size = 4, 3344 }, 3345 .valid = { 3346 .min_access_size = 4, 3347 .max_access_size = 4, 3348 }, 3349 }; 3350 3351 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) 3352 { 3353 uintptr_t key = (uintptr_t)bus; 3354 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key); 3355 VTDAddressSpace *vtd_dev_as; 3356 char name[128]; 3357 3358 if (!vtd_bus) { 3359 uintptr_t *new_key = g_malloc(sizeof(*new_key)); 3360 *new_key = (uintptr_t)bus; 3361 /* No corresponding free() */ 3362 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \ 3363 PCI_DEVFN_MAX); 3364 vtd_bus->bus = bus; 3365 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); 3366 } 3367 3368 vtd_dev_as = vtd_bus->dev_as[devfn]; 3369 3370 if (!vtd_dev_as) { 3371 snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), 3372 PCI_FUNC(devfn)); 3373 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace)); 3374 3375 vtd_dev_as->bus = bus; 3376 vtd_dev_as->devfn = (uint8_t)devfn; 3377 vtd_dev_as->iommu_state = s; 3378 vtd_dev_as->context_cache_entry.context_cache_gen = 0; 3379 vtd_dev_as->iova_tree = iova_tree_new(); 3380 3381 memory_region_init(&vtd_dev_as->root, OBJECT(s), name, UINT64_MAX); 3382 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, "vtd-root"); 3383 3384 /* 3385 * Build the DMAR-disabled container with aliases to the 3386 * shared MRs. Note that aliasing to a shared memory region 3387 * could help the memory API to detect same FlatViews so we 3388 * can have devices to share the same FlatView when DMAR is 3389 * disabled (either by not providing "intel_iommu=on" or with 3390 * "iommu=pt"). It will greatly reduce the total number of 3391 * FlatViews of the system hence VM runs faster. 3392 */ 3393 memory_region_init_alias(&vtd_dev_as->nodmar, OBJECT(s), 3394 "vtd-nodmar", &s->mr_nodmar, 0, 3395 memory_region_size(&s->mr_nodmar)); 3396 3397 /* 3398 * Build the per-device DMAR-enabled container. 3399 * 3400 * TODO: currently we have per-device IOMMU memory region only 3401 * because we have per-device IOMMU notifiers for devices. If 3402 * one day we can abstract the IOMMU notifiers out of the 3403 * memory regions then we can also share the same memory 3404 * region here just like what we've done above with the nodmar 3405 * region. 3406 */ 3407 strcat(name, "-dmar"); 3408 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu), 3409 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s), 3410 name, UINT64_MAX); 3411 memory_region_init_alias(&vtd_dev_as->iommu_ir, OBJECT(s), "vtd-ir", 3412 &s->mr_ir, 0, memory_region_size(&s->mr_ir)); 3413 memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as->iommu), 3414 VTD_INTERRUPT_ADDR_FIRST, 3415 &vtd_dev_as->iommu_ir, 1); 3416 3417 /* 3418 * Hook both the containers under the root container, we 3419 * switch between DMAR & noDMAR by enable/disable 3420 * corresponding sub-containers 3421 */ 3422 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, 3423 MEMORY_REGION(&vtd_dev_as->iommu), 3424 0); 3425 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0, 3426 &vtd_dev_as->nodmar, 0); 3427 3428 vtd_switch_address_space(vtd_dev_as); 3429 } 3430 return vtd_dev_as; 3431 } 3432 3433 static uint64_t get_naturally_aligned_size(uint64_t start, 3434 uint64_t size, int gaw) 3435 { 3436 uint64_t max_mask = 1ULL << gaw; 3437 uint64_t alignment = start ? start & -start : max_mask; 3438 3439 alignment = MIN(alignment, max_mask); 3440 size = MIN(size, max_mask); 3441 3442 if (alignment <= size) { 3443 /* Increase the alignment of start */ 3444 return alignment; 3445 } else { 3446 /* Find the largest page mask from size */ 3447 return 1ULL << (63 - clz64(size)); 3448 } 3449 } 3450 3451 /* Unmap the whole range in the notifier's scope. */ 3452 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) 3453 { 3454 hwaddr size, remain; 3455 hwaddr start = n->start; 3456 hwaddr end = n->end; 3457 IntelIOMMUState *s = as->iommu_state; 3458 DMAMap map; 3459 3460 /* 3461 * Note: all the codes in this function has a assumption that IOVA 3462 * bits are no more than VTD_MGAW bits (which is restricted by 3463 * VT-d spec), otherwise we need to consider overflow of 64 bits. 3464 */ 3465 3466 if (end > VTD_ADDRESS_SIZE(s->aw_bits) - 1) { 3467 /* 3468 * Don't need to unmap regions that is bigger than the whole 3469 * VT-d supported address space size 3470 */ 3471 end = VTD_ADDRESS_SIZE(s->aw_bits) - 1; 3472 } 3473 3474 assert(start <= end); 3475 size = remain = end - start + 1; 3476 3477 while (remain >= VTD_PAGE_SIZE) { 3478 IOMMUTLBEntry entry; 3479 uint64_t mask = get_naturally_aligned_size(start, remain, s->aw_bits); 3480 3481 assert(mask); 3482 3483 entry.iova = start; 3484 entry.addr_mask = mask - 1; 3485 entry.target_as = &address_space_memory; 3486 entry.perm = IOMMU_NONE; 3487 /* This field is meaningless for unmap */ 3488 entry.translated_addr = 0; 3489 3490 memory_region_notify_one(n, &entry); 3491 3492 start += mask; 3493 remain -= mask; 3494 } 3495 3496 assert(!remain); 3497 3498 trace_vtd_as_unmap_whole(pci_bus_num(as->bus), 3499 VTD_PCI_SLOT(as->devfn), 3500 VTD_PCI_FUNC(as->devfn), 3501 n->start, size); 3502 3503 map.iova = n->start; 3504 map.size = size; 3505 iova_tree_remove(as->iova_tree, &map); 3506 } 3507 3508 static void vtd_address_space_unmap_all(IntelIOMMUState *s) 3509 { 3510 VTDAddressSpace *vtd_as; 3511 IOMMUNotifier *n; 3512 3513 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { 3514 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) { 3515 vtd_address_space_unmap(vtd_as, n); 3516 } 3517 } 3518 } 3519 3520 static void vtd_address_space_refresh_all(IntelIOMMUState *s) 3521 { 3522 vtd_address_space_unmap_all(s); 3523 vtd_switch_address_space_all(s); 3524 } 3525 3526 static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private) 3527 { 3528 memory_region_notify_one((IOMMUNotifier *)private, entry); 3529 return 0; 3530 } 3531 3532 static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) 3533 { 3534 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu); 3535 IntelIOMMUState *s = vtd_as->iommu_state; 3536 uint8_t bus_n = pci_bus_num(vtd_as->bus); 3537 VTDContextEntry ce; 3538 3539 /* 3540 * The replay can be triggered by either a invalidation or a newly 3541 * created entry. No matter what, we release existing mappings 3542 * (it means flushing caches for UNMAP-only registers). 3543 */ 3544 vtd_address_space_unmap(vtd_as, n); 3545 3546 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) { 3547 trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" : 3548 "legacy mode", 3549 bus_n, PCI_SLOT(vtd_as->devfn), 3550 PCI_FUNC(vtd_as->devfn), 3551 vtd_get_domain_id(s, &ce), 3552 ce.hi, ce.lo); 3553 if (vtd_as_has_map_notifier(vtd_as)) { 3554 /* This is required only for MAP typed notifiers */ 3555 vtd_page_walk_info info = { 3556 .hook_fn = vtd_replay_hook, 3557 .private = (void *)n, 3558 .notify_unmap = false, 3559 .aw = s->aw_bits, 3560 .as = vtd_as, 3561 .domain_id = vtd_get_domain_id(s, &ce), 3562 }; 3563 3564 vtd_page_walk(s, &ce, 0, ~0ULL, &info); 3565 } 3566 } else { 3567 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn), 3568 PCI_FUNC(vtd_as->devfn)); 3569 } 3570 3571 return; 3572 } 3573 3574 /* Do the initialization. It will also be called when reset, so pay 3575 * attention when adding new initialization stuff. 3576 */ 3577 static void vtd_init(IntelIOMMUState *s) 3578 { 3579 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 3580 3581 memset(s->csr, 0, DMAR_REG_SIZE); 3582 memset(s->wmask, 0, DMAR_REG_SIZE); 3583 memset(s->w1cmask, 0, DMAR_REG_SIZE); 3584 memset(s->womask, 0, DMAR_REG_SIZE); 3585 3586 s->root = 0; 3587 s->root_scalable = false; 3588 s->dmar_enabled = false; 3589 s->intr_enabled = false; 3590 s->iq_head = 0; 3591 s->iq_tail = 0; 3592 s->iq = 0; 3593 s->iq_size = 0; 3594 s->qi_enabled = false; 3595 s->iq_last_desc_type = VTD_INV_DESC_NONE; 3596 s->iq_dw = false; 3597 s->next_frcd_reg = 0; 3598 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | 3599 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | 3600 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits); 3601 if (s->dma_drain) { 3602 s->cap |= VTD_CAP_DRAIN; 3603 } 3604 if (s->aw_bits == VTD_HOST_AW_48BIT) { 3605 s->cap |= VTD_CAP_SAGAW_48bit; 3606 } 3607 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; 3608 3609 /* 3610 * Rsvd field masks for spte 3611 */ 3612 vtd_spte_rsvd[0] = ~0ULL; 3613 vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, 3614 x86_iommu->dt_supported); 3615 vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); 3616 vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); 3617 vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); 3618 3619 vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, 3620 x86_iommu->dt_supported); 3621 vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, 3622 x86_iommu->dt_supported); 3623 3624 if (x86_iommu_ir_supported(x86_iommu)) { 3625 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; 3626 if (s->intr_eim == ON_OFF_AUTO_ON) { 3627 s->ecap |= VTD_ECAP_EIM; 3628 } 3629 assert(s->intr_eim != ON_OFF_AUTO_AUTO); 3630 } 3631 3632 if (x86_iommu->dt_supported) { 3633 s->ecap |= VTD_ECAP_DT; 3634 } 3635 3636 if (x86_iommu->pt_supported) { 3637 s->ecap |= VTD_ECAP_PT; 3638 } 3639 3640 if (s->caching_mode) { 3641 s->cap |= VTD_CAP_CM; 3642 } 3643 3644 /* TODO: read cap/ecap from host to decide which cap to be exposed. */ 3645 if (s->scalable_mode) { 3646 s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; 3647 } 3648 3649 vtd_reset_caches(s); 3650 3651 /* Define registers with default values and bit semantics */ 3652 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0); 3653 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0); 3654 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0); 3655 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0); 3656 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL); 3657 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0); 3658 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffffc00ULL, 0); 3659 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0); 3660 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL); 3661 3662 /* Advanced Fault Logging not supported */ 3663 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL); 3664 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0); 3665 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0); 3666 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0); 3667 3668 /* Treated as RsvdZ when EIM in ECAP_REG is not supported 3669 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0); 3670 */ 3671 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0); 3672 3673 /* Treated as RO for implementations that PLMR and PHMR fields reported 3674 * as Clear in the CAP_REG. 3675 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0); 3676 */ 3677 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0); 3678 3679 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0); 3680 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0); 3681 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff807ULL, 0); 3682 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL); 3683 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0); 3684 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0); 3685 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0); 3686 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */ 3687 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0); 3688 3689 /* IOTLB registers */ 3690 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0); 3691 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0); 3692 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL); 3693 3694 /* Fault Recording Registers, 128-bit */ 3695 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0); 3696 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL); 3697 3698 /* 3699 * Interrupt remapping registers. 3700 */ 3701 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0); 3702 } 3703 3704 /* Should not reset address_spaces when reset because devices will still use 3705 * the address space they got at first (won't ask the bus again). 3706 */ 3707 static void vtd_reset(DeviceState *dev) 3708 { 3709 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); 3710 3711 vtd_init(s); 3712 vtd_address_space_refresh_all(s); 3713 } 3714 3715 static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 3716 { 3717 IntelIOMMUState *s = opaque; 3718 VTDAddressSpace *vtd_as; 3719 3720 assert(0 <= devfn && devfn < PCI_DEVFN_MAX); 3721 3722 vtd_as = vtd_find_add_as(s, bus, devfn); 3723 return &vtd_as->as; 3724 } 3725 3726 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) 3727 { 3728 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); 3729 3730 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu_ir_supported(x86_iommu)) { 3731 error_setg(errp, "eim=on cannot be selected without intremap=on"); 3732 return false; 3733 } 3734 3735 if (s->intr_eim == ON_OFF_AUTO_AUTO) { 3736 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim) 3737 && x86_iommu_ir_supported(x86_iommu) ? 3738 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 3739 } 3740 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) { 3741 if (!kvm_irqchip_in_kernel()) { 3742 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split"); 3743 return false; 3744 } 3745 if (!kvm_enable_x2apic()) { 3746 error_setg(errp, "eim=on requires support on the KVM side" 3747 "(X2APIC_API, first shipped in v4.7)"); 3748 return false; 3749 } 3750 } 3751 3752 /* Currently only address widths supported are 39 and 48 bits */ 3753 if ((s->aw_bits != VTD_HOST_AW_39BIT) && 3754 (s->aw_bits != VTD_HOST_AW_48BIT)) { 3755 error_setg(errp, "Supported values for x-aw-bits are: %d, %d", 3756 VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT); 3757 return false; 3758 } 3759 3760 if (s->scalable_mode && !s->dma_drain) { 3761 error_setg(errp, "Need to set dma_drain for scalable mode"); 3762 return false; 3763 } 3764 3765 return true; 3766 } 3767 3768 static int vtd_machine_done_notify_one(Object *child, void *unused) 3769 { 3770 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 3771 3772 /* 3773 * We hard-coded here because vfio-pci is the only special case 3774 * here. Let's be more elegant in the future when we can, but so 3775 * far there seems to be no better way. 3776 */ 3777 if (object_dynamic_cast(child, "vfio-pci") && !iommu->caching_mode) { 3778 vtd_panic_require_caching_mode(); 3779 } 3780 3781 return 0; 3782 } 3783 3784 static void vtd_machine_done_hook(Notifier *notifier, void *unused) 3785 { 3786 object_child_foreach_recursive(object_get_root(), 3787 vtd_machine_done_notify_one, NULL); 3788 } 3789 3790 static Notifier vtd_machine_done_notify = { 3791 .notify = vtd_machine_done_hook, 3792 }; 3793 3794 static void vtd_realize(DeviceState *dev, Error **errp) 3795 { 3796 MachineState *ms = MACHINE(qdev_get_machine()); 3797 PCMachineState *pcms = PC_MACHINE(ms); 3798 X86MachineState *x86ms = X86_MACHINE(ms); 3799 PCIBus *bus = pcms->bus; 3800 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev); 3801 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); 3802 3803 x86_iommu->type = TYPE_INTEL; 3804 3805 if (!vtd_decide_config(s, errp)) { 3806 return; 3807 } 3808 3809 QLIST_INIT(&s->vtd_as_with_notifiers); 3810 qemu_mutex_init(&s->iommu_lock); 3811 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num)); 3812 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s, 3813 "intel_iommu", DMAR_REG_SIZE); 3814 3815 /* Create the shared memory regions by all devices */ 3816 memory_region_init(&s->mr_nodmar, OBJECT(s), "vtd-nodmar", 3817 UINT64_MAX); 3818 memory_region_init_io(&s->mr_ir, OBJECT(s), &vtd_mem_ir_ops, 3819 s, "vtd-ir", VTD_INTERRUPT_ADDR_SIZE); 3820 memory_region_init_alias(&s->mr_sys_alias, OBJECT(s), 3821 "vtd-sys-alias", get_system_memory(), 0, 3822 memory_region_size(get_system_memory())); 3823 memory_region_add_subregion_overlap(&s->mr_nodmar, 0, 3824 &s->mr_sys_alias, 0); 3825 memory_region_add_subregion_overlap(&s->mr_nodmar, 3826 VTD_INTERRUPT_ADDR_FIRST, 3827 &s->mr_ir, 1); 3828 3829 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem); 3830 /* No corresponding destroy */ 3831 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, 3832 g_free, g_free); 3833 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, 3834 g_free, g_free); 3835 vtd_init(s); 3836 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 3837 pci_setup_iommu(bus, vtd_host_dma_iommu, dev); 3838 /* Pseudo address space under root PCI bus. */ 3839 x86ms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC); 3840 qemu_add_machine_init_done_notifier(&vtd_machine_done_notify); 3841 } 3842 3843 static void vtd_class_init(ObjectClass *klass, void *data) 3844 { 3845 DeviceClass *dc = DEVICE_CLASS(klass); 3846 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass); 3847 3848 dc->reset = vtd_reset; 3849 dc->vmsd = &vtd_vmstate; 3850 device_class_set_props(dc, vtd_properties); 3851 dc->hotpluggable = false; 3852 x86_class->realize = vtd_realize; 3853 x86_class->int_remap = vtd_int_remap; 3854 /* Supported by the pc-q35-* machine types */ 3855 dc->user_creatable = true; 3856 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3857 dc->desc = "Intel IOMMU (VT-d) DMA Remapping device"; 3858 } 3859 3860 static const TypeInfo vtd_info = { 3861 .name = TYPE_INTEL_IOMMU_DEVICE, 3862 .parent = TYPE_X86_IOMMU_DEVICE, 3863 .instance_size = sizeof(IntelIOMMUState), 3864 .class_init = vtd_class_init, 3865 }; 3866 3867 static void vtd_iommu_memory_region_class_init(ObjectClass *klass, 3868 void *data) 3869 { 3870 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 3871 3872 imrc->translate = vtd_iommu_translate; 3873 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed; 3874 imrc->replay = vtd_iommu_replay; 3875 } 3876 3877 static const TypeInfo vtd_iommu_memory_region_info = { 3878 .parent = TYPE_IOMMU_MEMORY_REGION, 3879 .name = TYPE_INTEL_IOMMU_MEMORY_REGION, 3880 .class_init = vtd_iommu_memory_region_class_init, 3881 }; 3882 3883 static void vtd_register_types(void) 3884 { 3885 type_register_static(&vtd_info); 3886 type_register_static(&vtd_iommu_memory_region_info); 3887 } 3888 3889 type_init(vtd_register_types) 3890