1 /* 2 * QEMU emulation of an AMD IOMMU (AMD-Vi) 3 * 4 * Copyright (C) 2011 Eduard - Gabriel Munteanu 5 * Copyright (C) 2015 David Kiarie, <davidkiarie4@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef AMD_IOMMU_H_ 22 #define AMD_IOMMU_H_ 23 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/msi.h" 27 #include "hw/sysbus.h" 28 #include "sysemu/dma.h" 29 #include "hw/i386/pc.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/i386/x86-iommu.h" 32 33 /* Capability registers */ 34 #define AMDVI_CAPAB_BAR_LOW 0x04 35 #define AMDVI_CAPAB_BAR_HIGH 0x08 36 #define AMDVI_CAPAB_RANGE 0x0C 37 #define AMDVI_CAPAB_MISC 0x10 38 39 #define AMDVI_CAPAB_SIZE 0x18 40 #define AMDVI_CAPAB_REG_SIZE 0x04 41 42 /* Capability header data */ 43 #define AMDVI_CAPAB_ID_SEC 0xf 44 #define AMDVI_CAPAB_FLAT_EXT (1 << 28) 45 #define AMDVI_CAPAB_EFR_SUP (1 << 27) 46 #define AMDVI_CAPAB_FLAG_NPCACHE (1 << 26) 47 #define AMDVI_CAPAB_FLAG_HTTUNNEL (1 << 25) 48 #define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24) 49 #define AMDVI_CAPAB_INIT_TYPE (3 << 16) 50 51 /* No. of used MMIO registers */ 52 #define AMDVI_MMIO_REGS_HIGH 7 53 #define AMDVI_MMIO_REGS_LOW 8 54 55 /* MMIO registers */ 56 #define AMDVI_MMIO_DEVICE_TABLE 0x0000 57 #define AMDVI_MMIO_COMMAND_BASE 0x0008 58 #define AMDVI_MMIO_EVENT_BASE 0x0010 59 #define AMDVI_MMIO_CONTROL 0x0018 60 #define AMDVI_MMIO_EXCL_BASE 0x0020 61 #define AMDVI_MMIO_EXCL_LIMIT 0x0028 62 #define AMDVI_MMIO_EXT_FEATURES 0x0030 63 #define AMDVI_MMIO_COMMAND_HEAD 0x2000 64 #define AMDVI_MMIO_COMMAND_TAIL 0x2008 65 #define AMDVI_MMIO_EVENT_HEAD 0x2010 66 #define AMDVI_MMIO_EVENT_TAIL 0x2018 67 #define AMDVI_MMIO_STATUS 0x2020 68 #define AMDVI_MMIO_PPR_BASE 0x0038 69 #define AMDVI_MMIO_PPR_HEAD 0x2030 70 #define AMDVI_MMIO_PPR_TAIL 0x2038 71 72 #define AMDVI_MMIO_SIZE 0x4000 73 74 #define AMDVI_MMIO_DEVTAB_SIZE_MASK ((1ULL << 12) - 1) 75 #define AMDVI_MMIO_DEVTAB_BASE_MASK (((1ULL << 52) - 1) & ~ \ 76 AMDVI_MMIO_DEVTAB_SIZE_MASK) 77 #define AMDVI_MMIO_DEVTAB_ENTRY_SIZE 32 78 #define AMDVI_MMIO_DEVTAB_SIZE_UNIT 4096 79 80 /* some of this are similar but just for readability */ 81 #define AMDVI_MMIO_CMDBUF_SIZE_BYTE (AMDVI_MMIO_COMMAND_BASE + 7) 82 #define AMDVI_MMIO_CMDBUF_SIZE_MASK 0x0f 83 #define AMDVI_MMIO_CMDBUF_BASE_MASK AMDVI_MMIO_DEVTAB_BASE_MASK 84 #define AMDVI_MMIO_CMDBUF_HEAD_MASK (((1ULL << 19) - 1) & ~0x0f) 85 #define AMDVI_MMIO_CMDBUF_TAIL_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK 86 87 #define AMDVI_MMIO_EVTLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7) 88 #define AMDVI_MMIO_EVTLOG_SIZE_MASK AMDVI_MMIO_CMDBUF_SIZE_MASK 89 #define AMDVI_MMIO_EVTLOG_BASE_MASK AMDVI_MMIO_CMDBUF_BASE_MASK 90 #define AMDVI_MMIO_EVTLOG_HEAD_MASK (((1ULL << 19) - 1) & ~0x0f) 91 #define AMDVI_MMIO_EVTLOG_TAIL_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK 92 93 #define AMDVI_MMIO_PPRLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7) 94 #define AMDVI_MMIO_PPRLOG_HEAD_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK 95 #define AMDVI_MMIO_PPRLOG_TAIL_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK 96 #define AMDVI_MMIO_PPRLOG_BASE_MASK AMDVI_MMIO_EVTLOG_BASE_MASK 97 #define AMDVI_MMIO_PPRLOG_SIZE_MASK AMDVI_MMIO_EVTLOG_SIZE_MASK 98 99 #define AMDVI_MMIO_EXCL_ENABLED_MASK (1ULL << 0) 100 #define AMDVI_MMIO_EXCL_ALLOW_MASK (1ULL << 1) 101 #define AMDVI_MMIO_EXCL_LIMIT_MASK AMDVI_MMIO_DEVTAB_BASE_MASK 102 #define AMDVI_MMIO_EXCL_LIMIT_LOW 0xfff 103 104 /* mmio control register flags */ 105 #define AMDVI_MMIO_CONTROL_AMDVIEN (1ULL << 0) 106 #define AMDVI_MMIO_CONTROL_HTTUNEN (1ULL << 1) 107 #define AMDVI_MMIO_CONTROL_EVENTLOGEN (1ULL << 2) 108 #define AMDVI_MMIO_CONTROL_EVENTINTEN (1ULL << 3) 109 #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) 110 #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) 111 112 /* MMIO status register bits */ 113 #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) 114 #define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) 115 #define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) 116 #define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0) 117 118 #define AMDVI_CMDBUF_ID_BYTE 0x07 119 #define AMDVI_CMDBUF_ID_RSHIFT 4 120 121 #define AMDVI_CMD_COMPLETION_WAIT 0x01 122 #define AMDVI_CMD_INVAL_DEVTAB_ENTRY 0x02 123 #define AMDVI_CMD_INVAL_AMDVI_PAGES 0x03 124 #define AMDVI_CMD_INVAL_IOTLB_PAGES 0x04 125 #define AMDVI_CMD_INVAL_INTR_TABLE 0x05 126 #define AMDVI_CMD_PREFETCH_AMDVI_PAGES 0x06 127 #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 128 #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 129 130 #define AMDVI_DEVTAB_ENTRY_SIZE 32 131 132 /* Device table entry bits 0:63 */ 133 #define AMDVI_DEV_VALID (1ULL << 0) 134 #define AMDVI_DEV_TRANSLATION_VALID (1ULL << 1) 135 #define AMDVI_DEV_MODE_MASK 0x7 136 #define AMDVI_DEV_MODE_RSHIFT 9 137 #define AMDVI_DEV_PT_ROOT_MASK 0xffffffffff000 138 #define AMDVI_DEV_PT_ROOT_RSHIFT 12 139 #define AMDVI_DEV_PERM_SHIFT 61 140 #define AMDVI_DEV_PERM_READ (1ULL << 61) 141 #define AMDVI_DEV_PERM_WRITE (1ULL << 62) 142 143 /* Device table entry bits 64:127 */ 144 #define AMDVI_DEV_DOMID_ID_MASK ((1ULL << 16) - 1) 145 146 /* Event codes and flags, as stored in the info field */ 147 #define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12) 148 #define AMDVI_EVENT_IOPF (0x2U << 12) 149 #define AMDVI_EVENT_IOPF_I (1U << 3) 150 #define AMDVI_EVENT_DEV_TAB_HW_ERROR (0x3U << 12) 151 #define AMDVI_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12) 152 #define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12) 153 #define AMDVI_EVENT_COMMAND_HW_ERROR (0x6U << 12) 154 155 #define AMDVI_EVENT_LEN 16 156 #define AMDVI_PERM_READ (1 << 0) 157 #define AMDVI_PERM_WRITE (1 << 1) 158 159 #define AMDVI_FEATURE_PREFETCH (1ULL << 0) /* page prefetch */ 160 #define AMDVI_FEATURE_PPR (1ULL << 1) /* PPR Support */ 161 #define AMDVI_FEATURE_GT (1ULL << 4) /* Guest Translation */ 162 #define AMDVI_FEATURE_IA (1ULL << 6) /* inval all support */ 163 #define AMDVI_FEATURE_GA (1ULL << 7) /* guest VAPIC support */ 164 #define AMDVI_FEATURE_HE (1ULL << 8) /* hardware error regs */ 165 #define AMDVI_FEATURE_PC (1ULL << 9) /* Perf counters */ 166 167 /* reserved DTE bits */ 168 #define AMDVI_DTE_LOWER_QUAD_RESERVED 0x80300000000000fc 169 #define AMDVI_DTE_MIDDLE_QUAD_RESERVED 0x0000000000000100 170 #define AMDVI_DTE_UPPER_QUAD_RESERVED 0x08f0000000000000 171 172 /* AMDVI paging mode */ 173 #define AMDVI_GATS_MODE (6ULL << 12) 174 #define AMDVI_HATS_MODE (6ULL << 10) 175 176 /* IOTLB */ 177 #define AMDVI_IOTLB_MAX_SIZE 1024 178 #define AMDVI_DEVID_SHIFT 36 179 180 /* extended feature support */ 181 #define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ 182 AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ 183 AMDVI_GATS_MODE | AMDVI_HATS_MODE) 184 185 /* capabilities header */ 186 #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ 187 AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ 188 | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \ 189 AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP) 190 191 /* AMDVI default address */ 192 #define AMDVI_BASE_ADDR 0xfed80000 193 194 /* page management constants */ 195 #define AMDVI_PAGE_SHIFT 12 196 #define AMDVI_PAGE_SIZE (1ULL << AMDVI_PAGE_SHIFT) 197 198 #define AMDVI_PAGE_SHIFT_4K 12 199 #define AMDVI_PAGE_MASK_4K (~((1ULL << AMDVI_PAGE_SHIFT_4K) - 1)) 200 201 #define AMDVI_MAX_VA_ADDR (48UL << 5) 202 #define AMDVI_MAX_PH_ADDR (40UL << 8) 203 #define AMDVI_MAX_GVA_ADDR (48UL << 15) 204 205 /* Completion Wait data size */ 206 #define AMDVI_COMPLETION_DATA_SIZE 8 207 208 #define AMDVI_COMMAND_SIZE 16 209 /* Completion Wait data size */ 210 #define AMDVI_COMPLETION_DATA_SIZE 8 211 212 #define AMDVI_COMMAND_SIZE 16 213 214 #define AMDVI_INT_ADDR_FIRST 0xfee00000 215 #define AMDVI_INT_ADDR_LAST 0xfeefffff 216 217 #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" 218 #define AMD_IOMMU_DEVICE(obj)\ 219 OBJECT_CHECK(AMDVIState, (obj), TYPE_AMD_IOMMU_DEVICE) 220 221 #define TYPE_AMD_IOMMU_PCI "AMDVI-PCI" 222 223 #define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region" 224 225 typedef struct AMDVIAddressSpace AMDVIAddressSpace; 226 227 /* functions to steal PCI config space */ 228 typedef struct AMDVIPCIState { 229 PCIDevice dev; /* The PCI device itself */ 230 } AMDVIPCIState; 231 232 typedef struct AMDVIState { 233 X86IOMMUState iommu; /* IOMMU bus device */ 234 AMDVIPCIState pci; /* IOMMU PCI device */ 235 236 uint32_t version; 237 uint32_t capab_offset; /* capability offset pointer */ 238 239 uint64_t mmio_addr; 240 241 uint32_t devid; /* auto-assigned devid */ 242 243 bool enabled; /* IOMMU enabled */ 244 bool ats_enabled; /* address translation enabled */ 245 bool cmdbuf_enabled; /* command buffer enabled */ 246 bool evtlog_enabled; /* event log enabled */ 247 bool excl_enabled; 248 249 hwaddr devtab; /* base address device table */ 250 size_t devtab_len; /* device table length */ 251 252 hwaddr cmdbuf; /* command buffer base address */ 253 uint64_t cmdbuf_len; /* command buffer length */ 254 uint32_t cmdbuf_head; /* current IOMMU read position */ 255 uint32_t cmdbuf_tail; /* next Software write position */ 256 bool completion_wait_intr; 257 258 hwaddr evtlog; /* base address event log */ 259 bool evtlog_intr; 260 uint32_t evtlog_len; /* event log length */ 261 uint32_t evtlog_head; /* current IOMMU write position */ 262 uint32_t evtlog_tail; /* current Software read position */ 263 264 /* unused for now */ 265 hwaddr excl_base; /* base DVA - IOMMU exclusion range */ 266 hwaddr excl_limit; /* limit of IOMMU exclusion range */ 267 bool excl_allow; /* translate accesses to the exclusion range */ 268 bool excl_enable; /* exclusion range enabled */ 269 270 hwaddr ppr_log; /* base address ppr log */ 271 uint32_t pprlog_len; /* ppr log len */ 272 uint32_t pprlog_head; /* ppr log head */ 273 uint32_t pprlog_tail; /* ppr log tail */ 274 275 MemoryRegion mmio; /* MMIO region */ 276 uint8_t mmior[AMDVI_MMIO_SIZE]; /* read/write MMIO */ 277 uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */ 278 uint8_t romask[AMDVI_MMIO_SIZE]; /* MMIO read/only mask */ 279 bool mmio_enabled; 280 281 /* for each served device */ 282 AMDVIAddressSpace **address_spaces[PCI_BUS_MAX]; 283 284 /* IOTLB */ 285 GHashTable *iotlb; 286 } AMDVIState; 287 288 #endif 289