1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/piix.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/ich9.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 #include "hw/acpi/cxl.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool has_hpet; 117 #ifdef CONFIG_TPM 118 TPMVersion tpm_version; 119 #endif 120 const unsigned char *dsdt_code; 121 unsigned dsdt_size; 122 } AcpiMiscInfo; 123 124 typedef struct FwCfgTPMConfig { 125 uint32_t tpmppi_address; 126 uint8_t tpm_version; 127 uint8_t tpmppi_version; 128 } QEMU_PACKED FwCfgTPMConfig; 129 130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 131 132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 133 .space_id = AML_AS_SYSTEM_IO, 134 .address = NVDIMM_ACPI_IO_BASE, 135 .bit_width = NVDIMM_ACPI_IO_LEN << 3 136 }; 137 138 static void init_common_fadt_data(MachineState *ms, Object *o, 139 AcpiFadtData *data) 140 { 141 X86MachineState *x86ms = X86_MACHINE(ms); 142 /* 143 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 144 * behavior for compatibility irrelevant to smm_enabled, which doesn't 145 * comforms to ACPI spec. 146 */ 147 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 148 true : x86_machine_is_smm_enabled(x86ms); 149 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 150 AmlAddressSpace as = AML_AS_SYSTEM_IO; 151 AcpiFadtData fadt = { 152 .rev = 3, 153 .flags = 154 (1 << ACPI_FADT_F_WBINVD) | 155 (1 << ACPI_FADT_F_PROC_C1) | 156 (1 << ACPI_FADT_F_SLP_BUTTON) | 157 (1 << ACPI_FADT_F_RTC_S4) | 158 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 159 /* APIC destination mode ("Flat Logical") has an upper limit of 8 160 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 161 * used 162 */ 163 ((ms->smp.max_cpus > 8) ? 164 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 165 .int_model = 1 /* Multiple APIC */, 166 .rtc_century = RTC_CENTURY, 167 .plvl2_lat = 0xfff /* C2 state not supported */, 168 .plvl3_lat = 0xfff /* C3 state not supported */, 169 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 170 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 171 .acpi_enable_cmd = 172 smm_enabled ? 173 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 174 0, 175 .acpi_disable_cmd = 176 smm_enabled ? 177 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 178 0, 179 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 180 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 181 .address = io + 0x04 }, 182 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 183 .gpe0_blk = { .space_id = as, .bit_width = 184 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 185 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 186 }, 187 }; 188 189 /* 190 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 191 * Flags, bit offset 1 - 8042. 192 */ 193 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 194 195 *data = fadt; 196 } 197 198 static Object *object_resolve_type_unambiguous(const char *typename) 199 { 200 bool ambig; 201 Object *o = object_resolve_path_type("", typename, &ambig); 202 203 if (ambig || !o) { 204 return NULL; 205 } 206 return o; 207 } 208 209 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 210 { 211 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 212 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 213 Object *obj = piix ? piix : lpc; 214 QObject *o; 215 pm->cpu_hp_io_base = 0; 216 pm->pcihp_io_base = 0; 217 pm->pcihp_io_len = 0; 218 pm->smi_on_cpuhp = false; 219 pm->smi_on_cpu_unplug = false; 220 221 assert(obj); 222 init_common_fadt_data(machine, obj, &pm->fadt); 223 if (piix) { 224 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 225 pm->fadt.rev = 1; 226 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 227 } 228 if (lpc) { 229 uint64_t smi_features = object_property_get_uint(lpc, 230 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 231 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 232 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 233 pm->fadt.reset_reg = r; 234 pm->fadt.reset_val = 0xf; 235 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 236 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 237 pm->smi_on_cpuhp = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 239 pm->smi_on_cpu_unplug = 240 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 241 } 242 pm->pcihp_io_base = 243 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 244 pm->pcihp_io_len = 245 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 246 247 /* The above need not be conditional on machine type because the reset port 248 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 249 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 250 251 /* Fill in optional s3/s4 related properties */ 252 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 253 if (o) { 254 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 255 } else { 256 pm->s3_disabled = false; 257 } 258 qobject_unref(o); 259 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 260 if (o) { 261 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 262 } else { 263 pm->s4_disabled = false; 264 } 265 qobject_unref(o); 266 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 267 if (o) { 268 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 269 } else { 270 pm->s4_val = false; 271 } 272 qobject_unref(o); 273 274 pm->pcihp_bridge_en = 275 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 276 NULL); 277 pm->pcihp_root_en = 278 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 279 NULL); 280 } 281 282 static void acpi_get_misc_info(AcpiMiscInfo *info) 283 { 284 info->has_hpet = hpet_find(); 285 #ifdef CONFIG_TPM 286 info->tpm_version = tpm_get_version(tpm_find()); 287 #endif 288 } 289 290 /* 291 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 292 * On i386 arch we only have two pci hosts, so we can look only for them. 293 */ 294 Object *acpi_get_i386_pci_host(void) 295 { 296 PCIHostState *host; 297 298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 299 if (!host) { 300 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 301 } 302 303 return OBJECT(host); 304 } 305 306 static void acpi_get_pci_holes(Range *hole, Range *hole64) 307 { 308 Object *pci_host; 309 310 pci_host = acpi_get_i386_pci_host(); 311 312 if (!pci_host) { 313 return; 314 } 315 316 range_set_bounds1(hole, 317 object_property_get_uint(pci_host, 318 PCI_HOST_PROP_PCI_HOLE_START, 319 NULL), 320 object_property_get_uint(pci_host, 321 PCI_HOST_PROP_PCI_HOLE_END, 322 NULL)); 323 range_set_bounds1(hole64, 324 object_property_get_uint(pci_host, 325 PCI_HOST_PROP_PCI_HOLE64_START, 326 NULL), 327 object_property_get_uint(pci_host, 328 PCI_HOST_PROP_PCI_HOLE64_END, 329 NULL)); 330 } 331 332 static void acpi_align_size(GArray *blob, unsigned align) 333 { 334 /* Align size to multiple of given size. This reduces the chance 335 * we need to change size in the future (breaking cross version migration). 336 */ 337 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 338 } 339 340 /* 341 * ACPI spec 1.0b, 342 * 5.2.6 Firmware ACPI Control Structure 343 */ 344 static void 345 build_facs(GArray *table_data) 346 { 347 const char *sig = "FACS"; 348 const uint8_t reserved[40] = {}; 349 350 g_array_append_vals(table_data, sig, 4); /* Signature */ 351 build_append_int_noprefix(table_data, 64, 4); /* Length */ 352 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 353 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 354 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 355 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 356 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 357 } 358 359 Aml *aml_pci_device_dsm(void) 360 { 361 Aml *method; 362 363 method = aml_method("_DSM", 4, AML_SERIALIZED); 364 { 365 Aml *params = aml_local(0); 366 Aml *pkg = aml_package(2); 367 aml_append(pkg, aml_name("BSEL")); 368 aml_append(pkg, aml_name("ASUN")); 369 aml_append(method, aml_store(pkg, params)); 370 aml_append(method, 371 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 372 aml_arg(2), aml_arg(3), params)) 373 ); 374 } 375 return method; 376 } 377 378 static void build_append_pcihp_notify_entry(Aml *method, int slot) 379 { 380 Aml *if_ctx; 381 int32_t devfn = PCI_DEVFN(slot, 0); 382 383 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 384 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 385 aml_append(method, if_ctx); 386 } 387 388 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 389 bool pcihp_bridge_en) 390 { 391 Aml *dev, *notify_method = NULL, *method; 392 QObject *bsel; 393 PCIBus *sec; 394 int devfn; 395 396 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 397 if (bsel) { 398 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 399 400 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 401 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 402 } 403 404 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 405 DeviceClass *dc; 406 PCIDevice *pdev = bus->devices[devfn]; 407 int slot = PCI_SLOT(devfn); 408 int func = PCI_FUNC(devfn); 409 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 410 int adr = slot << 16 | func; 411 bool hotpluggbale_slot = false; 412 bool bridge_in_acpi = false; 413 bool cold_plugged_bridge = false; 414 415 if (pdev) { 416 dc = DEVICE_GET_CLASS(pdev); 417 418 /* 419 * Cold plugged bridges aren't themselves hot-pluggable. 420 * Hotplugged bridges *are* hot-pluggable. 421 */ 422 cold_plugged_bridge = IS_PCI_BRIDGE(pdev) && 423 !DEVICE(pdev)->hotplugged; 424 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 425 426 hotpluggbale_slot = bsel && dc->hotpluggable && 427 !cold_plugged_bridge; 428 429 /* 430 * allow describing coldplugged bridges in ACPI even if they are not 431 * on function 0, as they are not unpluggable, for all other devices 432 * generate description only for function 0 per slot, and for other 433 * functions if device on function provides its own AML 434 */ 435 if (func && !bridge_in_acpi && !get_dev_aml_func(DEVICE(pdev))) { 436 continue; 437 } 438 } else { 439 /* 440 * hotplug is supported only for non-multifunction device 441 * so generate device description only for function 0 442 */ 443 if (bsel && !func) { 444 if (pci_bus_is_express(bus) && slot > 0) { 445 break; 446 } 447 /* mark it as empty hotpluggable slot */ 448 hotpluggbale_slot = true; 449 } else { 450 continue; 451 } 452 } 453 454 /* start to compose PCI device descriptor */ 455 dev = aml_device("S%.02X", devfn); 456 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 457 458 if (bsel) { 459 /* 460 * Can't declare _SUN here for every device as it changes 'slot' 461 * enumeration order in linux kernel, so use another variable for it 462 */ 463 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 464 aml_append(dev, aml_pci_device_dsm()); 465 } 466 467 call_dev_aml_func(DEVICE(pdev), dev); 468 469 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 470 if (bridge_in_acpi) { 471 /* 472 * device is coldplugged bridge, 473 * add child device descriptions into its scope 474 */ 475 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 476 477 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 478 } 479 480 if (hotpluggbale_slot) { 481 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 482 /* add _EJ0 to make slot hotpluggable */ 483 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 484 aml_append(method, 485 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 486 ); 487 aml_append(dev, method); 488 489 build_append_pcihp_notify_entry(notify_method, slot); 490 } 491 492 /* device descriptor has been composed, add it into parent context */ 493 aml_append(parent_scope, dev); 494 } 495 496 if (bsel) { 497 aml_append(parent_scope, notify_method); 498 } 499 500 /* Append PCNT method to notify about events on local and child buses. 501 * Add this method for root bus only when hotplug is enabled since DSDT 502 * expects it. 503 */ 504 if (bsel || pcihp_bridge_en) { 505 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 506 507 /* If bus supports hotplug select it and notify about local events */ 508 if (bsel) { 509 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 510 511 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 512 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 513 aml_int(1))); /* Device Check */ 514 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 515 aml_int(3))); /* Eject Request */ 516 } 517 518 /* Notify about child bus events in any case */ 519 if (pcihp_bridge_en) { 520 QLIST_FOREACH(sec, &bus->child, sibling) { 521 if (pci_bus_is_root(sec)) { 522 continue; 523 } 524 525 aml_append(method, aml_name("^S%.02X.PCNT", 526 sec->parent_dev->devfn)); 527 } 528 } 529 530 aml_append(parent_scope, method); 531 } 532 qobject_unref(bsel); 533 } 534 535 static Aml *aml_pci_pdsm(void) 536 { 537 Aml *method, *UUID, *ifctx, *ifctx1; 538 Aml *ret = aml_local(0); 539 Aml *caps = aml_local(1); 540 Aml *acpi_index = aml_local(2); 541 Aml *zero = aml_int(0); 542 Aml *one = aml_int(1); 543 Aml *func = aml_arg(2); 544 Aml *rev = aml_arg(1); 545 Aml *params = aml_arg(4); 546 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 547 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 548 549 method = aml_method("PDSM", 5, AML_SERIALIZED); 550 551 /* get supported functions */ 552 ifctx = aml_if(aml_equal(func, zero)); 553 { 554 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 555 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); 556 aml_append(ifctx, aml_store(zero, caps)); 557 558 /* 559 * PCI Firmware Specification 3.1 560 * 4.6. _DSM Definitions for PCI 561 */ 562 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 563 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 564 { 565 /* call is for unsupported UUID, bail out */ 566 aml_append(ifctx1, aml_return(ret)); 567 } 568 aml_append(ifctx, ifctx1); 569 570 ifctx1 = aml_if(aml_lless(rev, aml_int(2))); 571 { 572 /* call is for unsupported REV, bail out */ 573 aml_append(ifctx1, aml_return(ret)); 574 } 575 aml_append(ifctx, ifctx1); 576 577 aml_append(ifctx, 578 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 579 /* 580 * advertise function 7 if device has acpi-index 581 * acpi_index values: 582 * 0: not present (default value) 583 * FFFFFFFF: not supported (old QEMU without PIDX reg) 584 * other: device's acpi-index 585 */ 586 ifctx1 = aml_if(aml_lnot( 587 aml_or(aml_equal(acpi_index, zero), 588 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 589 )); 590 { 591 /* have supported functions */ 592 aml_append(ifctx1, aml_or(caps, one, caps)); 593 /* support for function 7 */ 594 aml_append(ifctx1, 595 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 596 } 597 aml_append(ifctx, ifctx1); 598 599 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 600 aml_append(ifctx, aml_return(ret)); 601 } 602 aml_append(method, ifctx); 603 604 /* handle specific functions requests */ 605 /* 606 * PCI Firmware Specification 3.1 607 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 608 * Operating Systems 609 */ 610 ifctx = aml_if(aml_equal(func, aml_int(7))); 611 { 612 Aml *pkg = aml_package(2); 613 614 aml_append(pkg, zero); 615 /* 616 * optional, if not impl. should return null string 617 */ 618 aml_append(pkg, aml_string("%s", "")); 619 aml_append(ifctx, aml_store(pkg, ret)); 620 621 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 622 /* 623 * update acpi-index to actual value 624 */ 625 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 626 aml_append(ifctx, aml_return(ret)); 627 } 628 629 aml_append(method, ifctx); 630 return method; 631 } 632 633 /** 634 * build_prt_entry: 635 * @link_name: link name for PCI route entry 636 * 637 * build AML package containing a PCI route entry for @link_name 638 */ 639 static Aml *build_prt_entry(const char *link_name) 640 { 641 Aml *a_zero = aml_int(0); 642 Aml *pkg = aml_package(4); 643 aml_append(pkg, a_zero); 644 aml_append(pkg, a_zero); 645 aml_append(pkg, aml_name("%s", link_name)); 646 aml_append(pkg, a_zero); 647 return pkg; 648 } 649 650 /* 651 * initialize_route - Initialize the interrupt routing rule 652 * through a specific LINK: 653 * if (lnk_idx == idx) 654 * route using link 'link_name' 655 */ 656 static Aml *initialize_route(Aml *route, const char *link_name, 657 Aml *lnk_idx, int idx) 658 { 659 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 660 Aml *pkg = build_prt_entry(link_name); 661 662 aml_append(if_ctx, aml_store(pkg, route)); 663 664 return if_ctx; 665 } 666 667 /* 668 * build_prt - Define interrupt rounting rules 669 * 670 * Returns an array of 128 routes, one for each device, 671 * based on device location. 672 * The main goal is to equaly distribute the interrupts 673 * over the 4 existing ACPI links (works only for i440fx). 674 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 675 * 676 */ 677 static Aml *build_prt(bool is_pci0_prt) 678 { 679 Aml *method, *while_ctx, *pin, *res; 680 681 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 682 res = aml_local(0); 683 pin = aml_local(1); 684 aml_append(method, aml_store(aml_package(128), res)); 685 aml_append(method, aml_store(aml_int(0), pin)); 686 687 /* while (pin < 128) */ 688 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 689 { 690 Aml *slot = aml_local(2); 691 Aml *lnk_idx = aml_local(3); 692 Aml *route = aml_local(4); 693 694 /* slot = pin >> 2 */ 695 aml_append(while_ctx, 696 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 697 /* lnk_idx = (slot + pin) & 3 */ 698 aml_append(while_ctx, 699 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 700 lnk_idx)); 701 702 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 703 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 704 if (is_pci0_prt) { 705 Aml *if_device_1, *if_pin_4, *else_pin_4; 706 707 /* device 1 is the power-management device, needs SCI */ 708 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 709 { 710 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 711 { 712 aml_append(if_pin_4, 713 aml_store(build_prt_entry("LNKS"), route)); 714 } 715 aml_append(if_device_1, if_pin_4); 716 else_pin_4 = aml_else(); 717 { 718 aml_append(else_pin_4, 719 aml_store(build_prt_entry("LNKA"), route)); 720 } 721 aml_append(if_device_1, else_pin_4); 722 } 723 aml_append(while_ctx, if_device_1); 724 } else { 725 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 726 } 727 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 728 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 729 730 /* route[0] = 0x[slot]FFFF */ 731 aml_append(while_ctx, 732 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 733 NULL), 734 aml_index(route, aml_int(0)))); 735 /* route[1] = pin & 3 */ 736 aml_append(while_ctx, 737 aml_store(aml_and(pin, aml_int(3), NULL), 738 aml_index(route, aml_int(1)))); 739 /* res[pin] = route */ 740 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 741 /* pin++ */ 742 aml_append(while_ctx, aml_increment(pin)); 743 } 744 aml_append(method, while_ctx); 745 /* return res*/ 746 aml_append(method, aml_return(res)); 747 748 return method; 749 } 750 751 static void build_hpet_aml(Aml *table) 752 { 753 Aml *crs; 754 Aml *field; 755 Aml *method; 756 Aml *if_ctx; 757 Aml *scope = aml_scope("_SB"); 758 Aml *dev = aml_device("HPET"); 759 Aml *zero = aml_int(0); 760 Aml *id = aml_local(0); 761 Aml *period = aml_local(1); 762 763 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 764 aml_append(dev, aml_name_decl("_UID", zero)); 765 766 aml_append(dev, 767 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 768 HPET_LEN)); 769 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 770 aml_append(field, aml_named_field("VEND", 32)); 771 aml_append(field, aml_named_field("PRD", 32)); 772 aml_append(dev, field); 773 774 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 775 aml_append(method, aml_store(aml_name("VEND"), id)); 776 aml_append(method, aml_store(aml_name("PRD"), period)); 777 aml_append(method, aml_shiftright(id, aml_int(16), id)); 778 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 779 aml_equal(id, aml_int(0xffff)))); 780 { 781 aml_append(if_ctx, aml_return(zero)); 782 } 783 aml_append(method, if_ctx); 784 785 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 786 aml_lgreater(period, aml_int(100000000)))); 787 { 788 aml_append(if_ctx, aml_return(zero)); 789 } 790 aml_append(method, if_ctx); 791 792 aml_append(method, aml_return(aml_int(0x0F))); 793 aml_append(dev, method); 794 795 crs = aml_resource_template(); 796 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 797 aml_append(dev, aml_name_decl("_CRS", crs)); 798 799 aml_append(scope, dev); 800 aml_append(table, scope); 801 } 802 803 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 804 { 805 Aml *dev; 806 Aml *method; 807 Aml *crs; 808 809 dev = aml_device("VMBS"); 810 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 811 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 812 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 813 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 814 815 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 816 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 817 aml_name("STA"))); 818 aml_append(dev, method); 819 820 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 821 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 822 aml_name("STA"))); 823 aml_append(dev, method); 824 825 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 826 aml_append(method, aml_return(aml_name("STA"))); 827 aml_append(dev, method); 828 829 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 830 831 crs = aml_resource_template(); 832 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 833 aml_append(dev, aml_name_decl("_CRS", crs)); 834 835 return dev; 836 } 837 838 static void build_dbg_aml(Aml *table) 839 { 840 Aml *field; 841 Aml *method; 842 Aml *while_ctx; 843 Aml *scope = aml_scope("\\"); 844 Aml *buf = aml_local(0); 845 Aml *len = aml_local(1); 846 Aml *idx = aml_local(2); 847 848 aml_append(scope, 849 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 850 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 851 aml_append(field, aml_named_field("DBGB", 8)); 852 aml_append(scope, field); 853 854 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 855 856 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 857 aml_append(method, aml_to_buffer(buf, buf)); 858 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 859 aml_append(method, aml_store(aml_int(0), idx)); 860 861 while_ctx = aml_while(aml_lless(idx, len)); 862 aml_append(while_ctx, 863 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 864 aml_append(while_ctx, aml_increment(idx)); 865 aml_append(method, while_ctx); 866 867 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 868 aml_append(scope, method); 869 870 aml_append(table, scope); 871 } 872 873 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 874 { 875 Aml *dev; 876 Aml *crs; 877 Aml *method; 878 uint32_t irqs[] = {5, 10, 11}; 879 880 dev = aml_device("%s", name); 881 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 882 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 883 884 crs = aml_resource_template(); 885 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 886 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 887 aml_append(dev, aml_name_decl("_PRS", crs)); 888 889 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 890 aml_append(method, aml_return(aml_call1("IQST", reg))); 891 aml_append(dev, method); 892 893 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 894 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 895 aml_append(dev, method); 896 897 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 898 aml_append(method, aml_return(aml_call1("IQCR", reg))); 899 aml_append(dev, method); 900 901 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 902 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 903 aml_append(method, aml_store(aml_name("PRRI"), reg)); 904 aml_append(dev, method); 905 906 return dev; 907 } 908 909 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 910 { 911 Aml *dev; 912 Aml *crs; 913 Aml *method; 914 uint32_t irqs; 915 916 dev = aml_device("%s", name); 917 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 918 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 919 920 crs = aml_resource_template(); 921 irqs = gsi; 922 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 923 AML_SHARED, &irqs, 1)); 924 aml_append(dev, aml_name_decl("_PRS", crs)); 925 926 aml_append(dev, aml_name_decl("_CRS", crs)); 927 928 /* 929 * _DIS can be no-op because the interrupt cannot be disabled. 930 */ 931 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 932 aml_append(dev, method); 933 934 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 935 aml_append(dev, method); 936 937 return dev; 938 } 939 940 /* _CRS method - get current settings */ 941 static Aml *build_iqcr_method(bool is_piix4) 942 { 943 Aml *if_ctx; 944 uint32_t irqs; 945 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 946 Aml *crs = aml_resource_template(); 947 948 irqs = 0; 949 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 950 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 951 aml_append(method, aml_name_decl("PRR0", crs)); 952 953 aml_append(method, 954 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 955 956 if (is_piix4) { 957 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 958 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 959 aml_append(method, if_ctx); 960 } else { 961 aml_append(method, 962 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 963 aml_name("PRRI"))); 964 } 965 966 aml_append(method, aml_return(aml_name("PRR0"))); 967 return method; 968 } 969 970 /* _STA method - get status */ 971 static Aml *build_irq_status_method(void) 972 { 973 Aml *if_ctx; 974 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 975 976 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 977 aml_append(if_ctx, aml_return(aml_int(0x09))); 978 aml_append(method, if_ctx); 979 aml_append(method, aml_return(aml_int(0x0B))); 980 return method; 981 } 982 983 static void build_piix4_pci0_int(Aml *table) 984 { 985 Aml *dev; 986 Aml *crs; 987 Aml *method; 988 uint32_t irqs; 989 Aml *sb_scope = aml_scope("_SB"); 990 Aml *pci0_scope = aml_scope("PCI0"); 991 992 aml_append(pci0_scope, build_prt(true)); 993 aml_append(sb_scope, pci0_scope); 994 995 aml_append(sb_scope, build_irq_status_method()); 996 aml_append(sb_scope, build_iqcr_method(true)); 997 998 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 999 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1000 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1001 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1002 1003 dev = aml_device("LNKS"); 1004 { 1005 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1006 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1007 1008 crs = aml_resource_template(); 1009 irqs = 9; 1010 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1011 AML_ACTIVE_HIGH, AML_SHARED, 1012 &irqs, 1)); 1013 aml_append(dev, aml_name_decl("_PRS", crs)); 1014 1015 /* The SCI cannot be disabled and is always attached to GSI 9, 1016 * so these are no-ops. We only need this link to override the 1017 * polarity to active high and match the content of the MADT. 1018 */ 1019 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1020 aml_append(method, aml_return(aml_int(0x0b))); 1021 aml_append(dev, method); 1022 1023 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1024 aml_append(dev, method); 1025 1026 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1027 aml_append(method, aml_return(aml_name("_PRS"))); 1028 aml_append(dev, method); 1029 1030 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1031 aml_append(dev, method); 1032 } 1033 aml_append(sb_scope, dev); 1034 1035 aml_append(table, sb_scope); 1036 } 1037 1038 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1039 { 1040 int i; 1041 int head; 1042 Aml *pkg; 1043 char base = name[3] < 'E' ? 'A' : 'E'; 1044 char *s = g_strdup(name); 1045 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1046 1047 assert(strlen(s) == 4); 1048 1049 head = name[3] - base; 1050 for (i = 0; i < 4; i++) { 1051 if (head + i > 3) { 1052 head = i * -1; 1053 } 1054 s[3] = base + head + i; 1055 pkg = aml_package(4); 1056 aml_append(pkg, a_nr); 1057 aml_append(pkg, aml_int(i)); 1058 aml_append(pkg, aml_name("%s", s)); 1059 aml_append(pkg, aml_int(0)); 1060 aml_append(ctx, pkg); 1061 } 1062 g_free(s); 1063 } 1064 1065 static Aml *build_q35_routing_table(const char *str) 1066 { 1067 int i; 1068 Aml *pkg; 1069 char *name = g_strdup_printf("%s ", str); 1070 1071 pkg = aml_package(128); 1072 for (i = 0; i < 0x18; i++) { 1073 name[3] = 'E' + (i & 0x3); 1074 append_q35_prt_entry(pkg, i, name); 1075 } 1076 1077 name[3] = 'E'; 1078 append_q35_prt_entry(pkg, 0x18, name); 1079 1080 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1081 for (i = 0x0019; i < 0x1e; i++) { 1082 name[3] = 'A'; 1083 append_q35_prt_entry(pkg, i, name); 1084 } 1085 1086 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1087 name[3] = 'E'; 1088 append_q35_prt_entry(pkg, 0x1e, name); 1089 name[3] = 'A'; 1090 append_q35_prt_entry(pkg, 0x1f, name); 1091 1092 g_free(name); 1093 return pkg; 1094 } 1095 1096 static void build_q35_pci0_int(Aml *table) 1097 { 1098 Aml *method; 1099 Aml *sb_scope = aml_scope("_SB"); 1100 Aml *pci0_scope = aml_scope("PCI0"); 1101 1102 /* Zero => PIC mode, One => APIC Mode */ 1103 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1104 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1105 { 1106 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1107 } 1108 aml_append(table, method); 1109 1110 aml_append(pci0_scope, 1111 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1112 aml_append(pci0_scope, 1113 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1114 1115 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1116 { 1117 Aml *if_ctx; 1118 Aml *else_ctx; 1119 1120 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1121 section 6.2.8.1 */ 1122 /* Note: we provide the same info as the PCI routing 1123 table of the Bochs BIOS */ 1124 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1125 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1126 aml_append(method, if_ctx); 1127 else_ctx = aml_else(); 1128 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1129 aml_append(method, else_ctx); 1130 } 1131 aml_append(pci0_scope, method); 1132 aml_append(sb_scope, pci0_scope); 1133 1134 aml_append(sb_scope, build_irq_status_method()); 1135 aml_append(sb_scope, build_iqcr_method(false)); 1136 1137 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1138 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1139 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1140 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1141 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1142 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1143 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1144 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1145 1146 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1147 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1148 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1149 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1150 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1151 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1152 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1153 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1154 1155 aml_append(table, sb_scope); 1156 } 1157 1158 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1159 { 1160 Aml *dev; 1161 Aml *resource_template; 1162 1163 /* DRAM controller */ 1164 dev = aml_device("DRAC"); 1165 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1166 1167 resource_template = aml_resource_template(); 1168 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1169 aml_append(resource_template, 1170 aml_qword_memory(AML_POS_DECODE, 1171 AML_MIN_FIXED, 1172 AML_MAX_FIXED, 1173 AML_NON_CACHEABLE, 1174 AML_READ_WRITE, 1175 0x0000000000000000, 1176 mcfg->base, 1177 mcfg->base + mcfg->size - 1, 1178 0x0000000000000000, 1179 mcfg->size)); 1180 } else { 1181 aml_append(resource_template, 1182 aml_dword_memory(AML_POS_DECODE, 1183 AML_MIN_FIXED, 1184 AML_MAX_FIXED, 1185 AML_NON_CACHEABLE, 1186 AML_READ_WRITE, 1187 0x0000000000000000, 1188 mcfg->base, 1189 mcfg->base + mcfg->size - 1, 1190 0x0000000000000000, 1191 mcfg->size)); 1192 } 1193 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1194 1195 return dev; 1196 } 1197 1198 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1199 { 1200 Aml *scope; 1201 Aml *field; 1202 Aml *method; 1203 1204 scope = aml_scope("_SB.PCI0"); 1205 1206 aml_append(scope, 1207 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1208 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1209 aml_append(field, aml_named_field("PCIU", 32)); 1210 aml_append(field, aml_named_field("PCID", 32)); 1211 aml_append(scope, field); 1212 1213 aml_append(scope, 1214 aml_operation_region("SEJ", AML_SYSTEM_IO, 1215 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1216 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1217 aml_append(field, aml_named_field("B0EJ", 32)); 1218 aml_append(scope, field); 1219 1220 aml_append(scope, 1221 aml_operation_region("BNMR", AML_SYSTEM_IO, 1222 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1223 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1224 aml_append(field, aml_named_field("BNUM", 32)); 1225 aml_append(field, aml_named_field("PIDX", 32)); 1226 aml_append(scope, field); 1227 1228 aml_append(scope, aml_mutex("BLCK", 0)); 1229 1230 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1231 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1232 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1233 aml_append(method, 1234 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1235 aml_append(method, aml_release(aml_name("BLCK"))); 1236 aml_append(method, aml_return(aml_int(0))); 1237 aml_append(scope, method); 1238 1239 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1240 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1241 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1242 aml_append(method, 1243 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1244 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1245 aml_append(method, aml_release(aml_name("BLCK"))); 1246 aml_append(method, aml_return(aml_local(0))); 1247 aml_append(scope, method); 1248 1249 aml_append(scope, aml_pci_pdsm()); 1250 1251 aml_append(table, scope); 1252 } 1253 1254 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1255 { 1256 Aml *if_ctx; 1257 Aml *if_ctx2; 1258 Aml *else_ctx; 1259 Aml *method; 1260 Aml *a_cwd1 = aml_name("CDW1"); 1261 Aml *a_ctrl = aml_local(0); 1262 1263 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1264 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1265 1266 if_ctx = aml_if(aml_equal( 1267 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1268 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1269 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1270 1271 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1272 1273 /* 1274 * Always allow native PME, AER (no dependencies) 1275 * Allow SHPC (PCI bridges can have SHPC controller) 1276 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1277 */ 1278 aml_append(if_ctx, aml_and(a_ctrl, 1279 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1280 1281 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1282 /* Unknown revision */ 1283 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1284 aml_append(if_ctx, if_ctx2); 1285 1286 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1287 /* Capabilities bits were masked */ 1288 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1289 aml_append(if_ctx, if_ctx2); 1290 1291 /* Update DWORD3 in the buffer */ 1292 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1293 aml_append(method, if_ctx); 1294 1295 else_ctx = aml_else(); 1296 /* Unrecognized UUID */ 1297 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1298 aml_append(method, else_ctx); 1299 1300 aml_append(method, aml_return(aml_arg(3))); 1301 return method; 1302 } 1303 1304 static void build_acpi0017(Aml *table) 1305 { 1306 Aml *dev, *scope, *method; 1307 1308 scope = aml_scope("_SB"); 1309 dev = aml_device("CXLM"); 1310 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1311 1312 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1313 aml_append(method, aml_return(aml_int(0x01))); 1314 aml_append(dev, method); 1315 1316 aml_append(scope, dev); 1317 aml_append(table, scope); 1318 } 1319 1320 static void 1321 build_dsdt(GArray *table_data, BIOSLinker *linker, 1322 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1323 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1324 { 1325 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1326 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1327 CrsRangeEntry *entry; 1328 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1329 CrsRangeSet crs_range_set; 1330 PCMachineState *pcms = PC_MACHINE(machine); 1331 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1332 X86MachineState *x86ms = X86_MACHINE(machine); 1333 AcpiMcfgInfo mcfg; 1334 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1335 uint32_t nr_mem = machine->ram_slots; 1336 int root_bus_limit = 0xFF; 1337 PCIBus *bus = NULL; 1338 #ifdef CONFIG_TPM 1339 TPMIf *tpm = tpm_find(); 1340 #endif 1341 bool cxl_present = false; 1342 int i; 1343 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1344 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1345 .oem_table_id = x86ms->oem_table_id }; 1346 1347 assert(!!i440fx != !!q35); 1348 1349 acpi_table_begin(&table, table_data); 1350 dsdt = init_aml_allocator(); 1351 1352 build_dbg_aml(dsdt); 1353 if (i440fx) { 1354 sb_scope = aml_scope("_SB"); 1355 dev = aml_device("PCI0"); 1356 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1357 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1358 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1359 aml_append(sb_scope, dev); 1360 aml_append(dsdt, sb_scope); 1361 1362 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1363 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1364 } 1365 build_piix4_pci0_int(dsdt); 1366 } else if (q35) { 1367 sb_scope = aml_scope("_SB"); 1368 dev = aml_device("PCI0"); 1369 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1370 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1371 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1372 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1373 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1374 aml_append(sb_scope, dev); 1375 if (mcfg_valid) { 1376 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1377 } 1378 1379 if (pm->smi_on_cpuhp) { 1380 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1381 dev = aml_device("PCI0.SMI0"); 1382 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1383 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1384 crs = aml_resource_template(); 1385 aml_append(crs, 1386 aml_io( 1387 AML_DECODE16, 1388 ACPI_PORT_SMI_CMD, 1389 ACPI_PORT_SMI_CMD, 1390 1, 1391 2) 1392 ); 1393 aml_append(dev, aml_name_decl("_CRS", crs)); 1394 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1395 aml_int(ACPI_PORT_SMI_CMD), 2)); 1396 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1397 AML_WRITE_AS_ZEROS); 1398 aml_append(field, aml_named_field("SMIC", 8)); 1399 aml_append(field, aml_reserved_field(8)); 1400 aml_append(dev, field); 1401 aml_append(sb_scope, dev); 1402 } 1403 1404 aml_append(dsdt, sb_scope); 1405 1406 if (pm->pcihp_bridge_en) { 1407 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1408 } 1409 build_q35_pci0_int(dsdt); 1410 } 1411 1412 if (misc->has_hpet) { 1413 build_hpet_aml(dsdt); 1414 } 1415 1416 if (vmbus_bridge) { 1417 sb_scope = aml_scope("_SB"); 1418 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1419 aml_append(dsdt, sb_scope); 1420 } 1421 1422 scope = aml_scope("_GPE"); 1423 { 1424 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1425 if (machine->nvdimms_state->is_enabled) { 1426 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1427 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1428 aml_int(0x80))); 1429 aml_append(scope, method); 1430 } 1431 } 1432 aml_append(dsdt, scope); 1433 1434 if (pcmc->legacy_cpu_hotplug) { 1435 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1436 } else { 1437 CPUHotplugFeatures opts = { 1438 .acpi_1_compatible = true, .has_legacy_cphp = true, 1439 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1440 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1441 }; 1442 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1443 "\\_SB.PCI0", "\\_GPE._E02"); 1444 } 1445 1446 if (pcms->memhp_io_base && nr_mem) { 1447 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1448 "\\_GPE._E03", AML_SYSTEM_IO, 1449 pcms->memhp_io_base); 1450 } 1451 1452 crs_range_set_init(&crs_range_set); 1453 bus = PC_MACHINE(machine)->bus; 1454 if (bus) { 1455 QLIST_FOREACH(bus, &bus->child, sibling) { 1456 uint8_t bus_num = pci_bus_num(bus); 1457 uint8_t numa_node = pci_bus_numa_node(bus); 1458 1459 /* look only for expander root buses */ 1460 if (!pci_bus_is_root(bus)) { 1461 continue; 1462 } 1463 1464 if (bus_num < root_bus_limit) { 1465 root_bus_limit = bus_num - 1; 1466 } 1467 1468 scope = aml_scope("\\_SB"); 1469 1470 if (pci_bus_is_cxl(bus)) { 1471 dev = aml_device("CL%.02X", bus_num); 1472 } else { 1473 dev = aml_device("PC%.02X", bus_num); 1474 } 1475 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1476 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1477 if (pci_bus_is_cxl(bus)) { 1478 struct Aml *pkg = aml_package(2); 1479 1480 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1481 aml_append(pkg, aml_eisaid("PNP0A08")); 1482 aml_append(pkg, aml_eisaid("PNP0A03")); 1483 aml_append(dev, aml_name_decl("_CID", pkg)); 1484 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1485 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1486 build_cxl_osc_method(dev); 1487 } else if (pci_bus_is_express(bus)) { 1488 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1489 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1490 1491 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1492 aml_append(dev, build_q35_osc_method(true)); 1493 } else { 1494 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1495 } 1496 1497 if (numa_node != NUMA_NODE_UNASSIGNED) { 1498 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1499 } 1500 1501 aml_append(dev, build_prt(false)); 1502 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1503 0, 0, 0, 0); 1504 aml_append(dev, aml_name_decl("_CRS", crs)); 1505 aml_append(scope, dev); 1506 aml_append(dsdt, scope); 1507 1508 /* Handle the ranges for the PXB expanders */ 1509 if (pci_bus_is_cxl(bus)) { 1510 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1511 uint64_t base = mr->addr; 1512 1513 cxl_present = true; 1514 crs_range_insert(crs_range_set.mem_ranges, base, 1515 base + memory_region_size(mr) - 1); 1516 } 1517 } 1518 } 1519 1520 if (cxl_present) { 1521 build_acpi0017(dsdt); 1522 } 1523 1524 /* 1525 * At this point crs_range_set has all the ranges used by pci 1526 * busses *other* than PCI0. These ranges will be excluded from 1527 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1528 * too. 1529 */ 1530 if (mcfg_valid) { 1531 crs_range_insert(crs_range_set.mem_ranges, 1532 mcfg.base, mcfg.base + mcfg.size - 1); 1533 } 1534 1535 scope = aml_scope("\\_SB.PCI0"); 1536 /* build PCI0._CRS */ 1537 crs = aml_resource_template(); 1538 aml_append(crs, 1539 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1540 0x0000, 0x0, root_bus_limit, 1541 0x0000, root_bus_limit + 1)); 1542 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1543 1544 aml_append(crs, 1545 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1546 AML_POS_DECODE, AML_ENTIRE_RANGE, 1547 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1548 1549 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1550 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1551 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1552 aml_append(crs, 1553 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1554 AML_POS_DECODE, AML_ENTIRE_RANGE, 1555 0x0000, entry->base, entry->limit, 1556 0x0000, entry->limit - entry->base + 1)); 1557 } 1558 1559 aml_append(crs, 1560 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1561 AML_CACHEABLE, AML_READ_WRITE, 1562 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1563 1564 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1565 range_lob(pci_hole), 1566 range_upb(pci_hole)); 1567 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1568 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1569 aml_append(crs, 1570 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1571 AML_NON_CACHEABLE, AML_READ_WRITE, 1572 0, entry->base, entry->limit, 1573 0, entry->limit - entry->base + 1)); 1574 } 1575 1576 if (!range_is_empty(pci_hole64)) { 1577 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1578 range_lob(pci_hole64), 1579 range_upb(pci_hole64)); 1580 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1581 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1582 aml_append(crs, 1583 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1584 AML_MAX_FIXED, 1585 AML_CACHEABLE, AML_READ_WRITE, 1586 0, entry->base, entry->limit, 1587 0, entry->limit - entry->base + 1)); 1588 } 1589 } 1590 1591 #ifdef CONFIG_TPM 1592 if (TPM_IS_TIS_ISA(tpm_find())) { 1593 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1594 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1595 } 1596 #endif 1597 aml_append(scope, aml_name_decl("_CRS", crs)); 1598 1599 /* reserve GPE0 block resources */ 1600 dev = aml_device("GPE0"); 1601 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1602 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1603 /* device present, functioning, decoding, not shown in UI */ 1604 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1605 crs = aml_resource_template(); 1606 aml_append(crs, 1607 aml_io( 1608 AML_DECODE16, 1609 pm->fadt.gpe0_blk.address, 1610 pm->fadt.gpe0_blk.address, 1611 1, 1612 pm->fadt.gpe0_blk.bit_width / 8) 1613 ); 1614 aml_append(dev, aml_name_decl("_CRS", crs)); 1615 aml_append(scope, dev); 1616 1617 crs_range_set_free(&crs_range_set); 1618 1619 /* reserve PCIHP resources */ 1620 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1621 dev = aml_device("PHPR"); 1622 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1623 aml_append(dev, 1624 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1625 /* device present, functioning, decoding, not shown in UI */ 1626 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1627 crs = aml_resource_template(); 1628 aml_append(crs, 1629 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1630 pm->pcihp_io_len) 1631 ); 1632 aml_append(dev, aml_name_decl("_CRS", crs)); 1633 aml_append(scope, dev); 1634 } 1635 aml_append(dsdt, scope); 1636 1637 /* create S3_ / S4_ / S5_ packages if necessary */ 1638 scope = aml_scope("\\"); 1639 if (!pm->s3_disabled) { 1640 pkg = aml_package(4); 1641 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1642 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1643 aml_append(pkg, aml_int(0)); /* reserved */ 1644 aml_append(pkg, aml_int(0)); /* reserved */ 1645 aml_append(scope, aml_name_decl("_S3", pkg)); 1646 } 1647 1648 if (!pm->s4_disabled) { 1649 pkg = aml_package(4); 1650 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1651 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1652 aml_append(pkg, aml_int(pm->s4_val)); 1653 aml_append(pkg, aml_int(0)); /* reserved */ 1654 aml_append(pkg, aml_int(0)); /* reserved */ 1655 aml_append(scope, aml_name_decl("_S4", pkg)); 1656 } 1657 1658 pkg = aml_package(4); 1659 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1660 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1661 aml_append(pkg, aml_int(0)); /* reserved */ 1662 aml_append(pkg, aml_int(0)); /* reserved */ 1663 aml_append(scope, aml_name_decl("_S5", pkg)); 1664 aml_append(dsdt, scope); 1665 1666 /* create fw_cfg node, unconditionally */ 1667 { 1668 scope = aml_scope("\\_SB.PCI0"); 1669 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1670 aml_append(dsdt, scope); 1671 } 1672 1673 sb_scope = aml_scope("\\_SB"); 1674 { 1675 Object *pci_host = acpi_get_i386_pci_host(); 1676 1677 if (pci_host) { 1678 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1679 Aml *scope = aml_scope("PCI0"); 1680 /* Scan all PCI buses. Generate tables to support hotplug. */ 1681 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1682 aml_append(sb_scope, scope); 1683 } 1684 } 1685 1686 #ifdef CONFIG_TPM 1687 if (TPM_IS_CRB(tpm)) { 1688 dev = aml_device("TPM"); 1689 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1690 aml_append(dev, aml_name_decl("_STR", 1691 aml_string("TPM 2.0 Device"))); 1692 crs = aml_resource_template(); 1693 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1694 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1695 aml_append(dev, aml_name_decl("_CRS", crs)); 1696 1697 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1698 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1699 1700 tpm_build_ppi_acpi(tpm, dev); 1701 1702 aml_append(sb_scope, dev); 1703 } 1704 #endif 1705 1706 if (pcms->sgx_epc.size != 0) { 1707 uint64_t epc_base = pcms->sgx_epc.base; 1708 uint64_t epc_size = pcms->sgx_epc.size; 1709 1710 dev = aml_device("EPC"); 1711 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1712 aml_append(dev, aml_name_decl("_STR", 1713 aml_unicode("Enclave Page Cache 1.0"))); 1714 crs = aml_resource_template(); 1715 aml_append(crs, 1716 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1717 AML_MAX_FIXED, AML_NON_CACHEABLE, 1718 AML_READ_WRITE, 0, epc_base, 1719 epc_base + epc_size - 1, 0, epc_size)); 1720 aml_append(dev, aml_name_decl("_CRS", crs)); 1721 1722 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1723 aml_append(method, aml_return(aml_int(0x0f))); 1724 aml_append(dev, method); 1725 1726 aml_append(sb_scope, dev); 1727 } 1728 aml_append(dsdt, sb_scope); 1729 1730 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1731 scope = aml_scope("_GPE"); 1732 { 1733 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1734 aml_append(method, 1735 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1736 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1737 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1738 aml_append(scope, method); 1739 } 1740 aml_append(dsdt, scope); 1741 } 1742 1743 /* copy AML table into ACPI tables blob and patch header there */ 1744 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1745 acpi_table_end(linker, &table); 1746 free_aml_allocator(); 1747 } 1748 1749 /* 1750 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1751 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1752 */ 1753 static void 1754 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1755 const char *oem_table_id) 1756 { 1757 AcpiTable table = { .sig = "HPET", .rev = 1, 1758 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1759 1760 acpi_table_begin(&table, table_data); 1761 /* Note timer_block_id value must be kept in sync with value advertised by 1762 * emulated hpet 1763 */ 1764 /* Event Timer Block ID */ 1765 build_append_int_noprefix(table_data, 0x8086a201, 4); 1766 /* BASE_ADDRESS */ 1767 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1768 /* HPET Number */ 1769 build_append_int_noprefix(table_data, 0, 1); 1770 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1771 build_append_int_noprefix(table_data, 0, 2); 1772 /* Page Protection And OEM Attribute */ 1773 build_append_int_noprefix(table_data, 0, 1); 1774 acpi_table_end(linker, &table); 1775 } 1776 1777 #ifdef CONFIG_TPM 1778 /* 1779 * TCPA Description Table 1780 * 1781 * Following Level 00, Rev 00.37 of specs: 1782 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1783 * 7.1.2 ACPI Table Layout 1784 */ 1785 static void 1786 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1787 const char *oem_id, const char *oem_table_id) 1788 { 1789 unsigned log_addr_offset; 1790 AcpiTable table = { .sig = "TCPA", .rev = 2, 1791 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1792 1793 acpi_table_begin(&table, table_data); 1794 /* Platform Class */ 1795 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1796 /* Log Area Minimum Length (LAML) */ 1797 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1798 /* Log Area Start Address (LASA) */ 1799 log_addr_offset = table_data->len; 1800 build_append_int_noprefix(table_data, 0, 8); 1801 1802 /* allocate/reserve space for TPM log area */ 1803 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1804 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1805 false /* high memory */); 1806 /* log area start address to be filled by Guest linker */ 1807 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1808 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1809 1810 acpi_table_end(linker, &table); 1811 } 1812 #endif 1813 1814 #define HOLE_640K_START (640 * KiB) 1815 #define HOLE_640K_END (1 * MiB) 1816 1817 /* 1818 * ACPI spec, Revision 3.0 1819 * 5.2.15 System Resource Affinity Table (SRAT) 1820 */ 1821 static void 1822 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1823 { 1824 int i; 1825 int numa_mem_start, slots; 1826 uint64_t mem_len, mem_base, next_base; 1827 MachineClass *mc = MACHINE_GET_CLASS(machine); 1828 X86MachineState *x86ms = X86_MACHINE(machine); 1829 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1830 PCMachineState *pcms = PC_MACHINE(machine); 1831 int nb_numa_nodes = machine->numa_state->num_nodes; 1832 NodeInfo *numa_info = machine->numa_state->nodes; 1833 ram_addr_t hotpluggable_address_space_size = 1834 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1835 NULL); 1836 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1837 .oem_table_id = x86ms->oem_table_id }; 1838 1839 acpi_table_begin(&table, table_data); 1840 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1841 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1842 1843 for (i = 0; i < apic_ids->len; i++) { 1844 int node_id = apic_ids->cpus[i].props.node_id; 1845 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1846 1847 if (apic_id < 255) { 1848 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1849 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1850 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1851 /* Proximity Domain [7:0] */ 1852 build_append_int_noprefix(table_data, node_id, 1); 1853 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1854 /* Flags, Table 5-36 */ 1855 build_append_int_noprefix(table_data, 1, 4); 1856 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1857 /* Proximity Domain [31:8] */ 1858 build_append_int_noprefix(table_data, 0, 3); 1859 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1860 } else { 1861 /* 1862 * ACPI spec, Revision 4.0 1863 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1864 */ 1865 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1866 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1867 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1868 /* Proximity Domain */ 1869 build_append_int_noprefix(table_data, node_id, 4); 1870 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1871 /* Flags, Table 5-39 */ 1872 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1873 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1874 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1875 } 1876 } 1877 1878 /* the memory map is a bit tricky, it contains at least one hole 1879 * from 640k-1M and possibly another one from 3.5G-4G. 1880 */ 1881 next_base = 0; 1882 numa_mem_start = table_data->len; 1883 1884 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1885 mem_base = next_base; 1886 mem_len = numa_info[i - 1].node_mem; 1887 next_base = mem_base + mem_len; 1888 1889 /* Cut out the 640K hole */ 1890 if (mem_base <= HOLE_640K_START && 1891 next_base > HOLE_640K_START) { 1892 mem_len -= next_base - HOLE_640K_START; 1893 if (mem_len > 0) { 1894 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1895 MEM_AFFINITY_ENABLED); 1896 } 1897 1898 /* Check for the rare case: 640K < RAM < 1M */ 1899 if (next_base <= HOLE_640K_END) { 1900 next_base = HOLE_640K_END; 1901 continue; 1902 } 1903 mem_base = HOLE_640K_END; 1904 mem_len = next_base - HOLE_640K_END; 1905 } 1906 1907 /* Cut out the ACPI_PCI hole */ 1908 if (mem_base <= x86ms->below_4g_mem_size && 1909 next_base > x86ms->below_4g_mem_size) { 1910 mem_len -= next_base - x86ms->below_4g_mem_size; 1911 if (mem_len > 0) { 1912 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1913 MEM_AFFINITY_ENABLED); 1914 } 1915 mem_base = x86ms->above_4g_mem_start; 1916 mem_len = next_base - x86ms->below_4g_mem_size; 1917 next_base = mem_base + mem_len; 1918 } 1919 1920 if (mem_len > 0) { 1921 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1922 MEM_AFFINITY_ENABLED); 1923 } 1924 } 1925 1926 if (machine->nvdimms_state->is_enabled) { 1927 nvdimm_build_srat(table_data); 1928 } 1929 1930 sgx_epc_build_srat(table_data); 1931 1932 /* 1933 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1934 * without these entries. But I recall there were issues the last time I 1935 * tried to remove it with some ancient guest OS, however I can't remember 1936 * what that was so keep this around for now 1937 */ 1938 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1939 for (; slots < nb_numa_nodes + 2; slots++) { 1940 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1941 } 1942 1943 /* 1944 * Entry is required for Windows to enable memory hotplug in OS 1945 * and for Linux to enable SWIOTLB when booted with less than 1946 * 4G of RAM. Windows works better if the entry sets proximity 1947 * to the highest NUMA node in the machine. 1948 * Memory devices may override proximity set by this entry, 1949 * providing _PXM method if necessary. 1950 */ 1951 if (hotpluggable_address_space_size) { 1952 build_srat_memory(table_data, machine->device_memory->base, 1953 hotpluggable_address_space_size, nb_numa_nodes - 1, 1954 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1955 } 1956 1957 acpi_table_end(linker, &table); 1958 } 1959 1960 /* 1961 * Insert DMAR scope for PCI bridges and endpoint devcie 1962 */ 1963 static void 1964 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1965 { 1966 const size_t device_scope_size = 6 /* device scope structure */ + 1967 2 /* 1 path entry */; 1968 GArray *scope_blob = opaque; 1969 1970 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1971 /* Dmar Scope Type: 0x02 for PCI Bridge */ 1972 build_append_int_noprefix(scope_blob, 0x02, 1); 1973 } else { 1974 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 1975 build_append_int_noprefix(scope_blob, 0x01, 1); 1976 } 1977 1978 /* length */ 1979 build_append_int_noprefix(scope_blob, device_scope_size, 1); 1980 /* reserved */ 1981 build_append_int_noprefix(scope_blob, 0, 2); 1982 /* enumeration_id */ 1983 build_append_int_noprefix(scope_blob, 0, 1); 1984 /* bus */ 1985 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 1986 /* device */ 1987 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 1988 /* function */ 1989 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 1990 } 1991 1992 /* For a given PCI host bridge, walk and insert DMAR scope */ 1993 static int 1994 dmar_host_bridges(Object *obj, void *opaque) 1995 { 1996 GArray *scope_blob = opaque; 1997 1998 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1999 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2000 2001 if (bus && !pci_bus_bypass_iommu(bus)) { 2002 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2003 } 2004 } 2005 2006 return 0; 2007 } 2008 2009 /* 2010 * Intel ® Virtualization Technology for Directed I/O 2011 * Architecture Specification. Revision 3.3 2012 * 8.1 DMA Remapping Reporting Structure 2013 */ 2014 static void 2015 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2016 const char *oem_table_id) 2017 { 2018 uint8_t dmar_flags = 0; 2019 uint8_t rsvd10[10] = {}; 2020 /* Root complex IOAPIC uses one path only */ 2021 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2022 2 /* 1 path entry */; 2023 X86IOMMUState *iommu = x86_iommu_get_default(); 2024 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2025 GArray *scope_blob = g_array_new(false, true, 1); 2026 2027 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2028 .oem_table_id = oem_table_id }; 2029 2030 /* 2031 * A PCI bus walk, for each PCI host bridge. 2032 * Insert scope for each PCI bridge and endpoint device which 2033 * is attached to a bus with iommu enabled. 2034 */ 2035 object_child_foreach_recursive(object_get_root(), 2036 dmar_host_bridges, scope_blob); 2037 2038 assert(iommu); 2039 if (x86_iommu_ir_supported(iommu)) { 2040 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2041 } 2042 2043 acpi_table_begin(&table, table_data); 2044 /* Host Address Width */ 2045 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2046 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2047 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2048 2049 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2050 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2051 /* Length */ 2052 build_append_int_noprefix(table_data, 2053 16 + ioapic_scope_size + scope_blob->len, 2); 2054 /* Flags */ 2055 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2056 1); 2057 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2058 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2059 /* Register Base Address */ 2060 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2061 2062 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2063 * 8.3.1 (version Oct. 2014 or later). */ 2064 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2065 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2066 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2067 /* Enumeration ID */ 2068 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2069 /* Start Bus Number */ 2070 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2071 /* Path, {Device, Function} pair */ 2072 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2073 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2074 2075 /* Add scope found above */ 2076 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2077 g_array_free(scope_blob, true); 2078 2079 if (iommu->dt_supported) { 2080 /* 8.5 Root Port ATS Capability Reporting Structure */ 2081 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2082 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2083 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2084 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2085 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2086 } 2087 2088 acpi_table_end(linker, &table); 2089 } 2090 2091 /* 2092 * Windows ACPI Emulated Devices Table 2093 * (Version 1.0 - April 6, 2009) 2094 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2095 * 2096 * Helpful to speedup Windows guests and ignored by others. 2097 */ 2098 static void 2099 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2100 const char *oem_table_id) 2101 { 2102 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2103 .oem_table_id = oem_table_id }; 2104 2105 acpi_table_begin(&table, table_data); 2106 /* 2107 * Set "ACPI PM timer good" flag. 2108 * 2109 * Tells Windows guests that our ACPI PM timer is reliable in the 2110 * sense that guest can read it only once to obtain a reliable value. 2111 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2112 */ 2113 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2114 acpi_table_end(linker, &table); 2115 } 2116 2117 /* 2118 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2119 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2120 */ 2121 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2122 2123 /* 2124 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2125 * necessary for the PCI topology. 2126 */ 2127 static void 2128 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2129 { 2130 GArray *table_data = opaque; 2131 uint32_t entry; 2132 2133 /* "Select" IVHD entry, type 0x2 */ 2134 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2135 build_append_int_noprefix(table_data, entry, 4); 2136 2137 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2138 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2139 uint8_t sec = pci_bus_num(sec_bus); 2140 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2141 2142 if (pci_bus_is_express(sec_bus)) { 2143 /* 2144 * Walk the bus if there are subordinates, otherwise use a range 2145 * to cover an entire leaf bus. We could potentially also use a 2146 * range for traversed buses, but we'd need to take care not to 2147 * create both Select and Range entries covering the same device. 2148 * This is easier and potentially more compact. 2149 * 2150 * An example bare metal system seems to use Select entries for 2151 * root ports without a slot (ie. built-ins) and Range entries 2152 * when there is a slot. The same system also only hard-codes 2153 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2154 * making no effort to support nested bridges. We attempt to 2155 * be more thorough here. 2156 */ 2157 if (sec == sub) { /* leaf bus */ 2158 /* "Start of Range" IVHD entry, type 0x3 */ 2159 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2160 build_append_int_noprefix(table_data, entry, 4); 2161 /* "End of Range" IVHD entry, type 0x4 */ 2162 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2163 build_append_int_noprefix(table_data, entry, 4); 2164 } else { 2165 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2166 } 2167 } else { 2168 /* 2169 * If the secondary bus is conventional, then we need to create an 2170 * Alias range for everything downstream. The range covers the 2171 * first devfn on the secondary bus to the last devfn on the 2172 * subordinate bus. The alias target depends on legacy versus 2173 * express bridges, just as in pci_device_iommu_address_space(). 2174 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2175 */ 2176 uint16_t dev_id_a, dev_id_b; 2177 2178 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2179 2180 if (pci_is_express(dev) && 2181 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2182 dev_id_b = dev_id_a; 2183 } else { 2184 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2185 } 2186 2187 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2188 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2189 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2190 2191 /* "End of Range" IVHD entry, type 0x4 */ 2192 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2193 build_append_int_noprefix(table_data, entry, 4); 2194 } 2195 } 2196 } 2197 2198 /* For all PCI host bridges, walk and insert IVHD entries */ 2199 static int 2200 ivrs_host_bridges(Object *obj, void *opaque) 2201 { 2202 GArray *ivhd_blob = opaque; 2203 2204 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2205 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2206 2207 if (bus && !pci_bus_bypass_iommu(bus)) { 2208 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2209 } 2210 } 2211 2212 return 0; 2213 } 2214 2215 static void 2216 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2217 const char *oem_table_id) 2218 { 2219 int ivhd_table_len = 24; 2220 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2221 GArray *ivhd_blob = g_array_new(false, true, 1); 2222 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2223 .oem_table_id = oem_table_id }; 2224 2225 acpi_table_begin(&table, table_data); 2226 /* IVinfo - IO virtualization information common to all 2227 * IOMMU units in a system 2228 */ 2229 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2230 /* reserved */ 2231 build_append_int_noprefix(table_data, 0, 8); 2232 2233 /* IVHD definition - type 10h */ 2234 build_append_int_noprefix(table_data, 0x10, 1); 2235 /* virtualization flags */ 2236 build_append_int_noprefix(table_data, 2237 (1UL << 0) | /* HtTunEn */ 2238 (1UL << 4) | /* iotblSup */ 2239 (1UL << 6) | /* PrefSup */ 2240 (1UL << 7), /* PPRSup */ 2241 1); 2242 2243 /* 2244 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2245 * complete set of IVHD entries. Do this into a separate blob so that we 2246 * can calculate the total IVRS table length here and then append the new 2247 * blob further below. Fall back to an entry covering all devices, which 2248 * is sufficient when no aliases are present. 2249 */ 2250 object_child_foreach_recursive(object_get_root(), 2251 ivrs_host_bridges, ivhd_blob); 2252 2253 if (!ivhd_blob->len) { 2254 /* 2255 * Type 1 device entry reporting all devices 2256 * These are 4-byte device entries currently reporting the range of 2257 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2258 */ 2259 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2260 } 2261 2262 ivhd_table_len += ivhd_blob->len; 2263 2264 /* 2265 * When interrupt remapping is supported, we add a special IVHD device 2266 * for type IO-APIC. 2267 */ 2268 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2269 ivhd_table_len += 8; 2270 } 2271 2272 /* IVHD length */ 2273 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2274 /* DeviceID */ 2275 build_append_int_noprefix(table_data, s->devid, 2); 2276 /* Capability offset */ 2277 build_append_int_noprefix(table_data, s->capab_offset, 2); 2278 /* IOMMU base address */ 2279 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2280 /* PCI Segment Group */ 2281 build_append_int_noprefix(table_data, 0, 2); 2282 /* IOMMU info */ 2283 build_append_int_noprefix(table_data, 0, 2); 2284 /* IOMMU Feature Reporting */ 2285 build_append_int_noprefix(table_data, 2286 (48UL << 30) | /* HATS */ 2287 (48UL << 28) | /* GATS */ 2288 (1UL << 2) | /* GTSup */ 2289 (1UL << 6), /* GASup */ 2290 4); 2291 2292 /* IVHD entries as found above */ 2293 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2294 g_array_free(ivhd_blob, TRUE); 2295 2296 /* 2297 * Add a special IVHD device type. 2298 * Refer to spec - Table 95: IVHD device entry type codes 2299 * 2300 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2301 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2302 */ 2303 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2304 build_append_int_noprefix(table_data, 2305 (0x1ull << 56) | /* type IOAPIC */ 2306 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2307 0x48, /* special device */ 2308 8); 2309 } 2310 acpi_table_end(linker, &table); 2311 } 2312 2313 typedef 2314 struct AcpiBuildState { 2315 /* Copy of table in RAM (for patching). */ 2316 MemoryRegion *table_mr; 2317 /* Is table patched? */ 2318 uint8_t patched; 2319 void *rsdp; 2320 MemoryRegion *rsdp_mr; 2321 MemoryRegion *linker_mr; 2322 } AcpiBuildState; 2323 2324 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2325 { 2326 Object *pci_host; 2327 QObject *o; 2328 2329 pci_host = acpi_get_i386_pci_host(); 2330 if (!pci_host) { 2331 return false; 2332 } 2333 2334 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2335 if (!o) { 2336 return false; 2337 } 2338 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2339 qobject_unref(o); 2340 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2341 return false; 2342 } 2343 2344 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2345 assert(o); 2346 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2347 qobject_unref(o); 2348 return true; 2349 } 2350 2351 static 2352 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2353 { 2354 PCMachineState *pcms = PC_MACHINE(machine); 2355 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2356 X86MachineState *x86ms = X86_MACHINE(machine); 2357 DeviceState *iommu = pcms->iommu; 2358 GArray *table_offsets; 2359 unsigned facs, dsdt, rsdt, fadt; 2360 AcpiPmInfo pm; 2361 AcpiMiscInfo misc; 2362 AcpiMcfgInfo mcfg; 2363 Range pci_hole = {}, pci_hole64 = {}; 2364 uint8_t *u; 2365 size_t aml_len = 0; 2366 GArray *tables_blob = tables->table_data; 2367 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2368 Object *vmgenid_dev; 2369 char *oem_id; 2370 char *oem_table_id; 2371 2372 acpi_get_pm_info(machine, &pm); 2373 acpi_get_misc_info(&misc); 2374 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2375 acpi_get_slic_oem(&slic_oem); 2376 2377 if (slic_oem.id) { 2378 oem_id = slic_oem.id; 2379 } else { 2380 oem_id = x86ms->oem_id; 2381 } 2382 2383 if (slic_oem.table_id) { 2384 oem_table_id = slic_oem.table_id; 2385 } else { 2386 oem_table_id = x86ms->oem_table_id; 2387 } 2388 2389 table_offsets = g_array_new(false, true /* clear */, 2390 sizeof(uint32_t)); 2391 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2392 2393 bios_linker_loader_alloc(tables->linker, 2394 ACPI_BUILD_TABLE_FILE, tables_blob, 2395 64 /* Ensure FACS is aligned */, 2396 false /* high memory */); 2397 2398 /* 2399 * FACS is pointed to by FADT. 2400 * We place it first since it's the only table that has alignment 2401 * requirements. 2402 */ 2403 facs = tables_blob->len; 2404 build_facs(tables_blob); 2405 2406 /* DSDT is pointed to by FADT */ 2407 dsdt = tables_blob->len; 2408 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2409 &pci_hole, &pci_hole64, machine); 2410 2411 /* Count the size of the DSDT and SSDT, we will need it for legacy 2412 * sizing of ACPI tables. 2413 */ 2414 aml_len += tables_blob->len - dsdt; 2415 2416 /* ACPI tables pointed to by RSDT */ 2417 fadt = tables_blob->len; 2418 acpi_add_table(table_offsets, tables_blob); 2419 pm.fadt.facs_tbl_offset = &facs; 2420 pm.fadt.dsdt_tbl_offset = &dsdt; 2421 pm.fadt.xdsdt_tbl_offset = &dsdt; 2422 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2423 aml_len += tables_blob->len - fadt; 2424 2425 acpi_add_table(table_offsets, tables_blob); 2426 acpi_build_madt(tables_blob, tables->linker, x86ms, 2427 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2428 x86ms->oem_table_id); 2429 2430 #ifdef CONFIG_ACPI_ERST 2431 { 2432 Object *erst_dev; 2433 erst_dev = find_erst_dev(); 2434 if (erst_dev) { 2435 acpi_add_table(table_offsets, tables_blob); 2436 build_erst(tables_blob, tables->linker, erst_dev, 2437 x86ms->oem_id, x86ms->oem_table_id); 2438 } 2439 } 2440 #endif 2441 2442 vmgenid_dev = find_vmgenid_dev(); 2443 if (vmgenid_dev) { 2444 acpi_add_table(table_offsets, tables_blob); 2445 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2446 tables->vmgenid, tables->linker, x86ms->oem_id); 2447 } 2448 2449 if (misc.has_hpet) { 2450 acpi_add_table(table_offsets, tables_blob); 2451 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2452 x86ms->oem_table_id); 2453 } 2454 #ifdef CONFIG_TPM 2455 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2456 if (misc.tpm_version == TPM_VERSION_1_2) { 2457 acpi_add_table(table_offsets, tables_blob); 2458 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2459 x86ms->oem_id, x86ms->oem_table_id); 2460 } else { /* TPM_VERSION_2_0 */ 2461 acpi_add_table(table_offsets, tables_blob); 2462 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2463 x86ms->oem_id, x86ms->oem_table_id); 2464 } 2465 } 2466 #endif 2467 if (machine->numa_state->num_nodes) { 2468 acpi_add_table(table_offsets, tables_blob); 2469 build_srat(tables_blob, tables->linker, machine); 2470 if (machine->numa_state->have_numa_distance) { 2471 acpi_add_table(table_offsets, tables_blob); 2472 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2473 x86ms->oem_table_id); 2474 } 2475 if (machine->numa_state->hmat_enabled) { 2476 acpi_add_table(table_offsets, tables_blob); 2477 build_hmat(tables_blob, tables->linker, machine->numa_state, 2478 x86ms->oem_id, x86ms->oem_table_id); 2479 } 2480 } 2481 if (acpi_get_mcfg(&mcfg)) { 2482 acpi_add_table(table_offsets, tables_blob); 2483 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2484 x86ms->oem_table_id); 2485 } 2486 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2487 acpi_add_table(table_offsets, tables_blob); 2488 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2489 x86ms->oem_table_id); 2490 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2491 acpi_add_table(table_offsets, tables_blob); 2492 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2493 x86ms->oem_table_id); 2494 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2495 PCIDevice *pdev = PCI_DEVICE(iommu); 2496 2497 acpi_add_table(table_offsets, tables_blob); 2498 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2499 x86ms->oem_id, x86ms->oem_table_id); 2500 } 2501 if (machine->nvdimms_state->is_enabled) { 2502 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2503 machine->nvdimms_state, machine->ram_slots, 2504 x86ms->oem_id, x86ms->oem_table_id); 2505 } 2506 if (pcms->cxl_devices_state.is_enabled) { 2507 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2508 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2509 } 2510 2511 acpi_add_table(table_offsets, tables_blob); 2512 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2513 2514 /* Add tables supplied by user (if any) */ 2515 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2516 unsigned len = acpi_table_len(u); 2517 2518 acpi_add_table(table_offsets, tables_blob); 2519 g_array_append_vals(tables_blob, u, len); 2520 } 2521 2522 /* RSDT is pointed to by RSDP */ 2523 rsdt = tables_blob->len; 2524 build_rsdt(tables_blob, tables->linker, table_offsets, 2525 oem_id, oem_table_id); 2526 2527 /* RSDP is in FSEG memory, so allocate it separately */ 2528 { 2529 AcpiRsdpData rsdp_data = { 2530 .revision = 0, 2531 .oem_id = x86ms->oem_id, 2532 .xsdt_tbl_offset = NULL, 2533 .rsdt_tbl_offset = &rsdt, 2534 }; 2535 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2536 if (!pcmc->rsdp_in_ram) { 2537 /* We used to allocate some extra space for RSDP revision 2 but 2538 * only used the RSDP revision 0 space. The extra bytes were 2539 * zeroed out and not used. 2540 * Here we continue wasting those extra 16 bytes to make sure we 2541 * don't break migration for machine types 2.2 and older due to 2542 * RSDP blob size mismatch. 2543 */ 2544 build_append_int_noprefix(tables->rsdp, 0, 16); 2545 } 2546 } 2547 2548 /* We'll expose it all to Guest so we want to reduce 2549 * chance of size changes. 2550 * 2551 * We used to align the tables to 4k, but of course this would 2552 * too simple to be enough. 4k turned out to be too small an 2553 * alignment very soon, and in fact it is almost impossible to 2554 * keep the table size stable for all (max_cpus, max_memory_slots) 2555 * combinations. So the table size is always 64k for pc-i440fx-2.1 2556 * and we give an error if the table grows beyond that limit. 2557 * 2558 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2559 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2560 * than 2.0 and we can always pad the smaller tables with zeros. We can 2561 * then use the exact size of the 2.0 tables. 2562 * 2563 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2564 */ 2565 if (pcmc->legacy_acpi_table_size) { 2566 /* Subtracting aml_len gives the size of fixed tables. Then add the 2567 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2568 */ 2569 int legacy_aml_len = 2570 pcmc->legacy_acpi_table_size + 2571 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2572 int legacy_table_size = 2573 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2574 ACPI_BUILD_ALIGN_SIZE); 2575 if (tables_blob->len > legacy_table_size) { 2576 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2577 warn_report("ACPI table size %u exceeds %d bytes," 2578 " migration may not work", 2579 tables_blob->len, legacy_table_size); 2580 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2581 " or PCI bridges."); 2582 } 2583 g_array_set_size(tables_blob, legacy_table_size); 2584 } else { 2585 /* Make sure we have a buffer in case we need to resize the tables. */ 2586 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2587 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2588 warn_report("ACPI table size %u exceeds %d bytes," 2589 " migration may not work", 2590 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2591 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2592 " or PCI bridges."); 2593 } 2594 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2595 } 2596 2597 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2598 2599 /* Cleanup memory that's no longer used. */ 2600 g_array_free(table_offsets, true); 2601 g_free(slic_oem.id); 2602 g_free(slic_oem.table_id); 2603 } 2604 2605 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2606 { 2607 uint32_t size = acpi_data_len(data); 2608 2609 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2610 memory_region_ram_resize(mr, size, &error_abort); 2611 2612 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2613 memory_region_set_dirty(mr, 0, size); 2614 } 2615 2616 static void acpi_build_update(void *build_opaque) 2617 { 2618 AcpiBuildState *build_state = build_opaque; 2619 AcpiBuildTables tables; 2620 2621 /* No state to update or already patched? Nothing to do. */ 2622 if (!build_state || build_state->patched) { 2623 return; 2624 } 2625 build_state->patched = 1; 2626 2627 acpi_build_tables_init(&tables); 2628 2629 acpi_build(&tables, MACHINE(qdev_get_machine())); 2630 2631 acpi_ram_update(build_state->table_mr, tables.table_data); 2632 2633 if (build_state->rsdp) { 2634 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2635 } else { 2636 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2637 } 2638 2639 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2640 acpi_build_tables_cleanup(&tables, true); 2641 } 2642 2643 static void acpi_build_reset(void *build_opaque) 2644 { 2645 AcpiBuildState *build_state = build_opaque; 2646 build_state->patched = 0; 2647 } 2648 2649 static const VMStateDescription vmstate_acpi_build = { 2650 .name = "acpi_build", 2651 .version_id = 1, 2652 .minimum_version_id = 1, 2653 .fields = (VMStateField[]) { 2654 VMSTATE_UINT8(patched, AcpiBuildState), 2655 VMSTATE_END_OF_LIST() 2656 }, 2657 }; 2658 2659 void acpi_setup(void) 2660 { 2661 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2662 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2663 X86MachineState *x86ms = X86_MACHINE(pcms); 2664 AcpiBuildTables tables; 2665 AcpiBuildState *build_state; 2666 Object *vmgenid_dev; 2667 #ifdef CONFIG_TPM 2668 TPMIf *tpm; 2669 static FwCfgTPMConfig tpm_config; 2670 #endif 2671 2672 if (!x86ms->fw_cfg) { 2673 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2674 return; 2675 } 2676 2677 if (!pcms->acpi_build_enabled) { 2678 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2679 return; 2680 } 2681 2682 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2683 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2684 return; 2685 } 2686 2687 build_state = g_malloc0(sizeof *build_state); 2688 2689 acpi_build_tables_init(&tables); 2690 acpi_build(&tables, MACHINE(pcms)); 2691 2692 /* Now expose it all to Guest */ 2693 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2694 build_state, tables.table_data, 2695 ACPI_BUILD_TABLE_FILE); 2696 assert(build_state->table_mr != NULL); 2697 2698 build_state->linker_mr = 2699 acpi_add_rom_blob(acpi_build_update, build_state, 2700 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2701 2702 #ifdef CONFIG_TPM 2703 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2704 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2705 2706 tpm = tpm_find(); 2707 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2708 tpm_config = (FwCfgTPMConfig) { 2709 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2710 .tpm_version = tpm_get_version(tpm), 2711 .tpmppi_version = TPM_PPI_VERSION_1_30 2712 }; 2713 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2714 &tpm_config, sizeof tpm_config); 2715 } 2716 #endif 2717 2718 vmgenid_dev = find_vmgenid_dev(); 2719 if (vmgenid_dev) { 2720 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2721 tables.vmgenid); 2722 } 2723 2724 if (!pcmc->rsdp_in_ram) { 2725 /* 2726 * Keep for compatibility with old machine types. 2727 * Though RSDP is small, its contents isn't immutable, so 2728 * we'll update it along with the rest of tables on guest access. 2729 */ 2730 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2731 2732 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2733 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2734 acpi_build_update, NULL, build_state, 2735 build_state->rsdp, rsdp_size, true); 2736 build_state->rsdp_mr = NULL; 2737 } else { 2738 build_state->rsdp = NULL; 2739 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2740 build_state, tables.rsdp, 2741 ACPI_BUILD_RSDP_FILE); 2742 } 2743 2744 qemu_register_reset(acpi_build_reset, build_state); 2745 acpi_build_reset(build_state); 2746 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2747 2748 /* Cleanup tables but don't free the memory: we track it 2749 * in build_state. 2750 */ 2751 acpi_build_tables_cleanup(&tables, false); 2752 } 2753