1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "sysemu/tpm_backend.h" 47 #include "hw/rtc/mc146818rtc_regs.h" 48 #include "migration/vmstate.h" 49 #include "hw/mem/memory-device.h" 50 #include "hw/mem/nvdimm.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 #include "hw/hyperv/vmbus-bridge.h" 54 55 /* Supported chipsets: */ 56 #include "hw/southbridge/piix.h" 57 #include "hw/acpi/pcihp.h" 58 #include "hw/i386/fw_cfg.h" 59 #include "hw/i386/ich9.h" 60 #include "hw/pci/pci_bus.h" 61 #include "hw/pci-host/q35.h" 62 #include "hw/i386/x86-iommu.h" 63 64 #include "hw/acpi/aml-build.h" 65 #include "hw/acpi/utils.h" 66 #include "hw/acpi/pci.h" 67 68 #include "qom/qom-qobject.h" 69 #include "hw/i386/amd_iommu.h" 70 #include "hw/i386/intel_iommu.h" 71 72 #include "hw/acpi/ipmi.h" 73 #include "hw/acpi/hmat.h" 74 75 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 76 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 77 * a little bit, there should be plenty of free space since the DSDT 78 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 79 */ 80 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 81 #define ACPI_BUILD_ALIGN_SIZE 0x1000 82 83 #define ACPI_BUILD_TABLE_SIZE 0x20000 84 85 /* #define DEBUG_ACPI_BUILD */ 86 #ifdef DEBUG_ACPI_BUILD 87 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 88 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 89 #else 90 #define ACPI_BUILD_DPRINTF(fmt, ...) 91 #endif 92 93 typedef struct AcpiPmInfo { 94 bool s3_disabled; 95 bool s4_disabled; 96 bool pcihp_bridge_en; 97 bool smi_on_cpuhp; 98 bool smi_on_cpu_unplug; 99 bool pcihp_root_en; 100 uint8_t s4_val; 101 AcpiFadtData fadt; 102 uint16_t cpu_hp_io_base; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool is_piix4; 109 bool has_hpet; 110 #ifdef CONFIG_TPM 111 TPMVersion tpm_version; 112 #endif 113 const unsigned char *dsdt_code; 114 unsigned dsdt_size; 115 uint16_t pvpanic_port; 116 uint16_t applesmc_io_base; 117 } AcpiMiscInfo; 118 119 typedef struct AcpiBuildPciBusHotplugState { 120 GArray *device_table; 121 GArray *notify_table; 122 struct AcpiBuildPciBusHotplugState *parent; 123 bool pcihp_bridge_en; 124 } AcpiBuildPciBusHotplugState; 125 126 typedef struct FwCfgTPMConfig { 127 uint32_t tpmppi_address; 128 uint8_t tpm_version; 129 uint8_t tpmppi_version; 130 } QEMU_PACKED FwCfgTPMConfig; 131 132 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 133 134 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 135 .space_id = AML_AS_SYSTEM_IO, 136 .address = NVDIMM_ACPI_IO_BASE, 137 .bit_width = NVDIMM_ACPI_IO_LEN << 3 138 }; 139 140 static void init_common_fadt_data(MachineState *ms, Object *o, 141 AcpiFadtData *data) 142 { 143 X86MachineState *x86ms = X86_MACHINE(ms); 144 /* 145 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 146 * behavior for compatibility irrelevant to smm_enabled, which doesn't 147 * comforms to ACPI spec. 148 */ 149 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 150 true : x86_machine_is_smm_enabled(x86ms); 151 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 152 AmlAddressSpace as = AML_AS_SYSTEM_IO; 153 AcpiFadtData fadt = { 154 .rev = 3, 155 .flags = 156 (1 << ACPI_FADT_F_WBINVD) | 157 (1 << ACPI_FADT_F_PROC_C1) | 158 (1 << ACPI_FADT_F_SLP_BUTTON) | 159 (1 << ACPI_FADT_F_RTC_S4) | 160 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 161 /* APIC destination mode ("Flat Logical") has an upper limit of 8 162 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 163 * used 164 */ 165 ((ms->smp.max_cpus > 8) ? 166 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 167 .int_model = 1 /* Multiple APIC */, 168 .rtc_century = RTC_CENTURY, 169 .plvl2_lat = 0xfff /* C2 state not supported */, 170 .plvl3_lat = 0xfff /* C3 state not supported */, 171 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 172 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 173 .acpi_enable_cmd = 174 smm_enabled ? 175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 176 0, 177 .acpi_disable_cmd = 178 smm_enabled ? 179 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 180 0, 181 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 182 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 183 .address = io + 0x04 }, 184 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 185 .gpe0_blk = { .space_id = as, .bit_width = 186 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 187 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 188 }, 189 }; 190 *data = fadt; 191 } 192 193 static Object *object_resolve_type_unambiguous(const char *typename) 194 { 195 bool ambig; 196 Object *o = object_resolve_path_type("", typename, &ambig); 197 198 if (ambig || !o) { 199 return NULL; 200 } 201 return o; 202 } 203 204 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 205 { 206 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 207 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 208 Object *obj = piix ? piix : lpc; 209 QObject *o; 210 pm->cpu_hp_io_base = 0; 211 pm->pcihp_io_base = 0; 212 pm->pcihp_io_len = 0; 213 pm->smi_on_cpuhp = false; 214 pm->smi_on_cpu_unplug = false; 215 216 assert(obj); 217 init_common_fadt_data(machine, obj, &pm->fadt); 218 if (piix) { 219 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 220 pm->fadt.rev = 1; 221 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 222 pm->pcihp_io_base = 223 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 224 pm->pcihp_io_len = 225 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 226 } 227 if (lpc) { 228 uint64_t smi_features = object_property_get_uint(lpc, 229 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 230 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 231 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 232 pm->fadt.reset_reg = r; 233 pm->fadt.reset_val = 0xf; 234 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 235 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 236 pm->smi_on_cpuhp = 237 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 238 pm->smi_on_cpu_unplug = 239 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 240 } 241 242 /* The above need not be conditional on machine type because the reset port 243 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 244 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 245 246 /* Fill in optional s3/s4 related properties */ 247 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 248 if (o) { 249 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 250 } else { 251 pm->s3_disabled = false; 252 } 253 qobject_unref(o); 254 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 255 if (o) { 256 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 257 } else { 258 pm->s4_disabled = false; 259 } 260 qobject_unref(o); 261 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 262 if (o) { 263 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 264 } else { 265 pm->s4_val = false; 266 } 267 qobject_unref(o); 268 269 pm->pcihp_bridge_en = 270 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 271 NULL); 272 pm->pcihp_root_en = 273 object_property_get_bool(obj, "acpi-root-pci-hotplug", 274 NULL); 275 } 276 277 static void acpi_get_misc_info(AcpiMiscInfo *info) 278 { 279 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 280 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 281 assert(!!piix != !!lpc); 282 283 if (piix) { 284 info->is_piix4 = true; 285 } 286 if (lpc) { 287 info->is_piix4 = false; 288 } 289 290 info->has_hpet = hpet_find(); 291 #ifdef CONFIG_TPM 292 info->tpm_version = tpm_get_version(tpm_find()); 293 #endif 294 info->pvpanic_port = pvpanic_port(); 295 info->applesmc_io_base = applesmc_port(); 296 } 297 298 /* 299 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 300 * On i386 arch we only have two pci hosts, so we can look only for them. 301 */ 302 static Object *acpi_get_i386_pci_host(void) 303 { 304 PCIHostState *host; 305 306 host = OBJECT_CHECK(PCIHostState, 307 object_resolve_path("/machine/i440fx", NULL), 308 TYPE_PCI_HOST_BRIDGE); 309 if (!host) { 310 host = OBJECT_CHECK(PCIHostState, 311 object_resolve_path("/machine/q35", NULL), 312 TYPE_PCI_HOST_BRIDGE); 313 } 314 315 return OBJECT(host); 316 } 317 318 static void acpi_get_pci_holes(Range *hole, Range *hole64) 319 { 320 Object *pci_host; 321 322 pci_host = acpi_get_i386_pci_host(); 323 g_assert(pci_host); 324 325 range_set_bounds1(hole, 326 object_property_get_uint(pci_host, 327 PCI_HOST_PROP_PCI_HOLE_START, 328 NULL), 329 object_property_get_uint(pci_host, 330 PCI_HOST_PROP_PCI_HOLE_END, 331 NULL)); 332 range_set_bounds1(hole64, 333 object_property_get_uint(pci_host, 334 PCI_HOST_PROP_PCI_HOLE64_START, 335 NULL), 336 object_property_get_uint(pci_host, 337 PCI_HOST_PROP_PCI_HOLE64_END, 338 NULL)); 339 } 340 341 static void acpi_align_size(GArray *blob, unsigned align) 342 { 343 /* Align size to multiple of given size. This reduces the chance 344 * we need to change size in the future (breaking cross version migration). 345 */ 346 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 347 } 348 349 /* FACS */ 350 static void 351 build_facs(GArray *table_data) 352 { 353 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 354 memcpy(&facs->signature, "FACS", 4); 355 facs->length = cpu_to_le32(sizeof(*facs)); 356 } 357 358 static void build_append_pcihp_notify_entry(Aml *method, int slot) 359 { 360 Aml *if_ctx; 361 int32_t devfn = PCI_DEVFN(slot, 0); 362 363 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 364 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 365 aml_append(method, if_ctx); 366 } 367 368 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 369 bool pcihp_bridge_en) 370 { 371 Aml *dev, *notify_method = NULL, *method; 372 QObject *bsel; 373 PCIBus *sec; 374 int i; 375 376 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 377 if (bsel) { 378 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 379 380 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 381 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 382 } 383 384 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 385 DeviceClass *dc; 386 PCIDeviceClass *pc; 387 PCIDevice *pdev = bus->devices[i]; 388 int slot = PCI_SLOT(i); 389 bool hotplug_enabled_dev; 390 bool bridge_in_acpi; 391 bool cold_plugged_bridge; 392 393 if (!pdev) { 394 if (bsel) { /* add hotplug slots for non present devices */ 395 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 396 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 397 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 398 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 399 aml_append(method, 400 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 401 ); 402 aml_append(dev, method); 403 method = aml_method("_DSM", 4, AML_SERIALIZED); 404 aml_append(method, 405 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), 406 aml_arg(2), aml_arg(3), 407 aml_name("BSEL"), aml_name("_SUN"))) 408 ); 409 aml_append(dev, method); 410 aml_append(parent_scope, dev); 411 412 build_append_pcihp_notify_entry(notify_method, slot); 413 } 414 continue; 415 } 416 417 pc = PCI_DEVICE_GET_CLASS(pdev); 418 dc = DEVICE_GET_CLASS(pdev); 419 420 /* 421 * Cold plugged bridges aren't themselves hot-pluggable. 422 * Hotplugged bridges *are* hot-pluggable. 423 */ 424 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 425 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 426 427 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 428 429 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 430 continue; 431 } 432 433 /* start to compose PCI slot descriptor */ 434 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 435 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 436 437 if (bsel) { 438 /* 439 * Can't declare _SUN here for every device as it changes 'slot' 440 * enumeration order in linux kernel, so use another variable for it 441 */ 442 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 443 method = aml_method("_DSM", 4, AML_SERIALIZED); 444 aml_append(method, aml_return( 445 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), 446 aml_arg(3), aml_name("BSEL"), aml_name("ASUN")) 447 )); 448 aml_append(dev, method); 449 } 450 451 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 452 /* add VGA specific AML methods */ 453 int s3d; 454 455 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 456 s3d = 3; 457 } else { 458 s3d = 0; 459 } 460 461 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 462 aml_append(method, aml_return(aml_int(0))); 463 aml_append(dev, method); 464 465 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 466 aml_append(method, aml_return(aml_int(0))); 467 aml_append(dev, method); 468 469 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 470 aml_append(method, aml_return(aml_int(s3d))); 471 aml_append(dev, method); 472 } else if (hotplug_enabled_dev) { 473 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 474 /* add _EJ0 to make slot hotpluggable */ 475 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 476 aml_append(method, 477 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 478 ); 479 aml_append(dev, method); 480 481 if (bsel) { 482 build_append_pcihp_notify_entry(notify_method, slot); 483 } 484 } else if (bridge_in_acpi) { 485 /* 486 * device is coldplugged bridge, 487 * add child device descriptions into its scope 488 */ 489 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 490 491 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 492 } 493 /* slot descriptor has been composed, add it into parent context */ 494 aml_append(parent_scope, dev); 495 } 496 497 if (bsel) { 498 aml_append(parent_scope, notify_method); 499 } 500 501 /* Append PCNT method to notify about events on local and child buses. 502 * Add this method for root bus only when hotplug is enabled since DSDT 503 * expects it. 504 */ 505 if (bsel || pcihp_bridge_en) { 506 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 507 508 /* If bus supports hotplug select it and notify about local events */ 509 if (bsel) { 510 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 511 512 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 513 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 514 aml_int(1))); /* Device Check */ 515 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 516 aml_int(3))); /* Eject Request */ 517 } 518 519 /* Notify about child bus events in any case */ 520 if (pcihp_bridge_en) { 521 QLIST_FOREACH(sec, &bus->child, sibling) { 522 int32_t devfn = sec->parent_dev->devfn; 523 524 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 525 continue; 526 } 527 528 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 529 } 530 } 531 532 aml_append(parent_scope, method); 533 } 534 qobject_unref(bsel); 535 } 536 537 Aml *aml_pci_device_dsm(void) 538 { 539 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; 540 Aml *acpi_index = aml_local(0); 541 Aml *zero = aml_int(0); 542 Aml *bnum = aml_arg(4); 543 Aml *func = aml_arg(2); 544 Aml *rev = aml_arg(1); 545 Aml *sun = aml_arg(5); 546 547 method = aml_method("PDSM", 6, AML_SERIALIZED); 548 549 /* 550 * PCI Firmware Specification 3.1 551 * 4.6. _DSM Definitions for PCI 552 */ 553 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 554 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 555 { 556 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index)); 557 ifctx1 = aml_if(aml_equal(func, zero)); 558 { 559 uint8_t byte_list[1]; 560 561 ifctx2 = aml_if(aml_equal(rev, aml_int(2))); 562 { 563 /* 564 * advertise function 7 if device has acpi-index 565 * acpi_index values: 566 * 0: not present (default value) 567 * FFFFFFFF: not supported (old QEMU without PIDX reg) 568 * other: device's acpi-index 569 */ 570 ifctx3 = aml_if(aml_lnot( 571 aml_or(aml_equal(acpi_index, zero), 572 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 573 )); 574 { 575 byte_list[0] = 576 1 /* have supported functions */ | 577 1 << 7 /* support for function 7 */ 578 ; 579 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); 580 } 581 aml_append(ifctx2, ifctx3); 582 } 583 aml_append(ifctx1, ifctx2); 584 585 byte_list[0] = 0; /* nothing supported */ 586 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); 587 } 588 aml_append(ifctx, ifctx1); 589 elsectx = aml_else(); 590 /* 591 * PCI Firmware Specification 3.1 592 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 593 * Operating Systems 594 */ 595 ifctx1 = aml_if(aml_equal(func, aml_int(7))); 596 { 597 Aml *pkg = aml_package(2); 598 Aml *ret = aml_local(1); 599 600 aml_append(pkg, zero); 601 /* 602 * optional, if not impl. should return null string 603 */ 604 aml_append(pkg, aml_string("%s", "")); 605 aml_append(ifctx1, aml_store(pkg, ret)); 606 /* 607 * update acpi-index to actual value 608 */ 609 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 610 aml_append(ifctx1, aml_return(ret)); 611 } 612 aml_append(elsectx, ifctx1); 613 aml_append(ifctx, elsectx); 614 } 615 aml_append(method, ifctx); 616 return method; 617 } 618 619 /** 620 * build_prt_entry: 621 * @link_name: link name for PCI route entry 622 * 623 * build AML package containing a PCI route entry for @link_name 624 */ 625 static Aml *build_prt_entry(const char *link_name) 626 { 627 Aml *a_zero = aml_int(0); 628 Aml *pkg = aml_package(4); 629 aml_append(pkg, a_zero); 630 aml_append(pkg, a_zero); 631 aml_append(pkg, aml_name("%s", link_name)); 632 aml_append(pkg, a_zero); 633 return pkg; 634 } 635 636 /* 637 * initialize_route - Initialize the interrupt routing rule 638 * through a specific LINK: 639 * if (lnk_idx == idx) 640 * route using link 'link_name' 641 */ 642 static Aml *initialize_route(Aml *route, const char *link_name, 643 Aml *lnk_idx, int idx) 644 { 645 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 646 Aml *pkg = build_prt_entry(link_name); 647 648 aml_append(if_ctx, aml_store(pkg, route)); 649 650 return if_ctx; 651 } 652 653 /* 654 * build_prt - Define interrupt rounting rules 655 * 656 * Returns an array of 128 routes, one for each device, 657 * based on device location. 658 * The main goal is to equaly distribute the interrupts 659 * over the 4 existing ACPI links (works only for i440fx). 660 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 661 * 662 */ 663 static Aml *build_prt(bool is_pci0_prt) 664 { 665 Aml *method, *while_ctx, *pin, *res; 666 667 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 668 res = aml_local(0); 669 pin = aml_local(1); 670 aml_append(method, aml_store(aml_package(128), res)); 671 aml_append(method, aml_store(aml_int(0), pin)); 672 673 /* while (pin < 128) */ 674 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 675 { 676 Aml *slot = aml_local(2); 677 Aml *lnk_idx = aml_local(3); 678 Aml *route = aml_local(4); 679 680 /* slot = pin >> 2 */ 681 aml_append(while_ctx, 682 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 683 /* lnk_idx = (slot + pin) & 3 */ 684 aml_append(while_ctx, 685 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 686 lnk_idx)); 687 688 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 689 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 690 if (is_pci0_prt) { 691 Aml *if_device_1, *if_pin_4, *else_pin_4; 692 693 /* device 1 is the power-management device, needs SCI */ 694 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 695 { 696 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 697 { 698 aml_append(if_pin_4, 699 aml_store(build_prt_entry("LNKS"), route)); 700 } 701 aml_append(if_device_1, if_pin_4); 702 else_pin_4 = aml_else(); 703 { 704 aml_append(else_pin_4, 705 aml_store(build_prt_entry("LNKA"), route)); 706 } 707 aml_append(if_device_1, else_pin_4); 708 } 709 aml_append(while_ctx, if_device_1); 710 } else { 711 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 712 } 713 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 714 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 715 716 /* route[0] = 0x[slot]FFFF */ 717 aml_append(while_ctx, 718 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 719 NULL), 720 aml_index(route, aml_int(0)))); 721 /* route[1] = pin & 3 */ 722 aml_append(while_ctx, 723 aml_store(aml_and(pin, aml_int(3), NULL), 724 aml_index(route, aml_int(1)))); 725 /* res[pin] = route */ 726 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 727 /* pin++ */ 728 aml_append(while_ctx, aml_increment(pin)); 729 } 730 aml_append(method, while_ctx); 731 /* return res*/ 732 aml_append(method, aml_return(res)); 733 734 return method; 735 } 736 737 static void build_hpet_aml(Aml *table) 738 { 739 Aml *crs; 740 Aml *field; 741 Aml *method; 742 Aml *if_ctx; 743 Aml *scope = aml_scope("_SB"); 744 Aml *dev = aml_device("HPET"); 745 Aml *zero = aml_int(0); 746 Aml *id = aml_local(0); 747 Aml *period = aml_local(1); 748 749 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 750 aml_append(dev, aml_name_decl("_UID", zero)); 751 752 aml_append(dev, 753 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 754 HPET_LEN)); 755 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 756 aml_append(field, aml_named_field("VEND", 32)); 757 aml_append(field, aml_named_field("PRD", 32)); 758 aml_append(dev, field); 759 760 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 761 aml_append(method, aml_store(aml_name("VEND"), id)); 762 aml_append(method, aml_store(aml_name("PRD"), period)); 763 aml_append(method, aml_shiftright(id, aml_int(16), id)); 764 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 765 aml_equal(id, aml_int(0xffff)))); 766 { 767 aml_append(if_ctx, aml_return(zero)); 768 } 769 aml_append(method, if_ctx); 770 771 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 772 aml_lgreater(period, aml_int(100000000)))); 773 { 774 aml_append(if_ctx, aml_return(zero)); 775 } 776 aml_append(method, if_ctx); 777 778 aml_append(method, aml_return(aml_int(0x0F))); 779 aml_append(dev, method); 780 781 crs = aml_resource_template(); 782 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 783 aml_append(dev, aml_name_decl("_CRS", crs)); 784 785 aml_append(scope, dev); 786 aml_append(table, scope); 787 } 788 789 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 790 { 791 Aml *dev; 792 Aml *method; 793 Aml *crs; 794 795 dev = aml_device("VMBS"); 796 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 797 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 798 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 799 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 800 801 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 802 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 803 aml_name("STA"))); 804 aml_append(dev, method); 805 806 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 807 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 808 aml_name("STA"))); 809 aml_append(dev, method); 810 811 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 812 aml_append(method, aml_return(aml_name("STA"))); 813 aml_append(dev, method); 814 815 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 816 817 crs = aml_resource_template(); 818 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 819 aml_append(dev, aml_name_decl("_CRS", crs)); 820 821 return dev; 822 } 823 824 static void build_isa_devices_aml(Aml *table) 825 { 826 bool ambiguous; 827 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 828 Aml *scope; 829 830 assert(obj && !ambiguous); 831 832 scope = aml_scope("_SB.PCI0.ISA"); 833 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 834 isa_build_aml(ISA_BUS(obj), scope); 835 836 aml_append(table, scope); 837 } 838 839 static void build_dbg_aml(Aml *table) 840 { 841 Aml *field; 842 Aml *method; 843 Aml *while_ctx; 844 Aml *scope = aml_scope("\\"); 845 Aml *buf = aml_local(0); 846 Aml *len = aml_local(1); 847 Aml *idx = aml_local(2); 848 849 aml_append(scope, 850 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 851 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 852 aml_append(field, aml_named_field("DBGB", 8)); 853 aml_append(scope, field); 854 855 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 856 857 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 858 aml_append(method, aml_to_buffer(buf, buf)); 859 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 860 aml_append(method, aml_store(aml_int(0), idx)); 861 862 while_ctx = aml_while(aml_lless(idx, len)); 863 aml_append(while_ctx, 864 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 865 aml_append(while_ctx, aml_increment(idx)); 866 aml_append(method, while_ctx); 867 868 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 869 aml_append(scope, method); 870 871 aml_append(table, scope); 872 } 873 874 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 875 { 876 Aml *dev; 877 Aml *crs; 878 Aml *method; 879 uint32_t irqs[] = {5, 10, 11}; 880 881 dev = aml_device("%s", name); 882 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 883 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 884 885 crs = aml_resource_template(); 886 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 887 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 888 aml_append(dev, aml_name_decl("_PRS", crs)); 889 890 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 891 aml_append(method, aml_return(aml_call1("IQST", reg))); 892 aml_append(dev, method); 893 894 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 895 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 896 aml_append(dev, method); 897 898 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 899 aml_append(method, aml_return(aml_call1("IQCR", reg))); 900 aml_append(dev, method); 901 902 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 903 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 904 aml_append(method, aml_store(aml_name("PRRI"), reg)); 905 aml_append(dev, method); 906 907 return dev; 908 } 909 910 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 911 { 912 Aml *dev; 913 Aml *crs; 914 Aml *method; 915 uint32_t irqs; 916 917 dev = aml_device("%s", name); 918 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 919 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 920 921 crs = aml_resource_template(); 922 irqs = gsi; 923 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 924 AML_SHARED, &irqs, 1)); 925 aml_append(dev, aml_name_decl("_PRS", crs)); 926 927 aml_append(dev, aml_name_decl("_CRS", crs)); 928 929 /* 930 * _DIS can be no-op because the interrupt cannot be disabled. 931 */ 932 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 933 aml_append(dev, method); 934 935 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 936 aml_append(dev, method); 937 938 return dev; 939 } 940 941 /* _CRS method - get current settings */ 942 static Aml *build_iqcr_method(bool is_piix4) 943 { 944 Aml *if_ctx; 945 uint32_t irqs; 946 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 947 Aml *crs = aml_resource_template(); 948 949 irqs = 0; 950 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 951 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 952 aml_append(method, aml_name_decl("PRR0", crs)); 953 954 aml_append(method, 955 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 956 957 if (is_piix4) { 958 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 959 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 960 aml_append(method, if_ctx); 961 } else { 962 aml_append(method, 963 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 964 aml_name("PRRI"))); 965 } 966 967 aml_append(method, aml_return(aml_name("PRR0"))); 968 return method; 969 } 970 971 /* _STA method - get status */ 972 static Aml *build_irq_status_method(void) 973 { 974 Aml *if_ctx; 975 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 976 977 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 978 aml_append(if_ctx, aml_return(aml_int(0x09))); 979 aml_append(method, if_ctx); 980 aml_append(method, aml_return(aml_int(0x0B))); 981 return method; 982 } 983 984 static void build_piix4_pci0_int(Aml *table) 985 { 986 Aml *dev; 987 Aml *crs; 988 Aml *field; 989 Aml *method; 990 uint32_t irqs; 991 Aml *sb_scope = aml_scope("_SB"); 992 Aml *pci0_scope = aml_scope("PCI0"); 993 994 aml_append(pci0_scope, build_prt(true)); 995 aml_append(sb_scope, pci0_scope); 996 997 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 998 aml_append(field, aml_named_field("PRQ0", 8)); 999 aml_append(field, aml_named_field("PRQ1", 8)); 1000 aml_append(field, aml_named_field("PRQ2", 8)); 1001 aml_append(field, aml_named_field("PRQ3", 8)); 1002 aml_append(sb_scope, field); 1003 1004 aml_append(sb_scope, build_irq_status_method()); 1005 aml_append(sb_scope, build_iqcr_method(true)); 1006 1007 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1008 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1009 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1010 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1011 1012 dev = aml_device("LNKS"); 1013 { 1014 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1015 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1016 1017 crs = aml_resource_template(); 1018 irqs = 9; 1019 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1020 AML_ACTIVE_HIGH, AML_SHARED, 1021 &irqs, 1)); 1022 aml_append(dev, aml_name_decl("_PRS", crs)); 1023 1024 /* The SCI cannot be disabled and is always attached to GSI 9, 1025 * so these are no-ops. We only need this link to override the 1026 * polarity to active high and match the content of the MADT. 1027 */ 1028 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1029 aml_append(method, aml_return(aml_int(0x0b))); 1030 aml_append(dev, method); 1031 1032 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1033 aml_append(dev, method); 1034 1035 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1036 aml_append(method, aml_return(aml_name("_PRS"))); 1037 aml_append(dev, method); 1038 1039 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1040 aml_append(dev, method); 1041 } 1042 aml_append(sb_scope, dev); 1043 1044 aml_append(table, sb_scope); 1045 } 1046 1047 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1048 { 1049 int i; 1050 int head; 1051 Aml *pkg; 1052 char base = name[3] < 'E' ? 'A' : 'E'; 1053 char *s = g_strdup(name); 1054 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1055 1056 assert(strlen(s) == 4); 1057 1058 head = name[3] - base; 1059 for (i = 0; i < 4; i++) { 1060 if (head + i > 3) { 1061 head = i * -1; 1062 } 1063 s[3] = base + head + i; 1064 pkg = aml_package(4); 1065 aml_append(pkg, a_nr); 1066 aml_append(pkg, aml_int(i)); 1067 aml_append(pkg, aml_name("%s", s)); 1068 aml_append(pkg, aml_int(0)); 1069 aml_append(ctx, pkg); 1070 } 1071 g_free(s); 1072 } 1073 1074 static Aml *build_q35_routing_table(const char *str) 1075 { 1076 int i; 1077 Aml *pkg; 1078 char *name = g_strdup_printf("%s ", str); 1079 1080 pkg = aml_package(128); 1081 for (i = 0; i < 0x18; i++) { 1082 name[3] = 'E' + (i & 0x3); 1083 append_q35_prt_entry(pkg, i, name); 1084 } 1085 1086 name[3] = 'E'; 1087 append_q35_prt_entry(pkg, 0x18, name); 1088 1089 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1090 for (i = 0x0019; i < 0x1e; i++) { 1091 name[3] = 'A'; 1092 append_q35_prt_entry(pkg, i, name); 1093 } 1094 1095 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1096 name[3] = 'E'; 1097 append_q35_prt_entry(pkg, 0x1e, name); 1098 name[3] = 'A'; 1099 append_q35_prt_entry(pkg, 0x1f, name); 1100 1101 g_free(name); 1102 return pkg; 1103 } 1104 1105 static void build_q35_pci0_int(Aml *table) 1106 { 1107 Aml *field; 1108 Aml *method; 1109 Aml *sb_scope = aml_scope("_SB"); 1110 Aml *pci0_scope = aml_scope("PCI0"); 1111 1112 /* Zero => PIC mode, One => APIC Mode */ 1113 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1114 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1115 { 1116 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1117 } 1118 aml_append(table, method); 1119 1120 aml_append(pci0_scope, 1121 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1122 aml_append(pci0_scope, 1123 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1124 1125 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1126 { 1127 Aml *if_ctx; 1128 Aml *else_ctx; 1129 1130 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1131 section 6.2.8.1 */ 1132 /* Note: we provide the same info as the PCI routing 1133 table of the Bochs BIOS */ 1134 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1135 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1136 aml_append(method, if_ctx); 1137 else_ctx = aml_else(); 1138 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1139 aml_append(method, else_ctx); 1140 } 1141 aml_append(pci0_scope, method); 1142 aml_append(sb_scope, pci0_scope); 1143 1144 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1145 aml_append(field, aml_named_field("PRQA", 8)); 1146 aml_append(field, aml_named_field("PRQB", 8)); 1147 aml_append(field, aml_named_field("PRQC", 8)); 1148 aml_append(field, aml_named_field("PRQD", 8)); 1149 aml_append(field, aml_reserved_field(0x20)); 1150 aml_append(field, aml_named_field("PRQE", 8)); 1151 aml_append(field, aml_named_field("PRQF", 8)); 1152 aml_append(field, aml_named_field("PRQG", 8)); 1153 aml_append(field, aml_named_field("PRQH", 8)); 1154 aml_append(sb_scope, field); 1155 1156 aml_append(sb_scope, build_irq_status_method()); 1157 aml_append(sb_scope, build_iqcr_method(false)); 1158 1159 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1160 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1161 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1162 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1163 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1164 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1165 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1166 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1167 1168 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1169 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1170 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1171 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1172 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1173 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1174 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1175 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1176 1177 aml_append(table, sb_scope); 1178 } 1179 1180 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1181 { 1182 Aml *dev; 1183 Aml *resource_template; 1184 1185 /* DRAM controller */ 1186 dev = aml_device("DRAC"); 1187 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1188 1189 resource_template = aml_resource_template(); 1190 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1191 aml_append(resource_template, 1192 aml_qword_memory(AML_POS_DECODE, 1193 AML_MIN_FIXED, 1194 AML_MAX_FIXED, 1195 AML_NON_CACHEABLE, 1196 AML_READ_WRITE, 1197 0x0000000000000000, 1198 mcfg->base, 1199 mcfg->base + mcfg->size - 1, 1200 0x0000000000000000, 1201 mcfg->size)); 1202 } else { 1203 aml_append(resource_template, 1204 aml_dword_memory(AML_POS_DECODE, 1205 AML_MIN_FIXED, 1206 AML_MAX_FIXED, 1207 AML_NON_CACHEABLE, 1208 AML_READ_WRITE, 1209 0x0000000000000000, 1210 mcfg->base, 1211 mcfg->base + mcfg->size - 1, 1212 0x0000000000000000, 1213 mcfg->size)); 1214 } 1215 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1216 1217 return dev; 1218 } 1219 1220 static void build_q35_isa_bridge(Aml *table) 1221 { 1222 Aml *dev; 1223 Aml *scope; 1224 1225 scope = aml_scope("_SB.PCI0"); 1226 dev = aml_device("ISA"); 1227 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1228 1229 /* ICH9 PCI to ISA irq remapping */ 1230 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1231 aml_int(0x60), 0x0C)); 1232 1233 aml_append(scope, dev); 1234 aml_append(table, scope); 1235 } 1236 1237 static void build_piix4_isa_bridge(Aml *table) 1238 { 1239 Aml *dev; 1240 Aml *scope; 1241 1242 scope = aml_scope("_SB.PCI0"); 1243 dev = aml_device("ISA"); 1244 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1245 1246 /* PIIX PCI to ISA irq remapping */ 1247 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1248 aml_int(0x60), 0x04)); 1249 1250 aml_append(scope, dev); 1251 aml_append(table, scope); 1252 } 1253 1254 static void build_piix4_pci_hotplug(Aml *table) 1255 { 1256 Aml *scope; 1257 Aml *field; 1258 Aml *method; 1259 1260 scope = aml_scope("_SB.PCI0"); 1261 1262 aml_append(scope, 1263 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1264 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1265 aml_append(field, aml_named_field("PCIU", 32)); 1266 aml_append(field, aml_named_field("PCID", 32)); 1267 aml_append(scope, field); 1268 1269 aml_append(scope, 1270 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1271 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1272 aml_append(field, aml_named_field("B0EJ", 32)); 1273 aml_append(scope, field); 1274 1275 aml_append(scope, 1276 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08)); 1277 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1278 aml_append(field, aml_named_field("BNUM", 32)); 1279 aml_append(field, aml_named_field("PIDX", 32)); 1280 aml_append(scope, field); 1281 1282 aml_append(scope, aml_mutex("BLCK", 0)); 1283 1284 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1285 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1286 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1287 aml_append(method, 1288 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1289 aml_append(method, aml_release(aml_name("BLCK"))); 1290 aml_append(method, aml_return(aml_int(0))); 1291 aml_append(scope, method); 1292 1293 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1294 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1295 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1296 aml_append(method, 1297 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1298 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1299 aml_append(method, aml_release(aml_name("BLCK"))); 1300 aml_append(method, aml_return(aml_local(0))); 1301 aml_append(scope, method); 1302 1303 aml_append(scope, aml_pci_device_dsm()); 1304 1305 aml_append(table, scope); 1306 } 1307 1308 static Aml *build_q35_osc_method(void) 1309 { 1310 Aml *if_ctx; 1311 Aml *if_ctx2; 1312 Aml *else_ctx; 1313 Aml *method; 1314 Aml *a_cwd1 = aml_name("CDW1"); 1315 Aml *a_ctrl = aml_local(0); 1316 1317 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1318 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1319 1320 if_ctx = aml_if(aml_equal( 1321 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1322 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1323 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1324 1325 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1326 1327 /* 1328 * Always allow native PME, AER (no dependencies) 1329 * Allow SHPC (PCI bridges can have SHPC controller) 1330 */ 1331 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1332 1333 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1334 /* Unknown revision */ 1335 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1336 aml_append(if_ctx, if_ctx2); 1337 1338 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1339 /* Capabilities bits were masked */ 1340 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1341 aml_append(if_ctx, if_ctx2); 1342 1343 /* Update DWORD3 in the buffer */ 1344 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1345 aml_append(method, if_ctx); 1346 1347 else_ctx = aml_else(); 1348 /* Unrecognized UUID */ 1349 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1350 aml_append(method, else_ctx); 1351 1352 aml_append(method, aml_return(aml_arg(3))); 1353 return method; 1354 } 1355 1356 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1357 { 1358 Aml *scope = aml_scope("_SB.PCI0"); 1359 Aml *dev = aml_device("SMB0"); 1360 1361 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1362 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1363 aml_append(scope, dev); 1364 aml_append(table, scope); 1365 } 1366 1367 static void 1368 build_dsdt(GArray *table_data, BIOSLinker *linker, 1369 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1370 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1371 { 1372 CrsRangeEntry *entry; 1373 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1374 CrsRangeSet crs_range_set; 1375 PCMachineState *pcms = PC_MACHINE(machine); 1376 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1377 X86MachineState *x86ms = X86_MACHINE(machine); 1378 AcpiMcfgInfo mcfg; 1379 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1380 uint32_t nr_mem = machine->ram_slots; 1381 int root_bus_limit = 0xFF; 1382 PCIBus *bus = NULL; 1383 #ifdef CONFIG_TPM 1384 TPMIf *tpm = tpm_find(); 1385 #endif 1386 int i; 1387 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1388 1389 dsdt = init_aml_allocator(); 1390 1391 /* Reserve space for header */ 1392 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1393 1394 build_dbg_aml(dsdt); 1395 if (misc->is_piix4) { 1396 sb_scope = aml_scope("_SB"); 1397 dev = aml_device("PCI0"); 1398 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1399 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1400 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1401 aml_append(sb_scope, dev); 1402 aml_append(dsdt, sb_scope); 1403 1404 if (misc->has_hpet) { 1405 build_hpet_aml(dsdt); 1406 } 1407 build_piix4_isa_bridge(dsdt); 1408 build_isa_devices_aml(dsdt); 1409 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1410 build_piix4_pci_hotplug(dsdt); 1411 } 1412 build_piix4_pci0_int(dsdt); 1413 } else { 1414 sb_scope = aml_scope("_SB"); 1415 dev = aml_device("PCI0"); 1416 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1417 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1418 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1419 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1420 aml_append(dev, build_q35_osc_method()); 1421 aml_append(sb_scope, dev); 1422 if (mcfg_valid) { 1423 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1424 } 1425 1426 if (pm->smi_on_cpuhp) { 1427 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1428 dev = aml_device("PCI0.SMI0"); 1429 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1430 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1431 crs = aml_resource_template(); 1432 aml_append(crs, 1433 aml_io( 1434 AML_DECODE16, 1435 ACPI_PORT_SMI_CMD, 1436 ACPI_PORT_SMI_CMD, 1437 1, 1438 2) 1439 ); 1440 aml_append(dev, aml_name_decl("_CRS", crs)); 1441 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1442 aml_int(ACPI_PORT_SMI_CMD), 2)); 1443 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1444 AML_WRITE_AS_ZEROS); 1445 aml_append(field, aml_named_field("SMIC", 8)); 1446 aml_append(field, aml_reserved_field(8)); 1447 aml_append(dev, field); 1448 aml_append(sb_scope, dev); 1449 } 1450 1451 aml_append(dsdt, sb_scope); 1452 1453 if (misc->has_hpet) { 1454 build_hpet_aml(dsdt); 1455 } 1456 build_q35_isa_bridge(dsdt); 1457 build_isa_devices_aml(dsdt); 1458 build_q35_pci0_int(dsdt); 1459 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1460 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1461 } 1462 } 1463 1464 if (vmbus_bridge) { 1465 sb_scope = aml_scope("_SB"); 1466 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1467 aml_append(dsdt, sb_scope); 1468 } 1469 1470 if (pcmc->legacy_cpu_hotplug) { 1471 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1472 } else { 1473 CPUHotplugFeatures opts = { 1474 .acpi_1_compatible = true, .has_legacy_cphp = true, 1475 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1476 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1477 }; 1478 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1479 "\\_SB.PCI0", "\\_GPE._E02"); 1480 } 1481 1482 if (pcms->memhp_io_base && nr_mem) { 1483 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1484 "\\_GPE._E03", AML_SYSTEM_IO, 1485 pcms->memhp_io_base); 1486 } 1487 1488 scope = aml_scope("_GPE"); 1489 { 1490 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1491 1492 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1493 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1494 aml_append(method, 1495 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1496 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1497 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1498 aml_append(scope, method); 1499 } 1500 1501 if (machine->nvdimms_state->is_enabled) { 1502 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1503 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1504 aml_int(0x80))); 1505 aml_append(scope, method); 1506 } 1507 } 1508 aml_append(dsdt, scope); 1509 1510 crs_range_set_init(&crs_range_set); 1511 bus = PC_MACHINE(machine)->bus; 1512 if (bus) { 1513 QLIST_FOREACH(bus, &bus->child, sibling) { 1514 uint8_t bus_num = pci_bus_num(bus); 1515 uint8_t numa_node = pci_bus_numa_node(bus); 1516 1517 /* look only for expander root buses */ 1518 if (!pci_bus_is_root(bus)) { 1519 continue; 1520 } 1521 1522 if (bus_num < root_bus_limit) { 1523 root_bus_limit = bus_num - 1; 1524 } 1525 1526 scope = aml_scope("\\_SB"); 1527 dev = aml_device("PC%.02X", bus_num); 1528 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1529 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1530 if (pci_bus_is_express(bus)) { 1531 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1532 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1533 aml_append(dev, build_q35_osc_method()); 1534 } else { 1535 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1536 } 1537 1538 if (numa_node != NUMA_NODE_UNASSIGNED) { 1539 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1540 } 1541 1542 aml_append(dev, build_prt(false)); 1543 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1544 0, 0, 0, 0); 1545 aml_append(dev, aml_name_decl("_CRS", crs)); 1546 aml_append(scope, dev); 1547 aml_append(dsdt, scope); 1548 } 1549 } 1550 1551 /* 1552 * At this point crs_range_set has all the ranges used by pci 1553 * busses *other* than PCI0. These ranges will be excluded from 1554 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1555 * too. 1556 */ 1557 if (mcfg_valid) { 1558 crs_range_insert(crs_range_set.mem_ranges, 1559 mcfg.base, mcfg.base + mcfg.size - 1); 1560 } 1561 1562 scope = aml_scope("\\_SB.PCI0"); 1563 /* build PCI0._CRS */ 1564 crs = aml_resource_template(); 1565 aml_append(crs, 1566 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1567 0x0000, 0x0, root_bus_limit, 1568 0x0000, root_bus_limit + 1)); 1569 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1570 1571 aml_append(crs, 1572 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1573 AML_POS_DECODE, AML_ENTIRE_RANGE, 1574 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1575 1576 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1577 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1578 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1579 aml_append(crs, 1580 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1581 AML_POS_DECODE, AML_ENTIRE_RANGE, 1582 0x0000, entry->base, entry->limit, 1583 0x0000, entry->limit - entry->base + 1)); 1584 } 1585 1586 aml_append(crs, 1587 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1588 AML_CACHEABLE, AML_READ_WRITE, 1589 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1590 1591 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1592 range_lob(pci_hole), 1593 range_upb(pci_hole)); 1594 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1595 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1596 aml_append(crs, 1597 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1598 AML_NON_CACHEABLE, AML_READ_WRITE, 1599 0, entry->base, entry->limit, 1600 0, entry->limit - entry->base + 1)); 1601 } 1602 1603 if (!range_is_empty(pci_hole64)) { 1604 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1605 range_lob(pci_hole64), 1606 range_upb(pci_hole64)); 1607 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1608 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1609 aml_append(crs, 1610 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1611 AML_MAX_FIXED, 1612 AML_CACHEABLE, AML_READ_WRITE, 1613 0, entry->base, entry->limit, 1614 0, entry->limit - entry->base + 1)); 1615 } 1616 } 1617 1618 #ifdef CONFIG_TPM 1619 if (TPM_IS_TIS_ISA(tpm_find())) { 1620 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1621 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1622 } 1623 #endif 1624 aml_append(scope, aml_name_decl("_CRS", crs)); 1625 1626 /* reserve GPE0 block resources */ 1627 dev = aml_device("GPE0"); 1628 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1629 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1630 /* device present, functioning, decoding, not shown in UI */ 1631 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1632 crs = aml_resource_template(); 1633 aml_append(crs, 1634 aml_io( 1635 AML_DECODE16, 1636 pm->fadt.gpe0_blk.address, 1637 pm->fadt.gpe0_blk.address, 1638 1, 1639 pm->fadt.gpe0_blk.bit_width / 8) 1640 ); 1641 aml_append(dev, aml_name_decl("_CRS", crs)); 1642 aml_append(scope, dev); 1643 1644 crs_range_set_free(&crs_range_set); 1645 1646 /* reserve PCIHP resources */ 1647 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1648 dev = aml_device("PHPR"); 1649 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1650 aml_append(dev, 1651 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1652 /* device present, functioning, decoding, not shown in UI */ 1653 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1654 crs = aml_resource_template(); 1655 aml_append(crs, 1656 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1657 pm->pcihp_io_len) 1658 ); 1659 aml_append(dev, aml_name_decl("_CRS", crs)); 1660 aml_append(scope, dev); 1661 } 1662 aml_append(dsdt, scope); 1663 1664 /* create S3_ / S4_ / S5_ packages if necessary */ 1665 scope = aml_scope("\\"); 1666 if (!pm->s3_disabled) { 1667 pkg = aml_package(4); 1668 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1669 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1670 aml_append(pkg, aml_int(0)); /* reserved */ 1671 aml_append(pkg, aml_int(0)); /* reserved */ 1672 aml_append(scope, aml_name_decl("_S3", pkg)); 1673 } 1674 1675 if (!pm->s4_disabled) { 1676 pkg = aml_package(4); 1677 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1678 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1679 aml_append(pkg, aml_int(pm->s4_val)); 1680 aml_append(pkg, aml_int(0)); /* reserved */ 1681 aml_append(pkg, aml_int(0)); /* reserved */ 1682 aml_append(scope, aml_name_decl("_S4", pkg)); 1683 } 1684 1685 pkg = aml_package(4); 1686 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1687 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1688 aml_append(pkg, aml_int(0)); /* reserved */ 1689 aml_append(pkg, aml_int(0)); /* reserved */ 1690 aml_append(scope, aml_name_decl("_S5", pkg)); 1691 aml_append(dsdt, scope); 1692 1693 /* create fw_cfg node, unconditionally */ 1694 { 1695 scope = aml_scope("\\_SB.PCI0"); 1696 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1697 aml_append(dsdt, scope); 1698 } 1699 1700 if (misc->applesmc_io_base) { 1701 scope = aml_scope("\\_SB.PCI0.ISA"); 1702 dev = aml_device("SMC"); 1703 1704 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1705 /* device present, functioning, decoding, not shown in UI */ 1706 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1707 1708 crs = aml_resource_template(); 1709 aml_append(crs, 1710 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1711 0x01, APPLESMC_MAX_DATA_LENGTH) 1712 ); 1713 aml_append(crs, aml_irq_no_flags(6)); 1714 aml_append(dev, aml_name_decl("_CRS", crs)); 1715 1716 aml_append(scope, dev); 1717 aml_append(dsdt, scope); 1718 } 1719 1720 if (misc->pvpanic_port) { 1721 scope = aml_scope("\\_SB.PCI0.ISA"); 1722 1723 dev = aml_device("PEVT"); 1724 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1725 1726 crs = aml_resource_template(); 1727 aml_append(crs, 1728 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1729 ); 1730 aml_append(dev, aml_name_decl("_CRS", crs)); 1731 1732 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1733 aml_int(misc->pvpanic_port), 1)); 1734 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1735 aml_append(field, aml_named_field("PEPT", 8)); 1736 aml_append(dev, field); 1737 1738 /* device present, functioning, decoding, shown in UI */ 1739 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1740 1741 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1742 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1743 aml_append(method, aml_return(aml_local(0))); 1744 aml_append(dev, method); 1745 1746 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1747 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1748 aml_append(dev, method); 1749 1750 aml_append(scope, dev); 1751 aml_append(dsdt, scope); 1752 } 1753 1754 sb_scope = aml_scope("\\_SB"); 1755 { 1756 Object *pci_host; 1757 PCIBus *bus = NULL; 1758 1759 pci_host = acpi_get_i386_pci_host(); 1760 if (pci_host) { 1761 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1762 } 1763 1764 if (bus) { 1765 Aml *scope = aml_scope("PCI0"); 1766 /* Scan all PCI buses. Generate tables to support hotplug. */ 1767 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1768 1769 #ifdef CONFIG_TPM 1770 if (TPM_IS_TIS_ISA(tpm)) { 1771 if (misc->tpm_version == TPM_VERSION_2_0) { 1772 dev = aml_device("TPM"); 1773 aml_append(dev, aml_name_decl("_HID", 1774 aml_string("MSFT0101"))); 1775 } else { 1776 dev = aml_device("ISA.TPM"); 1777 aml_append(dev, aml_name_decl("_HID", 1778 aml_eisaid("PNP0C31"))); 1779 } 1780 1781 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1782 crs = aml_resource_template(); 1783 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1784 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1785 /* 1786 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1787 Rewrite to take IRQ from TPM device model and 1788 fix default IRQ value there to use some unused IRQ 1789 */ 1790 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1791 aml_append(dev, aml_name_decl("_CRS", crs)); 1792 1793 tpm_build_ppi_acpi(tpm, dev); 1794 1795 aml_append(scope, dev); 1796 } 1797 #endif 1798 1799 aml_append(sb_scope, scope); 1800 } 1801 } 1802 1803 #ifdef CONFIG_TPM 1804 if (TPM_IS_CRB(tpm)) { 1805 dev = aml_device("TPM"); 1806 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1807 crs = aml_resource_template(); 1808 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1809 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1810 aml_append(dev, aml_name_decl("_CRS", crs)); 1811 1812 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1813 1814 tpm_build_ppi_acpi(tpm, dev); 1815 1816 aml_append(sb_scope, dev); 1817 } 1818 #endif 1819 1820 aml_append(dsdt, sb_scope); 1821 1822 /* copy AML table into ACPI tables blob and patch header there */ 1823 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1824 build_header(linker, table_data, 1825 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1826 "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id); 1827 free_aml_allocator(); 1828 } 1829 1830 static void 1831 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1832 const char *oem_table_id) 1833 { 1834 Acpi20Hpet *hpet; 1835 int hpet_start = table_data->len; 1836 1837 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1838 /* Note timer_block_id value must be kept in sync with value advertised by 1839 * emulated hpet 1840 */ 1841 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1842 hpet->addr.address = cpu_to_le64(HPET_BASE); 1843 build_header(linker, table_data, 1844 (void *)(table_data->data + hpet_start), 1845 "HPET", sizeof(*hpet), 1, oem_id, oem_table_id); 1846 } 1847 1848 #ifdef CONFIG_TPM 1849 static void 1850 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1851 const char *oem_id, const char *oem_table_id) 1852 { 1853 int tcpa_start = table_data->len; 1854 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1855 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1856 unsigned log_addr_offset = 1857 (char *)&tcpa->log_area_start_address - table_data->data; 1858 1859 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1860 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1861 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1862 1863 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1864 false /* high memory */); 1865 1866 /* log area start address to be filled by Guest linker */ 1867 bios_linker_loader_add_pointer(linker, 1868 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1869 ACPI_BUILD_TPMLOG_FILE, 0); 1870 1871 build_header(linker, table_data, 1872 (void *)(table_data->data + tcpa_start), 1873 "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id); 1874 } 1875 #endif 1876 1877 #define HOLE_640K_START (640 * KiB) 1878 #define HOLE_640K_END (1 * MiB) 1879 1880 static void 1881 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1882 { 1883 AcpiSystemResourceAffinityTable *srat; 1884 AcpiSratMemoryAffinity *numamem; 1885 1886 int i; 1887 int srat_start, numa_start, slots; 1888 uint64_t mem_len, mem_base, next_base; 1889 MachineClass *mc = MACHINE_GET_CLASS(machine); 1890 X86MachineState *x86ms = X86_MACHINE(machine); 1891 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1892 PCMachineState *pcms = PC_MACHINE(machine); 1893 ram_addr_t hotplugabble_address_space_size = 1894 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1895 NULL); 1896 1897 srat_start = table_data->len; 1898 1899 srat = acpi_data_push(table_data, sizeof *srat); 1900 srat->reserved1 = cpu_to_le32(1); 1901 1902 for (i = 0; i < apic_ids->len; i++) { 1903 int node_id = apic_ids->cpus[i].props.node_id; 1904 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1905 1906 if (apic_id < 255) { 1907 AcpiSratProcessorAffinity *core; 1908 1909 core = acpi_data_push(table_data, sizeof *core); 1910 core->type = ACPI_SRAT_PROCESSOR_APIC; 1911 core->length = sizeof(*core); 1912 core->local_apic_id = apic_id; 1913 core->proximity_lo = node_id; 1914 memset(core->proximity_hi, 0, 3); 1915 core->local_sapic_eid = 0; 1916 core->flags = cpu_to_le32(1); 1917 } else { 1918 AcpiSratProcessorX2ApicAffinity *core; 1919 1920 core = acpi_data_push(table_data, sizeof *core); 1921 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 1922 core->length = sizeof(*core); 1923 core->x2apic_id = cpu_to_le32(apic_id); 1924 core->proximity_domain = cpu_to_le32(node_id); 1925 core->flags = cpu_to_le32(1); 1926 } 1927 } 1928 1929 1930 /* the memory map is a bit tricky, it contains at least one hole 1931 * from 640k-1M and possibly another one from 3.5G-4G. 1932 */ 1933 next_base = 0; 1934 numa_start = table_data->len; 1935 1936 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 1937 mem_base = next_base; 1938 mem_len = pcms->node_mem[i - 1]; 1939 next_base = mem_base + mem_len; 1940 1941 /* Cut out the 640K hole */ 1942 if (mem_base <= HOLE_640K_START && 1943 next_base > HOLE_640K_START) { 1944 mem_len -= next_base - HOLE_640K_START; 1945 if (mem_len > 0) { 1946 numamem = acpi_data_push(table_data, sizeof *numamem); 1947 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1948 MEM_AFFINITY_ENABLED); 1949 } 1950 1951 /* Check for the rare case: 640K < RAM < 1M */ 1952 if (next_base <= HOLE_640K_END) { 1953 next_base = HOLE_640K_END; 1954 continue; 1955 } 1956 mem_base = HOLE_640K_END; 1957 mem_len = next_base - HOLE_640K_END; 1958 } 1959 1960 /* Cut out the ACPI_PCI hole */ 1961 if (mem_base <= x86ms->below_4g_mem_size && 1962 next_base > x86ms->below_4g_mem_size) { 1963 mem_len -= next_base - x86ms->below_4g_mem_size; 1964 if (mem_len > 0) { 1965 numamem = acpi_data_push(table_data, sizeof *numamem); 1966 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1967 MEM_AFFINITY_ENABLED); 1968 } 1969 mem_base = 1ULL << 32; 1970 mem_len = next_base - x86ms->below_4g_mem_size; 1971 next_base = mem_base + mem_len; 1972 } 1973 1974 if (mem_len > 0) { 1975 numamem = acpi_data_push(table_data, sizeof *numamem); 1976 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1977 MEM_AFFINITY_ENABLED); 1978 } 1979 } 1980 1981 if (machine->nvdimms_state->is_enabled) { 1982 nvdimm_build_srat(table_data); 1983 } 1984 1985 slots = (table_data->len - numa_start) / sizeof *numamem; 1986 for (; slots < pcms->numa_nodes + 2; slots++) { 1987 numamem = acpi_data_push(table_data, sizeof *numamem); 1988 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1989 } 1990 1991 /* 1992 * Entry is required for Windows to enable memory hotplug in OS 1993 * and for Linux to enable SWIOTLB when booted with less than 1994 * 4G of RAM. Windows works better if the entry sets proximity 1995 * to the highest NUMA node in the machine. 1996 * Memory devices may override proximity set by this entry, 1997 * providing _PXM method if necessary. 1998 */ 1999 if (hotplugabble_address_space_size) { 2000 numamem = acpi_data_push(table_data, sizeof *numamem); 2001 build_srat_memory(numamem, machine->device_memory->base, 2002 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2003 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2004 } 2005 2006 build_header(linker, table_data, 2007 (void *)(table_data->data + srat_start), 2008 "SRAT", 2009 table_data->len - srat_start, 1, x86ms->oem_id, 2010 x86ms->oem_table_id); 2011 } 2012 2013 /* 2014 * VT-d spec 8.1 DMA Remapping Reporting Structure 2015 * (version Oct. 2014 or later) 2016 */ 2017 static void 2018 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2019 const char *oem_table_id) 2020 { 2021 int dmar_start = table_data->len; 2022 2023 AcpiTableDmar *dmar; 2024 AcpiDmarHardwareUnit *drhd; 2025 AcpiDmarRootPortATS *atsr; 2026 uint8_t dmar_flags = 0; 2027 X86IOMMUState *iommu = x86_iommu_get_default(); 2028 AcpiDmarDeviceScope *scope = NULL; 2029 /* Root complex IOAPIC use one path[0] only */ 2030 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2031 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2032 2033 assert(iommu); 2034 if (x86_iommu_ir_supported(iommu)) { 2035 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2036 } 2037 2038 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2039 dmar->host_address_width = intel_iommu->aw_bits - 1; 2040 dmar->flags = dmar_flags; 2041 2042 /* DMAR Remapping Hardware Unit Definition structure */ 2043 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2044 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2045 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2046 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2047 drhd->pci_segment = cpu_to_le16(0); 2048 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2049 2050 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2051 * 8.3.1 (version Oct. 2014 or later). */ 2052 scope = &drhd->scope[0]; 2053 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2054 scope->length = ioapic_scope_size; 2055 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2056 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2057 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2058 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2059 2060 if (iommu->dt_supported) { 2061 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2062 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2063 atsr->length = cpu_to_le16(sizeof(*atsr)); 2064 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2065 atsr->pci_segment = cpu_to_le16(0); 2066 } 2067 2068 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2069 "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id); 2070 } 2071 2072 /* 2073 * Windows ACPI Emulated Devices Table 2074 * (Version 1.0 - April 6, 2009) 2075 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2076 * 2077 * Helpful to speedup Windows guests and ignored by others. 2078 */ 2079 static void 2080 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2081 const char *oem_table_id) 2082 { 2083 int waet_start = table_data->len; 2084 2085 /* WAET header */ 2086 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2087 /* 2088 * Set "ACPI PM timer good" flag. 2089 * 2090 * Tells Windows guests that our ACPI PM timer is reliable in the 2091 * sense that guest can read it only once to obtain a reliable value. 2092 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2093 */ 2094 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2095 2096 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2097 "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id); 2098 } 2099 2100 /* 2101 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2102 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2103 */ 2104 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2105 2106 /* 2107 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2108 * necessary for the PCI topology. 2109 */ 2110 static void 2111 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2112 { 2113 GArray *table_data = opaque; 2114 uint32_t entry; 2115 2116 /* "Select" IVHD entry, type 0x2 */ 2117 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2118 build_append_int_noprefix(table_data, entry, 4); 2119 2120 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2121 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2122 uint8_t sec = pci_bus_num(sec_bus); 2123 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2124 2125 if (pci_bus_is_express(sec_bus)) { 2126 /* 2127 * Walk the bus if there are subordinates, otherwise use a range 2128 * to cover an entire leaf bus. We could potentially also use a 2129 * range for traversed buses, but we'd need to take care not to 2130 * create both Select and Range entries covering the same device. 2131 * This is easier and potentially more compact. 2132 * 2133 * An example bare metal system seems to use Select entries for 2134 * root ports without a slot (ie. built-ins) and Range entries 2135 * when there is a slot. The same system also only hard-codes 2136 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2137 * making no effort to support nested bridges. We attempt to 2138 * be more thorough here. 2139 */ 2140 if (sec == sub) { /* leaf bus */ 2141 /* "Start of Range" IVHD entry, type 0x3 */ 2142 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2143 build_append_int_noprefix(table_data, entry, 4); 2144 /* "End of Range" IVHD entry, type 0x4 */ 2145 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2146 build_append_int_noprefix(table_data, entry, 4); 2147 } else { 2148 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2149 } 2150 } else { 2151 /* 2152 * If the secondary bus is conventional, then we need to create an 2153 * Alias range for everything downstream. The range covers the 2154 * first devfn on the secondary bus to the last devfn on the 2155 * subordinate bus. The alias target depends on legacy versus 2156 * express bridges, just as in pci_device_iommu_address_space(). 2157 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2158 */ 2159 uint16_t dev_id_a, dev_id_b; 2160 2161 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2162 2163 if (pci_is_express(dev) && 2164 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2165 dev_id_b = dev_id_a; 2166 } else { 2167 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2168 } 2169 2170 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2171 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2172 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2173 2174 /* "End of Range" IVHD entry, type 0x4 */ 2175 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2176 build_append_int_noprefix(table_data, entry, 4); 2177 } 2178 } 2179 } 2180 2181 /* For all PCI host bridges, walk and insert IVHD entries */ 2182 static int 2183 ivrs_host_bridges(Object *obj, void *opaque) 2184 { 2185 GArray *ivhd_blob = opaque; 2186 2187 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2188 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2189 2190 if (bus) { 2191 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2192 } 2193 } 2194 2195 return 0; 2196 } 2197 2198 static void 2199 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2200 const char *oem_table_id) 2201 { 2202 int ivhd_table_len = 24; 2203 int iommu_start = table_data->len; 2204 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2205 GArray *ivhd_blob = g_array_new(false, true, 1); 2206 2207 /* IVRS header */ 2208 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2209 /* IVinfo - IO virtualization information common to all 2210 * IOMMU units in a system 2211 */ 2212 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2213 /* reserved */ 2214 build_append_int_noprefix(table_data, 0, 8); 2215 2216 /* IVHD definition - type 10h */ 2217 build_append_int_noprefix(table_data, 0x10, 1); 2218 /* virtualization flags */ 2219 build_append_int_noprefix(table_data, 2220 (1UL << 0) | /* HtTunEn */ 2221 (1UL << 4) | /* iotblSup */ 2222 (1UL << 6) | /* PrefSup */ 2223 (1UL << 7), /* PPRSup */ 2224 1); 2225 2226 /* 2227 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2228 * complete set of IVHD entries. Do this into a separate blob so that we 2229 * can calculate the total IVRS table length here and then append the new 2230 * blob further below. Fall back to an entry covering all devices, which 2231 * is sufficient when no aliases are present. 2232 */ 2233 object_child_foreach_recursive(object_get_root(), 2234 ivrs_host_bridges, ivhd_blob); 2235 2236 if (!ivhd_blob->len) { 2237 /* 2238 * Type 1 device entry reporting all devices 2239 * These are 4-byte device entries currently reporting the range of 2240 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2241 */ 2242 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2243 } 2244 2245 ivhd_table_len += ivhd_blob->len; 2246 2247 /* 2248 * When interrupt remapping is supported, we add a special IVHD device 2249 * for type IO-APIC. 2250 */ 2251 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2252 ivhd_table_len += 8; 2253 } 2254 2255 /* IVHD length */ 2256 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2257 /* DeviceID */ 2258 build_append_int_noprefix(table_data, s->devid, 2); 2259 /* Capability offset */ 2260 build_append_int_noprefix(table_data, s->capab_offset, 2); 2261 /* IOMMU base address */ 2262 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2263 /* PCI Segment Group */ 2264 build_append_int_noprefix(table_data, 0, 2); 2265 /* IOMMU info */ 2266 build_append_int_noprefix(table_data, 0, 2); 2267 /* IOMMU Feature Reporting */ 2268 build_append_int_noprefix(table_data, 2269 (48UL << 30) | /* HATS */ 2270 (48UL << 28) | /* GATS */ 2271 (1UL << 2) | /* GTSup */ 2272 (1UL << 6), /* GASup */ 2273 4); 2274 2275 /* IVHD entries as found above */ 2276 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2277 g_array_free(ivhd_blob, TRUE); 2278 2279 /* 2280 * Add a special IVHD device type. 2281 * Refer to spec - Table 95: IVHD device entry type codes 2282 * 2283 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2284 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2285 */ 2286 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2287 build_append_int_noprefix(table_data, 2288 (0x1ull << 56) | /* type IOAPIC */ 2289 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2290 0x48, /* special device */ 2291 8); 2292 } 2293 2294 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2295 "IVRS", table_data->len - iommu_start, 1, oem_id, 2296 oem_table_id); 2297 } 2298 2299 typedef 2300 struct AcpiBuildState { 2301 /* Copy of table in RAM (for patching). */ 2302 MemoryRegion *table_mr; 2303 /* Is table patched? */ 2304 uint8_t patched; 2305 void *rsdp; 2306 MemoryRegion *rsdp_mr; 2307 MemoryRegion *linker_mr; 2308 } AcpiBuildState; 2309 2310 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2311 { 2312 Object *pci_host; 2313 QObject *o; 2314 2315 pci_host = acpi_get_i386_pci_host(); 2316 g_assert(pci_host); 2317 2318 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2319 if (!o) { 2320 return false; 2321 } 2322 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2323 qobject_unref(o); 2324 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2325 return false; 2326 } 2327 2328 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2329 assert(o); 2330 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2331 qobject_unref(o); 2332 return true; 2333 } 2334 2335 static 2336 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2337 { 2338 PCMachineState *pcms = PC_MACHINE(machine); 2339 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2340 X86MachineState *x86ms = X86_MACHINE(machine); 2341 GArray *table_offsets; 2342 unsigned facs, dsdt, rsdt, fadt; 2343 AcpiPmInfo pm; 2344 AcpiMiscInfo misc; 2345 AcpiMcfgInfo mcfg; 2346 Range pci_hole, pci_hole64; 2347 uint8_t *u; 2348 size_t aml_len = 0; 2349 GArray *tables_blob = tables->table_data; 2350 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2351 Object *vmgenid_dev; 2352 char *oem_id; 2353 char *oem_table_id; 2354 2355 acpi_get_pm_info(machine, &pm); 2356 acpi_get_misc_info(&misc); 2357 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2358 acpi_get_slic_oem(&slic_oem); 2359 2360 if (slic_oem.id) { 2361 oem_id = slic_oem.id; 2362 } else { 2363 oem_id = x86ms->oem_id; 2364 } 2365 2366 if (slic_oem.table_id) { 2367 oem_table_id = slic_oem.table_id; 2368 } else { 2369 oem_table_id = x86ms->oem_table_id; 2370 } 2371 2372 table_offsets = g_array_new(false, true /* clear */, 2373 sizeof(uint32_t)); 2374 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2375 2376 bios_linker_loader_alloc(tables->linker, 2377 ACPI_BUILD_TABLE_FILE, tables_blob, 2378 64 /* Ensure FACS is aligned */, 2379 false /* high memory */); 2380 2381 /* 2382 * FACS is pointed to by FADT. 2383 * We place it first since it's the only table that has alignment 2384 * requirements. 2385 */ 2386 facs = tables_blob->len; 2387 build_facs(tables_blob); 2388 2389 /* DSDT is pointed to by FADT */ 2390 dsdt = tables_blob->len; 2391 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2392 &pci_hole, &pci_hole64, machine); 2393 2394 /* Count the size of the DSDT and SSDT, we will need it for legacy 2395 * sizing of ACPI tables. 2396 */ 2397 aml_len += tables_blob->len - dsdt; 2398 2399 /* ACPI tables pointed to by RSDT */ 2400 fadt = tables_blob->len; 2401 acpi_add_table(table_offsets, tables_blob); 2402 pm.fadt.facs_tbl_offset = &facs; 2403 pm.fadt.dsdt_tbl_offset = &dsdt; 2404 pm.fadt.xdsdt_tbl_offset = &dsdt; 2405 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2406 aml_len += tables_blob->len - fadt; 2407 2408 acpi_add_table(table_offsets, tables_blob); 2409 acpi_build_madt(tables_blob, tables->linker, x86ms, 2410 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2411 x86ms->oem_table_id); 2412 2413 vmgenid_dev = find_vmgenid_dev(); 2414 if (vmgenid_dev) { 2415 acpi_add_table(table_offsets, tables_blob); 2416 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2417 tables->vmgenid, tables->linker, x86ms->oem_id); 2418 } 2419 2420 if (misc.has_hpet) { 2421 acpi_add_table(table_offsets, tables_blob); 2422 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2423 x86ms->oem_table_id); 2424 } 2425 #ifdef CONFIG_TPM 2426 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2427 if (misc.tpm_version == TPM_VERSION_1_2) { 2428 acpi_add_table(table_offsets, tables_blob); 2429 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2430 x86ms->oem_id, x86ms->oem_table_id); 2431 } else { /* TPM_VERSION_2_0 */ 2432 acpi_add_table(table_offsets, tables_blob); 2433 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2434 x86ms->oem_id, x86ms->oem_table_id); 2435 } 2436 } 2437 #endif 2438 if (pcms->numa_nodes) { 2439 acpi_add_table(table_offsets, tables_blob); 2440 build_srat(tables_blob, tables->linker, machine); 2441 if (machine->numa_state->have_numa_distance) { 2442 acpi_add_table(table_offsets, tables_blob); 2443 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2444 x86ms->oem_table_id); 2445 } 2446 if (machine->numa_state->hmat_enabled) { 2447 acpi_add_table(table_offsets, tables_blob); 2448 build_hmat(tables_blob, tables->linker, machine->numa_state, 2449 x86ms->oem_id, x86ms->oem_table_id); 2450 } 2451 } 2452 if (acpi_get_mcfg(&mcfg)) { 2453 acpi_add_table(table_offsets, tables_blob); 2454 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2455 x86ms->oem_table_id); 2456 } 2457 if (x86_iommu_get_default()) { 2458 IommuType IOMMUType = x86_iommu_get_type(); 2459 if (IOMMUType == TYPE_AMD) { 2460 acpi_add_table(table_offsets, tables_blob); 2461 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2462 x86ms->oem_table_id); 2463 } else if (IOMMUType == TYPE_INTEL) { 2464 acpi_add_table(table_offsets, tables_blob); 2465 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2466 x86ms->oem_table_id); 2467 } 2468 } 2469 if (machine->nvdimms_state->is_enabled) { 2470 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2471 machine->nvdimms_state, machine->ram_slots, 2472 x86ms->oem_id, x86ms->oem_table_id); 2473 } 2474 2475 acpi_add_table(table_offsets, tables_blob); 2476 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2477 2478 /* Add tables supplied by user (if any) */ 2479 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2480 unsigned len = acpi_table_len(u); 2481 2482 acpi_add_table(table_offsets, tables_blob); 2483 g_array_append_vals(tables_blob, u, len); 2484 } 2485 2486 /* RSDT is pointed to by RSDP */ 2487 rsdt = tables_blob->len; 2488 build_rsdt(tables_blob, tables->linker, table_offsets, 2489 oem_id, oem_table_id); 2490 2491 /* RSDP is in FSEG memory, so allocate it separately */ 2492 { 2493 AcpiRsdpData rsdp_data = { 2494 .revision = 0, 2495 .oem_id = x86ms->oem_id, 2496 .xsdt_tbl_offset = NULL, 2497 .rsdt_tbl_offset = &rsdt, 2498 }; 2499 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2500 if (!pcmc->rsdp_in_ram) { 2501 /* We used to allocate some extra space for RSDP revision 2 but 2502 * only used the RSDP revision 0 space. The extra bytes were 2503 * zeroed out and not used. 2504 * Here we continue wasting those extra 16 bytes to make sure we 2505 * don't break migration for machine types 2.2 and older due to 2506 * RSDP blob size mismatch. 2507 */ 2508 build_append_int_noprefix(tables->rsdp, 0, 16); 2509 } 2510 } 2511 2512 /* We'll expose it all to Guest so we want to reduce 2513 * chance of size changes. 2514 * 2515 * We used to align the tables to 4k, but of course this would 2516 * too simple to be enough. 4k turned out to be too small an 2517 * alignment very soon, and in fact it is almost impossible to 2518 * keep the table size stable for all (max_cpus, max_memory_slots) 2519 * combinations. So the table size is always 64k for pc-i440fx-2.1 2520 * and we give an error if the table grows beyond that limit. 2521 * 2522 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2523 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2524 * than 2.0 and we can always pad the smaller tables with zeros. We can 2525 * then use the exact size of the 2.0 tables. 2526 * 2527 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2528 */ 2529 if (pcmc->legacy_acpi_table_size) { 2530 /* Subtracting aml_len gives the size of fixed tables. Then add the 2531 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2532 */ 2533 int legacy_aml_len = 2534 pcmc->legacy_acpi_table_size + 2535 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2536 int legacy_table_size = 2537 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2538 ACPI_BUILD_ALIGN_SIZE); 2539 if (tables_blob->len > legacy_table_size) { 2540 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2541 warn_report("ACPI table size %u exceeds %d bytes," 2542 " migration may not work", 2543 tables_blob->len, legacy_table_size); 2544 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2545 " or PCI bridges."); 2546 } 2547 g_array_set_size(tables_blob, legacy_table_size); 2548 } else { 2549 /* Make sure we have a buffer in case we need to resize the tables. */ 2550 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2551 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2552 warn_report("ACPI table size %u exceeds %d bytes," 2553 " migration may not work", 2554 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2555 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2556 " or PCI bridges."); 2557 } 2558 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2559 } 2560 2561 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2562 2563 /* Cleanup memory that's no longer used. */ 2564 g_array_free(table_offsets, true); 2565 } 2566 2567 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2568 { 2569 uint32_t size = acpi_data_len(data); 2570 2571 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2572 memory_region_ram_resize(mr, size, &error_abort); 2573 2574 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2575 memory_region_set_dirty(mr, 0, size); 2576 } 2577 2578 static void acpi_build_update(void *build_opaque) 2579 { 2580 AcpiBuildState *build_state = build_opaque; 2581 AcpiBuildTables tables; 2582 2583 /* No state to update or already patched? Nothing to do. */ 2584 if (!build_state || build_state->patched) { 2585 return; 2586 } 2587 build_state->patched = 1; 2588 2589 acpi_build_tables_init(&tables); 2590 2591 acpi_build(&tables, MACHINE(qdev_get_machine())); 2592 2593 acpi_ram_update(build_state->table_mr, tables.table_data); 2594 2595 if (build_state->rsdp) { 2596 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2597 } else { 2598 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2599 } 2600 2601 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2602 acpi_build_tables_cleanup(&tables, true); 2603 } 2604 2605 static void acpi_build_reset(void *build_opaque) 2606 { 2607 AcpiBuildState *build_state = build_opaque; 2608 build_state->patched = 0; 2609 } 2610 2611 static const VMStateDescription vmstate_acpi_build = { 2612 .name = "acpi_build", 2613 .version_id = 1, 2614 .minimum_version_id = 1, 2615 .fields = (VMStateField[]) { 2616 VMSTATE_UINT8(patched, AcpiBuildState), 2617 VMSTATE_END_OF_LIST() 2618 }, 2619 }; 2620 2621 void acpi_setup(void) 2622 { 2623 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2624 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2625 X86MachineState *x86ms = X86_MACHINE(pcms); 2626 AcpiBuildTables tables; 2627 AcpiBuildState *build_state; 2628 Object *vmgenid_dev; 2629 #ifdef CONFIG_TPM 2630 TPMIf *tpm; 2631 static FwCfgTPMConfig tpm_config; 2632 #endif 2633 2634 if (!x86ms->fw_cfg) { 2635 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2636 return; 2637 } 2638 2639 if (!pcms->acpi_build_enabled) { 2640 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2641 return; 2642 } 2643 2644 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2645 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2646 return; 2647 } 2648 2649 build_state = g_malloc0(sizeof *build_state); 2650 2651 acpi_build_tables_init(&tables); 2652 acpi_build(&tables, MACHINE(pcms)); 2653 2654 /* Now expose it all to Guest */ 2655 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2656 build_state, tables.table_data, 2657 ACPI_BUILD_TABLE_FILE); 2658 assert(build_state->table_mr != NULL); 2659 2660 build_state->linker_mr = 2661 acpi_add_rom_blob(acpi_build_update, build_state, 2662 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2663 2664 #ifdef CONFIG_TPM 2665 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2666 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2667 2668 tpm = tpm_find(); 2669 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2670 tpm_config = (FwCfgTPMConfig) { 2671 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2672 .tpm_version = tpm_get_version(tpm), 2673 .tpmppi_version = TPM_PPI_VERSION_1_30 2674 }; 2675 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2676 &tpm_config, sizeof tpm_config); 2677 } 2678 #endif 2679 2680 vmgenid_dev = find_vmgenid_dev(); 2681 if (vmgenid_dev) { 2682 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2683 tables.vmgenid); 2684 } 2685 2686 if (!pcmc->rsdp_in_ram) { 2687 /* 2688 * Keep for compatibility with old machine types. 2689 * Though RSDP is small, its contents isn't immutable, so 2690 * we'll update it along with the rest of tables on guest access. 2691 */ 2692 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2693 2694 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2695 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2696 acpi_build_update, NULL, build_state, 2697 build_state->rsdp, rsdp_size, true); 2698 build_state->rsdp_mr = NULL; 2699 } else { 2700 build_state->rsdp = NULL; 2701 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2702 build_state, tables.rsdp, 2703 ACPI_BUILD_RSDP_FILE); 2704 } 2705 2706 qemu_register_reset(acpi_build_reset, build_state); 2707 acpi_build_reset(build_state); 2708 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2709 2710 /* Cleanup tables but don't free the memory: we track it 2711 * in build_state. 2712 */ 2713 acpi_build_tables_cleanup(&tables, false); 2714 } 2715