1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "hw/core/cpu.h" 31 #include "target/i386/cpu.h" 32 #include "hw/misc/pvpanic.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/isa/isa.h" 40 #include "hw/block/fdc.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "sysemu/tpm.h" 43 #include "hw/acpi/tpm.h" 44 #include "hw/acpi/vmgenid.h" 45 #include "hw/boards.h" 46 #include "sysemu/tpm_backend.h" 47 #include "hw/rtc/mc146818rtc_regs.h" 48 #include "migration/vmstate.h" 49 #include "hw/mem/memory-device.h" 50 #include "hw/mem/nvdimm.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/reset.h" 53 54 /* Supported chipsets: */ 55 #include "hw/southbridge/piix.h" 56 #include "hw/acpi/pcihp.h" 57 #include "hw/i386/fw_cfg.h" 58 #include "hw/i386/ich9.h" 59 #include "hw/pci/pci_bus.h" 60 #include "hw/pci-host/q35.h" 61 #include "hw/i386/x86-iommu.h" 62 63 #include "hw/acpi/aml-build.h" 64 #include "hw/acpi/utils.h" 65 #include "hw/acpi/pci.h" 66 67 #include "qom/qom-qobject.h" 68 #include "hw/i386/amd_iommu.h" 69 #include "hw/i386/intel_iommu.h" 70 71 #include "hw/acpi/ipmi.h" 72 #include "hw/acpi/hmat.h" 73 74 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 75 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 76 * a little bit, there should be plenty of free space since the DSDT 77 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 78 */ 79 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 80 #define ACPI_BUILD_ALIGN_SIZE 0x1000 81 82 #define ACPI_BUILD_TABLE_SIZE 0x20000 83 84 /* #define DEBUG_ACPI_BUILD */ 85 #ifdef DEBUG_ACPI_BUILD 86 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 87 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 88 #else 89 #define ACPI_BUILD_DPRINTF(fmt, ...) 90 #endif 91 92 /* Default IOAPIC ID */ 93 #define ACPI_BUILD_IOAPIC_ID 0x0 94 95 typedef struct AcpiPmInfo { 96 bool s3_disabled; 97 bool s4_disabled; 98 bool pcihp_bridge_en; 99 uint8_t s4_val; 100 AcpiFadtData fadt; 101 uint16_t cpu_hp_io_base; 102 uint16_t pcihp_io_base; 103 uint16_t pcihp_io_len; 104 } AcpiPmInfo; 105 106 typedef struct AcpiMiscInfo { 107 bool is_piix4; 108 bool has_hpet; 109 TPMVersion tpm_version; 110 const unsigned char *dsdt_code; 111 unsigned dsdt_size; 112 uint16_t pvpanic_port; 113 uint16_t applesmc_io_base; 114 } AcpiMiscInfo; 115 116 typedef struct AcpiBuildPciBusHotplugState { 117 GArray *device_table; 118 GArray *notify_table; 119 struct AcpiBuildPciBusHotplugState *parent; 120 bool pcihp_bridge_en; 121 } AcpiBuildPciBusHotplugState; 122 123 typedef struct FwCfgTPMConfig { 124 uint32_t tpmppi_address; 125 uint8_t tpm_version; 126 uint8_t tpmppi_version; 127 } QEMU_PACKED FwCfgTPMConfig; 128 129 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 130 131 static void init_common_fadt_data(MachineState *ms, Object *o, 132 AcpiFadtData *data) 133 { 134 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 135 AmlAddressSpace as = AML_AS_SYSTEM_IO; 136 AcpiFadtData fadt = { 137 .rev = 3, 138 .flags = 139 (1 << ACPI_FADT_F_WBINVD) | 140 (1 << ACPI_FADT_F_PROC_C1) | 141 (1 << ACPI_FADT_F_SLP_BUTTON) | 142 (1 << ACPI_FADT_F_RTC_S4) | 143 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 144 /* APIC destination mode ("Flat Logical") has an upper limit of 8 145 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 146 * used 147 */ 148 ((ms->smp.max_cpus > 8) ? 149 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 150 .int_model = 1 /* Multiple APIC */, 151 .rtc_century = RTC_CENTURY, 152 .plvl2_lat = 0xfff /* C2 state not supported */, 153 .plvl3_lat = 0xfff /* C3 state not supported */, 154 .smi_cmd = ACPI_PORT_SMI_CMD, 155 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 156 .acpi_enable_cmd = 157 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 158 .acpi_disable_cmd = 159 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 160 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 161 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 162 .address = io + 0x04 }, 163 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 164 .gpe0_blk = { .space_id = as, .bit_width = 165 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 166 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 167 }, 168 }; 169 *data = fadt; 170 } 171 172 static Object *object_resolve_type_unambiguous(const char *typename) 173 { 174 bool ambig; 175 Object *o = object_resolve_path_type("", typename, &ambig); 176 177 if (ambig || !o) { 178 return NULL; 179 } 180 return o; 181 } 182 183 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 184 { 185 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 186 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 187 Object *obj = piix ? piix : lpc; 188 QObject *o; 189 pm->cpu_hp_io_base = 0; 190 pm->pcihp_io_base = 0; 191 pm->pcihp_io_len = 0; 192 193 assert(obj); 194 init_common_fadt_data(machine, obj, &pm->fadt); 195 if (piix) { 196 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 197 pm->fadt.rev = 1; 198 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 199 pm->pcihp_io_base = 200 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 201 pm->pcihp_io_len = 202 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 203 } 204 if (lpc) { 205 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 206 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 207 pm->fadt.reset_reg = r; 208 pm->fadt.reset_val = 0xf; 209 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 210 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 211 } 212 213 /* The above need not be conditional on machine type because the reset port 214 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 215 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 216 217 /* Fill in optional s3/s4 related properties */ 218 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 219 if (o) { 220 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 221 } else { 222 pm->s3_disabled = false; 223 } 224 qobject_unref(o); 225 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 226 if (o) { 227 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 228 } else { 229 pm->s4_disabled = false; 230 } 231 qobject_unref(o); 232 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 233 if (o) { 234 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 235 } else { 236 pm->s4_val = false; 237 } 238 qobject_unref(o); 239 240 pm->pcihp_bridge_en = 241 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 242 NULL); 243 } 244 245 static void acpi_get_misc_info(AcpiMiscInfo *info) 246 { 247 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 248 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 249 assert(!!piix != !!lpc); 250 251 if (piix) { 252 info->is_piix4 = true; 253 } 254 if (lpc) { 255 info->is_piix4 = false; 256 } 257 258 info->has_hpet = hpet_find(); 259 info->tpm_version = tpm_get_version(tpm_find()); 260 info->pvpanic_port = pvpanic_port(); 261 info->applesmc_io_base = applesmc_port(); 262 } 263 264 /* 265 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 266 * On i386 arch we only have two pci hosts, so we can look only for them. 267 */ 268 static Object *acpi_get_i386_pci_host(void) 269 { 270 PCIHostState *host; 271 272 host = OBJECT_CHECK(PCIHostState, 273 object_resolve_path("/machine/i440fx", NULL), 274 TYPE_PCI_HOST_BRIDGE); 275 if (!host) { 276 host = OBJECT_CHECK(PCIHostState, 277 object_resolve_path("/machine/q35", NULL), 278 TYPE_PCI_HOST_BRIDGE); 279 } 280 281 return OBJECT(host); 282 } 283 284 static void acpi_get_pci_holes(Range *hole, Range *hole64) 285 { 286 Object *pci_host; 287 288 pci_host = acpi_get_i386_pci_host(); 289 g_assert(pci_host); 290 291 range_set_bounds1(hole, 292 object_property_get_uint(pci_host, 293 PCI_HOST_PROP_PCI_HOLE_START, 294 NULL), 295 object_property_get_uint(pci_host, 296 PCI_HOST_PROP_PCI_HOLE_END, 297 NULL)); 298 range_set_bounds1(hole64, 299 object_property_get_uint(pci_host, 300 PCI_HOST_PROP_PCI_HOLE64_START, 301 NULL), 302 object_property_get_uint(pci_host, 303 PCI_HOST_PROP_PCI_HOLE64_END, 304 NULL)); 305 } 306 307 static void acpi_align_size(GArray *blob, unsigned align) 308 { 309 /* Align size to multiple of given size. This reduces the chance 310 * we need to change size in the future (breaking cross version migration). 311 */ 312 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 313 } 314 315 /* FACS */ 316 static void 317 build_facs(GArray *table_data) 318 { 319 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 320 memcpy(&facs->signature, "FACS", 4); 321 facs->length = cpu_to_le32(sizeof(*facs)); 322 } 323 324 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 325 const CPUArchIdList *apic_ids, GArray *entry) 326 { 327 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 328 329 /* ACPI spec says that LAPIC entry for non present 330 * CPU may be omitted from MADT or it must be marked 331 * as disabled. However omitting non present CPU from 332 * MADT breaks hotplug on linux. So possible CPUs 333 * should be put in MADT but kept disabled. 334 */ 335 if (apic_id < 255) { 336 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 337 338 apic->type = ACPI_APIC_PROCESSOR; 339 apic->length = sizeof(*apic); 340 apic->processor_id = uid; 341 apic->local_apic_id = apic_id; 342 if (apic_ids->cpus[uid].cpu != NULL) { 343 apic->flags = cpu_to_le32(1); 344 } else { 345 apic->flags = cpu_to_le32(0); 346 } 347 } else { 348 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 349 350 apic->type = ACPI_APIC_LOCAL_X2APIC; 351 apic->length = sizeof(*apic); 352 apic->uid = cpu_to_le32(uid); 353 apic->x2apic_id = cpu_to_le32(apic_id); 354 if (apic_ids->cpus[uid].cpu != NULL) { 355 apic->flags = cpu_to_le32(1); 356 } else { 357 apic->flags = cpu_to_le32(0); 358 } 359 } 360 } 361 362 static void 363 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 364 { 365 MachineClass *mc = MACHINE_GET_CLASS(pcms); 366 X86MachineState *x86ms = X86_MACHINE(pcms); 367 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 368 int madt_start = table_data->len; 369 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 370 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 371 bool x2apic_mode = false; 372 373 AcpiMultipleApicTable *madt; 374 AcpiMadtIoApic *io_apic; 375 AcpiMadtIntsrcovr *intsrcovr; 376 int i; 377 378 madt = acpi_data_push(table_data, sizeof *madt); 379 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 380 madt->flags = cpu_to_le32(1); 381 382 for (i = 0; i < apic_ids->len; i++) { 383 adevc->madt_cpu(adev, i, apic_ids, table_data); 384 if (apic_ids->cpus[i].arch_id > 254) { 385 x2apic_mode = true; 386 } 387 } 388 389 io_apic = acpi_data_push(table_data, sizeof *io_apic); 390 io_apic->type = ACPI_APIC_IO; 391 io_apic->length = sizeof(*io_apic); 392 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 393 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 394 io_apic->interrupt = cpu_to_le32(0); 395 396 if (x86ms->apic_xrupt_override) { 397 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 398 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 399 intsrcovr->length = sizeof(*intsrcovr); 400 intsrcovr->source = 0; 401 intsrcovr->gsi = cpu_to_le32(2); 402 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 403 } 404 for (i = 1; i < 16; i++) { 405 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 406 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 407 /* No need for a INT source override structure. */ 408 continue; 409 } 410 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 411 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 412 intsrcovr->length = sizeof(*intsrcovr); 413 intsrcovr->source = i; 414 intsrcovr->gsi = cpu_to_le32(i); 415 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 416 } 417 418 if (x2apic_mode) { 419 AcpiMadtLocalX2ApicNmi *local_nmi; 420 421 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 422 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 423 local_nmi->length = sizeof(*local_nmi); 424 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 425 local_nmi->flags = cpu_to_le16(0); 426 local_nmi->lint = 1; /* ACPI_LINT1 */ 427 } else { 428 AcpiMadtLocalNmi *local_nmi; 429 430 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 431 local_nmi->type = ACPI_APIC_LOCAL_NMI; 432 local_nmi->length = sizeof(*local_nmi); 433 local_nmi->processor_id = 0xff; /* all processors */ 434 local_nmi->flags = cpu_to_le16(0); 435 local_nmi->lint = 1; /* ACPI_LINT1 */ 436 } 437 438 build_header(linker, table_data, 439 (void *)(table_data->data + madt_start), "APIC", 440 table_data->len - madt_start, 1, NULL, NULL); 441 } 442 443 static void build_append_pcihp_notify_entry(Aml *method, int slot) 444 { 445 Aml *if_ctx; 446 int32_t devfn = PCI_DEVFN(slot, 0); 447 448 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 449 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 450 aml_append(method, if_ctx); 451 } 452 453 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 454 bool pcihp_bridge_en) 455 { 456 Aml *dev, *notify_method = NULL, *method; 457 QObject *bsel; 458 PCIBus *sec; 459 int i; 460 461 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 462 if (bsel) { 463 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 464 465 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 466 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 467 } 468 469 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 470 DeviceClass *dc; 471 PCIDeviceClass *pc; 472 PCIDevice *pdev = bus->devices[i]; 473 int slot = PCI_SLOT(i); 474 bool hotplug_enabled_dev; 475 bool bridge_in_acpi; 476 477 if (!pdev) { 478 if (bsel) { /* add hotplug slots for non present devices */ 479 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 480 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 481 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 482 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 483 aml_append(method, 484 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 485 ); 486 aml_append(dev, method); 487 aml_append(parent_scope, dev); 488 489 build_append_pcihp_notify_entry(notify_method, slot); 490 } 491 continue; 492 } 493 494 pc = PCI_DEVICE_GET_CLASS(pdev); 495 dc = DEVICE_GET_CLASS(pdev); 496 497 /* When hotplug for bridges is enabled, bridges are 498 * described in ACPI separately (see build_pci_bus_end). 499 * In this case they aren't themselves hot-pluggable. 500 * Hotplugged bridges *are* hot-pluggable. 501 */ 502 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 503 !DEVICE(pdev)->hotplugged; 504 505 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 506 507 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 508 continue; 509 } 510 511 /* start to compose PCI slot descriptor */ 512 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 513 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 514 515 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 516 /* add VGA specific AML methods */ 517 int s3d; 518 519 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 520 s3d = 3; 521 } else { 522 s3d = 0; 523 } 524 525 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 526 aml_append(method, aml_return(aml_int(0))); 527 aml_append(dev, method); 528 529 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 530 aml_append(method, aml_return(aml_int(0))); 531 aml_append(dev, method); 532 533 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 534 aml_append(method, aml_return(aml_int(s3d))); 535 aml_append(dev, method); 536 } else if (hotplug_enabled_dev) { 537 /* add _SUN/_EJ0 to make slot hotpluggable */ 538 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 539 540 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 541 aml_append(method, 542 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 543 ); 544 aml_append(dev, method); 545 546 if (bsel) { 547 build_append_pcihp_notify_entry(notify_method, slot); 548 } 549 } else if (bridge_in_acpi) { 550 /* 551 * device is coldplugged bridge, 552 * add child device descriptions into its scope 553 */ 554 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 555 556 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 557 } 558 /* slot descriptor has been composed, add it into parent context */ 559 aml_append(parent_scope, dev); 560 } 561 562 if (bsel) { 563 aml_append(parent_scope, notify_method); 564 } 565 566 /* Append PCNT method to notify about events on local and child buses. 567 * Add unconditionally for root since DSDT expects it. 568 */ 569 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 570 571 /* If bus supports hotplug select it and notify about local events */ 572 if (bsel) { 573 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 574 575 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 576 aml_append(method, 577 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 578 ); 579 aml_append(method, 580 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 581 ); 582 } 583 584 /* Notify about child bus events in any case */ 585 if (pcihp_bridge_en) { 586 QLIST_FOREACH(sec, &bus->child, sibling) { 587 int32_t devfn = sec->parent_dev->devfn; 588 589 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 590 continue; 591 } 592 593 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 594 } 595 } 596 aml_append(parent_scope, method); 597 qobject_unref(bsel); 598 } 599 600 /** 601 * build_prt_entry: 602 * @link_name: link name for PCI route entry 603 * 604 * build AML package containing a PCI route entry for @link_name 605 */ 606 static Aml *build_prt_entry(const char *link_name) 607 { 608 Aml *a_zero = aml_int(0); 609 Aml *pkg = aml_package(4); 610 aml_append(pkg, a_zero); 611 aml_append(pkg, a_zero); 612 aml_append(pkg, aml_name("%s", link_name)); 613 aml_append(pkg, a_zero); 614 return pkg; 615 } 616 617 /* 618 * initialize_route - Initialize the interrupt routing rule 619 * through a specific LINK: 620 * if (lnk_idx == idx) 621 * route using link 'link_name' 622 */ 623 static Aml *initialize_route(Aml *route, const char *link_name, 624 Aml *lnk_idx, int idx) 625 { 626 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 627 Aml *pkg = build_prt_entry(link_name); 628 629 aml_append(if_ctx, aml_store(pkg, route)); 630 631 return if_ctx; 632 } 633 634 /* 635 * build_prt - Define interrupt rounting rules 636 * 637 * Returns an array of 128 routes, one for each device, 638 * based on device location. 639 * The main goal is to equaly distribute the interrupts 640 * over the 4 existing ACPI links (works only for i440fx). 641 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 642 * 643 */ 644 static Aml *build_prt(bool is_pci0_prt) 645 { 646 Aml *method, *while_ctx, *pin, *res; 647 648 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 649 res = aml_local(0); 650 pin = aml_local(1); 651 aml_append(method, aml_store(aml_package(128), res)); 652 aml_append(method, aml_store(aml_int(0), pin)); 653 654 /* while (pin < 128) */ 655 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 656 { 657 Aml *slot = aml_local(2); 658 Aml *lnk_idx = aml_local(3); 659 Aml *route = aml_local(4); 660 661 /* slot = pin >> 2 */ 662 aml_append(while_ctx, 663 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 664 /* lnk_idx = (slot + pin) & 3 */ 665 aml_append(while_ctx, 666 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 667 lnk_idx)); 668 669 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 670 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 671 if (is_pci0_prt) { 672 Aml *if_device_1, *if_pin_4, *else_pin_4; 673 674 /* device 1 is the power-management device, needs SCI */ 675 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 676 { 677 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 678 { 679 aml_append(if_pin_4, 680 aml_store(build_prt_entry("LNKS"), route)); 681 } 682 aml_append(if_device_1, if_pin_4); 683 else_pin_4 = aml_else(); 684 { 685 aml_append(else_pin_4, 686 aml_store(build_prt_entry("LNKA"), route)); 687 } 688 aml_append(if_device_1, else_pin_4); 689 } 690 aml_append(while_ctx, if_device_1); 691 } else { 692 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 693 } 694 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 695 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 696 697 /* route[0] = 0x[slot]FFFF */ 698 aml_append(while_ctx, 699 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 700 NULL), 701 aml_index(route, aml_int(0)))); 702 /* route[1] = pin & 3 */ 703 aml_append(while_ctx, 704 aml_store(aml_and(pin, aml_int(3), NULL), 705 aml_index(route, aml_int(1)))); 706 /* res[pin] = route */ 707 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 708 /* pin++ */ 709 aml_append(while_ctx, aml_increment(pin)); 710 } 711 aml_append(method, while_ctx); 712 /* return res*/ 713 aml_append(method, aml_return(res)); 714 715 return method; 716 } 717 718 typedef struct CrsRangeEntry { 719 uint64_t base; 720 uint64_t limit; 721 } CrsRangeEntry; 722 723 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 724 { 725 CrsRangeEntry *entry; 726 727 entry = g_malloc(sizeof(*entry)); 728 entry->base = base; 729 entry->limit = limit; 730 731 g_ptr_array_add(ranges, entry); 732 } 733 734 static void crs_range_free(gpointer data) 735 { 736 CrsRangeEntry *entry = (CrsRangeEntry *)data; 737 g_free(entry); 738 } 739 740 typedef struct CrsRangeSet { 741 GPtrArray *io_ranges; 742 GPtrArray *mem_ranges; 743 GPtrArray *mem_64bit_ranges; 744 } CrsRangeSet; 745 746 static void crs_range_set_init(CrsRangeSet *range_set) 747 { 748 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 749 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 750 range_set->mem_64bit_ranges = 751 g_ptr_array_new_with_free_func(crs_range_free); 752 } 753 754 static void crs_range_set_free(CrsRangeSet *range_set) 755 { 756 g_ptr_array_free(range_set->io_ranges, true); 757 g_ptr_array_free(range_set->mem_ranges, true); 758 g_ptr_array_free(range_set->mem_64bit_ranges, true); 759 } 760 761 static gint crs_range_compare(gconstpointer a, gconstpointer b) 762 { 763 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 764 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 765 766 if (entry_a->base < entry_b->base) { 767 return -1; 768 } else if (entry_a->base > entry_b->base) { 769 return 1; 770 } else { 771 return 0; 772 } 773 } 774 775 /* 776 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 777 * interval, computes the 'free' ranges from the same interval. 778 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 779 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 780 */ 781 static void crs_replace_with_free_ranges(GPtrArray *ranges, 782 uint64_t start, uint64_t end) 783 { 784 GPtrArray *free_ranges = g_ptr_array_new(); 785 uint64_t free_base = start; 786 int i; 787 788 g_ptr_array_sort(ranges, crs_range_compare); 789 for (i = 0; i < ranges->len; i++) { 790 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 791 792 if (free_base < used->base) { 793 crs_range_insert(free_ranges, free_base, used->base - 1); 794 } 795 796 free_base = used->limit + 1; 797 } 798 799 if (free_base < end) { 800 crs_range_insert(free_ranges, free_base, end); 801 } 802 803 g_ptr_array_set_size(ranges, 0); 804 for (i = 0; i < free_ranges->len; i++) { 805 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 806 } 807 808 g_ptr_array_free(free_ranges, true); 809 } 810 811 /* 812 * crs_range_merge - merges adjacent ranges in the given array. 813 * Array elements are deleted and replaced with the merged ranges. 814 */ 815 static void crs_range_merge(GPtrArray *range) 816 { 817 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 818 CrsRangeEntry *entry; 819 uint64_t range_base, range_limit; 820 int i; 821 822 if (!range->len) { 823 return; 824 } 825 826 g_ptr_array_sort(range, crs_range_compare); 827 828 entry = g_ptr_array_index(range, 0); 829 range_base = entry->base; 830 range_limit = entry->limit; 831 for (i = 1; i < range->len; i++) { 832 entry = g_ptr_array_index(range, i); 833 if (entry->base - 1 == range_limit) { 834 range_limit = entry->limit; 835 } else { 836 crs_range_insert(tmp, range_base, range_limit); 837 range_base = entry->base; 838 range_limit = entry->limit; 839 } 840 } 841 crs_range_insert(tmp, range_base, range_limit); 842 843 g_ptr_array_set_size(range, 0); 844 for (i = 0; i < tmp->len; i++) { 845 entry = g_ptr_array_index(tmp, i); 846 crs_range_insert(range, entry->base, entry->limit); 847 } 848 g_ptr_array_free(tmp, true); 849 } 850 851 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 852 { 853 Aml *crs = aml_resource_template(); 854 CrsRangeSet temp_range_set; 855 CrsRangeEntry *entry; 856 uint8_t max_bus = pci_bus_num(host->bus); 857 uint8_t type; 858 int devfn; 859 int i; 860 861 crs_range_set_init(&temp_range_set); 862 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 863 uint64_t range_base, range_limit; 864 PCIDevice *dev = host->bus->devices[devfn]; 865 866 if (!dev) { 867 continue; 868 } 869 870 for (i = 0; i < PCI_NUM_REGIONS; i++) { 871 PCIIORegion *r = &dev->io_regions[i]; 872 873 range_base = r->addr; 874 range_limit = r->addr + r->size - 1; 875 876 /* 877 * Work-around for old bioses 878 * that do not support multiple root buses 879 */ 880 if (!range_base || range_base > range_limit) { 881 continue; 882 } 883 884 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 885 crs_range_insert(temp_range_set.io_ranges, 886 range_base, range_limit); 887 } else { /* "memory" */ 888 crs_range_insert(temp_range_set.mem_ranges, 889 range_base, range_limit); 890 } 891 } 892 893 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 894 if (type == PCI_HEADER_TYPE_BRIDGE) { 895 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 896 if (subordinate > max_bus) { 897 max_bus = subordinate; 898 } 899 900 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 901 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 902 903 /* 904 * Work-around for old bioses 905 * that do not support multiple root buses 906 */ 907 if (range_base && range_base <= range_limit) { 908 crs_range_insert(temp_range_set.io_ranges, 909 range_base, range_limit); 910 } 911 912 range_base = 913 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 914 range_limit = 915 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 916 917 /* 918 * Work-around for old bioses 919 * that do not support multiple root buses 920 */ 921 if (range_base && range_base <= range_limit) { 922 uint64_t length = range_limit - range_base + 1; 923 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 924 crs_range_insert(temp_range_set.mem_ranges, 925 range_base, range_limit); 926 } else { 927 crs_range_insert(temp_range_set.mem_64bit_ranges, 928 range_base, range_limit); 929 } 930 } 931 932 range_base = 933 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 934 range_limit = 935 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 936 937 /* 938 * Work-around for old bioses 939 * that do not support multiple root buses 940 */ 941 if (range_base && range_base <= range_limit) { 942 uint64_t length = range_limit - range_base + 1; 943 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 944 crs_range_insert(temp_range_set.mem_ranges, 945 range_base, range_limit); 946 } else { 947 crs_range_insert(temp_range_set.mem_64bit_ranges, 948 range_base, range_limit); 949 } 950 } 951 } 952 } 953 954 crs_range_merge(temp_range_set.io_ranges); 955 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 956 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 957 aml_append(crs, 958 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 959 AML_POS_DECODE, AML_ENTIRE_RANGE, 960 0, entry->base, entry->limit, 0, 961 entry->limit - entry->base + 1)); 962 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 963 } 964 965 crs_range_merge(temp_range_set.mem_ranges); 966 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 967 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 968 aml_append(crs, 969 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 970 AML_MAX_FIXED, AML_NON_CACHEABLE, 971 AML_READ_WRITE, 972 0, entry->base, entry->limit, 0, 973 entry->limit - entry->base + 1)); 974 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 975 } 976 977 crs_range_merge(temp_range_set.mem_64bit_ranges); 978 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 979 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 980 aml_append(crs, 981 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 982 AML_MAX_FIXED, AML_NON_CACHEABLE, 983 AML_READ_WRITE, 984 0, entry->base, entry->limit, 0, 985 entry->limit - entry->base + 1)); 986 crs_range_insert(range_set->mem_64bit_ranges, 987 entry->base, entry->limit); 988 } 989 990 crs_range_set_free(&temp_range_set); 991 992 aml_append(crs, 993 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 994 0, 995 pci_bus_num(host->bus), 996 max_bus, 997 0, 998 max_bus - pci_bus_num(host->bus) + 1)); 999 1000 return crs; 1001 } 1002 1003 static void build_hpet_aml(Aml *table) 1004 { 1005 Aml *crs; 1006 Aml *field; 1007 Aml *method; 1008 Aml *if_ctx; 1009 Aml *scope = aml_scope("_SB"); 1010 Aml *dev = aml_device("HPET"); 1011 Aml *zero = aml_int(0); 1012 Aml *id = aml_local(0); 1013 Aml *period = aml_local(1); 1014 1015 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1016 aml_append(dev, aml_name_decl("_UID", zero)); 1017 1018 aml_append(dev, 1019 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1020 HPET_LEN)); 1021 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1022 aml_append(field, aml_named_field("VEND", 32)); 1023 aml_append(field, aml_named_field("PRD", 32)); 1024 aml_append(dev, field); 1025 1026 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1027 aml_append(method, aml_store(aml_name("VEND"), id)); 1028 aml_append(method, aml_store(aml_name("PRD"), period)); 1029 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1030 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1031 aml_equal(id, aml_int(0xffff)))); 1032 { 1033 aml_append(if_ctx, aml_return(zero)); 1034 } 1035 aml_append(method, if_ctx); 1036 1037 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1038 aml_lgreater(period, aml_int(100000000)))); 1039 { 1040 aml_append(if_ctx, aml_return(zero)); 1041 } 1042 aml_append(method, if_ctx); 1043 1044 aml_append(method, aml_return(aml_int(0x0F))); 1045 aml_append(dev, method); 1046 1047 crs = aml_resource_template(); 1048 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1049 aml_append(dev, aml_name_decl("_CRS", crs)); 1050 1051 aml_append(scope, dev); 1052 aml_append(table, scope); 1053 } 1054 1055 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1056 { 1057 Aml *dev, *fdi; 1058 uint8_t maxc, maxh, maxs; 1059 1060 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1061 1062 dev = aml_device("FLP%c", 'A' + idx); 1063 1064 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1065 1066 fdi = aml_package(16); 1067 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1068 aml_append(fdi, 1069 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1070 /* 1071 * the values below are the limits of the drive, and are thus independent 1072 * of the inserted media 1073 */ 1074 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1075 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1076 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1077 /* 1078 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1079 * the drive type, so shall we 1080 */ 1081 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1082 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1083 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1084 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1085 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1086 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1087 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1088 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1089 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1090 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1091 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1092 1093 aml_append(dev, aml_name_decl("_FDI", fdi)); 1094 return dev; 1095 } 1096 1097 static Aml *build_fdc_device_aml(ISADevice *fdc) 1098 { 1099 int i; 1100 Aml *dev; 1101 Aml *crs; 1102 1103 #define ACPI_FDE_MAX_FD 4 1104 uint32_t fde_buf[5] = { 1105 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1106 cpu_to_le32(2) /* tape presence (2 == never present) */ 1107 }; 1108 1109 dev = aml_device("FDC0"); 1110 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1111 1112 crs = aml_resource_template(); 1113 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1114 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1115 aml_append(crs, aml_irq_no_flags(6)); 1116 aml_append(crs, 1117 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1118 aml_append(dev, aml_name_decl("_CRS", crs)); 1119 1120 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1121 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1122 1123 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1124 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1125 aml_append(dev, build_fdinfo_aml(i, type)); 1126 } 1127 } 1128 aml_append(dev, aml_name_decl("_FDE", 1129 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1130 1131 return dev; 1132 } 1133 1134 static Aml *build_rtc_device_aml(void) 1135 { 1136 Aml *dev; 1137 Aml *crs; 1138 1139 dev = aml_device("RTC"); 1140 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1141 crs = aml_resource_template(); 1142 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1143 aml_append(crs, aml_irq_no_flags(8)); 1144 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1145 aml_append(dev, aml_name_decl("_CRS", crs)); 1146 1147 return dev; 1148 } 1149 1150 static Aml *build_kbd_device_aml(void) 1151 { 1152 Aml *dev; 1153 Aml *crs; 1154 Aml *method; 1155 1156 dev = aml_device("KBD"); 1157 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1158 1159 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1160 aml_append(method, aml_return(aml_int(0x0f))); 1161 aml_append(dev, method); 1162 1163 crs = aml_resource_template(); 1164 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1165 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1166 aml_append(crs, aml_irq_no_flags(1)); 1167 aml_append(dev, aml_name_decl("_CRS", crs)); 1168 1169 return dev; 1170 } 1171 1172 static Aml *build_mouse_device_aml(void) 1173 { 1174 Aml *dev; 1175 Aml *crs; 1176 Aml *method; 1177 1178 dev = aml_device("MOU"); 1179 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1180 1181 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1182 aml_append(method, aml_return(aml_int(0x0f))); 1183 aml_append(dev, method); 1184 1185 crs = aml_resource_template(); 1186 aml_append(crs, aml_irq_no_flags(12)); 1187 aml_append(dev, aml_name_decl("_CRS", crs)); 1188 1189 return dev; 1190 } 1191 1192 static Aml *build_lpt_device_aml(void) 1193 { 1194 Aml *dev; 1195 Aml *crs; 1196 Aml *method; 1197 Aml *if_ctx; 1198 Aml *else_ctx; 1199 Aml *zero = aml_int(0); 1200 Aml *is_present = aml_local(0); 1201 1202 dev = aml_device("LPT"); 1203 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1204 1205 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1206 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1207 if_ctx = aml_if(aml_equal(is_present, zero)); 1208 { 1209 aml_append(if_ctx, aml_return(aml_int(0x00))); 1210 } 1211 aml_append(method, if_ctx); 1212 else_ctx = aml_else(); 1213 { 1214 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1215 } 1216 aml_append(method, else_ctx); 1217 aml_append(dev, method); 1218 1219 crs = aml_resource_template(); 1220 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1221 aml_append(crs, aml_irq_no_flags(7)); 1222 aml_append(dev, aml_name_decl("_CRS", crs)); 1223 1224 return dev; 1225 } 1226 1227 static Aml *build_com_device_aml(uint8_t uid) 1228 { 1229 Aml *dev; 1230 Aml *crs; 1231 Aml *method; 1232 Aml *if_ctx; 1233 Aml *else_ctx; 1234 Aml *zero = aml_int(0); 1235 Aml *is_present = aml_local(0); 1236 const char *enabled_field = "CAEN"; 1237 uint8_t irq = 4; 1238 uint16_t io_port = 0x03F8; 1239 1240 assert(uid == 1 || uid == 2); 1241 if (uid == 2) { 1242 enabled_field = "CBEN"; 1243 irq = 3; 1244 io_port = 0x02F8; 1245 } 1246 1247 dev = aml_device("COM%d", uid); 1248 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1249 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1250 1251 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1252 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1253 if_ctx = aml_if(aml_equal(is_present, zero)); 1254 { 1255 aml_append(if_ctx, aml_return(aml_int(0x00))); 1256 } 1257 aml_append(method, if_ctx); 1258 else_ctx = aml_else(); 1259 { 1260 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1261 } 1262 aml_append(method, else_ctx); 1263 aml_append(dev, method); 1264 1265 crs = aml_resource_template(); 1266 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1267 aml_append(crs, aml_irq_no_flags(irq)); 1268 aml_append(dev, aml_name_decl("_CRS", crs)); 1269 1270 return dev; 1271 } 1272 1273 static void build_isa_devices_aml(Aml *table) 1274 { 1275 ISADevice *fdc = pc_find_fdc0(); 1276 bool ambiguous; 1277 1278 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1279 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1280 1281 aml_append(scope, build_rtc_device_aml()); 1282 aml_append(scope, build_kbd_device_aml()); 1283 aml_append(scope, build_mouse_device_aml()); 1284 if (fdc) { 1285 aml_append(scope, build_fdc_device_aml(fdc)); 1286 } 1287 aml_append(scope, build_lpt_device_aml()); 1288 aml_append(scope, build_com_device_aml(1)); 1289 aml_append(scope, build_com_device_aml(2)); 1290 1291 if (ambiguous) { 1292 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1293 } else if (!obj) { 1294 error_report("No ISA bus, unable to define IPMI ACPI data"); 1295 } else { 1296 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 1297 } 1298 1299 aml_append(table, scope); 1300 } 1301 1302 static void build_dbg_aml(Aml *table) 1303 { 1304 Aml *field; 1305 Aml *method; 1306 Aml *while_ctx; 1307 Aml *scope = aml_scope("\\"); 1308 Aml *buf = aml_local(0); 1309 Aml *len = aml_local(1); 1310 Aml *idx = aml_local(2); 1311 1312 aml_append(scope, 1313 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1314 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1315 aml_append(field, aml_named_field("DBGB", 8)); 1316 aml_append(scope, field); 1317 1318 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1319 1320 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1321 aml_append(method, aml_to_buffer(buf, buf)); 1322 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1323 aml_append(method, aml_store(aml_int(0), idx)); 1324 1325 while_ctx = aml_while(aml_lless(idx, len)); 1326 aml_append(while_ctx, 1327 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1328 aml_append(while_ctx, aml_increment(idx)); 1329 aml_append(method, while_ctx); 1330 1331 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1332 aml_append(scope, method); 1333 1334 aml_append(table, scope); 1335 } 1336 1337 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1338 { 1339 Aml *dev; 1340 Aml *crs; 1341 Aml *method; 1342 uint32_t irqs[] = {5, 10, 11}; 1343 1344 dev = aml_device("%s", name); 1345 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1346 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1347 1348 crs = aml_resource_template(); 1349 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1350 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1351 aml_append(dev, aml_name_decl("_PRS", crs)); 1352 1353 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1354 aml_append(method, aml_return(aml_call1("IQST", reg))); 1355 aml_append(dev, method); 1356 1357 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1358 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1359 aml_append(dev, method); 1360 1361 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1362 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1363 aml_append(dev, method); 1364 1365 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1366 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1367 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1368 aml_append(dev, method); 1369 1370 return dev; 1371 } 1372 1373 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1374 { 1375 Aml *dev; 1376 Aml *crs; 1377 Aml *method; 1378 uint32_t irqs; 1379 1380 dev = aml_device("%s", name); 1381 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1382 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1383 1384 crs = aml_resource_template(); 1385 irqs = gsi; 1386 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1387 AML_SHARED, &irqs, 1)); 1388 aml_append(dev, aml_name_decl("_PRS", crs)); 1389 1390 aml_append(dev, aml_name_decl("_CRS", crs)); 1391 1392 /* 1393 * _DIS can be no-op because the interrupt cannot be disabled. 1394 */ 1395 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1396 aml_append(dev, method); 1397 1398 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1399 aml_append(dev, method); 1400 1401 return dev; 1402 } 1403 1404 /* _CRS method - get current settings */ 1405 static Aml *build_iqcr_method(bool is_piix4) 1406 { 1407 Aml *if_ctx; 1408 uint32_t irqs; 1409 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1410 Aml *crs = aml_resource_template(); 1411 1412 irqs = 0; 1413 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1414 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1415 aml_append(method, aml_name_decl("PRR0", crs)); 1416 1417 aml_append(method, 1418 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1419 1420 if (is_piix4) { 1421 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1422 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1423 aml_append(method, if_ctx); 1424 } else { 1425 aml_append(method, 1426 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1427 aml_name("PRRI"))); 1428 } 1429 1430 aml_append(method, aml_return(aml_name("PRR0"))); 1431 return method; 1432 } 1433 1434 /* _STA method - get status */ 1435 static Aml *build_irq_status_method(void) 1436 { 1437 Aml *if_ctx; 1438 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1439 1440 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1441 aml_append(if_ctx, aml_return(aml_int(0x09))); 1442 aml_append(method, if_ctx); 1443 aml_append(method, aml_return(aml_int(0x0B))); 1444 return method; 1445 } 1446 1447 static void build_piix4_pci0_int(Aml *table) 1448 { 1449 Aml *dev; 1450 Aml *crs; 1451 Aml *field; 1452 Aml *method; 1453 uint32_t irqs; 1454 Aml *sb_scope = aml_scope("_SB"); 1455 Aml *pci0_scope = aml_scope("PCI0"); 1456 1457 aml_append(pci0_scope, build_prt(true)); 1458 aml_append(sb_scope, pci0_scope); 1459 1460 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1461 aml_append(field, aml_named_field("PRQ0", 8)); 1462 aml_append(field, aml_named_field("PRQ1", 8)); 1463 aml_append(field, aml_named_field("PRQ2", 8)); 1464 aml_append(field, aml_named_field("PRQ3", 8)); 1465 aml_append(sb_scope, field); 1466 1467 aml_append(sb_scope, build_irq_status_method()); 1468 aml_append(sb_scope, build_iqcr_method(true)); 1469 1470 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1471 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1472 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1473 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1474 1475 dev = aml_device("LNKS"); 1476 { 1477 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1478 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1479 1480 crs = aml_resource_template(); 1481 irqs = 9; 1482 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1483 AML_ACTIVE_HIGH, AML_SHARED, 1484 &irqs, 1)); 1485 aml_append(dev, aml_name_decl("_PRS", crs)); 1486 1487 /* The SCI cannot be disabled and is always attached to GSI 9, 1488 * so these are no-ops. We only need this link to override the 1489 * polarity to active high and match the content of the MADT. 1490 */ 1491 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1492 aml_append(method, aml_return(aml_int(0x0b))); 1493 aml_append(dev, method); 1494 1495 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1496 aml_append(dev, method); 1497 1498 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1499 aml_append(method, aml_return(aml_name("_PRS"))); 1500 aml_append(dev, method); 1501 1502 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1503 aml_append(dev, method); 1504 } 1505 aml_append(sb_scope, dev); 1506 1507 aml_append(table, sb_scope); 1508 } 1509 1510 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1511 { 1512 int i; 1513 int head; 1514 Aml *pkg; 1515 char base = name[3] < 'E' ? 'A' : 'E'; 1516 char *s = g_strdup(name); 1517 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1518 1519 assert(strlen(s) == 4); 1520 1521 head = name[3] - base; 1522 for (i = 0; i < 4; i++) { 1523 if (head + i > 3) { 1524 head = i * -1; 1525 } 1526 s[3] = base + head + i; 1527 pkg = aml_package(4); 1528 aml_append(pkg, a_nr); 1529 aml_append(pkg, aml_int(i)); 1530 aml_append(pkg, aml_name("%s", s)); 1531 aml_append(pkg, aml_int(0)); 1532 aml_append(ctx, pkg); 1533 } 1534 g_free(s); 1535 } 1536 1537 static Aml *build_q35_routing_table(const char *str) 1538 { 1539 int i; 1540 Aml *pkg; 1541 char *name = g_strdup_printf("%s ", str); 1542 1543 pkg = aml_package(128); 1544 for (i = 0; i < 0x18; i++) { 1545 name[3] = 'E' + (i & 0x3); 1546 append_q35_prt_entry(pkg, i, name); 1547 } 1548 1549 name[3] = 'E'; 1550 append_q35_prt_entry(pkg, 0x18, name); 1551 1552 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1553 for (i = 0x0019; i < 0x1e; i++) { 1554 name[3] = 'A'; 1555 append_q35_prt_entry(pkg, i, name); 1556 } 1557 1558 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1559 name[3] = 'E'; 1560 append_q35_prt_entry(pkg, 0x1e, name); 1561 name[3] = 'A'; 1562 append_q35_prt_entry(pkg, 0x1f, name); 1563 1564 g_free(name); 1565 return pkg; 1566 } 1567 1568 static void build_q35_pci0_int(Aml *table) 1569 { 1570 Aml *field; 1571 Aml *method; 1572 Aml *sb_scope = aml_scope("_SB"); 1573 Aml *pci0_scope = aml_scope("PCI0"); 1574 1575 /* Zero => PIC mode, One => APIC Mode */ 1576 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1577 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1578 { 1579 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1580 } 1581 aml_append(table, method); 1582 1583 aml_append(pci0_scope, 1584 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1585 aml_append(pci0_scope, 1586 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1587 1588 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1589 { 1590 Aml *if_ctx; 1591 Aml *else_ctx; 1592 1593 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1594 section 6.2.8.1 */ 1595 /* Note: we provide the same info as the PCI routing 1596 table of the Bochs BIOS */ 1597 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1598 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1599 aml_append(method, if_ctx); 1600 else_ctx = aml_else(); 1601 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1602 aml_append(method, else_ctx); 1603 } 1604 aml_append(pci0_scope, method); 1605 aml_append(sb_scope, pci0_scope); 1606 1607 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1608 aml_append(field, aml_named_field("PRQA", 8)); 1609 aml_append(field, aml_named_field("PRQB", 8)); 1610 aml_append(field, aml_named_field("PRQC", 8)); 1611 aml_append(field, aml_named_field("PRQD", 8)); 1612 aml_append(field, aml_reserved_field(0x20)); 1613 aml_append(field, aml_named_field("PRQE", 8)); 1614 aml_append(field, aml_named_field("PRQF", 8)); 1615 aml_append(field, aml_named_field("PRQG", 8)); 1616 aml_append(field, aml_named_field("PRQH", 8)); 1617 aml_append(sb_scope, field); 1618 1619 aml_append(sb_scope, build_irq_status_method()); 1620 aml_append(sb_scope, build_iqcr_method(false)); 1621 1622 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1623 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1624 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1625 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1626 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1627 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1628 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1629 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1630 1631 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1632 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1633 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1634 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1635 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1636 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1637 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1638 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1639 1640 aml_append(table, sb_scope); 1641 } 1642 1643 static void build_q35_isa_bridge(Aml *table) 1644 { 1645 Aml *dev; 1646 Aml *scope; 1647 Aml *field; 1648 1649 scope = aml_scope("_SB.PCI0"); 1650 dev = aml_device("ISA"); 1651 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1652 1653 /* ICH9 PCI to ISA irq remapping */ 1654 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1655 aml_int(0x60), 0x0C)); 1656 1657 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1658 aml_int(0x80), 0x02)); 1659 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1660 aml_append(field, aml_named_field("COMA", 3)); 1661 aml_append(field, aml_reserved_field(1)); 1662 aml_append(field, aml_named_field("COMB", 3)); 1663 aml_append(field, aml_reserved_field(1)); 1664 aml_append(field, aml_named_field("LPTD", 2)); 1665 aml_append(dev, field); 1666 1667 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1668 aml_int(0x82), 0x02)); 1669 /* enable bits */ 1670 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1671 aml_append(field, aml_named_field("CAEN", 1)); 1672 aml_append(field, aml_named_field("CBEN", 1)); 1673 aml_append(field, aml_named_field("LPEN", 1)); 1674 aml_append(dev, field); 1675 1676 aml_append(scope, dev); 1677 aml_append(table, scope); 1678 } 1679 1680 static void build_piix4_pm(Aml *table) 1681 { 1682 Aml *dev; 1683 Aml *scope; 1684 1685 scope = aml_scope("_SB.PCI0"); 1686 dev = aml_device("PX13"); 1687 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1688 1689 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1690 aml_int(0x00), 0xff)); 1691 aml_append(scope, dev); 1692 aml_append(table, scope); 1693 } 1694 1695 static void build_piix4_isa_bridge(Aml *table) 1696 { 1697 Aml *dev; 1698 Aml *scope; 1699 Aml *field; 1700 1701 scope = aml_scope("_SB.PCI0"); 1702 dev = aml_device("ISA"); 1703 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1704 1705 /* PIIX PCI to ISA irq remapping */ 1706 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1707 aml_int(0x60), 0x04)); 1708 /* enable bits */ 1709 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1710 /* Offset(0x5f),, 7, */ 1711 aml_append(field, aml_reserved_field(0x2f8)); 1712 aml_append(field, aml_reserved_field(7)); 1713 aml_append(field, aml_named_field("LPEN", 1)); 1714 /* Offset(0x67),, 3, */ 1715 aml_append(field, aml_reserved_field(0x38)); 1716 aml_append(field, aml_reserved_field(3)); 1717 aml_append(field, aml_named_field("CAEN", 1)); 1718 aml_append(field, aml_reserved_field(3)); 1719 aml_append(field, aml_named_field("CBEN", 1)); 1720 aml_append(dev, field); 1721 1722 aml_append(scope, dev); 1723 aml_append(table, scope); 1724 } 1725 1726 static void build_piix4_pci_hotplug(Aml *table) 1727 { 1728 Aml *scope; 1729 Aml *field; 1730 Aml *method; 1731 1732 scope = aml_scope("_SB.PCI0"); 1733 1734 aml_append(scope, 1735 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1736 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1737 aml_append(field, aml_named_field("PCIU", 32)); 1738 aml_append(field, aml_named_field("PCID", 32)); 1739 aml_append(scope, field); 1740 1741 aml_append(scope, 1742 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1743 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1744 aml_append(field, aml_named_field("B0EJ", 32)); 1745 aml_append(scope, field); 1746 1747 aml_append(scope, 1748 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1749 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1750 aml_append(field, aml_named_field("BNUM", 32)); 1751 aml_append(scope, field); 1752 1753 aml_append(scope, aml_mutex("BLCK", 0)); 1754 1755 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1756 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1757 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1758 aml_append(method, 1759 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1760 aml_append(method, aml_release(aml_name("BLCK"))); 1761 aml_append(method, aml_return(aml_int(0))); 1762 aml_append(scope, method); 1763 1764 aml_append(table, scope); 1765 } 1766 1767 static Aml *build_q35_osc_method(void) 1768 { 1769 Aml *if_ctx; 1770 Aml *if_ctx2; 1771 Aml *else_ctx; 1772 Aml *method; 1773 Aml *a_cwd1 = aml_name("CDW1"); 1774 Aml *a_ctrl = aml_local(0); 1775 1776 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1777 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1778 1779 if_ctx = aml_if(aml_equal( 1780 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1781 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1782 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1783 1784 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1785 1786 /* 1787 * Always allow native PME, AER (no dependencies) 1788 * Allow SHPC (PCI bridges can have SHPC controller) 1789 */ 1790 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1791 1792 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1793 /* Unknown revision */ 1794 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1795 aml_append(if_ctx, if_ctx2); 1796 1797 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1798 /* Capabilities bits were masked */ 1799 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1800 aml_append(if_ctx, if_ctx2); 1801 1802 /* Update DWORD3 in the buffer */ 1803 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1804 aml_append(method, if_ctx); 1805 1806 else_ctx = aml_else(); 1807 /* Unrecognized UUID */ 1808 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1809 aml_append(method, else_ctx); 1810 1811 aml_append(method, aml_return(aml_arg(3))); 1812 return method; 1813 } 1814 1815 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1816 { 1817 Aml *scope = aml_scope("_SB.PCI0"); 1818 Aml *dev = aml_device("SMB0"); 1819 1820 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1821 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1822 aml_append(scope, dev); 1823 aml_append(table, scope); 1824 } 1825 1826 static void 1827 build_dsdt(GArray *table_data, BIOSLinker *linker, 1828 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1829 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1830 { 1831 CrsRangeEntry *entry; 1832 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1833 CrsRangeSet crs_range_set; 1834 PCMachineState *pcms = PC_MACHINE(machine); 1835 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1836 X86MachineState *x86ms = X86_MACHINE(machine); 1837 AcpiMcfgInfo mcfg; 1838 uint32_t nr_mem = machine->ram_slots; 1839 int root_bus_limit = 0xFF; 1840 PCIBus *bus = NULL; 1841 TPMIf *tpm = tpm_find(); 1842 int i; 1843 1844 dsdt = init_aml_allocator(); 1845 1846 /* Reserve space for header */ 1847 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1848 1849 build_dbg_aml(dsdt); 1850 if (misc->is_piix4) { 1851 sb_scope = aml_scope("_SB"); 1852 dev = aml_device("PCI0"); 1853 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1854 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1855 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1856 aml_append(sb_scope, dev); 1857 aml_append(dsdt, sb_scope); 1858 1859 build_hpet_aml(dsdt); 1860 build_piix4_pm(dsdt); 1861 build_piix4_isa_bridge(dsdt); 1862 build_isa_devices_aml(dsdt); 1863 build_piix4_pci_hotplug(dsdt); 1864 build_piix4_pci0_int(dsdt); 1865 } else { 1866 sb_scope = aml_scope("_SB"); 1867 dev = aml_device("PCI0"); 1868 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1869 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1870 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1871 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1872 aml_append(dev, build_q35_osc_method()); 1873 aml_append(sb_scope, dev); 1874 aml_append(dsdt, sb_scope); 1875 1876 build_hpet_aml(dsdt); 1877 build_q35_isa_bridge(dsdt); 1878 build_isa_devices_aml(dsdt); 1879 build_q35_pci0_int(dsdt); 1880 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1881 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1882 } 1883 } 1884 1885 if (pcmc->legacy_cpu_hotplug) { 1886 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1887 } else { 1888 CPUHotplugFeatures opts = { 1889 .acpi_1_compatible = true, .has_legacy_cphp = true 1890 }; 1891 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1892 "\\_SB.PCI0", "\\_GPE._E02"); 1893 } 1894 1895 if (pcms->memhp_io_base && nr_mem) { 1896 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1897 "\\_GPE._E03", AML_SYSTEM_IO, 1898 pcms->memhp_io_base); 1899 } 1900 1901 scope = aml_scope("_GPE"); 1902 { 1903 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1904 1905 if (misc->is_piix4) { 1906 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1907 aml_append(method, 1908 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1909 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1910 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1911 aml_append(scope, method); 1912 } 1913 1914 if (machine->nvdimms_state->is_enabled) { 1915 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1916 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1917 aml_int(0x80))); 1918 aml_append(scope, method); 1919 } 1920 } 1921 aml_append(dsdt, scope); 1922 1923 crs_range_set_init(&crs_range_set); 1924 bus = PC_MACHINE(machine)->bus; 1925 if (bus) { 1926 QLIST_FOREACH(bus, &bus->child, sibling) { 1927 uint8_t bus_num = pci_bus_num(bus); 1928 uint8_t numa_node = pci_bus_numa_node(bus); 1929 1930 /* look only for expander root buses */ 1931 if (!pci_bus_is_root(bus)) { 1932 continue; 1933 } 1934 1935 if (bus_num < root_bus_limit) { 1936 root_bus_limit = bus_num - 1; 1937 } 1938 1939 scope = aml_scope("\\_SB"); 1940 dev = aml_device("PC%.02X", bus_num); 1941 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1942 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1943 if (pci_bus_is_express(bus)) { 1944 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1945 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1946 aml_append(dev, build_q35_osc_method()); 1947 } else { 1948 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1949 } 1950 1951 if (numa_node != NUMA_NODE_UNASSIGNED) { 1952 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1953 } 1954 1955 aml_append(dev, build_prt(false)); 1956 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1957 aml_append(dev, aml_name_decl("_CRS", crs)); 1958 aml_append(scope, dev); 1959 aml_append(dsdt, scope); 1960 } 1961 } 1962 1963 /* 1964 * At this point crs_range_set has all the ranges used by pci 1965 * busses *other* than PCI0. These ranges will be excluded from 1966 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1967 * too. 1968 */ 1969 if (acpi_get_mcfg(&mcfg)) { 1970 crs_range_insert(crs_range_set.mem_ranges, 1971 mcfg.base, mcfg.base + mcfg.size - 1); 1972 } 1973 1974 scope = aml_scope("\\_SB.PCI0"); 1975 /* build PCI0._CRS */ 1976 crs = aml_resource_template(); 1977 aml_append(crs, 1978 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1979 0x0000, 0x0, root_bus_limit, 1980 0x0000, root_bus_limit + 1)); 1981 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1982 1983 aml_append(crs, 1984 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1985 AML_POS_DECODE, AML_ENTIRE_RANGE, 1986 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1987 1988 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1989 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1990 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1991 aml_append(crs, 1992 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1993 AML_POS_DECODE, AML_ENTIRE_RANGE, 1994 0x0000, entry->base, entry->limit, 1995 0x0000, entry->limit - entry->base + 1)); 1996 } 1997 1998 aml_append(crs, 1999 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2000 AML_CACHEABLE, AML_READ_WRITE, 2001 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2002 2003 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 2004 range_lob(pci_hole), 2005 range_upb(pci_hole)); 2006 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 2007 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 2008 aml_append(crs, 2009 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2010 AML_NON_CACHEABLE, AML_READ_WRITE, 2011 0, entry->base, entry->limit, 2012 0, entry->limit - entry->base + 1)); 2013 } 2014 2015 if (!range_is_empty(pci_hole64)) { 2016 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 2017 range_lob(pci_hole64), 2018 range_upb(pci_hole64)); 2019 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 2020 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 2021 aml_append(crs, 2022 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 2023 AML_MAX_FIXED, 2024 AML_CACHEABLE, AML_READ_WRITE, 2025 0, entry->base, entry->limit, 2026 0, entry->limit - entry->base + 1)); 2027 } 2028 } 2029 2030 if (TPM_IS_TIS_ISA(tpm_find())) { 2031 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2032 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2033 } 2034 aml_append(scope, aml_name_decl("_CRS", crs)); 2035 2036 /* reserve GPE0 block resources */ 2037 dev = aml_device("GPE0"); 2038 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2039 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2040 /* device present, functioning, decoding, not shown in UI */ 2041 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2042 crs = aml_resource_template(); 2043 aml_append(crs, 2044 aml_io( 2045 AML_DECODE16, 2046 pm->fadt.gpe0_blk.address, 2047 pm->fadt.gpe0_blk.address, 2048 1, 2049 pm->fadt.gpe0_blk.bit_width / 8) 2050 ); 2051 aml_append(dev, aml_name_decl("_CRS", crs)); 2052 aml_append(scope, dev); 2053 2054 crs_range_set_free(&crs_range_set); 2055 2056 /* reserve PCIHP resources */ 2057 if (pm->pcihp_io_len) { 2058 dev = aml_device("PHPR"); 2059 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2060 aml_append(dev, 2061 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2062 /* device present, functioning, decoding, not shown in UI */ 2063 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2064 crs = aml_resource_template(); 2065 aml_append(crs, 2066 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2067 pm->pcihp_io_len) 2068 ); 2069 aml_append(dev, aml_name_decl("_CRS", crs)); 2070 aml_append(scope, dev); 2071 } 2072 aml_append(dsdt, scope); 2073 2074 /* create S3_ / S4_ / S5_ packages if necessary */ 2075 scope = aml_scope("\\"); 2076 if (!pm->s3_disabled) { 2077 pkg = aml_package(4); 2078 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2079 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2080 aml_append(pkg, aml_int(0)); /* reserved */ 2081 aml_append(pkg, aml_int(0)); /* reserved */ 2082 aml_append(scope, aml_name_decl("_S3", pkg)); 2083 } 2084 2085 if (!pm->s4_disabled) { 2086 pkg = aml_package(4); 2087 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2088 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2089 aml_append(pkg, aml_int(pm->s4_val)); 2090 aml_append(pkg, aml_int(0)); /* reserved */ 2091 aml_append(pkg, aml_int(0)); /* reserved */ 2092 aml_append(scope, aml_name_decl("_S4", pkg)); 2093 } 2094 2095 pkg = aml_package(4); 2096 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2097 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2098 aml_append(pkg, aml_int(0)); /* reserved */ 2099 aml_append(pkg, aml_int(0)); /* reserved */ 2100 aml_append(scope, aml_name_decl("_S5", pkg)); 2101 aml_append(dsdt, scope); 2102 2103 /* create fw_cfg node, unconditionally */ 2104 { 2105 /* when using port i/o, the 8-bit data register *always* overlaps 2106 * with half of the 16-bit control register. Hence, the total size 2107 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2108 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2109 uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg), 2110 "dma_enabled", NULL) ? 2111 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2112 FW_CFG_CTL_SIZE; 2113 2114 scope = aml_scope("\\_SB.PCI0"); 2115 dev = aml_device("FWCF"); 2116 2117 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2118 2119 /* device present, functioning, decoding, not shown in UI */ 2120 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2121 2122 crs = aml_resource_template(); 2123 aml_append(crs, 2124 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2125 ); 2126 aml_append(dev, aml_name_decl("_CRS", crs)); 2127 2128 aml_append(scope, dev); 2129 aml_append(dsdt, scope); 2130 } 2131 2132 if (misc->applesmc_io_base) { 2133 scope = aml_scope("\\_SB.PCI0.ISA"); 2134 dev = aml_device("SMC"); 2135 2136 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2137 /* device present, functioning, decoding, not shown in UI */ 2138 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2139 2140 crs = aml_resource_template(); 2141 aml_append(crs, 2142 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2143 0x01, APPLESMC_MAX_DATA_LENGTH) 2144 ); 2145 aml_append(crs, aml_irq_no_flags(6)); 2146 aml_append(dev, aml_name_decl("_CRS", crs)); 2147 2148 aml_append(scope, dev); 2149 aml_append(dsdt, scope); 2150 } 2151 2152 if (misc->pvpanic_port) { 2153 scope = aml_scope("\\_SB.PCI0.ISA"); 2154 2155 dev = aml_device("PEVT"); 2156 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2157 2158 crs = aml_resource_template(); 2159 aml_append(crs, 2160 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2161 ); 2162 aml_append(dev, aml_name_decl("_CRS", crs)); 2163 2164 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2165 aml_int(misc->pvpanic_port), 1)); 2166 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2167 aml_append(field, aml_named_field("PEPT", 8)); 2168 aml_append(dev, field); 2169 2170 /* device present, functioning, decoding, shown in UI */ 2171 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2172 2173 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2174 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2175 aml_append(method, aml_return(aml_local(0))); 2176 aml_append(dev, method); 2177 2178 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2179 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2180 aml_append(dev, method); 2181 2182 aml_append(scope, dev); 2183 aml_append(dsdt, scope); 2184 } 2185 2186 sb_scope = aml_scope("\\_SB"); 2187 { 2188 Object *pci_host; 2189 PCIBus *bus = NULL; 2190 2191 pci_host = acpi_get_i386_pci_host(); 2192 if (pci_host) { 2193 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2194 } 2195 2196 if (bus) { 2197 Aml *scope = aml_scope("PCI0"); 2198 /* Scan all PCI buses. Generate tables to support hotplug. */ 2199 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2200 2201 if (TPM_IS_TIS_ISA(tpm)) { 2202 if (misc->tpm_version == TPM_VERSION_2_0) { 2203 dev = aml_device("TPM"); 2204 aml_append(dev, aml_name_decl("_HID", 2205 aml_string("MSFT0101"))); 2206 } else { 2207 dev = aml_device("ISA.TPM"); 2208 aml_append(dev, aml_name_decl("_HID", 2209 aml_eisaid("PNP0C31"))); 2210 } 2211 2212 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2213 crs = aml_resource_template(); 2214 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2215 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2216 /* 2217 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2218 Rewrite to take IRQ from TPM device model and 2219 fix default IRQ value there to use some unused IRQ 2220 */ 2221 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2222 aml_append(dev, aml_name_decl("_CRS", crs)); 2223 2224 tpm_build_ppi_acpi(tpm, dev); 2225 2226 aml_append(scope, dev); 2227 } 2228 2229 aml_append(sb_scope, scope); 2230 } 2231 } 2232 2233 if (TPM_IS_CRB(tpm)) { 2234 dev = aml_device("TPM"); 2235 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 2236 crs = aml_resource_template(); 2237 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 2238 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 2239 aml_append(dev, aml_name_decl("_CRS", crs)); 2240 2241 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 2242 aml_append(method, aml_return(aml_int(0x0f))); 2243 aml_append(dev, method); 2244 2245 tpm_build_ppi_acpi(tpm, dev); 2246 2247 aml_append(sb_scope, dev); 2248 } 2249 2250 aml_append(dsdt, sb_scope); 2251 2252 /* copy AML table into ACPI tables blob and patch header there */ 2253 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2254 build_header(linker, table_data, 2255 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2256 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2257 free_aml_allocator(); 2258 } 2259 2260 static void 2261 build_hpet(GArray *table_data, BIOSLinker *linker) 2262 { 2263 Acpi20Hpet *hpet; 2264 2265 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2266 /* Note timer_block_id value must be kept in sync with value advertised by 2267 * emulated hpet 2268 */ 2269 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2270 hpet->addr.address = cpu_to_le64(HPET_BASE); 2271 build_header(linker, table_data, 2272 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2273 } 2274 2275 static void 2276 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2277 { 2278 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2279 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2280 unsigned log_addr_offset = 2281 (char *)&tcpa->log_area_start_address - table_data->data; 2282 2283 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2284 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2285 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2286 2287 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2288 false /* high memory */); 2289 2290 /* log area start address to be filled by Guest linker */ 2291 bios_linker_loader_add_pointer(linker, 2292 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2293 ACPI_BUILD_TPMLOG_FILE, 0); 2294 2295 build_header(linker, table_data, 2296 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2297 } 2298 2299 static void 2300 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2301 { 2302 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2303 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address); 2304 unsigned log_addr_offset = 2305 (char *)&tpm2_ptr->log_area_start_address - table_data->data; 2306 2307 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2308 if (TPM_IS_TIS_ISA(tpm_find())) { 2309 tpm2_ptr->control_area_address = cpu_to_le64(0); 2310 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2311 } else if (TPM_IS_CRB(tpm_find())) { 2312 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL); 2313 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB); 2314 } else { 2315 g_warn_if_reached(); 2316 } 2317 2318 tpm2_ptr->log_area_minimum_length = 2319 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2320 2321 /* log area start address to be filled by Guest linker */ 2322 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2323 log_addr_offset, log_addr_size, 2324 ACPI_BUILD_TPMLOG_FILE, 0); 2325 build_header(linker, table_data, 2326 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2327 } 2328 2329 #define HOLE_640K_START (640 * KiB) 2330 #define HOLE_640K_END (1 * MiB) 2331 2332 static void 2333 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2334 { 2335 AcpiSystemResourceAffinityTable *srat; 2336 AcpiSratMemoryAffinity *numamem; 2337 2338 int i; 2339 int srat_start, numa_start, slots; 2340 uint64_t mem_len, mem_base, next_base; 2341 MachineClass *mc = MACHINE_GET_CLASS(machine); 2342 X86MachineState *x86ms = X86_MACHINE(machine); 2343 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2344 PCMachineState *pcms = PC_MACHINE(machine); 2345 ram_addr_t hotplugabble_address_space_size = 2346 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 2347 NULL); 2348 2349 srat_start = table_data->len; 2350 2351 srat = acpi_data_push(table_data, sizeof *srat); 2352 srat->reserved1 = cpu_to_le32(1); 2353 2354 for (i = 0; i < apic_ids->len; i++) { 2355 int node_id = apic_ids->cpus[i].props.node_id; 2356 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2357 2358 if (apic_id < 255) { 2359 AcpiSratProcessorAffinity *core; 2360 2361 core = acpi_data_push(table_data, sizeof *core); 2362 core->type = ACPI_SRAT_PROCESSOR_APIC; 2363 core->length = sizeof(*core); 2364 core->local_apic_id = apic_id; 2365 core->proximity_lo = node_id; 2366 memset(core->proximity_hi, 0, 3); 2367 core->local_sapic_eid = 0; 2368 core->flags = cpu_to_le32(1); 2369 } else { 2370 AcpiSratProcessorX2ApicAffinity *core; 2371 2372 core = acpi_data_push(table_data, sizeof *core); 2373 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2374 core->length = sizeof(*core); 2375 core->x2apic_id = cpu_to_le32(apic_id); 2376 core->proximity_domain = cpu_to_le32(node_id); 2377 core->flags = cpu_to_le32(1); 2378 } 2379 } 2380 2381 2382 /* the memory map is a bit tricky, it contains at least one hole 2383 * from 640k-1M and possibly another one from 3.5G-4G. 2384 */ 2385 next_base = 0; 2386 numa_start = table_data->len; 2387 2388 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2389 mem_base = next_base; 2390 mem_len = pcms->node_mem[i - 1]; 2391 next_base = mem_base + mem_len; 2392 2393 /* Cut out the 640K hole */ 2394 if (mem_base <= HOLE_640K_START && 2395 next_base > HOLE_640K_START) { 2396 mem_len -= next_base - HOLE_640K_START; 2397 if (mem_len > 0) { 2398 numamem = acpi_data_push(table_data, sizeof *numamem); 2399 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2400 MEM_AFFINITY_ENABLED); 2401 } 2402 2403 /* Check for the rare case: 640K < RAM < 1M */ 2404 if (next_base <= HOLE_640K_END) { 2405 next_base = HOLE_640K_END; 2406 continue; 2407 } 2408 mem_base = HOLE_640K_END; 2409 mem_len = next_base - HOLE_640K_END; 2410 } 2411 2412 /* Cut out the ACPI_PCI hole */ 2413 if (mem_base <= x86ms->below_4g_mem_size && 2414 next_base > x86ms->below_4g_mem_size) { 2415 mem_len -= next_base - x86ms->below_4g_mem_size; 2416 if (mem_len > 0) { 2417 numamem = acpi_data_push(table_data, sizeof *numamem); 2418 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2419 MEM_AFFINITY_ENABLED); 2420 } 2421 mem_base = 1ULL << 32; 2422 mem_len = next_base - x86ms->below_4g_mem_size; 2423 next_base = mem_base + mem_len; 2424 } 2425 2426 if (mem_len > 0) { 2427 numamem = acpi_data_push(table_data, sizeof *numamem); 2428 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2429 MEM_AFFINITY_ENABLED); 2430 } 2431 } 2432 slots = (table_data->len - numa_start) / sizeof *numamem; 2433 for (; slots < pcms->numa_nodes + 2; slots++) { 2434 numamem = acpi_data_push(table_data, sizeof *numamem); 2435 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2436 } 2437 2438 /* 2439 * Entry is required for Windows to enable memory hotplug in OS 2440 * and for Linux to enable SWIOTLB when booted with less than 2441 * 4G of RAM. Windows works better if the entry sets proximity 2442 * to the highest NUMA node in the machine. 2443 * Memory devices may override proximity set by this entry, 2444 * providing _PXM method if necessary. 2445 */ 2446 if (hotplugabble_address_space_size) { 2447 numamem = acpi_data_push(table_data, sizeof *numamem); 2448 build_srat_memory(numamem, machine->device_memory->base, 2449 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2450 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2451 } 2452 2453 build_header(linker, table_data, 2454 (void *)(table_data->data + srat_start), 2455 "SRAT", 2456 table_data->len - srat_start, 1, NULL, NULL); 2457 } 2458 2459 /* 2460 * VT-d spec 8.1 DMA Remapping Reporting Structure 2461 * (version Oct. 2014 or later) 2462 */ 2463 static void 2464 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2465 { 2466 int dmar_start = table_data->len; 2467 2468 AcpiTableDmar *dmar; 2469 AcpiDmarHardwareUnit *drhd; 2470 AcpiDmarRootPortATS *atsr; 2471 uint8_t dmar_flags = 0; 2472 X86IOMMUState *iommu = x86_iommu_get_default(); 2473 AcpiDmarDeviceScope *scope = NULL; 2474 /* Root complex IOAPIC use one path[0] only */ 2475 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2476 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2477 2478 assert(iommu); 2479 if (x86_iommu_ir_supported(iommu)) { 2480 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2481 } 2482 2483 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2484 dmar->host_address_width = intel_iommu->aw_bits - 1; 2485 dmar->flags = dmar_flags; 2486 2487 /* DMAR Remapping Hardware Unit Definition structure */ 2488 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2489 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2490 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2491 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2492 drhd->pci_segment = cpu_to_le16(0); 2493 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2494 2495 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2496 * 8.3.1 (version Oct. 2014 or later). */ 2497 scope = &drhd->scope[0]; 2498 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2499 scope->length = ioapic_scope_size; 2500 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2501 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2502 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2503 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2504 2505 if (iommu->dt_supported) { 2506 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2507 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2508 atsr->length = cpu_to_le16(sizeof(*atsr)); 2509 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2510 atsr->pci_segment = cpu_to_le16(0); 2511 } 2512 2513 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2514 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2515 } 2516 /* 2517 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2518 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2519 */ 2520 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2521 2522 /* 2523 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2524 * necessary for the PCI topology. 2525 */ 2526 static void 2527 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2528 { 2529 GArray *table_data = opaque; 2530 uint32_t entry; 2531 2532 /* "Select" IVHD entry, type 0x2 */ 2533 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2534 build_append_int_noprefix(table_data, entry, 4); 2535 2536 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2537 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2538 uint8_t sec = pci_bus_num(sec_bus); 2539 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2540 2541 if (pci_bus_is_express(sec_bus)) { 2542 /* 2543 * Walk the bus if there are subordinates, otherwise use a range 2544 * to cover an entire leaf bus. We could potentially also use a 2545 * range for traversed buses, but we'd need to take care not to 2546 * create both Select and Range entries covering the same device. 2547 * This is easier and potentially more compact. 2548 * 2549 * An example bare metal system seems to use Select entries for 2550 * root ports without a slot (ie. built-ins) and Range entries 2551 * when there is a slot. The same system also only hard-codes 2552 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2553 * making no effort to support nested bridges. We attempt to 2554 * be more thorough here. 2555 */ 2556 if (sec == sub) { /* leaf bus */ 2557 /* "Start of Range" IVHD entry, type 0x3 */ 2558 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2559 build_append_int_noprefix(table_data, entry, 4); 2560 /* "End of Range" IVHD entry, type 0x4 */ 2561 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2562 build_append_int_noprefix(table_data, entry, 4); 2563 } else { 2564 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2565 } 2566 } else { 2567 /* 2568 * If the secondary bus is conventional, then we need to create an 2569 * Alias range for everything downstream. The range covers the 2570 * first devfn on the secondary bus to the last devfn on the 2571 * subordinate bus. The alias target depends on legacy versus 2572 * express bridges, just as in pci_device_iommu_address_space(). 2573 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2574 */ 2575 uint16_t dev_id_a, dev_id_b; 2576 2577 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2578 2579 if (pci_is_express(dev) && 2580 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2581 dev_id_b = dev_id_a; 2582 } else { 2583 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2584 } 2585 2586 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2587 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2588 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2589 2590 /* "End of Range" IVHD entry, type 0x4 */ 2591 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2592 build_append_int_noprefix(table_data, entry, 4); 2593 } 2594 } 2595 } 2596 2597 /* For all PCI host bridges, walk and insert IVHD entries */ 2598 static int 2599 ivrs_host_bridges(Object *obj, void *opaque) 2600 { 2601 GArray *ivhd_blob = opaque; 2602 2603 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2604 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2605 2606 if (bus) { 2607 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2608 } 2609 } 2610 2611 return 0; 2612 } 2613 2614 static void 2615 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2616 { 2617 int ivhd_table_len = 24; 2618 int iommu_start = table_data->len; 2619 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2620 GArray *ivhd_blob = g_array_new(false, true, 1); 2621 2622 /* IVRS header */ 2623 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2624 /* IVinfo - IO virtualization information common to all 2625 * IOMMU units in a system 2626 */ 2627 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2628 /* reserved */ 2629 build_append_int_noprefix(table_data, 0, 8); 2630 2631 /* IVHD definition - type 10h */ 2632 build_append_int_noprefix(table_data, 0x10, 1); 2633 /* virtualization flags */ 2634 build_append_int_noprefix(table_data, 2635 (1UL << 0) | /* HtTunEn */ 2636 (1UL << 4) | /* iotblSup */ 2637 (1UL << 6) | /* PrefSup */ 2638 (1UL << 7), /* PPRSup */ 2639 1); 2640 2641 /* 2642 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2643 * complete set of IVHD entries. Do this into a separate blob so that we 2644 * can calculate the total IVRS table length here and then append the new 2645 * blob further below. Fall back to an entry covering all devices, which 2646 * is sufficient when no aliases are present. 2647 */ 2648 object_child_foreach_recursive(object_get_root(), 2649 ivrs_host_bridges, ivhd_blob); 2650 2651 if (!ivhd_blob->len) { 2652 /* 2653 * Type 1 device entry reporting all devices 2654 * These are 4-byte device entries currently reporting the range of 2655 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2656 */ 2657 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2658 } 2659 2660 ivhd_table_len += ivhd_blob->len; 2661 2662 /* 2663 * When interrupt remapping is supported, we add a special IVHD device 2664 * for type IO-APIC. 2665 */ 2666 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2667 ivhd_table_len += 8; 2668 } 2669 2670 /* IVHD length */ 2671 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2672 /* DeviceID */ 2673 build_append_int_noprefix(table_data, s->devid, 2); 2674 /* Capability offset */ 2675 build_append_int_noprefix(table_data, s->capab_offset, 2); 2676 /* IOMMU base address */ 2677 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2678 /* PCI Segment Group */ 2679 build_append_int_noprefix(table_data, 0, 2); 2680 /* IOMMU info */ 2681 build_append_int_noprefix(table_data, 0, 2); 2682 /* IOMMU Feature Reporting */ 2683 build_append_int_noprefix(table_data, 2684 (48UL << 30) | /* HATS */ 2685 (48UL << 28) | /* GATS */ 2686 (1UL << 2) | /* GTSup */ 2687 (1UL << 6), /* GASup */ 2688 4); 2689 2690 /* IVHD entries as found above */ 2691 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2692 g_array_free(ivhd_blob, TRUE); 2693 2694 /* 2695 * Add a special IVHD device type. 2696 * Refer to spec - Table 95: IVHD device entry type codes 2697 * 2698 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2699 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2700 */ 2701 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2702 build_append_int_noprefix(table_data, 2703 (0x1ull << 56) | /* type IOAPIC */ 2704 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2705 0x48, /* special device */ 2706 8); 2707 } 2708 2709 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2710 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2711 } 2712 2713 typedef 2714 struct AcpiBuildState { 2715 /* Copy of table in RAM (for patching). */ 2716 MemoryRegion *table_mr; 2717 /* Is table patched? */ 2718 uint8_t patched; 2719 void *rsdp; 2720 MemoryRegion *rsdp_mr; 2721 MemoryRegion *linker_mr; 2722 } AcpiBuildState; 2723 2724 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2725 { 2726 Object *pci_host; 2727 QObject *o; 2728 2729 pci_host = acpi_get_i386_pci_host(); 2730 g_assert(pci_host); 2731 2732 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2733 if (!o) { 2734 return false; 2735 } 2736 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2737 qobject_unref(o); 2738 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2739 return false; 2740 } 2741 2742 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2743 assert(o); 2744 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2745 qobject_unref(o); 2746 return true; 2747 } 2748 2749 static 2750 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2751 { 2752 PCMachineState *pcms = PC_MACHINE(machine); 2753 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2754 X86MachineState *x86ms = X86_MACHINE(machine); 2755 GArray *table_offsets; 2756 unsigned facs, dsdt, rsdt, fadt; 2757 AcpiPmInfo pm; 2758 AcpiMiscInfo misc; 2759 AcpiMcfgInfo mcfg; 2760 Range pci_hole, pci_hole64; 2761 uint8_t *u; 2762 size_t aml_len = 0; 2763 GArray *tables_blob = tables->table_data; 2764 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2765 Object *vmgenid_dev; 2766 2767 acpi_get_pm_info(machine, &pm); 2768 acpi_get_misc_info(&misc); 2769 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2770 acpi_get_slic_oem(&slic_oem); 2771 2772 table_offsets = g_array_new(false, true /* clear */, 2773 sizeof(uint32_t)); 2774 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2775 2776 bios_linker_loader_alloc(tables->linker, 2777 ACPI_BUILD_TABLE_FILE, tables_blob, 2778 64 /* Ensure FACS is aligned */, 2779 false /* high memory */); 2780 2781 /* 2782 * FACS is pointed to by FADT. 2783 * We place it first since it's the only table that has alignment 2784 * requirements. 2785 */ 2786 facs = tables_blob->len; 2787 build_facs(tables_blob); 2788 2789 /* DSDT is pointed to by FADT */ 2790 dsdt = tables_blob->len; 2791 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2792 &pci_hole, &pci_hole64, machine); 2793 2794 /* Count the size of the DSDT and SSDT, we will need it for legacy 2795 * sizing of ACPI tables. 2796 */ 2797 aml_len += tables_blob->len - dsdt; 2798 2799 /* ACPI tables pointed to by RSDT */ 2800 fadt = tables_blob->len; 2801 acpi_add_table(table_offsets, tables_blob); 2802 pm.fadt.facs_tbl_offset = &facs; 2803 pm.fadt.dsdt_tbl_offset = &dsdt; 2804 pm.fadt.xdsdt_tbl_offset = &dsdt; 2805 build_fadt(tables_blob, tables->linker, &pm.fadt, 2806 slic_oem.id, slic_oem.table_id); 2807 aml_len += tables_blob->len - fadt; 2808 2809 acpi_add_table(table_offsets, tables_blob); 2810 build_madt(tables_blob, tables->linker, pcms); 2811 2812 vmgenid_dev = find_vmgenid_dev(); 2813 if (vmgenid_dev) { 2814 acpi_add_table(table_offsets, tables_blob); 2815 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2816 tables->vmgenid, tables->linker); 2817 } 2818 2819 if (misc.has_hpet) { 2820 acpi_add_table(table_offsets, tables_blob); 2821 build_hpet(tables_blob, tables->linker); 2822 } 2823 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2824 acpi_add_table(table_offsets, tables_blob); 2825 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2826 2827 if (misc.tpm_version == TPM_VERSION_2_0) { 2828 acpi_add_table(table_offsets, tables_blob); 2829 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2830 } 2831 } 2832 if (pcms->numa_nodes) { 2833 acpi_add_table(table_offsets, tables_blob); 2834 build_srat(tables_blob, tables->linker, machine); 2835 if (machine->numa_state->have_numa_distance) { 2836 acpi_add_table(table_offsets, tables_blob); 2837 build_slit(tables_blob, tables->linker, machine); 2838 } 2839 if (machine->numa_state->hmat_enabled) { 2840 acpi_add_table(table_offsets, tables_blob); 2841 build_hmat(tables_blob, tables->linker, machine->numa_state); 2842 } 2843 } 2844 if (acpi_get_mcfg(&mcfg)) { 2845 acpi_add_table(table_offsets, tables_blob); 2846 build_mcfg(tables_blob, tables->linker, &mcfg); 2847 } 2848 if (x86_iommu_get_default()) { 2849 IommuType IOMMUType = x86_iommu_get_type(); 2850 if (IOMMUType == TYPE_AMD) { 2851 acpi_add_table(table_offsets, tables_blob); 2852 build_amd_iommu(tables_blob, tables->linker); 2853 } else if (IOMMUType == TYPE_INTEL) { 2854 acpi_add_table(table_offsets, tables_blob); 2855 build_dmar_q35(tables_blob, tables->linker); 2856 } 2857 } 2858 if (machine->nvdimms_state->is_enabled) { 2859 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2860 machine->nvdimms_state, machine->ram_slots); 2861 } 2862 2863 /* Add tables supplied by user (if any) */ 2864 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2865 unsigned len = acpi_table_len(u); 2866 2867 acpi_add_table(table_offsets, tables_blob); 2868 g_array_append_vals(tables_blob, u, len); 2869 } 2870 2871 /* RSDT is pointed to by RSDP */ 2872 rsdt = tables_blob->len; 2873 build_rsdt(tables_blob, tables->linker, table_offsets, 2874 slic_oem.id, slic_oem.table_id); 2875 2876 /* RSDP is in FSEG memory, so allocate it separately */ 2877 { 2878 AcpiRsdpData rsdp_data = { 2879 .revision = 0, 2880 .oem_id = ACPI_BUILD_APPNAME6, 2881 .xsdt_tbl_offset = NULL, 2882 .rsdt_tbl_offset = &rsdt, 2883 }; 2884 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2885 if (!pcmc->rsdp_in_ram) { 2886 /* We used to allocate some extra space for RSDP revision 2 but 2887 * only used the RSDP revision 0 space. The extra bytes were 2888 * zeroed out and not used. 2889 * Here we continue wasting those extra 16 bytes to make sure we 2890 * don't break migration for machine types 2.2 and older due to 2891 * RSDP blob size mismatch. 2892 */ 2893 build_append_int_noprefix(tables->rsdp, 0, 16); 2894 } 2895 } 2896 2897 /* We'll expose it all to Guest so we want to reduce 2898 * chance of size changes. 2899 * 2900 * We used to align the tables to 4k, but of course this would 2901 * too simple to be enough. 4k turned out to be too small an 2902 * alignment very soon, and in fact it is almost impossible to 2903 * keep the table size stable for all (max_cpus, max_memory_slots) 2904 * combinations. So the table size is always 64k for pc-i440fx-2.1 2905 * and we give an error if the table grows beyond that limit. 2906 * 2907 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2908 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2909 * than 2.0 and we can always pad the smaller tables with zeros. We can 2910 * then use the exact size of the 2.0 tables. 2911 * 2912 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2913 */ 2914 if (pcmc->legacy_acpi_table_size) { 2915 /* Subtracting aml_len gives the size of fixed tables. Then add the 2916 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2917 */ 2918 int legacy_aml_len = 2919 pcmc->legacy_acpi_table_size + 2920 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2921 int legacy_table_size = 2922 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2923 ACPI_BUILD_ALIGN_SIZE); 2924 if (tables_blob->len > legacy_table_size) { 2925 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2926 warn_report("ACPI table size %u exceeds %d bytes," 2927 " migration may not work", 2928 tables_blob->len, legacy_table_size); 2929 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2930 " or PCI bridges."); 2931 } 2932 g_array_set_size(tables_blob, legacy_table_size); 2933 } else { 2934 /* Make sure we have a buffer in case we need to resize the tables. */ 2935 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2936 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2937 warn_report("ACPI table size %u exceeds %d bytes," 2938 " migration may not work", 2939 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2940 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2941 " or PCI bridges."); 2942 } 2943 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2944 } 2945 2946 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2947 2948 /* Cleanup memory that's no longer used. */ 2949 g_array_free(table_offsets, true); 2950 } 2951 2952 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2953 { 2954 uint32_t size = acpi_data_len(data); 2955 2956 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2957 memory_region_ram_resize(mr, size, &error_abort); 2958 2959 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2960 memory_region_set_dirty(mr, 0, size); 2961 } 2962 2963 static void acpi_build_update(void *build_opaque) 2964 { 2965 AcpiBuildState *build_state = build_opaque; 2966 AcpiBuildTables tables; 2967 2968 /* No state to update or already patched? Nothing to do. */ 2969 if (!build_state || build_state->patched) { 2970 return; 2971 } 2972 build_state->patched = 1; 2973 2974 acpi_build_tables_init(&tables); 2975 2976 acpi_build(&tables, MACHINE(qdev_get_machine())); 2977 2978 acpi_ram_update(build_state->table_mr, tables.table_data); 2979 2980 if (build_state->rsdp) { 2981 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2982 } else { 2983 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2984 } 2985 2986 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2987 acpi_build_tables_cleanup(&tables, true); 2988 } 2989 2990 static void acpi_build_reset(void *build_opaque) 2991 { 2992 AcpiBuildState *build_state = build_opaque; 2993 build_state->patched = 0; 2994 } 2995 2996 static const VMStateDescription vmstate_acpi_build = { 2997 .name = "acpi_build", 2998 .version_id = 1, 2999 .minimum_version_id = 1, 3000 .fields = (VMStateField[]) { 3001 VMSTATE_UINT8(patched, AcpiBuildState), 3002 VMSTATE_END_OF_LIST() 3003 }, 3004 }; 3005 3006 void acpi_setup(void) 3007 { 3008 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 3009 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 3010 X86MachineState *x86ms = X86_MACHINE(pcms); 3011 AcpiBuildTables tables; 3012 AcpiBuildState *build_state; 3013 Object *vmgenid_dev; 3014 TPMIf *tpm; 3015 static FwCfgTPMConfig tpm_config; 3016 3017 if (!x86ms->fw_cfg) { 3018 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 3019 return; 3020 } 3021 3022 if (!pcms->acpi_build_enabled) { 3023 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 3024 return; 3025 } 3026 3027 if (!acpi_enabled) { 3028 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 3029 return; 3030 } 3031 3032 build_state = g_malloc0(sizeof *build_state); 3033 3034 acpi_build_tables_init(&tables); 3035 acpi_build(&tables, MACHINE(pcms)); 3036 3037 /* Now expose it all to Guest */ 3038 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 3039 build_state, tables.table_data, 3040 ACPI_BUILD_TABLE_FILE, 3041 ACPI_BUILD_TABLE_MAX_SIZE); 3042 assert(build_state->table_mr != NULL); 3043 3044 build_state->linker_mr = 3045 acpi_add_rom_blob(acpi_build_update, build_state, 3046 tables.linker->cmd_blob, "etc/table-loader", 0); 3047 3048 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 3049 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 3050 3051 tpm = tpm_find(); 3052 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 3053 tpm_config = (FwCfgTPMConfig) { 3054 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 3055 .tpm_version = tpm_get_version(tpm), 3056 .tpmppi_version = TPM_PPI_VERSION_1_30 3057 }; 3058 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 3059 &tpm_config, sizeof tpm_config); 3060 } 3061 3062 vmgenid_dev = find_vmgenid_dev(); 3063 if (vmgenid_dev) { 3064 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 3065 tables.vmgenid); 3066 } 3067 3068 if (!pcmc->rsdp_in_ram) { 3069 /* 3070 * Keep for compatibility with old machine types. 3071 * Though RSDP is small, its contents isn't immutable, so 3072 * we'll update it along with the rest of tables on guest access. 3073 */ 3074 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 3075 3076 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 3077 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 3078 acpi_build_update, NULL, build_state, 3079 build_state->rsdp, rsdp_size, true); 3080 build_state->rsdp_mr = NULL; 3081 } else { 3082 build_state->rsdp = NULL; 3083 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 3084 build_state, tables.rsdp, 3085 ACPI_BUILD_RSDP_FILE, 0); 3086 } 3087 3088 qemu_register_reset(acpi_build_reset, build_state); 3089 acpi_build_reset(build_state); 3090 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 3091 3092 /* Cleanup tables but don't free the memory: we track it 3093 * in build_state. 3094 */ 3095 acpi_build_tables_cleanup(&tables, false); 3096 } 3097