1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "target/i386/cpu.h" 32 #include "hw/misc/pvpanic.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/acpi/piix4.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/timer/mc146818rtc_regs.h" 49 #include "hw/mem/memory-device.h" 50 #include "sysemu/numa.h" 51 52 /* Supported chipsets: */ 53 #include "hw/acpi/piix4.h" 54 #include "hw/acpi/pcihp.h" 55 #include "hw/i386/ich9.h" 56 #include "hw/pci/pci_bus.h" 57 #include "hw/pci-host/q35.h" 58 #include "hw/i386/x86-iommu.h" 59 60 #include "hw/acpi/aml-build.h" 61 #include "hw/acpi/utils.h" 62 #include "hw/acpi/pci.h" 63 64 #include "qom/qom-qobject.h" 65 #include "hw/i386/amd_iommu.h" 66 #include "hw/i386/intel_iommu.h" 67 68 #include "hw/acpi/ipmi.h" 69 70 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 71 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 72 * a little bit, there should be plenty of free space since the DSDT 73 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 74 */ 75 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 76 #define ACPI_BUILD_ALIGN_SIZE 0x1000 77 78 #define ACPI_BUILD_TABLE_SIZE 0x20000 79 80 /* #define DEBUG_ACPI_BUILD */ 81 #ifdef DEBUG_ACPI_BUILD 82 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 83 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 84 #else 85 #define ACPI_BUILD_DPRINTF(fmt, ...) 86 #endif 87 88 /* Default IOAPIC ID */ 89 #define ACPI_BUILD_IOAPIC_ID 0x0 90 91 typedef struct AcpiPmInfo { 92 bool s3_disabled; 93 bool s4_disabled; 94 bool pcihp_bridge_en; 95 uint8_t s4_val; 96 AcpiFadtData fadt; 97 uint16_t cpu_hp_io_base; 98 uint16_t pcihp_io_base; 99 uint16_t pcihp_io_len; 100 } AcpiPmInfo; 101 102 typedef struct AcpiMiscInfo { 103 bool is_piix4; 104 bool has_hpet; 105 TPMVersion tpm_version; 106 const unsigned char *dsdt_code; 107 unsigned dsdt_size; 108 uint16_t pvpanic_port; 109 uint16_t applesmc_io_base; 110 } AcpiMiscInfo; 111 112 typedef struct AcpiBuildPciBusHotplugState { 113 GArray *device_table; 114 GArray *notify_table; 115 struct AcpiBuildPciBusHotplugState *parent; 116 bool pcihp_bridge_en; 117 } AcpiBuildPciBusHotplugState; 118 119 typedef struct FwCfgTPMConfig { 120 uint32_t tpmppi_address; 121 uint8_t tpm_version; 122 uint8_t tpmppi_version; 123 } QEMU_PACKED FwCfgTPMConfig; 124 125 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 126 127 static void init_common_fadt_data(MachineState *ms, Object *o, 128 AcpiFadtData *data) 129 { 130 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 131 AmlAddressSpace as = AML_AS_SYSTEM_IO; 132 AcpiFadtData fadt = { 133 .rev = 3, 134 .flags = 135 (1 << ACPI_FADT_F_WBINVD) | 136 (1 << ACPI_FADT_F_PROC_C1) | 137 (1 << ACPI_FADT_F_SLP_BUTTON) | 138 (1 << ACPI_FADT_F_RTC_S4) | 139 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 140 /* APIC destination mode ("Flat Logical") has an upper limit of 8 141 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 142 * used 143 */ 144 ((ms->smp.max_cpus > 8) ? 145 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 146 .int_model = 1 /* Multiple APIC */, 147 .rtc_century = RTC_CENTURY, 148 .plvl2_lat = 0xfff /* C2 state not supported */, 149 .plvl3_lat = 0xfff /* C3 state not supported */, 150 .smi_cmd = ACPI_PORT_SMI_CMD, 151 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 152 .acpi_enable_cmd = 153 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 154 .acpi_disable_cmd = 155 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 156 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 157 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 158 .address = io + 0x04 }, 159 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 160 .gpe0_blk = { .space_id = as, .bit_width = 161 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 162 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 163 }, 164 }; 165 *data = fadt; 166 } 167 168 static Object *object_resolve_type_unambiguous(const char *typename) 169 { 170 bool ambig; 171 Object *o = object_resolve_path_type("", typename, &ambig); 172 173 if (ambig || !o) { 174 return NULL; 175 } 176 return o; 177 } 178 179 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 180 { 181 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 182 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 183 Object *obj = piix ? piix : lpc; 184 QObject *o; 185 pm->cpu_hp_io_base = 0; 186 pm->pcihp_io_base = 0; 187 pm->pcihp_io_len = 0; 188 189 assert(obj); 190 init_common_fadt_data(machine, obj, &pm->fadt); 191 if (piix) { 192 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 193 pm->fadt.rev = 1; 194 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 195 pm->pcihp_io_base = 196 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 197 pm->pcihp_io_len = 198 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 199 } 200 if (lpc) { 201 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 202 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 203 pm->fadt.reset_reg = r; 204 pm->fadt.reset_val = 0xf; 205 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 206 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 207 } 208 209 /* The above need not be conditional on machine type because the reset port 210 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 211 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); 212 213 /* Fill in optional s3/s4 related properties */ 214 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 215 if (o) { 216 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 217 } else { 218 pm->s3_disabled = false; 219 } 220 qobject_unref(o); 221 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 222 if (o) { 223 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 224 } else { 225 pm->s4_disabled = false; 226 } 227 qobject_unref(o); 228 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 229 if (o) { 230 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 231 } else { 232 pm->s4_val = false; 233 } 234 qobject_unref(o); 235 236 pm->pcihp_bridge_en = 237 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 238 NULL); 239 } 240 241 static void acpi_get_misc_info(AcpiMiscInfo *info) 242 { 243 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 244 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 245 assert(!!piix != !!lpc); 246 247 if (piix) { 248 info->is_piix4 = true; 249 } 250 if (lpc) { 251 info->is_piix4 = false; 252 } 253 254 info->has_hpet = hpet_find(); 255 info->tpm_version = tpm_get_version(tpm_find()); 256 info->pvpanic_port = pvpanic_port(); 257 info->applesmc_io_base = applesmc_port(); 258 } 259 260 /* 261 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 262 * On i386 arch we only have two pci hosts, so we can look only for them. 263 */ 264 static Object *acpi_get_i386_pci_host(void) 265 { 266 PCIHostState *host; 267 268 host = OBJECT_CHECK(PCIHostState, 269 object_resolve_path("/machine/i440fx", NULL), 270 TYPE_PCI_HOST_BRIDGE); 271 if (!host) { 272 host = OBJECT_CHECK(PCIHostState, 273 object_resolve_path("/machine/q35", NULL), 274 TYPE_PCI_HOST_BRIDGE); 275 } 276 277 return OBJECT(host); 278 } 279 280 static void acpi_get_pci_holes(Range *hole, Range *hole64) 281 { 282 Object *pci_host; 283 284 pci_host = acpi_get_i386_pci_host(); 285 g_assert(pci_host); 286 287 range_set_bounds1(hole, 288 object_property_get_uint(pci_host, 289 PCI_HOST_PROP_PCI_HOLE_START, 290 NULL), 291 object_property_get_uint(pci_host, 292 PCI_HOST_PROP_PCI_HOLE_END, 293 NULL)); 294 range_set_bounds1(hole64, 295 object_property_get_uint(pci_host, 296 PCI_HOST_PROP_PCI_HOLE64_START, 297 NULL), 298 object_property_get_uint(pci_host, 299 PCI_HOST_PROP_PCI_HOLE64_END, 300 NULL)); 301 } 302 303 static void acpi_align_size(GArray *blob, unsigned align) 304 { 305 /* Align size to multiple of given size. This reduces the chance 306 * we need to change size in the future (breaking cross version migration). 307 */ 308 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 309 } 310 311 /* FACS */ 312 static void 313 build_facs(GArray *table_data) 314 { 315 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 316 memcpy(&facs->signature, "FACS", 4); 317 facs->length = cpu_to_le32(sizeof(*facs)); 318 } 319 320 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 321 const CPUArchIdList *apic_ids, GArray *entry) 322 { 323 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 324 325 /* ACPI spec says that LAPIC entry for non present 326 * CPU may be omitted from MADT or it must be marked 327 * as disabled. However omitting non present CPU from 328 * MADT breaks hotplug on linux. So possible CPUs 329 * should be put in MADT but kept disabled. 330 */ 331 if (apic_id < 255) { 332 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 333 334 apic->type = ACPI_APIC_PROCESSOR; 335 apic->length = sizeof(*apic); 336 apic->processor_id = uid; 337 apic->local_apic_id = apic_id; 338 if (apic_ids->cpus[uid].cpu != NULL) { 339 apic->flags = cpu_to_le32(1); 340 } else { 341 apic->flags = cpu_to_le32(0); 342 } 343 } else { 344 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 345 346 apic->type = ACPI_APIC_LOCAL_X2APIC; 347 apic->length = sizeof(*apic); 348 apic->uid = cpu_to_le32(uid); 349 apic->x2apic_id = cpu_to_le32(apic_id); 350 if (apic_ids->cpus[uid].cpu != NULL) { 351 apic->flags = cpu_to_le32(1); 352 } else { 353 apic->flags = cpu_to_le32(0); 354 } 355 } 356 } 357 358 static void 359 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 360 { 361 MachineClass *mc = MACHINE_GET_CLASS(pcms); 362 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 363 int madt_start = table_data->len; 364 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 365 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 366 bool x2apic_mode = false; 367 368 AcpiMultipleApicTable *madt; 369 AcpiMadtIoApic *io_apic; 370 AcpiMadtIntsrcovr *intsrcovr; 371 int i; 372 373 madt = acpi_data_push(table_data, sizeof *madt); 374 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 375 madt->flags = cpu_to_le32(1); 376 377 for (i = 0; i < apic_ids->len; i++) { 378 adevc->madt_cpu(adev, i, apic_ids, table_data); 379 if (apic_ids->cpus[i].arch_id > 254) { 380 x2apic_mode = true; 381 } 382 } 383 384 io_apic = acpi_data_push(table_data, sizeof *io_apic); 385 io_apic->type = ACPI_APIC_IO; 386 io_apic->length = sizeof(*io_apic); 387 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 388 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 389 io_apic->interrupt = cpu_to_le32(0); 390 391 if (pcms->apic_xrupt_override) { 392 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 393 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 394 intsrcovr->length = sizeof(*intsrcovr); 395 intsrcovr->source = 0; 396 intsrcovr->gsi = cpu_to_le32(2); 397 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 398 } 399 for (i = 1; i < 16; i++) { 400 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 401 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 402 /* No need for a INT source override structure. */ 403 continue; 404 } 405 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 406 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 407 intsrcovr->length = sizeof(*intsrcovr); 408 intsrcovr->source = i; 409 intsrcovr->gsi = cpu_to_le32(i); 410 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 411 } 412 413 if (x2apic_mode) { 414 AcpiMadtLocalX2ApicNmi *local_nmi; 415 416 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 417 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 418 local_nmi->length = sizeof(*local_nmi); 419 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 420 local_nmi->flags = cpu_to_le16(0); 421 local_nmi->lint = 1; /* ACPI_LINT1 */ 422 } else { 423 AcpiMadtLocalNmi *local_nmi; 424 425 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 426 local_nmi->type = ACPI_APIC_LOCAL_NMI; 427 local_nmi->length = sizeof(*local_nmi); 428 local_nmi->processor_id = 0xff; /* all processors */ 429 local_nmi->flags = cpu_to_le16(0); 430 local_nmi->lint = 1; /* ACPI_LINT1 */ 431 } 432 433 build_header(linker, table_data, 434 (void *)(table_data->data + madt_start), "APIC", 435 table_data->len - madt_start, 1, NULL, NULL); 436 } 437 438 static void build_append_pcihp_notify_entry(Aml *method, int slot) 439 { 440 Aml *if_ctx; 441 int32_t devfn = PCI_DEVFN(slot, 0); 442 443 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 444 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 445 aml_append(method, if_ctx); 446 } 447 448 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 449 bool pcihp_bridge_en) 450 { 451 Aml *dev, *notify_method = NULL, *method; 452 QObject *bsel; 453 PCIBus *sec; 454 int i; 455 456 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 457 if (bsel) { 458 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 459 460 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 461 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 462 } 463 464 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 465 DeviceClass *dc; 466 PCIDeviceClass *pc; 467 PCIDevice *pdev = bus->devices[i]; 468 int slot = PCI_SLOT(i); 469 bool hotplug_enabled_dev; 470 bool bridge_in_acpi; 471 472 if (!pdev) { 473 if (bsel) { /* add hotplug slots for non present devices */ 474 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 475 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 476 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 477 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 478 aml_append(method, 479 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 480 ); 481 aml_append(dev, method); 482 aml_append(parent_scope, dev); 483 484 build_append_pcihp_notify_entry(notify_method, slot); 485 } 486 continue; 487 } 488 489 pc = PCI_DEVICE_GET_CLASS(pdev); 490 dc = DEVICE_GET_CLASS(pdev); 491 492 /* When hotplug for bridges is enabled, bridges are 493 * described in ACPI separately (see build_pci_bus_end). 494 * In this case they aren't themselves hot-pluggable. 495 * Hotplugged bridges *are* hot-pluggable. 496 */ 497 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 498 !DEVICE(pdev)->hotplugged; 499 500 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 501 502 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 503 continue; 504 } 505 506 /* start to compose PCI slot descriptor */ 507 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 508 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 509 510 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 511 /* add VGA specific AML methods */ 512 int s3d; 513 514 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 515 s3d = 3; 516 } else { 517 s3d = 0; 518 } 519 520 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 521 aml_append(method, aml_return(aml_int(0))); 522 aml_append(dev, method); 523 524 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 525 aml_append(method, aml_return(aml_int(0))); 526 aml_append(dev, method); 527 528 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 529 aml_append(method, aml_return(aml_int(s3d))); 530 aml_append(dev, method); 531 } else if (hotplug_enabled_dev) { 532 /* add _SUN/_EJ0 to make slot hotpluggable */ 533 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 534 535 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 536 aml_append(method, 537 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 538 ); 539 aml_append(dev, method); 540 541 if (bsel) { 542 build_append_pcihp_notify_entry(notify_method, slot); 543 } 544 } else if (bridge_in_acpi) { 545 /* 546 * device is coldplugged bridge, 547 * add child device descriptions into its scope 548 */ 549 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 550 551 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 552 } 553 /* slot descriptor has been composed, add it into parent context */ 554 aml_append(parent_scope, dev); 555 } 556 557 if (bsel) { 558 aml_append(parent_scope, notify_method); 559 } 560 561 /* Append PCNT method to notify about events on local and child buses. 562 * Add unconditionally for root since DSDT expects it. 563 */ 564 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 565 566 /* If bus supports hotplug select it and notify about local events */ 567 if (bsel) { 568 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 569 570 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 571 aml_append(method, 572 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 573 ); 574 aml_append(method, 575 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 576 ); 577 } 578 579 /* Notify about child bus events in any case */ 580 if (pcihp_bridge_en) { 581 QLIST_FOREACH(sec, &bus->child, sibling) { 582 int32_t devfn = sec->parent_dev->devfn; 583 584 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 585 continue; 586 } 587 588 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 589 } 590 } 591 aml_append(parent_scope, method); 592 qobject_unref(bsel); 593 } 594 595 /** 596 * build_prt_entry: 597 * @link_name: link name for PCI route entry 598 * 599 * build AML package containing a PCI route entry for @link_name 600 */ 601 static Aml *build_prt_entry(const char *link_name) 602 { 603 Aml *a_zero = aml_int(0); 604 Aml *pkg = aml_package(4); 605 aml_append(pkg, a_zero); 606 aml_append(pkg, a_zero); 607 aml_append(pkg, aml_name("%s", link_name)); 608 aml_append(pkg, a_zero); 609 return pkg; 610 } 611 612 /* 613 * initialize_route - Initialize the interrupt routing rule 614 * through a specific LINK: 615 * if (lnk_idx == idx) 616 * route using link 'link_name' 617 */ 618 static Aml *initialize_route(Aml *route, const char *link_name, 619 Aml *lnk_idx, int idx) 620 { 621 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 622 Aml *pkg = build_prt_entry(link_name); 623 624 aml_append(if_ctx, aml_store(pkg, route)); 625 626 return if_ctx; 627 } 628 629 /* 630 * build_prt - Define interrupt rounting rules 631 * 632 * Returns an array of 128 routes, one for each device, 633 * based on device location. 634 * The main goal is to equaly distribute the interrupts 635 * over the 4 existing ACPI links (works only for i440fx). 636 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 637 * 638 */ 639 static Aml *build_prt(bool is_pci0_prt) 640 { 641 Aml *method, *while_ctx, *pin, *res; 642 643 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 644 res = aml_local(0); 645 pin = aml_local(1); 646 aml_append(method, aml_store(aml_package(128), res)); 647 aml_append(method, aml_store(aml_int(0), pin)); 648 649 /* while (pin < 128) */ 650 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 651 { 652 Aml *slot = aml_local(2); 653 Aml *lnk_idx = aml_local(3); 654 Aml *route = aml_local(4); 655 656 /* slot = pin >> 2 */ 657 aml_append(while_ctx, 658 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 659 /* lnk_idx = (slot + pin) & 3 */ 660 aml_append(while_ctx, 661 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 662 lnk_idx)); 663 664 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 665 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 666 if (is_pci0_prt) { 667 Aml *if_device_1, *if_pin_4, *else_pin_4; 668 669 /* device 1 is the power-management device, needs SCI */ 670 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 671 { 672 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 673 { 674 aml_append(if_pin_4, 675 aml_store(build_prt_entry("LNKS"), route)); 676 } 677 aml_append(if_device_1, if_pin_4); 678 else_pin_4 = aml_else(); 679 { 680 aml_append(else_pin_4, 681 aml_store(build_prt_entry("LNKA"), route)); 682 } 683 aml_append(if_device_1, else_pin_4); 684 } 685 aml_append(while_ctx, if_device_1); 686 } else { 687 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 688 } 689 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 690 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 691 692 /* route[0] = 0x[slot]FFFF */ 693 aml_append(while_ctx, 694 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 695 NULL), 696 aml_index(route, aml_int(0)))); 697 /* route[1] = pin & 3 */ 698 aml_append(while_ctx, 699 aml_store(aml_and(pin, aml_int(3), NULL), 700 aml_index(route, aml_int(1)))); 701 /* res[pin] = route */ 702 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 703 /* pin++ */ 704 aml_append(while_ctx, aml_increment(pin)); 705 } 706 aml_append(method, while_ctx); 707 /* return res*/ 708 aml_append(method, aml_return(res)); 709 710 return method; 711 } 712 713 typedef struct CrsRangeEntry { 714 uint64_t base; 715 uint64_t limit; 716 } CrsRangeEntry; 717 718 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 719 { 720 CrsRangeEntry *entry; 721 722 entry = g_malloc(sizeof(*entry)); 723 entry->base = base; 724 entry->limit = limit; 725 726 g_ptr_array_add(ranges, entry); 727 } 728 729 static void crs_range_free(gpointer data) 730 { 731 CrsRangeEntry *entry = (CrsRangeEntry *)data; 732 g_free(entry); 733 } 734 735 typedef struct CrsRangeSet { 736 GPtrArray *io_ranges; 737 GPtrArray *mem_ranges; 738 GPtrArray *mem_64bit_ranges; 739 } CrsRangeSet; 740 741 static void crs_range_set_init(CrsRangeSet *range_set) 742 { 743 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 744 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 745 range_set->mem_64bit_ranges = 746 g_ptr_array_new_with_free_func(crs_range_free); 747 } 748 749 static void crs_range_set_free(CrsRangeSet *range_set) 750 { 751 g_ptr_array_free(range_set->io_ranges, true); 752 g_ptr_array_free(range_set->mem_ranges, true); 753 g_ptr_array_free(range_set->mem_64bit_ranges, true); 754 } 755 756 static gint crs_range_compare(gconstpointer a, gconstpointer b) 757 { 758 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 759 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 760 761 if (entry_a->base < entry_b->base) { 762 return -1; 763 } else if (entry_a->base > entry_b->base) { 764 return 1; 765 } else { 766 return 0; 767 } 768 } 769 770 /* 771 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 772 * interval, computes the 'free' ranges from the same interval. 773 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 774 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 775 */ 776 static void crs_replace_with_free_ranges(GPtrArray *ranges, 777 uint64_t start, uint64_t end) 778 { 779 GPtrArray *free_ranges = g_ptr_array_new(); 780 uint64_t free_base = start; 781 int i; 782 783 g_ptr_array_sort(ranges, crs_range_compare); 784 for (i = 0; i < ranges->len; i++) { 785 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 786 787 if (free_base < used->base) { 788 crs_range_insert(free_ranges, free_base, used->base - 1); 789 } 790 791 free_base = used->limit + 1; 792 } 793 794 if (free_base < end) { 795 crs_range_insert(free_ranges, free_base, end); 796 } 797 798 g_ptr_array_set_size(ranges, 0); 799 for (i = 0; i < free_ranges->len; i++) { 800 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 801 } 802 803 g_ptr_array_free(free_ranges, true); 804 } 805 806 /* 807 * crs_range_merge - merges adjacent ranges in the given array. 808 * Array elements are deleted and replaced with the merged ranges. 809 */ 810 static void crs_range_merge(GPtrArray *range) 811 { 812 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 813 CrsRangeEntry *entry; 814 uint64_t range_base, range_limit; 815 int i; 816 817 if (!range->len) { 818 return; 819 } 820 821 g_ptr_array_sort(range, crs_range_compare); 822 823 entry = g_ptr_array_index(range, 0); 824 range_base = entry->base; 825 range_limit = entry->limit; 826 for (i = 1; i < range->len; i++) { 827 entry = g_ptr_array_index(range, i); 828 if (entry->base - 1 == range_limit) { 829 range_limit = entry->limit; 830 } else { 831 crs_range_insert(tmp, range_base, range_limit); 832 range_base = entry->base; 833 range_limit = entry->limit; 834 } 835 } 836 crs_range_insert(tmp, range_base, range_limit); 837 838 g_ptr_array_set_size(range, 0); 839 for (i = 0; i < tmp->len; i++) { 840 entry = g_ptr_array_index(tmp, i); 841 crs_range_insert(range, entry->base, entry->limit); 842 } 843 g_ptr_array_free(tmp, true); 844 } 845 846 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 847 { 848 Aml *crs = aml_resource_template(); 849 CrsRangeSet temp_range_set; 850 CrsRangeEntry *entry; 851 uint8_t max_bus = pci_bus_num(host->bus); 852 uint8_t type; 853 int devfn; 854 int i; 855 856 crs_range_set_init(&temp_range_set); 857 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 858 uint64_t range_base, range_limit; 859 PCIDevice *dev = host->bus->devices[devfn]; 860 861 if (!dev) { 862 continue; 863 } 864 865 for (i = 0; i < PCI_NUM_REGIONS; i++) { 866 PCIIORegion *r = &dev->io_regions[i]; 867 868 range_base = r->addr; 869 range_limit = r->addr + r->size - 1; 870 871 /* 872 * Work-around for old bioses 873 * that do not support multiple root buses 874 */ 875 if (!range_base || range_base > range_limit) { 876 continue; 877 } 878 879 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 880 crs_range_insert(temp_range_set.io_ranges, 881 range_base, range_limit); 882 } else { /* "memory" */ 883 crs_range_insert(temp_range_set.mem_ranges, 884 range_base, range_limit); 885 } 886 } 887 888 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 889 if (type == PCI_HEADER_TYPE_BRIDGE) { 890 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 891 if (subordinate > max_bus) { 892 max_bus = subordinate; 893 } 894 895 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 896 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 897 898 /* 899 * Work-around for old bioses 900 * that do not support multiple root buses 901 */ 902 if (range_base && range_base <= range_limit) { 903 crs_range_insert(temp_range_set.io_ranges, 904 range_base, range_limit); 905 } 906 907 range_base = 908 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 909 range_limit = 910 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 911 912 /* 913 * Work-around for old bioses 914 * that do not support multiple root buses 915 */ 916 if (range_base && range_base <= range_limit) { 917 uint64_t length = range_limit - range_base + 1; 918 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 919 crs_range_insert(temp_range_set.mem_ranges, 920 range_base, range_limit); 921 } else { 922 crs_range_insert(temp_range_set.mem_64bit_ranges, 923 range_base, range_limit); 924 } 925 } 926 927 range_base = 928 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 929 range_limit = 930 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 931 932 /* 933 * Work-around for old bioses 934 * that do not support multiple root buses 935 */ 936 if (range_base && range_base <= range_limit) { 937 uint64_t length = range_limit - range_base + 1; 938 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 939 crs_range_insert(temp_range_set.mem_ranges, 940 range_base, range_limit); 941 } else { 942 crs_range_insert(temp_range_set.mem_64bit_ranges, 943 range_base, range_limit); 944 } 945 } 946 } 947 } 948 949 crs_range_merge(temp_range_set.io_ranges); 950 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 951 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 952 aml_append(crs, 953 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 954 AML_POS_DECODE, AML_ENTIRE_RANGE, 955 0, entry->base, entry->limit, 0, 956 entry->limit - entry->base + 1)); 957 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 958 } 959 960 crs_range_merge(temp_range_set.mem_ranges); 961 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 962 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 963 aml_append(crs, 964 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 965 AML_MAX_FIXED, AML_NON_CACHEABLE, 966 AML_READ_WRITE, 967 0, entry->base, entry->limit, 0, 968 entry->limit - entry->base + 1)); 969 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 970 } 971 972 crs_range_merge(temp_range_set.mem_64bit_ranges); 973 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 974 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 975 aml_append(crs, 976 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 977 AML_MAX_FIXED, AML_NON_CACHEABLE, 978 AML_READ_WRITE, 979 0, entry->base, entry->limit, 0, 980 entry->limit - entry->base + 1)); 981 crs_range_insert(range_set->mem_64bit_ranges, 982 entry->base, entry->limit); 983 } 984 985 crs_range_set_free(&temp_range_set); 986 987 aml_append(crs, 988 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 989 0, 990 pci_bus_num(host->bus), 991 max_bus, 992 0, 993 max_bus - pci_bus_num(host->bus) + 1)); 994 995 return crs; 996 } 997 998 static void build_hpet_aml(Aml *table) 999 { 1000 Aml *crs; 1001 Aml *field; 1002 Aml *method; 1003 Aml *if_ctx; 1004 Aml *scope = aml_scope("_SB"); 1005 Aml *dev = aml_device("HPET"); 1006 Aml *zero = aml_int(0); 1007 Aml *id = aml_local(0); 1008 Aml *period = aml_local(1); 1009 1010 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1011 aml_append(dev, aml_name_decl("_UID", zero)); 1012 1013 aml_append(dev, 1014 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1015 HPET_LEN)); 1016 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1017 aml_append(field, aml_named_field("VEND", 32)); 1018 aml_append(field, aml_named_field("PRD", 32)); 1019 aml_append(dev, field); 1020 1021 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1022 aml_append(method, aml_store(aml_name("VEND"), id)); 1023 aml_append(method, aml_store(aml_name("PRD"), period)); 1024 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1025 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1026 aml_equal(id, aml_int(0xffff)))); 1027 { 1028 aml_append(if_ctx, aml_return(zero)); 1029 } 1030 aml_append(method, if_ctx); 1031 1032 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1033 aml_lgreater(period, aml_int(100000000)))); 1034 { 1035 aml_append(if_ctx, aml_return(zero)); 1036 } 1037 aml_append(method, if_ctx); 1038 1039 aml_append(method, aml_return(aml_int(0x0F))); 1040 aml_append(dev, method); 1041 1042 crs = aml_resource_template(); 1043 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1044 aml_append(dev, aml_name_decl("_CRS", crs)); 1045 1046 aml_append(scope, dev); 1047 aml_append(table, scope); 1048 } 1049 1050 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1051 { 1052 Aml *dev, *fdi; 1053 uint8_t maxc, maxh, maxs; 1054 1055 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1056 1057 dev = aml_device("FLP%c", 'A' + idx); 1058 1059 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1060 1061 fdi = aml_package(16); 1062 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1063 aml_append(fdi, 1064 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1065 /* 1066 * the values below are the limits of the drive, and are thus independent 1067 * of the inserted media 1068 */ 1069 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1070 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1071 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1072 /* 1073 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1074 * the drive type, so shall we 1075 */ 1076 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1077 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1078 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1079 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1080 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1081 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1082 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1083 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1084 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1085 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1086 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1087 1088 aml_append(dev, aml_name_decl("_FDI", fdi)); 1089 return dev; 1090 } 1091 1092 static Aml *build_fdc_device_aml(ISADevice *fdc) 1093 { 1094 int i; 1095 Aml *dev; 1096 Aml *crs; 1097 1098 #define ACPI_FDE_MAX_FD 4 1099 uint32_t fde_buf[5] = { 1100 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1101 cpu_to_le32(2) /* tape presence (2 == never present) */ 1102 }; 1103 1104 dev = aml_device("FDC0"); 1105 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1106 1107 crs = aml_resource_template(); 1108 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1109 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1110 aml_append(crs, aml_irq_no_flags(6)); 1111 aml_append(crs, 1112 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1113 aml_append(dev, aml_name_decl("_CRS", crs)); 1114 1115 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1116 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1117 1118 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1119 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1120 aml_append(dev, build_fdinfo_aml(i, type)); 1121 } 1122 } 1123 aml_append(dev, aml_name_decl("_FDE", 1124 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1125 1126 return dev; 1127 } 1128 1129 static Aml *build_rtc_device_aml(void) 1130 { 1131 Aml *dev; 1132 Aml *crs; 1133 1134 dev = aml_device("RTC"); 1135 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1136 crs = aml_resource_template(); 1137 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1138 aml_append(crs, aml_irq_no_flags(8)); 1139 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1140 aml_append(dev, aml_name_decl("_CRS", crs)); 1141 1142 return dev; 1143 } 1144 1145 static Aml *build_kbd_device_aml(void) 1146 { 1147 Aml *dev; 1148 Aml *crs; 1149 Aml *method; 1150 1151 dev = aml_device("KBD"); 1152 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1153 1154 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1155 aml_append(method, aml_return(aml_int(0x0f))); 1156 aml_append(dev, method); 1157 1158 crs = aml_resource_template(); 1159 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1160 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1161 aml_append(crs, aml_irq_no_flags(1)); 1162 aml_append(dev, aml_name_decl("_CRS", crs)); 1163 1164 return dev; 1165 } 1166 1167 static Aml *build_mouse_device_aml(void) 1168 { 1169 Aml *dev; 1170 Aml *crs; 1171 Aml *method; 1172 1173 dev = aml_device("MOU"); 1174 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1175 1176 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1177 aml_append(method, aml_return(aml_int(0x0f))); 1178 aml_append(dev, method); 1179 1180 crs = aml_resource_template(); 1181 aml_append(crs, aml_irq_no_flags(12)); 1182 aml_append(dev, aml_name_decl("_CRS", crs)); 1183 1184 return dev; 1185 } 1186 1187 static Aml *build_lpt_device_aml(void) 1188 { 1189 Aml *dev; 1190 Aml *crs; 1191 Aml *method; 1192 Aml *if_ctx; 1193 Aml *else_ctx; 1194 Aml *zero = aml_int(0); 1195 Aml *is_present = aml_local(0); 1196 1197 dev = aml_device("LPT"); 1198 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1199 1200 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1201 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1202 if_ctx = aml_if(aml_equal(is_present, zero)); 1203 { 1204 aml_append(if_ctx, aml_return(aml_int(0x00))); 1205 } 1206 aml_append(method, if_ctx); 1207 else_ctx = aml_else(); 1208 { 1209 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1210 } 1211 aml_append(method, else_ctx); 1212 aml_append(dev, method); 1213 1214 crs = aml_resource_template(); 1215 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1216 aml_append(crs, aml_irq_no_flags(7)); 1217 aml_append(dev, aml_name_decl("_CRS", crs)); 1218 1219 return dev; 1220 } 1221 1222 static Aml *build_com_device_aml(uint8_t uid) 1223 { 1224 Aml *dev; 1225 Aml *crs; 1226 Aml *method; 1227 Aml *if_ctx; 1228 Aml *else_ctx; 1229 Aml *zero = aml_int(0); 1230 Aml *is_present = aml_local(0); 1231 const char *enabled_field = "CAEN"; 1232 uint8_t irq = 4; 1233 uint16_t io_port = 0x03F8; 1234 1235 assert(uid == 1 || uid == 2); 1236 if (uid == 2) { 1237 enabled_field = "CBEN"; 1238 irq = 3; 1239 io_port = 0x02F8; 1240 } 1241 1242 dev = aml_device("COM%d", uid); 1243 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1244 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1245 1246 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1247 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1248 if_ctx = aml_if(aml_equal(is_present, zero)); 1249 { 1250 aml_append(if_ctx, aml_return(aml_int(0x00))); 1251 } 1252 aml_append(method, if_ctx); 1253 else_ctx = aml_else(); 1254 { 1255 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1256 } 1257 aml_append(method, else_ctx); 1258 aml_append(dev, method); 1259 1260 crs = aml_resource_template(); 1261 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1262 aml_append(crs, aml_irq_no_flags(irq)); 1263 aml_append(dev, aml_name_decl("_CRS", crs)); 1264 1265 return dev; 1266 } 1267 1268 static void build_isa_devices_aml(Aml *table) 1269 { 1270 ISADevice *fdc = pc_find_fdc0(); 1271 bool ambiguous; 1272 1273 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1274 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1275 1276 aml_append(scope, build_rtc_device_aml()); 1277 aml_append(scope, build_kbd_device_aml()); 1278 aml_append(scope, build_mouse_device_aml()); 1279 if (fdc) { 1280 aml_append(scope, build_fdc_device_aml(fdc)); 1281 } 1282 aml_append(scope, build_lpt_device_aml()); 1283 aml_append(scope, build_com_device_aml(1)); 1284 aml_append(scope, build_com_device_aml(2)); 1285 1286 if (ambiguous) { 1287 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1288 } else if (!obj) { 1289 error_report("No ISA bus, unable to define IPMI ACPI data"); 1290 } else { 1291 build_acpi_ipmi_devices(scope, BUS(obj)); 1292 } 1293 1294 aml_append(table, scope); 1295 } 1296 1297 static void build_dbg_aml(Aml *table) 1298 { 1299 Aml *field; 1300 Aml *method; 1301 Aml *while_ctx; 1302 Aml *scope = aml_scope("\\"); 1303 Aml *buf = aml_local(0); 1304 Aml *len = aml_local(1); 1305 Aml *idx = aml_local(2); 1306 1307 aml_append(scope, 1308 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1309 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1310 aml_append(field, aml_named_field("DBGB", 8)); 1311 aml_append(scope, field); 1312 1313 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1314 1315 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1316 aml_append(method, aml_to_buffer(buf, buf)); 1317 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1318 aml_append(method, aml_store(aml_int(0), idx)); 1319 1320 while_ctx = aml_while(aml_lless(idx, len)); 1321 aml_append(while_ctx, 1322 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1323 aml_append(while_ctx, aml_increment(idx)); 1324 aml_append(method, while_ctx); 1325 1326 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1327 aml_append(scope, method); 1328 1329 aml_append(table, scope); 1330 } 1331 1332 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1333 { 1334 Aml *dev; 1335 Aml *crs; 1336 Aml *method; 1337 uint32_t irqs[] = {5, 10, 11}; 1338 1339 dev = aml_device("%s", name); 1340 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1341 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1342 1343 crs = aml_resource_template(); 1344 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1345 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1346 aml_append(dev, aml_name_decl("_PRS", crs)); 1347 1348 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1349 aml_append(method, aml_return(aml_call1("IQST", reg))); 1350 aml_append(dev, method); 1351 1352 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1353 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1354 aml_append(dev, method); 1355 1356 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1357 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1358 aml_append(dev, method); 1359 1360 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1361 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1362 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1363 aml_append(dev, method); 1364 1365 return dev; 1366 } 1367 1368 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1369 { 1370 Aml *dev; 1371 Aml *crs; 1372 Aml *method; 1373 uint32_t irqs; 1374 1375 dev = aml_device("%s", name); 1376 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1377 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1378 1379 crs = aml_resource_template(); 1380 irqs = gsi; 1381 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1382 AML_SHARED, &irqs, 1)); 1383 aml_append(dev, aml_name_decl("_PRS", crs)); 1384 1385 aml_append(dev, aml_name_decl("_CRS", crs)); 1386 1387 /* 1388 * _DIS can be no-op because the interrupt cannot be disabled. 1389 */ 1390 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1391 aml_append(dev, method); 1392 1393 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1394 aml_append(dev, method); 1395 1396 return dev; 1397 } 1398 1399 /* _CRS method - get current settings */ 1400 static Aml *build_iqcr_method(bool is_piix4) 1401 { 1402 Aml *if_ctx; 1403 uint32_t irqs; 1404 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1405 Aml *crs = aml_resource_template(); 1406 1407 irqs = 0; 1408 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1409 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1410 aml_append(method, aml_name_decl("PRR0", crs)); 1411 1412 aml_append(method, 1413 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1414 1415 if (is_piix4) { 1416 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1417 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1418 aml_append(method, if_ctx); 1419 } else { 1420 aml_append(method, 1421 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1422 aml_name("PRRI"))); 1423 } 1424 1425 aml_append(method, aml_return(aml_name("PRR0"))); 1426 return method; 1427 } 1428 1429 /* _STA method - get status */ 1430 static Aml *build_irq_status_method(void) 1431 { 1432 Aml *if_ctx; 1433 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1434 1435 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1436 aml_append(if_ctx, aml_return(aml_int(0x09))); 1437 aml_append(method, if_ctx); 1438 aml_append(method, aml_return(aml_int(0x0B))); 1439 return method; 1440 } 1441 1442 static void build_piix4_pci0_int(Aml *table) 1443 { 1444 Aml *dev; 1445 Aml *crs; 1446 Aml *field; 1447 Aml *method; 1448 uint32_t irqs; 1449 Aml *sb_scope = aml_scope("_SB"); 1450 Aml *pci0_scope = aml_scope("PCI0"); 1451 1452 aml_append(pci0_scope, build_prt(true)); 1453 aml_append(sb_scope, pci0_scope); 1454 1455 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1456 aml_append(field, aml_named_field("PRQ0", 8)); 1457 aml_append(field, aml_named_field("PRQ1", 8)); 1458 aml_append(field, aml_named_field("PRQ2", 8)); 1459 aml_append(field, aml_named_field("PRQ3", 8)); 1460 aml_append(sb_scope, field); 1461 1462 aml_append(sb_scope, build_irq_status_method()); 1463 aml_append(sb_scope, build_iqcr_method(true)); 1464 1465 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1466 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1467 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1468 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1469 1470 dev = aml_device("LNKS"); 1471 { 1472 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1473 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1474 1475 crs = aml_resource_template(); 1476 irqs = 9; 1477 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1478 AML_ACTIVE_HIGH, AML_SHARED, 1479 &irqs, 1)); 1480 aml_append(dev, aml_name_decl("_PRS", crs)); 1481 1482 /* The SCI cannot be disabled and is always attached to GSI 9, 1483 * so these are no-ops. We only need this link to override the 1484 * polarity to active high and match the content of the MADT. 1485 */ 1486 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1487 aml_append(method, aml_return(aml_int(0x0b))); 1488 aml_append(dev, method); 1489 1490 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1491 aml_append(dev, method); 1492 1493 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1494 aml_append(method, aml_return(aml_name("_PRS"))); 1495 aml_append(dev, method); 1496 1497 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1498 aml_append(dev, method); 1499 } 1500 aml_append(sb_scope, dev); 1501 1502 aml_append(table, sb_scope); 1503 } 1504 1505 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1506 { 1507 int i; 1508 int head; 1509 Aml *pkg; 1510 char base = name[3] < 'E' ? 'A' : 'E'; 1511 char *s = g_strdup(name); 1512 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1513 1514 assert(strlen(s) == 4); 1515 1516 head = name[3] - base; 1517 for (i = 0; i < 4; i++) { 1518 if (head + i > 3) { 1519 head = i * -1; 1520 } 1521 s[3] = base + head + i; 1522 pkg = aml_package(4); 1523 aml_append(pkg, a_nr); 1524 aml_append(pkg, aml_int(i)); 1525 aml_append(pkg, aml_name("%s", s)); 1526 aml_append(pkg, aml_int(0)); 1527 aml_append(ctx, pkg); 1528 } 1529 g_free(s); 1530 } 1531 1532 static Aml *build_q35_routing_table(const char *str) 1533 { 1534 int i; 1535 Aml *pkg; 1536 char *name = g_strdup_printf("%s ", str); 1537 1538 pkg = aml_package(128); 1539 for (i = 0; i < 0x18; i++) { 1540 name[3] = 'E' + (i & 0x3); 1541 append_q35_prt_entry(pkg, i, name); 1542 } 1543 1544 name[3] = 'E'; 1545 append_q35_prt_entry(pkg, 0x18, name); 1546 1547 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1548 for (i = 0x0019; i < 0x1e; i++) { 1549 name[3] = 'A'; 1550 append_q35_prt_entry(pkg, i, name); 1551 } 1552 1553 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1554 name[3] = 'E'; 1555 append_q35_prt_entry(pkg, 0x1e, name); 1556 name[3] = 'A'; 1557 append_q35_prt_entry(pkg, 0x1f, name); 1558 1559 g_free(name); 1560 return pkg; 1561 } 1562 1563 static void build_q35_pci0_int(Aml *table) 1564 { 1565 Aml *field; 1566 Aml *method; 1567 Aml *sb_scope = aml_scope("_SB"); 1568 Aml *pci0_scope = aml_scope("PCI0"); 1569 1570 /* Zero => PIC mode, One => APIC Mode */ 1571 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1572 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1573 { 1574 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1575 } 1576 aml_append(table, method); 1577 1578 aml_append(pci0_scope, 1579 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1580 aml_append(pci0_scope, 1581 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1582 1583 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1584 { 1585 Aml *if_ctx; 1586 Aml *else_ctx; 1587 1588 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1589 section 6.2.8.1 */ 1590 /* Note: we provide the same info as the PCI routing 1591 table of the Bochs BIOS */ 1592 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1593 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1594 aml_append(method, if_ctx); 1595 else_ctx = aml_else(); 1596 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1597 aml_append(method, else_ctx); 1598 } 1599 aml_append(pci0_scope, method); 1600 aml_append(sb_scope, pci0_scope); 1601 1602 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1603 aml_append(field, aml_named_field("PRQA", 8)); 1604 aml_append(field, aml_named_field("PRQB", 8)); 1605 aml_append(field, aml_named_field("PRQC", 8)); 1606 aml_append(field, aml_named_field("PRQD", 8)); 1607 aml_append(field, aml_reserved_field(0x20)); 1608 aml_append(field, aml_named_field("PRQE", 8)); 1609 aml_append(field, aml_named_field("PRQF", 8)); 1610 aml_append(field, aml_named_field("PRQG", 8)); 1611 aml_append(field, aml_named_field("PRQH", 8)); 1612 aml_append(sb_scope, field); 1613 1614 aml_append(sb_scope, build_irq_status_method()); 1615 aml_append(sb_scope, build_iqcr_method(false)); 1616 1617 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1618 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1619 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1620 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1621 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1622 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1623 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1624 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1625 1626 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1627 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1628 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1629 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1630 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1631 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1632 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1633 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1634 1635 aml_append(table, sb_scope); 1636 } 1637 1638 static void build_q35_isa_bridge(Aml *table) 1639 { 1640 Aml *dev; 1641 Aml *scope; 1642 Aml *field; 1643 1644 scope = aml_scope("_SB.PCI0"); 1645 dev = aml_device("ISA"); 1646 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1647 1648 /* ICH9 PCI to ISA irq remapping */ 1649 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1650 aml_int(0x60), 0x0C)); 1651 1652 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1653 aml_int(0x80), 0x02)); 1654 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1655 aml_append(field, aml_named_field("COMA", 3)); 1656 aml_append(field, aml_reserved_field(1)); 1657 aml_append(field, aml_named_field("COMB", 3)); 1658 aml_append(field, aml_reserved_field(1)); 1659 aml_append(field, aml_named_field("LPTD", 2)); 1660 aml_append(dev, field); 1661 1662 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1663 aml_int(0x82), 0x02)); 1664 /* enable bits */ 1665 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1666 aml_append(field, aml_named_field("CAEN", 1)); 1667 aml_append(field, aml_named_field("CBEN", 1)); 1668 aml_append(field, aml_named_field("LPEN", 1)); 1669 aml_append(dev, field); 1670 1671 aml_append(scope, dev); 1672 aml_append(table, scope); 1673 } 1674 1675 static void build_piix4_pm(Aml *table) 1676 { 1677 Aml *dev; 1678 Aml *scope; 1679 1680 scope = aml_scope("_SB.PCI0"); 1681 dev = aml_device("PX13"); 1682 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1683 1684 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1685 aml_int(0x00), 0xff)); 1686 aml_append(scope, dev); 1687 aml_append(table, scope); 1688 } 1689 1690 static void build_piix4_isa_bridge(Aml *table) 1691 { 1692 Aml *dev; 1693 Aml *scope; 1694 Aml *field; 1695 1696 scope = aml_scope("_SB.PCI0"); 1697 dev = aml_device("ISA"); 1698 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1699 1700 /* PIIX PCI to ISA irq remapping */ 1701 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1702 aml_int(0x60), 0x04)); 1703 /* enable bits */ 1704 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1705 /* Offset(0x5f),, 7, */ 1706 aml_append(field, aml_reserved_field(0x2f8)); 1707 aml_append(field, aml_reserved_field(7)); 1708 aml_append(field, aml_named_field("LPEN", 1)); 1709 /* Offset(0x67),, 3, */ 1710 aml_append(field, aml_reserved_field(0x38)); 1711 aml_append(field, aml_reserved_field(3)); 1712 aml_append(field, aml_named_field("CAEN", 1)); 1713 aml_append(field, aml_reserved_field(3)); 1714 aml_append(field, aml_named_field("CBEN", 1)); 1715 aml_append(dev, field); 1716 1717 aml_append(scope, dev); 1718 aml_append(table, scope); 1719 } 1720 1721 static void build_piix4_pci_hotplug(Aml *table) 1722 { 1723 Aml *scope; 1724 Aml *field; 1725 Aml *method; 1726 1727 scope = aml_scope("_SB.PCI0"); 1728 1729 aml_append(scope, 1730 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1731 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1732 aml_append(field, aml_named_field("PCIU", 32)); 1733 aml_append(field, aml_named_field("PCID", 32)); 1734 aml_append(scope, field); 1735 1736 aml_append(scope, 1737 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1738 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1739 aml_append(field, aml_named_field("B0EJ", 32)); 1740 aml_append(scope, field); 1741 1742 aml_append(scope, 1743 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1744 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1745 aml_append(field, aml_named_field("BNUM", 32)); 1746 aml_append(scope, field); 1747 1748 aml_append(scope, aml_mutex("BLCK", 0)); 1749 1750 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1751 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1752 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1753 aml_append(method, 1754 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1755 aml_append(method, aml_release(aml_name("BLCK"))); 1756 aml_append(method, aml_return(aml_int(0))); 1757 aml_append(scope, method); 1758 1759 aml_append(table, scope); 1760 } 1761 1762 static Aml *build_q35_osc_method(void) 1763 { 1764 Aml *if_ctx; 1765 Aml *if_ctx2; 1766 Aml *else_ctx; 1767 Aml *method; 1768 Aml *a_cwd1 = aml_name("CDW1"); 1769 Aml *a_ctrl = aml_local(0); 1770 1771 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1772 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1773 1774 if_ctx = aml_if(aml_equal( 1775 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1776 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1777 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1778 1779 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1780 1781 /* 1782 * Always allow native PME, AER (no dependencies) 1783 * Allow SHPC (PCI bridges can have SHPC controller) 1784 */ 1785 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1786 1787 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1788 /* Unknown revision */ 1789 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1790 aml_append(if_ctx, if_ctx2); 1791 1792 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1793 /* Capabilities bits were masked */ 1794 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1795 aml_append(if_ctx, if_ctx2); 1796 1797 /* Update DWORD3 in the buffer */ 1798 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1799 aml_append(method, if_ctx); 1800 1801 else_ctx = aml_else(); 1802 /* Unrecognized UUID */ 1803 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1804 aml_append(method, else_ctx); 1805 1806 aml_append(method, aml_return(aml_arg(3))); 1807 return method; 1808 } 1809 1810 static void 1811 build_dsdt(GArray *table_data, BIOSLinker *linker, 1812 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1813 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1814 { 1815 CrsRangeEntry *entry; 1816 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1817 CrsRangeSet crs_range_set; 1818 PCMachineState *pcms = PC_MACHINE(machine); 1819 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1820 AcpiMcfgInfo mcfg; 1821 uint32_t nr_mem = machine->ram_slots; 1822 int root_bus_limit = 0xFF; 1823 PCIBus *bus = NULL; 1824 TPMIf *tpm = tpm_find(); 1825 int i; 1826 1827 dsdt = init_aml_allocator(); 1828 1829 /* Reserve space for header */ 1830 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1831 1832 build_dbg_aml(dsdt); 1833 if (misc->is_piix4) { 1834 sb_scope = aml_scope("_SB"); 1835 dev = aml_device("PCI0"); 1836 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1837 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1838 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1839 aml_append(sb_scope, dev); 1840 aml_append(dsdt, sb_scope); 1841 1842 build_hpet_aml(dsdt); 1843 build_piix4_pm(dsdt); 1844 build_piix4_isa_bridge(dsdt); 1845 build_isa_devices_aml(dsdt); 1846 build_piix4_pci_hotplug(dsdt); 1847 build_piix4_pci0_int(dsdt); 1848 } else { 1849 sb_scope = aml_scope("_SB"); 1850 dev = aml_device("PCI0"); 1851 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1852 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1853 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1854 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1855 aml_append(dev, build_q35_osc_method()); 1856 aml_append(sb_scope, dev); 1857 aml_append(dsdt, sb_scope); 1858 1859 build_hpet_aml(dsdt); 1860 build_q35_isa_bridge(dsdt); 1861 build_isa_devices_aml(dsdt); 1862 build_q35_pci0_int(dsdt); 1863 } 1864 1865 if (pcmc->legacy_cpu_hotplug) { 1866 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1867 } else { 1868 CPUHotplugFeatures opts = { 1869 .acpi_1_compatible = true, .has_legacy_cphp = true 1870 }; 1871 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1872 "\\_SB.PCI0", "\\_GPE._E02"); 1873 } 1874 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03"); 1875 1876 scope = aml_scope("_GPE"); 1877 { 1878 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1879 1880 if (misc->is_piix4) { 1881 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1882 aml_append(method, 1883 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1884 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1885 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1886 aml_append(scope, method); 1887 } 1888 1889 if (machine->nvdimms_state->is_enabled) { 1890 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1891 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1892 aml_int(0x80))); 1893 aml_append(scope, method); 1894 } 1895 } 1896 aml_append(dsdt, scope); 1897 1898 crs_range_set_init(&crs_range_set); 1899 bus = PC_MACHINE(machine)->bus; 1900 if (bus) { 1901 QLIST_FOREACH(bus, &bus->child, sibling) { 1902 uint8_t bus_num = pci_bus_num(bus); 1903 uint8_t numa_node = pci_bus_numa_node(bus); 1904 1905 /* look only for expander root buses */ 1906 if (!pci_bus_is_root(bus)) { 1907 continue; 1908 } 1909 1910 if (bus_num < root_bus_limit) { 1911 root_bus_limit = bus_num - 1; 1912 } 1913 1914 scope = aml_scope("\\_SB"); 1915 dev = aml_device("PC%.02X", bus_num); 1916 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1917 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1918 if (pci_bus_is_express(bus)) { 1919 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1920 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1921 aml_append(dev, build_q35_osc_method()); 1922 } else { 1923 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1924 } 1925 1926 if (numa_node != NUMA_NODE_UNASSIGNED) { 1927 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1928 } 1929 1930 aml_append(dev, build_prt(false)); 1931 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1932 aml_append(dev, aml_name_decl("_CRS", crs)); 1933 aml_append(scope, dev); 1934 aml_append(dsdt, scope); 1935 } 1936 } 1937 1938 /* 1939 * At this point crs_range_set has all the ranges used by pci 1940 * busses *other* than PCI0. These ranges will be excluded from 1941 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1942 * too. 1943 */ 1944 if (acpi_get_mcfg(&mcfg)) { 1945 crs_range_insert(crs_range_set.mem_ranges, 1946 mcfg.base, mcfg.base + mcfg.size - 1); 1947 } 1948 1949 scope = aml_scope("\\_SB.PCI0"); 1950 /* build PCI0._CRS */ 1951 crs = aml_resource_template(); 1952 aml_append(crs, 1953 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1954 0x0000, 0x0, root_bus_limit, 1955 0x0000, root_bus_limit + 1)); 1956 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1957 1958 aml_append(crs, 1959 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1960 AML_POS_DECODE, AML_ENTIRE_RANGE, 1961 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1962 1963 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1964 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1965 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1966 aml_append(crs, 1967 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1968 AML_POS_DECODE, AML_ENTIRE_RANGE, 1969 0x0000, entry->base, entry->limit, 1970 0x0000, entry->limit - entry->base + 1)); 1971 } 1972 1973 aml_append(crs, 1974 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1975 AML_CACHEABLE, AML_READ_WRITE, 1976 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1977 1978 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1979 range_lob(pci_hole), 1980 range_upb(pci_hole)); 1981 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1982 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1983 aml_append(crs, 1984 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1985 AML_NON_CACHEABLE, AML_READ_WRITE, 1986 0, entry->base, entry->limit, 1987 0, entry->limit - entry->base + 1)); 1988 } 1989 1990 if (!range_is_empty(pci_hole64)) { 1991 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1992 range_lob(pci_hole64), 1993 range_upb(pci_hole64)); 1994 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1995 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1996 aml_append(crs, 1997 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1998 AML_MAX_FIXED, 1999 AML_CACHEABLE, AML_READ_WRITE, 2000 0, entry->base, entry->limit, 2001 0, entry->limit - entry->base + 1)); 2002 } 2003 } 2004 2005 if (TPM_IS_TIS(tpm_find())) { 2006 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2007 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2008 } 2009 aml_append(scope, aml_name_decl("_CRS", crs)); 2010 2011 /* reserve GPE0 block resources */ 2012 dev = aml_device("GPE0"); 2013 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2014 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2015 /* device present, functioning, decoding, not shown in UI */ 2016 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2017 crs = aml_resource_template(); 2018 aml_append(crs, 2019 aml_io( 2020 AML_DECODE16, 2021 pm->fadt.gpe0_blk.address, 2022 pm->fadt.gpe0_blk.address, 2023 1, 2024 pm->fadt.gpe0_blk.bit_width / 8) 2025 ); 2026 aml_append(dev, aml_name_decl("_CRS", crs)); 2027 aml_append(scope, dev); 2028 2029 crs_range_set_free(&crs_range_set); 2030 2031 /* reserve PCIHP resources */ 2032 if (pm->pcihp_io_len) { 2033 dev = aml_device("PHPR"); 2034 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2035 aml_append(dev, 2036 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2037 /* device present, functioning, decoding, not shown in UI */ 2038 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2039 crs = aml_resource_template(); 2040 aml_append(crs, 2041 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2042 pm->pcihp_io_len) 2043 ); 2044 aml_append(dev, aml_name_decl("_CRS", crs)); 2045 aml_append(scope, dev); 2046 } 2047 aml_append(dsdt, scope); 2048 2049 /* create S3_ / S4_ / S5_ packages if necessary */ 2050 scope = aml_scope("\\"); 2051 if (!pm->s3_disabled) { 2052 pkg = aml_package(4); 2053 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2054 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2055 aml_append(pkg, aml_int(0)); /* reserved */ 2056 aml_append(pkg, aml_int(0)); /* reserved */ 2057 aml_append(scope, aml_name_decl("_S3", pkg)); 2058 } 2059 2060 if (!pm->s4_disabled) { 2061 pkg = aml_package(4); 2062 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2063 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2064 aml_append(pkg, aml_int(pm->s4_val)); 2065 aml_append(pkg, aml_int(0)); /* reserved */ 2066 aml_append(pkg, aml_int(0)); /* reserved */ 2067 aml_append(scope, aml_name_decl("_S4", pkg)); 2068 } 2069 2070 pkg = aml_package(4); 2071 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2072 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2073 aml_append(pkg, aml_int(0)); /* reserved */ 2074 aml_append(pkg, aml_int(0)); /* reserved */ 2075 aml_append(scope, aml_name_decl("_S5", pkg)); 2076 aml_append(dsdt, scope); 2077 2078 /* create fw_cfg node, unconditionally */ 2079 { 2080 /* when using port i/o, the 8-bit data register *always* overlaps 2081 * with half of the 16-bit control register. Hence, the total size 2082 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2083 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2084 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2085 "dma_enabled", NULL) ? 2086 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2087 FW_CFG_CTL_SIZE; 2088 2089 scope = aml_scope("\\_SB.PCI0"); 2090 dev = aml_device("FWCF"); 2091 2092 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2093 2094 /* device present, functioning, decoding, not shown in UI */ 2095 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2096 2097 crs = aml_resource_template(); 2098 aml_append(crs, 2099 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2100 ); 2101 aml_append(dev, aml_name_decl("_CRS", crs)); 2102 2103 aml_append(scope, dev); 2104 aml_append(dsdt, scope); 2105 } 2106 2107 if (misc->applesmc_io_base) { 2108 scope = aml_scope("\\_SB.PCI0.ISA"); 2109 dev = aml_device("SMC"); 2110 2111 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2112 /* device present, functioning, decoding, not shown in UI */ 2113 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2114 2115 crs = aml_resource_template(); 2116 aml_append(crs, 2117 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2118 0x01, APPLESMC_MAX_DATA_LENGTH) 2119 ); 2120 aml_append(crs, aml_irq_no_flags(6)); 2121 aml_append(dev, aml_name_decl("_CRS", crs)); 2122 2123 aml_append(scope, dev); 2124 aml_append(dsdt, scope); 2125 } 2126 2127 if (misc->pvpanic_port) { 2128 scope = aml_scope("\\_SB.PCI0.ISA"); 2129 2130 dev = aml_device("PEVT"); 2131 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2132 2133 crs = aml_resource_template(); 2134 aml_append(crs, 2135 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2136 ); 2137 aml_append(dev, aml_name_decl("_CRS", crs)); 2138 2139 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2140 aml_int(misc->pvpanic_port), 1)); 2141 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2142 aml_append(field, aml_named_field("PEPT", 8)); 2143 aml_append(dev, field); 2144 2145 /* device present, functioning, decoding, shown in UI */ 2146 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2147 2148 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2149 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2150 aml_append(method, aml_return(aml_local(0))); 2151 aml_append(dev, method); 2152 2153 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2154 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2155 aml_append(dev, method); 2156 2157 aml_append(scope, dev); 2158 aml_append(dsdt, scope); 2159 } 2160 2161 sb_scope = aml_scope("\\_SB"); 2162 { 2163 Object *pci_host; 2164 PCIBus *bus = NULL; 2165 2166 pci_host = acpi_get_i386_pci_host(); 2167 if (pci_host) { 2168 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2169 } 2170 2171 if (bus) { 2172 Aml *scope = aml_scope("PCI0"); 2173 /* Scan all PCI buses. Generate tables to support hotplug. */ 2174 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2175 2176 if (TPM_IS_TIS(tpm)) { 2177 if (misc->tpm_version == TPM_VERSION_2_0) { 2178 dev = aml_device("TPM"); 2179 aml_append(dev, aml_name_decl("_HID", 2180 aml_string("MSFT0101"))); 2181 } else { 2182 dev = aml_device("ISA.TPM"); 2183 aml_append(dev, aml_name_decl("_HID", 2184 aml_eisaid("PNP0C31"))); 2185 } 2186 2187 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2188 crs = aml_resource_template(); 2189 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2190 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2191 /* 2192 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2193 Rewrite to take IRQ from TPM device model and 2194 fix default IRQ value there to use some unused IRQ 2195 */ 2196 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2197 aml_append(dev, aml_name_decl("_CRS", crs)); 2198 2199 tpm_build_ppi_acpi(tpm, dev); 2200 2201 aml_append(scope, dev); 2202 } 2203 2204 aml_append(sb_scope, scope); 2205 } 2206 } 2207 2208 if (TPM_IS_CRB(tpm)) { 2209 dev = aml_device("TPM"); 2210 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 2211 crs = aml_resource_template(); 2212 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 2213 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 2214 aml_append(dev, aml_name_decl("_CRS", crs)); 2215 2216 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 2217 aml_append(method, aml_return(aml_int(0x0f))); 2218 aml_append(dev, method); 2219 2220 tpm_build_ppi_acpi(tpm, dev); 2221 2222 aml_append(sb_scope, dev); 2223 } 2224 2225 aml_append(dsdt, sb_scope); 2226 2227 /* copy AML table into ACPI tables blob and patch header there */ 2228 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2229 build_header(linker, table_data, 2230 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2231 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2232 free_aml_allocator(); 2233 } 2234 2235 static void 2236 build_hpet(GArray *table_data, BIOSLinker *linker) 2237 { 2238 Acpi20Hpet *hpet; 2239 2240 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2241 /* Note timer_block_id value must be kept in sync with value advertised by 2242 * emulated hpet 2243 */ 2244 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2245 hpet->addr.address = cpu_to_le64(HPET_BASE); 2246 build_header(linker, table_data, 2247 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2248 } 2249 2250 static void 2251 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2252 { 2253 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2254 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2255 unsigned log_addr_offset = 2256 (char *)&tcpa->log_area_start_address - table_data->data; 2257 2258 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2259 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2260 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2261 2262 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2263 false /* high memory */); 2264 2265 /* log area start address to be filled by Guest linker */ 2266 bios_linker_loader_add_pointer(linker, 2267 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2268 ACPI_BUILD_TPMLOG_FILE, 0); 2269 2270 build_header(linker, table_data, 2271 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2272 } 2273 2274 static void 2275 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2276 { 2277 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2278 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address); 2279 unsigned log_addr_offset = 2280 (char *)&tpm2_ptr->log_area_start_address - table_data->data; 2281 2282 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2283 if (TPM_IS_TIS(tpm_find())) { 2284 tpm2_ptr->control_area_address = cpu_to_le64(0); 2285 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2286 } else if (TPM_IS_CRB(tpm_find())) { 2287 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL); 2288 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB); 2289 } else { 2290 g_warn_if_reached(); 2291 } 2292 2293 tpm2_ptr->log_area_minimum_length = 2294 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2295 2296 /* log area start address to be filled by Guest linker */ 2297 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2298 log_addr_offset, log_addr_size, 2299 ACPI_BUILD_TPMLOG_FILE, 0); 2300 build_header(linker, table_data, 2301 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2302 } 2303 2304 #define HOLE_640K_START (640 * KiB) 2305 #define HOLE_640K_END (1 * MiB) 2306 2307 static void 2308 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2309 { 2310 AcpiSystemResourceAffinityTable *srat; 2311 AcpiSratMemoryAffinity *numamem; 2312 2313 int i; 2314 int srat_start, numa_start, slots; 2315 uint64_t mem_len, mem_base, next_base; 2316 MachineClass *mc = MACHINE_GET_CLASS(machine); 2317 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2318 PCMachineState *pcms = PC_MACHINE(machine); 2319 ram_addr_t hotplugabble_address_space_size = 2320 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 2321 NULL); 2322 2323 srat_start = table_data->len; 2324 2325 srat = acpi_data_push(table_data, sizeof *srat); 2326 srat->reserved1 = cpu_to_le32(1); 2327 2328 for (i = 0; i < apic_ids->len; i++) { 2329 int node_id = apic_ids->cpus[i].props.node_id; 2330 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2331 2332 if (apic_id < 255) { 2333 AcpiSratProcessorAffinity *core; 2334 2335 core = acpi_data_push(table_data, sizeof *core); 2336 core->type = ACPI_SRAT_PROCESSOR_APIC; 2337 core->length = sizeof(*core); 2338 core->local_apic_id = apic_id; 2339 core->proximity_lo = node_id; 2340 memset(core->proximity_hi, 0, 3); 2341 core->local_sapic_eid = 0; 2342 core->flags = cpu_to_le32(1); 2343 } else { 2344 AcpiSratProcessorX2ApicAffinity *core; 2345 2346 core = acpi_data_push(table_data, sizeof *core); 2347 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2348 core->length = sizeof(*core); 2349 core->x2apic_id = cpu_to_le32(apic_id); 2350 core->proximity_domain = cpu_to_le32(node_id); 2351 core->flags = cpu_to_le32(1); 2352 } 2353 } 2354 2355 2356 /* the memory map is a bit tricky, it contains at least one hole 2357 * from 640k-1M and possibly another one from 3.5G-4G. 2358 */ 2359 next_base = 0; 2360 numa_start = table_data->len; 2361 2362 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2363 mem_base = next_base; 2364 mem_len = pcms->node_mem[i - 1]; 2365 next_base = mem_base + mem_len; 2366 2367 /* Cut out the 640K hole */ 2368 if (mem_base <= HOLE_640K_START && 2369 next_base > HOLE_640K_START) { 2370 mem_len -= next_base - HOLE_640K_START; 2371 if (mem_len > 0) { 2372 numamem = acpi_data_push(table_data, sizeof *numamem); 2373 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2374 MEM_AFFINITY_ENABLED); 2375 } 2376 2377 /* Check for the rare case: 640K < RAM < 1M */ 2378 if (next_base <= HOLE_640K_END) { 2379 next_base = HOLE_640K_END; 2380 continue; 2381 } 2382 mem_base = HOLE_640K_END; 2383 mem_len = next_base - HOLE_640K_END; 2384 } 2385 2386 /* Cut out the ACPI_PCI hole */ 2387 if (mem_base <= pcms->below_4g_mem_size && 2388 next_base > pcms->below_4g_mem_size) { 2389 mem_len -= next_base - pcms->below_4g_mem_size; 2390 if (mem_len > 0) { 2391 numamem = acpi_data_push(table_data, sizeof *numamem); 2392 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2393 MEM_AFFINITY_ENABLED); 2394 } 2395 mem_base = 1ULL << 32; 2396 mem_len = next_base - pcms->below_4g_mem_size; 2397 next_base = mem_base + mem_len; 2398 } 2399 2400 if (mem_len > 0) { 2401 numamem = acpi_data_push(table_data, sizeof *numamem); 2402 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2403 MEM_AFFINITY_ENABLED); 2404 } 2405 } 2406 slots = (table_data->len - numa_start) / sizeof *numamem; 2407 for (; slots < pcms->numa_nodes + 2; slots++) { 2408 numamem = acpi_data_push(table_data, sizeof *numamem); 2409 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2410 } 2411 2412 /* 2413 * Entry is required for Windows to enable memory hotplug in OS 2414 * and for Linux to enable SWIOTLB when booted with less than 2415 * 4G of RAM. Windows works better if the entry sets proximity 2416 * to the highest NUMA node in the machine. 2417 * Memory devices may override proximity set by this entry, 2418 * providing _PXM method if necessary. 2419 */ 2420 if (hotplugabble_address_space_size) { 2421 numamem = acpi_data_push(table_data, sizeof *numamem); 2422 build_srat_memory(numamem, machine->device_memory->base, 2423 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2424 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2425 } 2426 2427 build_header(linker, table_data, 2428 (void *)(table_data->data + srat_start), 2429 "SRAT", 2430 table_data->len - srat_start, 1, NULL, NULL); 2431 } 2432 2433 /* 2434 * VT-d spec 8.1 DMA Remapping Reporting Structure 2435 * (version Oct. 2014 or later) 2436 */ 2437 static void 2438 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2439 { 2440 int dmar_start = table_data->len; 2441 2442 AcpiTableDmar *dmar; 2443 AcpiDmarHardwareUnit *drhd; 2444 AcpiDmarRootPortATS *atsr; 2445 uint8_t dmar_flags = 0; 2446 X86IOMMUState *iommu = x86_iommu_get_default(); 2447 AcpiDmarDeviceScope *scope = NULL; 2448 /* Root complex IOAPIC use one path[0] only */ 2449 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2450 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2451 2452 assert(iommu); 2453 if (x86_iommu_ir_supported(iommu)) { 2454 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2455 } 2456 2457 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2458 dmar->host_address_width = intel_iommu->aw_bits - 1; 2459 dmar->flags = dmar_flags; 2460 2461 /* DMAR Remapping Hardware Unit Definition structure */ 2462 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2463 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2464 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2465 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2466 drhd->pci_segment = cpu_to_le16(0); 2467 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2468 2469 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2470 * 8.3.1 (version Oct. 2014 or later). */ 2471 scope = &drhd->scope[0]; 2472 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2473 scope->length = ioapic_scope_size; 2474 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2475 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2476 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2477 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2478 2479 if (iommu->dt_supported) { 2480 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2481 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2482 atsr->length = cpu_to_le16(sizeof(*atsr)); 2483 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2484 atsr->pci_segment = cpu_to_le16(0); 2485 } 2486 2487 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2488 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2489 } 2490 /* 2491 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2492 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2493 */ 2494 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2495 2496 static void 2497 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2498 { 2499 int ivhd_table_len = 28; 2500 int iommu_start = table_data->len; 2501 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2502 2503 /* IVRS header */ 2504 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2505 /* IVinfo - IO virtualization information common to all 2506 * IOMMU units in a system 2507 */ 2508 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2509 /* reserved */ 2510 build_append_int_noprefix(table_data, 0, 8); 2511 2512 /* IVHD definition - type 10h */ 2513 build_append_int_noprefix(table_data, 0x10, 1); 2514 /* virtualization flags */ 2515 build_append_int_noprefix(table_data, 2516 (1UL << 0) | /* HtTunEn */ 2517 (1UL << 4) | /* iotblSup */ 2518 (1UL << 6) | /* PrefSup */ 2519 (1UL << 7), /* PPRSup */ 2520 1); 2521 2522 /* 2523 * When interrupt remapping is supported, we add a special IVHD device 2524 * for type IO-APIC. 2525 */ 2526 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2527 ivhd_table_len += 8; 2528 } 2529 /* IVHD length */ 2530 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2531 /* DeviceID */ 2532 build_append_int_noprefix(table_data, s->devid, 2); 2533 /* Capability offset */ 2534 build_append_int_noprefix(table_data, s->capab_offset, 2); 2535 /* IOMMU base address */ 2536 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2537 /* PCI Segment Group */ 2538 build_append_int_noprefix(table_data, 0, 2); 2539 /* IOMMU info */ 2540 build_append_int_noprefix(table_data, 0, 2); 2541 /* IOMMU Feature Reporting */ 2542 build_append_int_noprefix(table_data, 2543 (48UL << 30) | /* HATS */ 2544 (48UL << 28) | /* GATS */ 2545 (1UL << 2) | /* GTSup */ 2546 (1UL << 6), /* GASup */ 2547 4); 2548 /* 2549 * Type 1 device entry reporting all devices 2550 * These are 4-byte device entries currently reporting the range of 2551 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2552 */ 2553 build_append_int_noprefix(table_data, 0x0000001, 4); 2554 2555 /* 2556 * Add a special IVHD device type. 2557 * Refer to spec - Table 95: IVHD device entry type codes 2558 * 2559 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2560 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2561 */ 2562 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2563 build_append_int_noprefix(table_data, 2564 (0x1ull << 56) | /* type IOAPIC */ 2565 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2566 0x48, /* special device */ 2567 8); 2568 } 2569 2570 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2571 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2572 } 2573 2574 typedef 2575 struct AcpiBuildState { 2576 /* Copy of table in RAM (for patching). */ 2577 MemoryRegion *table_mr; 2578 /* Is table patched? */ 2579 uint8_t patched; 2580 void *rsdp; 2581 MemoryRegion *rsdp_mr; 2582 MemoryRegion *linker_mr; 2583 } AcpiBuildState; 2584 2585 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2586 { 2587 Object *pci_host; 2588 QObject *o; 2589 2590 pci_host = acpi_get_i386_pci_host(); 2591 g_assert(pci_host); 2592 2593 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2594 if (!o) { 2595 return false; 2596 } 2597 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2598 qobject_unref(o); 2599 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2600 return false; 2601 } 2602 2603 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2604 assert(o); 2605 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2606 qobject_unref(o); 2607 return true; 2608 } 2609 2610 static 2611 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2612 { 2613 PCMachineState *pcms = PC_MACHINE(machine); 2614 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2615 GArray *table_offsets; 2616 unsigned facs, dsdt, rsdt, fadt; 2617 AcpiPmInfo pm; 2618 AcpiMiscInfo misc; 2619 AcpiMcfgInfo mcfg; 2620 Range pci_hole, pci_hole64; 2621 uint8_t *u; 2622 size_t aml_len = 0; 2623 GArray *tables_blob = tables->table_data; 2624 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2625 Object *vmgenid_dev; 2626 2627 acpi_get_pm_info(machine, &pm); 2628 acpi_get_misc_info(&misc); 2629 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2630 acpi_get_slic_oem(&slic_oem); 2631 2632 table_offsets = g_array_new(false, true /* clear */, 2633 sizeof(uint32_t)); 2634 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2635 2636 bios_linker_loader_alloc(tables->linker, 2637 ACPI_BUILD_TABLE_FILE, tables_blob, 2638 64 /* Ensure FACS is aligned */, 2639 false /* high memory */); 2640 2641 /* 2642 * FACS is pointed to by FADT. 2643 * We place it first since it's the only table that has alignment 2644 * requirements. 2645 */ 2646 facs = tables_blob->len; 2647 build_facs(tables_blob); 2648 2649 /* DSDT is pointed to by FADT */ 2650 dsdt = tables_blob->len; 2651 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2652 &pci_hole, &pci_hole64, machine); 2653 2654 /* Count the size of the DSDT and SSDT, we will need it for legacy 2655 * sizing of ACPI tables. 2656 */ 2657 aml_len += tables_blob->len - dsdt; 2658 2659 /* ACPI tables pointed to by RSDT */ 2660 fadt = tables_blob->len; 2661 acpi_add_table(table_offsets, tables_blob); 2662 pm.fadt.facs_tbl_offset = &facs; 2663 pm.fadt.dsdt_tbl_offset = &dsdt; 2664 pm.fadt.xdsdt_tbl_offset = &dsdt; 2665 build_fadt(tables_blob, tables->linker, &pm.fadt, 2666 slic_oem.id, slic_oem.table_id); 2667 aml_len += tables_blob->len - fadt; 2668 2669 acpi_add_table(table_offsets, tables_blob); 2670 build_madt(tables_blob, tables->linker, pcms); 2671 2672 vmgenid_dev = find_vmgenid_dev(); 2673 if (vmgenid_dev) { 2674 acpi_add_table(table_offsets, tables_blob); 2675 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2676 tables->vmgenid, tables->linker); 2677 } 2678 2679 if (misc.has_hpet) { 2680 acpi_add_table(table_offsets, tables_blob); 2681 build_hpet(tables_blob, tables->linker); 2682 } 2683 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2684 acpi_add_table(table_offsets, tables_blob); 2685 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2686 2687 if (misc.tpm_version == TPM_VERSION_2_0) { 2688 acpi_add_table(table_offsets, tables_blob); 2689 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2690 } 2691 } 2692 if (pcms->numa_nodes) { 2693 acpi_add_table(table_offsets, tables_blob); 2694 build_srat(tables_blob, tables->linker, machine); 2695 if (have_numa_distance) { 2696 acpi_add_table(table_offsets, tables_blob); 2697 build_slit(tables_blob, tables->linker); 2698 } 2699 } 2700 if (acpi_get_mcfg(&mcfg)) { 2701 acpi_add_table(table_offsets, tables_blob); 2702 build_mcfg(tables_blob, tables->linker, &mcfg); 2703 } 2704 if (x86_iommu_get_default()) { 2705 IommuType IOMMUType = x86_iommu_get_type(); 2706 if (IOMMUType == TYPE_AMD) { 2707 acpi_add_table(table_offsets, tables_blob); 2708 build_amd_iommu(tables_blob, tables->linker); 2709 } else if (IOMMUType == TYPE_INTEL) { 2710 acpi_add_table(table_offsets, tables_blob); 2711 build_dmar_q35(tables_blob, tables->linker); 2712 } 2713 } 2714 if (machine->nvdimms_state->is_enabled) { 2715 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2716 machine->nvdimms_state, machine->ram_slots); 2717 } 2718 2719 /* Add tables supplied by user (if any) */ 2720 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2721 unsigned len = acpi_table_len(u); 2722 2723 acpi_add_table(table_offsets, tables_blob); 2724 g_array_append_vals(tables_blob, u, len); 2725 } 2726 2727 /* RSDT is pointed to by RSDP */ 2728 rsdt = tables_blob->len; 2729 build_rsdt(tables_blob, tables->linker, table_offsets, 2730 slic_oem.id, slic_oem.table_id); 2731 2732 /* RSDP is in FSEG memory, so allocate it separately */ 2733 { 2734 AcpiRsdpData rsdp_data = { 2735 .revision = 0, 2736 .oem_id = ACPI_BUILD_APPNAME6, 2737 .xsdt_tbl_offset = NULL, 2738 .rsdt_tbl_offset = &rsdt, 2739 }; 2740 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2741 if (!pcmc->rsdp_in_ram) { 2742 /* We used to allocate some extra space for RSDP revision 2 but 2743 * only used the RSDP revision 0 space. The extra bytes were 2744 * zeroed out and not used. 2745 * Here we continue wasting those extra 16 bytes to make sure we 2746 * don't break migration for machine types 2.2 and older due to 2747 * RSDP blob size mismatch. 2748 */ 2749 build_append_int_noprefix(tables->rsdp, 0, 16); 2750 } 2751 } 2752 2753 /* We'll expose it all to Guest so we want to reduce 2754 * chance of size changes. 2755 * 2756 * We used to align the tables to 4k, but of course this would 2757 * too simple to be enough. 4k turned out to be too small an 2758 * alignment very soon, and in fact it is almost impossible to 2759 * keep the table size stable for all (max_cpus, max_memory_slots) 2760 * combinations. So the table size is always 64k for pc-i440fx-2.1 2761 * and we give an error if the table grows beyond that limit. 2762 * 2763 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2764 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2765 * than 2.0 and we can always pad the smaller tables with zeros. We can 2766 * then use the exact size of the 2.0 tables. 2767 * 2768 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2769 */ 2770 if (pcmc->legacy_acpi_table_size) { 2771 /* Subtracting aml_len gives the size of fixed tables. Then add the 2772 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2773 */ 2774 int legacy_aml_len = 2775 pcmc->legacy_acpi_table_size + 2776 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit; 2777 int legacy_table_size = 2778 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2779 ACPI_BUILD_ALIGN_SIZE); 2780 if (tables_blob->len > legacy_table_size) { 2781 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2782 warn_report("ACPI table size %u exceeds %d bytes," 2783 " migration may not work", 2784 tables_blob->len, legacy_table_size); 2785 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2786 " or PCI bridges."); 2787 } 2788 g_array_set_size(tables_blob, legacy_table_size); 2789 } else { 2790 /* Make sure we have a buffer in case we need to resize the tables. */ 2791 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2792 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2793 warn_report("ACPI table size %u exceeds %d bytes," 2794 " migration may not work", 2795 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2796 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2797 " or PCI bridges."); 2798 } 2799 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2800 } 2801 2802 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2803 2804 /* Cleanup memory that's no longer used. */ 2805 g_array_free(table_offsets, true); 2806 } 2807 2808 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2809 { 2810 uint32_t size = acpi_data_len(data); 2811 2812 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2813 memory_region_ram_resize(mr, size, &error_abort); 2814 2815 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2816 memory_region_set_dirty(mr, 0, size); 2817 } 2818 2819 static void acpi_build_update(void *build_opaque) 2820 { 2821 AcpiBuildState *build_state = build_opaque; 2822 AcpiBuildTables tables; 2823 2824 /* No state to update or already patched? Nothing to do. */ 2825 if (!build_state || build_state->patched) { 2826 return; 2827 } 2828 build_state->patched = 1; 2829 2830 acpi_build_tables_init(&tables); 2831 2832 acpi_build(&tables, MACHINE(qdev_get_machine())); 2833 2834 acpi_ram_update(build_state->table_mr, tables.table_data); 2835 2836 if (build_state->rsdp) { 2837 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2838 } else { 2839 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2840 } 2841 2842 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2843 acpi_build_tables_cleanup(&tables, true); 2844 } 2845 2846 static void acpi_build_reset(void *build_opaque) 2847 { 2848 AcpiBuildState *build_state = build_opaque; 2849 build_state->patched = 0; 2850 } 2851 2852 static const VMStateDescription vmstate_acpi_build = { 2853 .name = "acpi_build", 2854 .version_id = 1, 2855 .minimum_version_id = 1, 2856 .fields = (VMStateField[]) { 2857 VMSTATE_UINT8(patched, AcpiBuildState), 2858 VMSTATE_END_OF_LIST() 2859 }, 2860 }; 2861 2862 void acpi_setup(void) 2863 { 2864 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2865 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2866 AcpiBuildTables tables; 2867 AcpiBuildState *build_state; 2868 Object *vmgenid_dev; 2869 TPMIf *tpm; 2870 static FwCfgTPMConfig tpm_config; 2871 2872 if (!pcms->fw_cfg) { 2873 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2874 return; 2875 } 2876 2877 if (!pcms->acpi_build_enabled) { 2878 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2879 return; 2880 } 2881 2882 if (!acpi_enabled) { 2883 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2884 return; 2885 } 2886 2887 build_state = g_malloc0(sizeof *build_state); 2888 2889 acpi_build_tables_init(&tables); 2890 acpi_build(&tables, MACHINE(pcms)); 2891 2892 /* Now expose it all to Guest */ 2893 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2894 build_state, tables.table_data, 2895 ACPI_BUILD_TABLE_FILE, 2896 ACPI_BUILD_TABLE_MAX_SIZE); 2897 assert(build_state->table_mr != NULL); 2898 2899 build_state->linker_mr = 2900 acpi_add_rom_blob(acpi_build_update, build_state, 2901 tables.linker->cmd_blob, "etc/table-loader", 0); 2902 2903 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2904 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2905 2906 tpm = tpm_find(); 2907 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2908 tpm_config = (FwCfgTPMConfig) { 2909 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2910 .tpm_version = tpm_get_version(tpm), 2911 .tpmppi_version = TPM_PPI_VERSION_1_30 2912 }; 2913 fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config", 2914 &tpm_config, sizeof tpm_config); 2915 } 2916 2917 vmgenid_dev = find_vmgenid_dev(); 2918 if (vmgenid_dev) { 2919 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, 2920 tables.vmgenid); 2921 } 2922 2923 if (!pcmc->rsdp_in_ram) { 2924 /* 2925 * Keep for compatibility with old machine types. 2926 * Though RSDP is small, its contents isn't immutable, so 2927 * we'll update it along with the rest of tables on guest access. 2928 */ 2929 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2930 2931 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2932 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2933 acpi_build_update, NULL, build_state, 2934 build_state->rsdp, rsdp_size, true); 2935 build_state->rsdp_mr = NULL; 2936 } else { 2937 build_state->rsdp = NULL; 2938 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2939 build_state, tables.rsdp, 2940 ACPI_BUILD_RSDP_FILE, 0); 2941 } 2942 2943 qemu_register_reset(acpi_build_reset, build_state); 2944 acpi_build_reset(build_state); 2945 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2946 2947 /* Cleanup tables but don't free the memory: we track it 2948 * in build_state. 2949 */ 2950 acpi_build_tables_cleanup(&tables, false); 2951 } 2952