xref: /openbmc/qemu/hw/i386/acpi-build.c (revision ebe15582)
1 /* Support for generating ACPI tables and passing them to Guests
2  *
3  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
4  * Copyright (C) 2006 Fabrice Bellard
5  * Copyright (C) 2013 Red Hat Inc
6  *
7  * Author: Michael S. Tsirkin <mst@redhat.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13 
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18 
19  * You should have received a copy of the GNU General Public License along
20  * with this program; if not, see <http://www.gnu.org/licenses/>.
21  */
22 
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "hw/core/cpu.h"
31 #include "target/i386/cpu.h"
32 #include "hw/misc/pvpanic.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/acpi/piix4.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/timer/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "sysemu/numa.h"
52 #include "sysemu/reset.h"
53 
54 /* Supported chipsets: */
55 #include "hw/acpi/piix4.h"
56 #include "hw/acpi/pcihp.h"
57 #include "hw/i386/ich9.h"
58 #include "hw/pci/pci_bus.h"
59 #include "hw/pci-host/q35.h"
60 #include "hw/i386/x86-iommu.h"
61 
62 #include "hw/acpi/aml-build.h"
63 #include "hw/acpi/utils.h"
64 #include "hw/acpi/pci.h"
65 
66 #include "qom/qom-qobject.h"
67 #include "hw/i386/amd_iommu.h"
68 #include "hw/i386/intel_iommu.h"
69 
70 #include "hw/acpi/ipmi.h"
71 
72 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
73  * -M pc-i440fx-2.0.  Even if the actual amount of AML generated grows
74  * a little bit, there should be plenty of free space since the DSDT
75  * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
76  */
77 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE    97
78 #define ACPI_BUILD_ALIGN_SIZE             0x1000
79 
80 #define ACPI_BUILD_TABLE_SIZE             0x20000
81 
82 /* #define DEBUG_ACPI_BUILD */
83 #ifdef DEBUG_ACPI_BUILD
84 #define ACPI_BUILD_DPRINTF(fmt, ...)        \
85     do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
86 #else
87 #define ACPI_BUILD_DPRINTF(fmt, ...)
88 #endif
89 
90 /* Default IOAPIC ID */
91 #define ACPI_BUILD_IOAPIC_ID 0x0
92 
93 typedef struct AcpiPmInfo {
94     bool s3_disabled;
95     bool s4_disabled;
96     bool pcihp_bridge_en;
97     uint8_t s4_val;
98     AcpiFadtData fadt;
99     uint16_t cpu_hp_io_base;
100     uint16_t pcihp_io_base;
101     uint16_t pcihp_io_len;
102 } AcpiPmInfo;
103 
104 typedef struct AcpiMiscInfo {
105     bool is_piix4;
106     bool has_hpet;
107     TPMVersion tpm_version;
108     const unsigned char *dsdt_code;
109     unsigned dsdt_size;
110     uint16_t pvpanic_port;
111     uint16_t applesmc_io_base;
112 } AcpiMiscInfo;
113 
114 typedef struct AcpiBuildPciBusHotplugState {
115     GArray *device_table;
116     GArray *notify_table;
117     struct AcpiBuildPciBusHotplugState *parent;
118     bool pcihp_bridge_en;
119 } AcpiBuildPciBusHotplugState;
120 
121 typedef struct FwCfgTPMConfig {
122     uint32_t tpmppi_address;
123     uint8_t tpm_version;
124     uint8_t tpmppi_version;
125 } QEMU_PACKED FwCfgTPMConfig;
126 
127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
128 
129 static void init_common_fadt_data(MachineState *ms, Object *o,
130                                   AcpiFadtData *data)
131 {
132     uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
133     AmlAddressSpace as = AML_AS_SYSTEM_IO;
134     AcpiFadtData fadt = {
135         .rev = 3,
136         .flags =
137             (1 << ACPI_FADT_F_WBINVD) |
138             (1 << ACPI_FADT_F_PROC_C1) |
139             (1 << ACPI_FADT_F_SLP_BUTTON) |
140             (1 << ACPI_FADT_F_RTC_S4) |
141             (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
142             /* APIC destination mode ("Flat Logical") has an upper limit of 8
143              * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
144              * used
145              */
146             ((ms->smp.max_cpus > 8) ?
147                         (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
148         .int_model = 1 /* Multiple APIC */,
149         .rtc_century = RTC_CENTURY,
150         .plvl2_lat = 0xfff /* C2 state not supported */,
151         .plvl3_lat = 0xfff /* C3 state not supported */,
152         .smi_cmd = ACPI_PORT_SMI_CMD,
153         .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
154         .acpi_enable_cmd =
155             object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
156         .acpi_disable_cmd =
157             object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
158         .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
159         .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
160                       .address = io + 0x04 },
161         .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
162         .gpe0_blk = { .space_id = as, .bit_width =
163             object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
164             .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
165         },
166     };
167     *data = fadt;
168 }
169 
170 static Object *object_resolve_type_unambiguous(const char *typename)
171 {
172     bool ambig;
173     Object *o = object_resolve_path_type("", typename, &ambig);
174 
175     if (ambig || !o) {
176         return NULL;
177     }
178     return o;
179 }
180 
181 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
182 {
183     Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
184     Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
185     Object *obj = piix ? piix : lpc;
186     QObject *o;
187     pm->cpu_hp_io_base = 0;
188     pm->pcihp_io_base = 0;
189     pm->pcihp_io_len = 0;
190 
191     assert(obj);
192     init_common_fadt_data(machine, obj, &pm->fadt);
193     if (piix) {
194         /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
195         pm->fadt.rev = 1;
196         pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
197         pm->pcihp_io_base =
198             object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
199         pm->pcihp_io_len =
200             object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
201     }
202     if (lpc) {
203         struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
204             .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
205         pm->fadt.reset_reg = r;
206         pm->fadt.reset_val = 0xf;
207         pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
208         pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
209     }
210 
211     /* The above need not be conditional on machine type because the reset port
212      * happens to be the same on PIIX (pc) and ICH9 (q35). */
213     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
214 
215     /* Fill in optional s3/s4 related properties */
216     o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
217     if (o) {
218         pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
219     } else {
220         pm->s3_disabled = false;
221     }
222     qobject_unref(o);
223     o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
224     if (o) {
225         pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
226     } else {
227         pm->s4_disabled = false;
228     }
229     qobject_unref(o);
230     o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
231     if (o) {
232         pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
233     } else {
234         pm->s4_val = false;
235     }
236     qobject_unref(o);
237 
238     pm->pcihp_bridge_en =
239         object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
240                                  NULL);
241 }
242 
243 static void acpi_get_misc_info(AcpiMiscInfo *info)
244 {
245     Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
246     Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
247     assert(!!piix != !!lpc);
248 
249     if (piix) {
250         info->is_piix4 = true;
251     }
252     if (lpc) {
253         info->is_piix4 = false;
254     }
255 
256     info->has_hpet = hpet_find();
257     info->tpm_version = tpm_get_version(tpm_find());
258     info->pvpanic_port = pvpanic_port();
259     info->applesmc_io_base = applesmc_port();
260 }
261 
262 /*
263  * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
264  * On i386 arch we only have two pci hosts, so we can look only for them.
265  */
266 static Object *acpi_get_i386_pci_host(void)
267 {
268     PCIHostState *host;
269 
270     host = OBJECT_CHECK(PCIHostState,
271                         object_resolve_path("/machine/i440fx", NULL),
272                         TYPE_PCI_HOST_BRIDGE);
273     if (!host) {
274         host = OBJECT_CHECK(PCIHostState,
275                             object_resolve_path("/machine/q35", NULL),
276                             TYPE_PCI_HOST_BRIDGE);
277     }
278 
279     return OBJECT(host);
280 }
281 
282 static void acpi_get_pci_holes(Range *hole, Range *hole64)
283 {
284     Object *pci_host;
285 
286     pci_host = acpi_get_i386_pci_host();
287     g_assert(pci_host);
288 
289     range_set_bounds1(hole,
290                       object_property_get_uint(pci_host,
291                                                PCI_HOST_PROP_PCI_HOLE_START,
292                                                NULL),
293                       object_property_get_uint(pci_host,
294                                                PCI_HOST_PROP_PCI_HOLE_END,
295                                                NULL));
296     range_set_bounds1(hole64,
297                       object_property_get_uint(pci_host,
298                                                PCI_HOST_PROP_PCI_HOLE64_START,
299                                                NULL),
300                       object_property_get_uint(pci_host,
301                                                PCI_HOST_PROP_PCI_HOLE64_END,
302                                                NULL));
303 }
304 
305 static void acpi_align_size(GArray *blob, unsigned align)
306 {
307     /* Align size to multiple of given size. This reduces the chance
308      * we need to change size in the future (breaking cross version migration).
309      */
310     g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
311 }
312 
313 /* FACS */
314 static void
315 build_facs(GArray *table_data)
316 {
317     AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
318     memcpy(&facs->signature, "FACS", 4);
319     facs->length = cpu_to_le32(sizeof(*facs));
320 }
321 
322 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
323                        const CPUArchIdList *apic_ids, GArray *entry)
324 {
325     uint32_t apic_id = apic_ids->cpus[uid].arch_id;
326 
327     /* ACPI spec says that LAPIC entry for non present
328      * CPU may be omitted from MADT or it must be marked
329      * as disabled. However omitting non present CPU from
330      * MADT breaks hotplug on linux. So possible CPUs
331      * should be put in MADT but kept disabled.
332      */
333     if (apic_id < 255) {
334         AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
335 
336         apic->type = ACPI_APIC_PROCESSOR;
337         apic->length = sizeof(*apic);
338         apic->processor_id = uid;
339         apic->local_apic_id = apic_id;
340         if (apic_ids->cpus[uid].cpu != NULL) {
341             apic->flags = cpu_to_le32(1);
342         } else {
343             apic->flags = cpu_to_le32(0);
344         }
345     } else {
346         AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
347 
348         apic->type = ACPI_APIC_LOCAL_X2APIC;
349         apic->length = sizeof(*apic);
350         apic->uid = cpu_to_le32(uid);
351         apic->x2apic_id = cpu_to_le32(apic_id);
352         if (apic_ids->cpus[uid].cpu != NULL) {
353             apic->flags = cpu_to_le32(1);
354         } else {
355             apic->flags = cpu_to_le32(0);
356         }
357     }
358 }
359 
360 static void
361 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
362 {
363     MachineClass *mc = MACHINE_GET_CLASS(pcms);
364     const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
365     int madt_start = table_data->len;
366     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
367     AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
368     bool x2apic_mode = false;
369 
370     AcpiMultipleApicTable *madt;
371     AcpiMadtIoApic *io_apic;
372     AcpiMadtIntsrcovr *intsrcovr;
373     int i;
374 
375     madt = acpi_data_push(table_data, sizeof *madt);
376     madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
377     madt->flags = cpu_to_le32(1);
378 
379     for (i = 0; i < apic_ids->len; i++) {
380         adevc->madt_cpu(adev, i, apic_ids, table_data);
381         if (apic_ids->cpus[i].arch_id > 254) {
382             x2apic_mode = true;
383         }
384     }
385 
386     io_apic = acpi_data_push(table_data, sizeof *io_apic);
387     io_apic->type = ACPI_APIC_IO;
388     io_apic->length = sizeof(*io_apic);
389     io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
390     io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
391     io_apic->interrupt = cpu_to_le32(0);
392 
393     if (pcms->apic_xrupt_override) {
394         intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
395         intsrcovr->type   = ACPI_APIC_XRUPT_OVERRIDE;
396         intsrcovr->length = sizeof(*intsrcovr);
397         intsrcovr->source = 0;
398         intsrcovr->gsi    = cpu_to_le32(2);
399         intsrcovr->flags  = cpu_to_le16(0); /* conforms to bus specifications */
400     }
401     for (i = 1; i < 16; i++) {
402 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
403         if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
404             /* No need for a INT source override structure. */
405             continue;
406         }
407         intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
408         intsrcovr->type   = ACPI_APIC_XRUPT_OVERRIDE;
409         intsrcovr->length = sizeof(*intsrcovr);
410         intsrcovr->source = i;
411         intsrcovr->gsi    = cpu_to_le32(i);
412         intsrcovr->flags  = cpu_to_le16(0xd); /* active high, level triggered */
413     }
414 
415     if (x2apic_mode) {
416         AcpiMadtLocalX2ApicNmi *local_nmi;
417 
418         local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
419         local_nmi->type   = ACPI_APIC_LOCAL_X2APIC_NMI;
420         local_nmi->length = sizeof(*local_nmi);
421         local_nmi->uid    = 0xFFFFFFFF; /* all processors */
422         local_nmi->flags  = cpu_to_le16(0);
423         local_nmi->lint   = 1; /* ACPI_LINT1 */
424     } else {
425         AcpiMadtLocalNmi *local_nmi;
426 
427         local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
428         local_nmi->type         = ACPI_APIC_LOCAL_NMI;
429         local_nmi->length       = sizeof(*local_nmi);
430         local_nmi->processor_id = 0xff; /* all processors */
431         local_nmi->flags        = cpu_to_le16(0);
432         local_nmi->lint         = 1; /* ACPI_LINT1 */
433     }
434 
435     build_header(linker, table_data,
436                  (void *)(table_data->data + madt_start), "APIC",
437                  table_data->len - madt_start, 1, NULL, NULL);
438 }
439 
440 static void build_append_pcihp_notify_entry(Aml *method, int slot)
441 {
442     Aml *if_ctx;
443     int32_t devfn = PCI_DEVFN(slot, 0);
444 
445     if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
446     aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
447     aml_append(method, if_ctx);
448 }
449 
450 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
451                                          bool pcihp_bridge_en)
452 {
453     Aml *dev, *notify_method = NULL, *method;
454     QObject *bsel;
455     PCIBus *sec;
456     int i;
457 
458     bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
459     if (bsel) {
460         uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
461 
462         aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
463         notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
464     }
465 
466     for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
467         DeviceClass *dc;
468         PCIDeviceClass *pc;
469         PCIDevice *pdev = bus->devices[i];
470         int slot = PCI_SLOT(i);
471         bool hotplug_enabled_dev;
472         bool bridge_in_acpi;
473 
474         if (!pdev) {
475             if (bsel) { /* add hotplug slots for non present devices */
476                 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
477                 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
478                 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
479                 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
480                 aml_append(method,
481                     aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
482                 );
483                 aml_append(dev, method);
484                 aml_append(parent_scope, dev);
485 
486                 build_append_pcihp_notify_entry(notify_method, slot);
487             }
488             continue;
489         }
490 
491         pc = PCI_DEVICE_GET_CLASS(pdev);
492         dc = DEVICE_GET_CLASS(pdev);
493 
494         /* When hotplug for bridges is enabled, bridges are
495          * described in ACPI separately (see build_pci_bus_end).
496          * In this case they aren't themselves hot-pluggable.
497          * Hotplugged bridges *are* hot-pluggable.
498          */
499         bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
500             !DEVICE(pdev)->hotplugged;
501 
502         hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
503 
504         if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
505             continue;
506         }
507 
508         /* start to compose PCI slot descriptor */
509         dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
510         aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
511 
512         if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
513             /* add VGA specific AML methods */
514             int s3d;
515 
516             if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
517                 s3d = 3;
518             } else {
519                 s3d = 0;
520             }
521 
522             method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
523             aml_append(method, aml_return(aml_int(0)));
524             aml_append(dev, method);
525 
526             method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
527             aml_append(method, aml_return(aml_int(0)));
528             aml_append(dev, method);
529 
530             method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
531             aml_append(method, aml_return(aml_int(s3d)));
532             aml_append(dev, method);
533         } else if (hotplug_enabled_dev) {
534             /* add _SUN/_EJ0 to make slot hotpluggable  */
535             aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
536 
537             method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
538             aml_append(method,
539                 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
540             );
541             aml_append(dev, method);
542 
543             if (bsel) {
544                 build_append_pcihp_notify_entry(notify_method, slot);
545             }
546         } else if (bridge_in_acpi) {
547             /*
548              * device is coldplugged bridge,
549              * add child device descriptions into its scope
550              */
551             PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
552 
553             build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
554         }
555         /* slot descriptor has been composed, add it into parent context */
556         aml_append(parent_scope, dev);
557     }
558 
559     if (bsel) {
560         aml_append(parent_scope, notify_method);
561     }
562 
563     /* Append PCNT method to notify about events on local and child buses.
564      * Add unconditionally for root since DSDT expects it.
565      */
566     method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
567 
568     /* If bus supports hotplug select it and notify about local events */
569     if (bsel) {
570         uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
571 
572         aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
573         aml_append(method,
574             aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
575         );
576         aml_append(method,
577             aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
578         );
579     }
580 
581     /* Notify about child bus events in any case */
582     if (pcihp_bridge_en) {
583         QLIST_FOREACH(sec, &bus->child, sibling) {
584             int32_t devfn = sec->parent_dev->devfn;
585 
586             if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
587                 continue;
588             }
589 
590             aml_append(method, aml_name("^S%.02X.PCNT", devfn));
591         }
592     }
593     aml_append(parent_scope, method);
594     qobject_unref(bsel);
595 }
596 
597 /**
598  * build_prt_entry:
599  * @link_name: link name for PCI route entry
600  *
601  * build AML package containing a PCI route entry for @link_name
602  */
603 static Aml *build_prt_entry(const char *link_name)
604 {
605     Aml *a_zero = aml_int(0);
606     Aml *pkg = aml_package(4);
607     aml_append(pkg, a_zero);
608     aml_append(pkg, a_zero);
609     aml_append(pkg, aml_name("%s", link_name));
610     aml_append(pkg, a_zero);
611     return pkg;
612 }
613 
614 /*
615  * initialize_route - Initialize the interrupt routing rule
616  * through a specific LINK:
617  *  if (lnk_idx == idx)
618  *      route using link 'link_name'
619  */
620 static Aml *initialize_route(Aml *route, const char *link_name,
621                              Aml *lnk_idx, int idx)
622 {
623     Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
624     Aml *pkg = build_prt_entry(link_name);
625 
626     aml_append(if_ctx, aml_store(pkg, route));
627 
628     return if_ctx;
629 }
630 
631 /*
632  * build_prt - Define interrupt rounting rules
633  *
634  * Returns an array of 128 routes, one for each device,
635  * based on device location.
636  * The main goal is to equaly distribute the interrupts
637  * over the 4 existing ACPI links (works only for i440fx).
638  * The hash function is  (slot + pin) & 3 -> "LNK[D|A|B|C]".
639  *
640  */
641 static Aml *build_prt(bool is_pci0_prt)
642 {
643     Aml *method, *while_ctx, *pin, *res;
644 
645     method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
646     res = aml_local(0);
647     pin = aml_local(1);
648     aml_append(method, aml_store(aml_package(128), res));
649     aml_append(method, aml_store(aml_int(0), pin));
650 
651     /* while (pin < 128) */
652     while_ctx = aml_while(aml_lless(pin, aml_int(128)));
653     {
654         Aml *slot = aml_local(2);
655         Aml *lnk_idx = aml_local(3);
656         Aml *route = aml_local(4);
657 
658         /* slot = pin >> 2 */
659         aml_append(while_ctx,
660                    aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
661         /* lnk_idx = (slot + pin) & 3 */
662         aml_append(while_ctx,
663             aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
664                       lnk_idx));
665 
666         /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3  */
667         aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
668         if (is_pci0_prt) {
669             Aml *if_device_1, *if_pin_4, *else_pin_4;
670 
671             /* device 1 is the power-management device, needs SCI */
672             if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
673             {
674                 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
675                 {
676                     aml_append(if_pin_4,
677                         aml_store(build_prt_entry("LNKS"), route));
678                 }
679                 aml_append(if_device_1, if_pin_4);
680                 else_pin_4 = aml_else();
681                 {
682                     aml_append(else_pin_4,
683                         aml_store(build_prt_entry("LNKA"), route));
684                 }
685                 aml_append(if_device_1, else_pin_4);
686             }
687             aml_append(while_ctx, if_device_1);
688         } else {
689             aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
690         }
691         aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
692         aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
693 
694         /* route[0] = 0x[slot]FFFF */
695         aml_append(while_ctx,
696             aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
697                              NULL),
698                       aml_index(route, aml_int(0))));
699         /* route[1] = pin & 3 */
700         aml_append(while_ctx,
701             aml_store(aml_and(pin, aml_int(3), NULL),
702                       aml_index(route, aml_int(1))));
703         /* res[pin] = route */
704         aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
705         /* pin++ */
706         aml_append(while_ctx, aml_increment(pin));
707     }
708     aml_append(method, while_ctx);
709     /* return res*/
710     aml_append(method, aml_return(res));
711 
712     return method;
713 }
714 
715 typedef struct CrsRangeEntry {
716     uint64_t base;
717     uint64_t limit;
718 } CrsRangeEntry;
719 
720 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
721 {
722     CrsRangeEntry *entry;
723 
724     entry = g_malloc(sizeof(*entry));
725     entry->base = base;
726     entry->limit = limit;
727 
728     g_ptr_array_add(ranges, entry);
729 }
730 
731 static void crs_range_free(gpointer data)
732 {
733     CrsRangeEntry *entry = (CrsRangeEntry *)data;
734     g_free(entry);
735 }
736 
737 typedef struct CrsRangeSet {
738     GPtrArray *io_ranges;
739     GPtrArray *mem_ranges;
740     GPtrArray *mem_64bit_ranges;
741  } CrsRangeSet;
742 
743 static void crs_range_set_init(CrsRangeSet *range_set)
744 {
745     range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
746     range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
747     range_set->mem_64bit_ranges =
748             g_ptr_array_new_with_free_func(crs_range_free);
749 }
750 
751 static void crs_range_set_free(CrsRangeSet *range_set)
752 {
753     g_ptr_array_free(range_set->io_ranges, true);
754     g_ptr_array_free(range_set->mem_ranges, true);
755     g_ptr_array_free(range_set->mem_64bit_ranges, true);
756 }
757 
758 static gint crs_range_compare(gconstpointer a, gconstpointer b)
759 {
760     CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
761     CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
762 
763     if (entry_a->base < entry_b->base) {
764         return -1;
765     } else if (entry_a->base > entry_b->base) {
766         return 1;
767     } else {
768         return 0;
769     }
770 }
771 
772 /*
773  * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
774  * interval, computes the 'free' ranges from the same interval.
775  * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
776  * will return { [base - a1], [a2 - b1], [b2 - limit] }.
777  */
778 static void crs_replace_with_free_ranges(GPtrArray *ranges,
779                                          uint64_t start, uint64_t end)
780 {
781     GPtrArray *free_ranges = g_ptr_array_new();
782     uint64_t free_base = start;
783     int i;
784 
785     g_ptr_array_sort(ranges, crs_range_compare);
786     for (i = 0; i < ranges->len; i++) {
787         CrsRangeEntry *used = g_ptr_array_index(ranges, i);
788 
789         if (free_base < used->base) {
790             crs_range_insert(free_ranges, free_base, used->base - 1);
791         }
792 
793         free_base = used->limit + 1;
794     }
795 
796     if (free_base < end) {
797         crs_range_insert(free_ranges, free_base, end);
798     }
799 
800     g_ptr_array_set_size(ranges, 0);
801     for (i = 0; i < free_ranges->len; i++) {
802         g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
803     }
804 
805     g_ptr_array_free(free_ranges, true);
806 }
807 
808 /*
809  * crs_range_merge - merges adjacent ranges in the given array.
810  * Array elements are deleted and replaced with the merged ranges.
811  */
812 static void crs_range_merge(GPtrArray *range)
813 {
814     GPtrArray *tmp =  g_ptr_array_new_with_free_func(crs_range_free);
815     CrsRangeEntry *entry;
816     uint64_t range_base, range_limit;
817     int i;
818 
819     if (!range->len) {
820         return;
821     }
822 
823     g_ptr_array_sort(range, crs_range_compare);
824 
825     entry = g_ptr_array_index(range, 0);
826     range_base = entry->base;
827     range_limit = entry->limit;
828     for (i = 1; i < range->len; i++) {
829         entry = g_ptr_array_index(range, i);
830         if (entry->base - 1 == range_limit) {
831             range_limit = entry->limit;
832         } else {
833             crs_range_insert(tmp, range_base, range_limit);
834             range_base = entry->base;
835             range_limit = entry->limit;
836         }
837     }
838     crs_range_insert(tmp, range_base, range_limit);
839 
840     g_ptr_array_set_size(range, 0);
841     for (i = 0; i < tmp->len; i++) {
842         entry = g_ptr_array_index(tmp, i);
843         crs_range_insert(range, entry->base, entry->limit);
844     }
845     g_ptr_array_free(tmp, true);
846 }
847 
848 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
849 {
850     Aml *crs = aml_resource_template();
851     CrsRangeSet temp_range_set;
852     CrsRangeEntry *entry;
853     uint8_t max_bus = pci_bus_num(host->bus);
854     uint8_t type;
855     int devfn;
856     int i;
857 
858     crs_range_set_init(&temp_range_set);
859     for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
860         uint64_t range_base, range_limit;
861         PCIDevice *dev = host->bus->devices[devfn];
862 
863         if (!dev) {
864             continue;
865         }
866 
867         for (i = 0; i < PCI_NUM_REGIONS; i++) {
868             PCIIORegion *r = &dev->io_regions[i];
869 
870             range_base = r->addr;
871             range_limit = r->addr + r->size - 1;
872 
873             /*
874              * Work-around for old bioses
875              * that do not support multiple root buses
876              */
877             if (!range_base || range_base > range_limit) {
878                 continue;
879             }
880 
881             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
882                 crs_range_insert(temp_range_set.io_ranges,
883                                  range_base, range_limit);
884             } else { /* "memory" */
885                 crs_range_insert(temp_range_set.mem_ranges,
886                                  range_base, range_limit);
887             }
888         }
889 
890         type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
891         if (type == PCI_HEADER_TYPE_BRIDGE) {
892             uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
893             if (subordinate > max_bus) {
894                 max_bus = subordinate;
895             }
896 
897             range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
898             range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
899 
900             /*
901              * Work-around for old bioses
902              * that do not support multiple root buses
903              */
904             if (range_base && range_base <= range_limit) {
905                 crs_range_insert(temp_range_set.io_ranges,
906                                  range_base, range_limit);
907             }
908 
909             range_base =
910                 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
911             range_limit =
912                 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
913 
914             /*
915              * Work-around for old bioses
916              * that do not support multiple root buses
917              */
918             if (range_base && range_base <= range_limit) {
919                 uint64_t length = range_limit - range_base + 1;
920                 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
921                     crs_range_insert(temp_range_set.mem_ranges,
922                                      range_base, range_limit);
923                 } else {
924                     crs_range_insert(temp_range_set.mem_64bit_ranges,
925                                      range_base, range_limit);
926                 }
927             }
928 
929             range_base =
930                 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
931             range_limit =
932                 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
933 
934             /*
935              * Work-around for old bioses
936              * that do not support multiple root buses
937              */
938             if (range_base && range_base <= range_limit) {
939                 uint64_t length = range_limit - range_base + 1;
940                 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
941                     crs_range_insert(temp_range_set.mem_ranges,
942                                      range_base, range_limit);
943                 } else {
944                     crs_range_insert(temp_range_set.mem_64bit_ranges,
945                                      range_base, range_limit);
946                 }
947             }
948         }
949     }
950 
951     crs_range_merge(temp_range_set.io_ranges);
952     for (i = 0; i < temp_range_set.io_ranges->len; i++) {
953         entry = g_ptr_array_index(temp_range_set.io_ranges, i);
954         aml_append(crs,
955                    aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
956                                AML_POS_DECODE, AML_ENTIRE_RANGE,
957                                0, entry->base, entry->limit, 0,
958                                entry->limit - entry->base + 1));
959         crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
960     }
961 
962     crs_range_merge(temp_range_set.mem_ranges);
963     for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
964         entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
965         aml_append(crs,
966                    aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
967                                     AML_MAX_FIXED, AML_NON_CACHEABLE,
968                                     AML_READ_WRITE,
969                                     0, entry->base, entry->limit, 0,
970                                     entry->limit - entry->base + 1));
971         crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
972     }
973 
974     crs_range_merge(temp_range_set.mem_64bit_ranges);
975     for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
976         entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
977         aml_append(crs,
978                    aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
979                                     AML_MAX_FIXED, AML_NON_CACHEABLE,
980                                     AML_READ_WRITE,
981                                     0, entry->base, entry->limit, 0,
982                                     entry->limit - entry->base + 1));
983         crs_range_insert(range_set->mem_64bit_ranges,
984                          entry->base, entry->limit);
985     }
986 
987     crs_range_set_free(&temp_range_set);
988 
989     aml_append(crs,
990         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
991                             0,
992                             pci_bus_num(host->bus),
993                             max_bus,
994                             0,
995                             max_bus - pci_bus_num(host->bus) + 1));
996 
997     return crs;
998 }
999 
1000 static void build_hpet_aml(Aml *table)
1001 {
1002     Aml *crs;
1003     Aml *field;
1004     Aml *method;
1005     Aml *if_ctx;
1006     Aml *scope = aml_scope("_SB");
1007     Aml *dev = aml_device("HPET");
1008     Aml *zero = aml_int(0);
1009     Aml *id = aml_local(0);
1010     Aml *period = aml_local(1);
1011 
1012     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1013     aml_append(dev, aml_name_decl("_UID", zero));
1014 
1015     aml_append(dev,
1016         aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1017                              HPET_LEN));
1018     field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1019     aml_append(field, aml_named_field("VEND", 32));
1020     aml_append(field, aml_named_field("PRD", 32));
1021     aml_append(dev, field);
1022 
1023     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1024     aml_append(method, aml_store(aml_name("VEND"), id));
1025     aml_append(method, aml_store(aml_name("PRD"), period));
1026     aml_append(method, aml_shiftright(id, aml_int(16), id));
1027     if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1028                             aml_equal(id, aml_int(0xffff))));
1029     {
1030         aml_append(if_ctx, aml_return(zero));
1031     }
1032     aml_append(method, if_ctx);
1033 
1034     if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1035                             aml_lgreater(period, aml_int(100000000))));
1036     {
1037         aml_append(if_ctx, aml_return(zero));
1038     }
1039     aml_append(method, if_ctx);
1040 
1041     aml_append(method, aml_return(aml_int(0x0F)));
1042     aml_append(dev, method);
1043 
1044     crs = aml_resource_template();
1045     aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1046     aml_append(dev, aml_name_decl("_CRS", crs));
1047 
1048     aml_append(scope, dev);
1049     aml_append(table, scope);
1050 }
1051 
1052 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1053 {
1054     Aml *dev, *fdi;
1055     uint8_t maxc, maxh, maxs;
1056 
1057     isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1058 
1059     dev = aml_device("FLP%c", 'A' + idx);
1060 
1061     aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1062 
1063     fdi = aml_package(16);
1064     aml_append(fdi, aml_int(idx));  /* Drive Number */
1065     aml_append(fdi,
1066         aml_int(cmos_get_fd_drive_type(type)));  /* Device Type */
1067     /*
1068      * the values below are the limits of the drive, and are thus independent
1069      * of the inserted media
1070      */
1071     aml_append(fdi, aml_int(maxc));  /* Maximum Cylinder Number */
1072     aml_append(fdi, aml_int(maxs));  /* Maximum Sector Number */
1073     aml_append(fdi, aml_int(maxh));  /* Maximum Head Number */
1074     /*
1075      * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1076      * the drive type, so shall we
1077      */
1078     aml_append(fdi, aml_int(0xAF));  /* disk_specify_1 */
1079     aml_append(fdi, aml_int(0x02));  /* disk_specify_2 */
1080     aml_append(fdi, aml_int(0x25));  /* disk_motor_wait */
1081     aml_append(fdi, aml_int(0x02));  /* disk_sector_siz */
1082     aml_append(fdi, aml_int(0x12));  /* disk_eot */
1083     aml_append(fdi, aml_int(0x1B));  /* disk_rw_gap */
1084     aml_append(fdi, aml_int(0xFF));  /* disk_dtl */
1085     aml_append(fdi, aml_int(0x6C));  /* disk_formt_gap */
1086     aml_append(fdi, aml_int(0xF6));  /* disk_fill */
1087     aml_append(fdi, aml_int(0x0F));  /* disk_head_sttl */
1088     aml_append(fdi, aml_int(0x08));  /* disk_motor_strt */
1089 
1090     aml_append(dev, aml_name_decl("_FDI", fdi));
1091     return dev;
1092 }
1093 
1094 static Aml *build_fdc_device_aml(ISADevice *fdc)
1095 {
1096     int i;
1097     Aml *dev;
1098     Aml *crs;
1099 
1100 #define ACPI_FDE_MAX_FD 4
1101     uint32_t fde_buf[5] = {
1102         0, 0, 0, 0,     /* presence of floppy drives #0 - #3 */
1103         cpu_to_le32(2)  /* tape presence (2 == never present) */
1104     };
1105 
1106     dev = aml_device("FDC0");
1107     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1108 
1109     crs = aml_resource_template();
1110     aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1111     aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1112     aml_append(crs, aml_irq_no_flags(6));
1113     aml_append(crs,
1114         aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1115     aml_append(dev, aml_name_decl("_CRS", crs));
1116 
1117     for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1118         FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1119 
1120         if (type < FLOPPY_DRIVE_TYPE_NONE) {
1121             fde_buf[i] = cpu_to_le32(1);  /* drive present */
1122             aml_append(dev, build_fdinfo_aml(i, type));
1123         }
1124     }
1125     aml_append(dev, aml_name_decl("_FDE",
1126                aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1127 
1128     return dev;
1129 }
1130 
1131 static Aml *build_rtc_device_aml(void)
1132 {
1133     Aml *dev;
1134     Aml *crs;
1135 
1136     dev = aml_device("RTC");
1137     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1138     crs = aml_resource_template();
1139     aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1140     aml_append(crs, aml_irq_no_flags(8));
1141     aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1142     aml_append(dev, aml_name_decl("_CRS", crs));
1143 
1144     return dev;
1145 }
1146 
1147 static Aml *build_kbd_device_aml(void)
1148 {
1149     Aml *dev;
1150     Aml *crs;
1151     Aml *method;
1152 
1153     dev = aml_device("KBD");
1154     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1155 
1156     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1157     aml_append(method, aml_return(aml_int(0x0f)));
1158     aml_append(dev, method);
1159 
1160     crs = aml_resource_template();
1161     aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1162     aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1163     aml_append(crs, aml_irq_no_flags(1));
1164     aml_append(dev, aml_name_decl("_CRS", crs));
1165 
1166     return dev;
1167 }
1168 
1169 static Aml *build_mouse_device_aml(void)
1170 {
1171     Aml *dev;
1172     Aml *crs;
1173     Aml *method;
1174 
1175     dev = aml_device("MOU");
1176     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1177 
1178     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1179     aml_append(method, aml_return(aml_int(0x0f)));
1180     aml_append(dev, method);
1181 
1182     crs = aml_resource_template();
1183     aml_append(crs, aml_irq_no_flags(12));
1184     aml_append(dev, aml_name_decl("_CRS", crs));
1185 
1186     return dev;
1187 }
1188 
1189 static Aml *build_lpt_device_aml(void)
1190 {
1191     Aml *dev;
1192     Aml *crs;
1193     Aml *method;
1194     Aml *if_ctx;
1195     Aml *else_ctx;
1196     Aml *zero = aml_int(0);
1197     Aml *is_present = aml_local(0);
1198 
1199     dev = aml_device("LPT");
1200     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1201 
1202     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1203     aml_append(method, aml_store(aml_name("LPEN"), is_present));
1204     if_ctx = aml_if(aml_equal(is_present, zero));
1205     {
1206         aml_append(if_ctx, aml_return(aml_int(0x00)));
1207     }
1208     aml_append(method, if_ctx);
1209     else_ctx = aml_else();
1210     {
1211         aml_append(else_ctx, aml_return(aml_int(0x0f)));
1212     }
1213     aml_append(method, else_ctx);
1214     aml_append(dev, method);
1215 
1216     crs = aml_resource_template();
1217     aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1218     aml_append(crs, aml_irq_no_flags(7));
1219     aml_append(dev, aml_name_decl("_CRS", crs));
1220 
1221     return dev;
1222 }
1223 
1224 static Aml *build_com_device_aml(uint8_t uid)
1225 {
1226     Aml *dev;
1227     Aml *crs;
1228     Aml *method;
1229     Aml *if_ctx;
1230     Aml *else_ctx;
1231     Aml *zero = aml_int(0);
1232     Aml *is_present = aml_local(0);
1233     const char *enabled_field = "CAEN";
1234     uint8_t irq = 4;
1235     uint16_t io_port = 0x03F8;
1236 
1237     assert(uid == 1 || uid == 2);
1238     if (uid == 2) {
1239         enabled_field = "CBEN";
1240         irq = 3;
1241         io_port = 0x02F8;
1242     }
1243 
1244     dev = aml_device("COM%d", uid);
1245     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1246     aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1247 
1248     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1249     aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1250     if_ctx = aml_if(aml_equal(is_present, zero));
1251     {
1252         aml_append(if_ctx, aml_return(aml_int(0x00)));
1253     }
1254     aml_append(method, if_ctx);
1255     else_ctx = aml_else();
1256     {
1257         aml_append(else_ctx, aml_return(aml_int(0x0f)));
1258     }
1259     aml_append(method, else_ctx);
1260     aml_append(dev, method);
1261 
1262     crs = aml_resource_template();
1263     aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1264     aml_append(crs, aml_irq_no_flags(irq));
1265     aml_append(dev, aml_name_decl("_CRS", crs));
1266 
1267     return dev;
1268 }
1269 
1270 static void build_isa_devices_aml(Aml *table)
1271 {
1272     ISADevice *fdc = pc_find_fdc0();
1273     bool ambiguous;
1274 
1275     Aml *scope = aml_scope("_SB.PCI0.ISA");
1276     Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1277 
1278     aml_append(scope, build_rtc_device_aml());
1279     aml_append(scope, build_kbd_device_aml());
1280     aml_append(scope, build_mouse_device_aml());
1281     if (fdc) {
1282         aml_append(scope, build_fdc_device_aml(fdc));
1283     }
1284     aml_append(scope, build_lpt_device_aml());
1285     aml_append(scope, build_com_device_aml(1));
1286     aml_append(scope, build_com_device_aml(2));
1287 
1288     if (ambiguous) {
1289         error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1290     } else if (!obj) {
1291         error_report("No ISA bus, unable to define IPMI ACPI data");
1292     } else {
1293         build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
1294     }
1295 
1296     aml_append(table, scope);
1297 }
1298 
1299 static void build_dbg_aml(Aml *table)
1300 {
1301     Aml *field;
1302     Aml *method;
1303     Aml *while_ctx;
1304     Aml *scope = aml_scope("\\");
1305     Aml *buf = aml_local(0);
1306     Aml *len = aml_local(1);
1307     Aml *idx = aml_local(2);
1308 
1309     aml_append(scope,
1310        aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1311     field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1312     aml_append(field, aml_named_field("DBGB", 8));
1313     aml_append(scope, field);
1314 
1315     method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1316 
1317     aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1318     aml_append(method, aml_to_buffer(buf, buf));
1319     aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1320     aml_append(method, aml_store(aml_int(0), idx));
1321 
1322     while_ctx = aml_while(aml_lless(idx, len));
1323     aml_append(while_ctx,
1324         aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1325     aml_append(while_ctx, aml_increment(idx));
1326     aml_append(method, while_ctx);
1327 
1328     aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1329     aml_append(scope, method);
1330 
1331     aml_append(table, scope);
1332 }
1333 
1334 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1335 {
1336     Aml *dev;
1337     Aml *crs;
1338     Aml *method;
1339     uint32_t irqs[] = {5, 10, 11};
1340 
1341     dev = aml_device("%s", name);
1342     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1343     aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1344 
1345     crs = aml_resource_template();
1346     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1347                                   AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1348     aml_append(dev, aml_name_decl("_PRS", crs));
1349 
1350     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1351     aml_append(method, aml_return(aml_call1("IQST", reg)));
1352     aml_append(dev, method);
1353 
1354     method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1355     aml_append(method, aml_or(reg, aml_int(0x80), reg));
1356     aml_append(dev, method);
1357 
1358     method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1359     aml_append(method, aml_return(aml_call1("IQCR", reg)));
1360     aml_append(dev, method);
1361 
1362     method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1363     aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1364     aml_append(method, aml_store(aml_name("PRRI"), reg));
1365     aml_append(dev, method);
1366 
1367     return dev;
1368  }
1369 
1370 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1371 {
1372     Aml *dev;
1373     Aml *crs;
1374     Aml *method;
1375     uint32_t irqs;
1376 
1377     dev = aml_device("%s", name);
1378     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1379     aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1380 
1381     crs = aml_resource_template();
1382     irqs = gsi;
1383     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1384                                   AML_SHARED, &irqs, 1));
1385     aml_append(dev, aml_name_decl("_PRS", crs));
1386 
1387     aml_append(dev, aml_name_decl("_CRS", crs));
1388 
1389     /*
1390      * _DIS can be no-op because the interrupt cannot be disabled.
1391      */
1392     method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1393     aml_append(dev, method);
1394 
1395     method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1396     aml_append(dev, method);
1397 
1398     return dev;
1399 }
1400 
1401 /* _CRS method - get current settings */
1402 static Aml *build_iqcr_method(bool is_piix4)
1403 {
1404     Aml *if_ctx;
1405     uint32_t irqs;
1406     Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1407     Aml *crs = aml_resource_template();
1408 
1409     irqs = 0;
1410     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1411                                   AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1412     aml_append(method, aml_name_decl("PRR0", crs));
1413 
1414     aml_append(method,
1415         aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1416 
1417     if (is_piix4) {
1418         if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1419         aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1420         aml_append(method, if_ctx);
1421     } else {
1422         aml_append(method,
1423             aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1424                       aml_name("PRRI")));
1425     }
1426 
1427     aml_append(method, aml_return(aml_name("PRR0")));
1428     return method;
1429 }
1430 
1431 /* _STA method - get status */
1432 static Aml *build_irq_status_method(void)
1433 {
1434     Aml *if_ctx;
1435     Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1436 
1437     if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1438     aml_append(if_ctx, aml_return(aml_int(0x09)));
1439     aml_append(method, if_ctx);
1440     aml_append(method, aml_return(aml_int(0x0B)));
1441     return method;
1442 }
1443 
1444 static void build_piix4_pci0_int(Aml *table)
1445 {
1446     Aml *dev;
1447     Aml *crs;
1448     Aml *field;
1449     Aml *method;
1450     uint32_t irqs;
1451     Aml *sb_scope = aml_scope("_SB");
1452     Aml *pci0_scope = aml_scope("PCI0");
1453 
1454     aml_append(pci0_scope, build_prt(true));
1455     aml_append(sb_scope, pci0_scope);
1456 
1457     field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1458     aml_append(field, aml_named_field("PRQ0", 8));
1459     aml_append(field, aml_named_field("PRQ1", 8));
1460     aml_append(field, aml_named_field("PRQ2", 8));
1461     aml_append(field, aml_named_field("PRQ3", 8));
1462     aml_append(sb_scope, field);
1463 
1464     aml_append(sb_scope, build_irq_status_method());
1465     aml_append(sb_scope, build_iqcr_method(true));
1466 
1467     aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1468     aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1469     aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1470     aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1471 
1472     dev = aml_device("LNKS");
1473     {
1474         aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1475         aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1476 
1477         crs = aml_resource_template();
1478         irqs = 9;
1479         aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1480                                       AML_ACTIVE_HIGH, AML_SHARED,
1481                                       &irqs, 1));
1482         aml_append(dev, aml_name_decl("_PRS", crs));
1483 
1484         /* The SCI cannot be disabled and is always attached to GSI 9,
1485          * so these are no-ops.  We only need this link to override the
1486          * polarity to active high and match the content of the MADT.
1487          */
1488         method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1489         aml_append(method, aml_return(aml_int(0x0b)));
1490         aml_append(dev, method);
1491 
1492         method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1493         aml_append(dev, method);
1494 
1495         method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1496         aml_append(method, aml_return(aml_name("_PRS")));
1497         aml_append(dev, method);
1498 
1499         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1500         aml_append(dev, method);
1501     }
1502     aml_append(sb_scope, dev);
1503 
1504     aml_append(table, sb_scope);
1505 }
1506 
1507 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1508 {
1509     int i;
1510     int head;
1511     Aml *pkg;
1512     char base = name[3] < 'E' ? 'A' : 'E';
1513     char *s = g_strdup(name);
1514     Aml *a_nr = aml_int((nr << 16) | 0xffff);
1515 
1516     assert(strlen(s) == 4);
1517 
1518     head = name[3] - base;
1519     for (i = 0; i < 4; i++) {
1520         if (head + i > 3) {
1521             head = i * -1;
1522         }
1523         s[3] = base + head + i;
1524         pkg = aml_package(4);
1525         aml_append(pkg, a_nr);
1526         aml_append(pkg, aml_int(i));
1527         aml_append(pkg, aml_name("%s", s));
1528         aml_append(pkg, aml_int(0));
1529         aml_append(ctx, pkg);
1530     }
1531     g_free(s);
1532 }
1533 
1534 static Aml *build_q35_routing_table(const char *str)
1535 {
1536     int i;
1537     Aml *pkg;
1538     char *name = g_strdup_printf("%s ", str);
1539 
1540     pkg = aml_package(128);
1541     for (i = 0; i < 0x18; i++) {
1542             name[3] = 'E' + (i & 0x3);
1543             append_q35_prt_entry(pkg, i, name);
1544     }
1545 
1546     name[3] = 'E';
1547     append_q35_prt_entry(pkg, 0x18, name);
1548 
1549     /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1550     for (i = 0x0019; i < 0x1e; i++) {
1551         name[3] = 'A';
1552         append_q35_prt_entry(pkg, i, name);
1553     }
1554 
1555     /* PCIe->PCI bridge. use PIRQ[E-H] */
1556     name[3] = 'E';
1557     append_q35_prt_entry(pkg, 0x1e, name);
1558     name[3] = 'A';
1559     append_q35_prt_entry(pkg, 0x1f, name);
1560 
1561     g_free(name);
1562     return pkg;
1563 }
1564 
1565 static void build_q35_pci0_int(Aml *table)
1566 {
1567     Aml *field;
1568     Aml *method;
1569     Aml *sb_scope = aml_scope("_SB");
1570     Aml *pci0_scope = aml_scope("PCI0");
1571 
1572     /* Zero => PIC mode, One => APIC Mode */
1573     aml_append(table, aml_name_decl("PICF", aml_int(0)));
1574     method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1575     {
1576         aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1577     }
1578     aml_append(table, method);
1579 
1580     aml_append(pci0_scope,
1581         aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1582     aml_append(pci0_scope,
1583         aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1584 
1585     method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1586     {
1587         Aml *if_ctx;
1588         Aml *else_ctx;
1589 
1590         /* PCI IRQ routing table, example from ACPI 2.0a specification,
1591            section 6.2.8.1 */
1592         /* Note: we provide the same info as the PCI routing
1593            table of the Bochs BIOS */
1594         if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1595         aml_append(if_ctx, aml_return(aml_name("PRTP")));
1596         aml_append(method, if_ctx);
1597         else_ctx = aml_else();
1598         aml_append(else_ctx, aml_return(aml_name("PRTA")));
1599         aml_append(method, else_ctx);
1600     }
1601     aml_append(pci0_scope, method);
1602     aml_append(sb_scope, pci0_scope);
1603 
1604     field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1605     aml_append(field, aml_named_field("PRQA", 8));
1606     aml_append(field, aml_named_field("PRQB", 8));
1607     aml_append(field, aml_named_field("PRQC", 8));
1608     aml_append(field, aml_named_field("PRQD", 8));
1609     aml_append(field, aml_reserved_field(0x20));
1610     aml_append(field, aml_named_field("PRQE", 8));
1611     aml_append(field, aml_named_field("PRQF", 8));
1612     aml_append(field, aml_named_field("PRQG", 8));
1613     aml_append(field, aml_named_field("PRQH", 8));
1614     aml_append(sb_scope, field);
1615 
1616     aml_append(sb_scope, build_irq_status_method());
1617     aml_append(sb_scope, build_iqcr_method(false));
1618 
1619     aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1620     aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1621     aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1622     aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1623     aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1624     aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1625     aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1626     aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1627 
1628     aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1629     aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1630     aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1631     aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1632     aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1633     aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1634     aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1635     aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1636 
1637     aml_append(table, sb_scope);
1638 }
1639 
1640 static void build_q35_isa_bridge(Aml *table)
1641 {
1642     Aml *dev;
1643     Aml *scope;
1644     Aml *field;
1645 
1646     scope =  aml_scope("_SB.PCI0");
1647     dev = aml_device("ISA");
1648     aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1649 
1650     /* ICH9 PCI to ISA irq remapping */
1651     aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1652                                          aml_int(0x60), 0x0C));
1653 
1654     aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1655                                          aml_int(0x80), 0x02));
1656     field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1657     aml_append(field, aml_named_field("COMA", 3));
1658     aml_append(field, aml_reserved_field(1));
1659     aml_append(field, aml_named_field("COMB", 3));
1660     aml_append(field, aml_reserved_field(1));
1661     aml_append(field, aml_named_field("LPTD", 2));
1662     aml_append(dev, field);
1663 
1664     aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1665                                          aml_int(0x82), 0x02));
1666     /* enable bits */
1667     field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1668     aml_append(field, aml_named_field("CAEN", 1));
1669     aml_append(field, aml_named_field("CBEN", 1));
1670     aml_append(field, aml_named_field("LPEN", 1));
1671     aml_append(dev, field);
1672 
1673     aml_append(scope, dev);
1674     aml_append(table, scope);
1675 }
1676 
1677 static void build_piix4_pm(Aml *table)
1678 {
1679     Aml *dev;
1680     Aml *scope;
1681 
1682     scope =  aml_scope("_SB.PCI0");
1683     dev = aml_device("PX13");
1684     aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1685 
1686     aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1687                                          aml_int(0x00), 0xff));
1688     aml_append(scope, dev);
1689     aml_append(table, scope);
1690 }
1691 
1692 static void build_piix4_isa_bridge(Aml *table)
1693 {
1694     Aml *dev;
1695     Aml *scope;
1696     Aml *field;
1697 
1698     scope =  aml_scope("_SB.PCI0");
1699     dev = aml_device("ISA");
1700     aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1701 
1702     /* PIIX PCI to ISA irq remapping */
1703     aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1704                                          aml_int(0x60), 0x04));
1705     /* enable bits */
1706     field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1707     /* Offset(0x5f),, 7, */
1708     aml_append(field, aml_reserved_field(0x2f8));
1709     aml_append(field, aml_reserved_field(7));
1710     aml_append(field, aml_named_field("LPEN", 1));
1711     /* Offset(0x67),, 3, */
1712     aml_append(field, aml_reserved_field(0x38));
1713     aml_append(field, aml_reserved_field(3));
1714     aml_append(field, aml_named_field("CAEN", 1));
1715     aml_append(field, aml_reserved_field(3));
1716     aml_append(field, aml_named_field("CBEN", 1));
1717     aml_append(dev, field);
1718 
1719     aml_append(scope, dev);
1720     aml_append(table, scope);
1721 }
1722 
1723 static void build_piix4_pci_hotplug(Aml *table)
1724 {
1725     Aml *scope;
1726     Aml *field;
1727     Aml *method;
1728 
1729     scope =  aml_scope("_SB.PCI0");
1730 
1731     aml_append(scope,
1732         aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1733     field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1734     aml_append(field, aml_named_field("PCIU", 32));
1735     aml_append(field, aml_named_field("PCID", 32));
1736     aml_append(scope, field);
1737 
1738     aml_append(scope,
1739         aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1740     field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1741     aml_append(field, aml_named_field("B0EJ", 32));
1742     aml_append(scope, field);
1743 
1744     aml_append(scope,
1745         aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1746     field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1747     aml_append(field, aml_named_field("BNUM", 32));
1748     aml_append(scope, field);
1749 
1750     aml_append(scope, aml_mutex("BLCK", 0));
1751 
1752     method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1753     aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1754     aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1755     aml_append(method,
1756         aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1757     aml_append(method, aml_release(aml_name("BLCK")));
1758     aml_append(method, aml_return(aml_int(0)));
1759     aml_append(scope, method);
1760 
1761     aml_append(table, scope);
1762 }
1763 
1764 static Aml *build_q35_osc_method(void)
1765 {
1766     Aml *if_ctx;
1767     Aml *if_ctx2;
1768     Aml *else_ctx;
1769     Aml *method;
1770     Aml *a_cwd1 = aml_name("CDW1");
1771     Aml *a_ctrl = aml_local(0);
1772 
1773     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1774     aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1775 
1776     if_ctx = aml_if(aml_equal(
1777         aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1778     aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1779     aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1780 
1781     aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1782 
1783     /*
1784      * Always allow native PME, AER (no dependencies)
1785      * Allow SHPC (PCI bridges can have SHPC controller)
1786      */
1787     aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1788 
1789     if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1790     /* Unknown revision */
1791     aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1792     aml_append(if_ctx, if_ctx2);
1793 
1794     if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1795     /* Capabilities bits were masked */
1796     aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1797     aml_append(if_ctx, if_ctx2);
1798 
1799     /* Update DWORD3 in the buffer */
1800     aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1801     aml_append(method, if_ctx);
1802 
1803     else_ctx = aml_else();
1804     /* Unrecognized UUID */
1805     aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1806     aml_append(method, else_ctx);
1807 
1808     aml_append(method, aml_return(aml_arg(3)));
1809     return method;
1810 }
1811 
1812 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1813 {
1814     Aml *scope = aml_scope("_SB.PCI0");
1815     Aml *dev = aml_device("SMB0");
1816 
1817     aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0005")));
1818     aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1819     build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1820     aml_append(scope, dev);
1821     aml_append(table, scope);
1822 }
1823 
1824 static void
1825 build_dsdt(GArray *table_data, BIOSLinker *linker,
1826            AcpiPmInfo *pm, AcpiMiscInfo *misc,
1827            Range *pci_hole, Range *pci_hole64, MachineState *machine)
1828 {
1829     CrsRangeEntry *entry;
1830     Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1831     CrsRangeSet crs_range_set;
1832     PCMachineState *pcms = PC_MACHINE(machine);
1833     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1834     AcpiMcfgInfo mcfg;
1835     uint32_t nr_mem = machine->ram_slots;
1836     int root_bus_limit = 0xFF;
1837     PCIBus *bus = NULL;
1838     TPMIf *tpm = tpm_find();
1839     int i;
1840 
1841     dsdt = init_aml_allocator();
1842 
1843     /* Reserve space for header */
1844     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1845 
1846     build_dbg_aml(dsdt);
1847     if (misc->is_piix4) {
1848         sb_scope = aml_scope("_SB");
1849         dev = aml_device("PCI0");
1850         aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1851         aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1852         aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1853         aml_append(sb_scope, dev);
1854         aml_append(dsdt, sb_scope);
1855 
1856         build_hpet_aml(dsdt);
1857         build_piix4_pm(dsdt);
1858         build_piix4_isa_bridge(dsdt);
1859         build_isa_devices_aml(dsdt);
1860         build_piix4_pci_hotplug(dsdt);
1861         build_piix4_pci0_int(dsdt);
1862     } else {
1863         sb_scope = aml_scope("_SB");
1864         dev = aml_device("PCI0");
1865         aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1866         aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1867         aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1868         aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1869         aml_append(dev, build_q35_osc_method());
1870         aml_append(sb_scope, dev);
1871         aml_append(dsdt, sb_scope);
1872 
1873         build_hpet_aml(dsdt);
1874         build_q35_isa_bridge(dsdt);
1875         build_isa_devices_aml(dsdt);
1876         build_q35_pci0_int(dsdt);
1877         if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1878             build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1879         }
1880     }
1881 
1882     if (pcmc->legacy_cpu_hotplug) {
1883         build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1884     } else {
1885         CPUHotplugFeatures opts = {
1886             .acpi_1_compatible = true, .has_legacy_cphp = true
1887         };
1888         build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1889                        "\\_SB.PCI0", "\\_GPE._E02");
1890     }
1891     build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1892 
1893     scope =  aml_scope("_GPE");
1894     {
1895         aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1896 
1897         if (misc->is_piix4) {
1898             method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1899             aml_append(method,
1900                 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1901             aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1902             aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1903             aml_append(scope, method);
1904         }
1905 
1906         if (machine->nvdimms_state->is_enabled) {
1907             method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1908             aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1909                                           aml_int(0x80)));
1910             aml_append(scope, method);
1911         }
1912     }
1913     aml_append(dsdt, scope);
1914 
1915     crs_range_set_init(&crs_range_set);
1916     bus = PC_MACHINE(machine)->bus;
1917     if (bus) {
1918         QLIST_FOREACH(bus, &bus->child, sibling) {
1919             uint8_t bus_num = pci_bus_num(bus);
1920             uint8_t numa_node = pci_bus_numa_node(bus);
1921 
1922             /* look only for expander root buses */
1923             if (!pci_bus_is_root(bus)) {
1924                 continue;
1925             }
1926 
1927             if (bus_num < root_bus_limit) {
1928                 root_bus_limit = bus_num - 1;
1929             }
1930 
1931             scope = aml_scope("\\_SB");
1932             dev = aml_device("PC%.02X", bus_num);
1933             aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1934             aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1935             if (pci_bus_is_express(bus)) {
1936                 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1937                 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1938                 aml_append(dev, build_q35_osc_method());
1939             } else {
1940                 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1941             }
1942 
1943             if (numa_node != NUMA_NODE_UNASSIGNED) {
1944                 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1945             }
1946 
1947             aml_append(dev, build_prt(false));
1948             crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1949             aml_append(dev, aml_name_decl("_CRS", crs));
1950             aml_append(scope, dev);
1951             aml_append(dsdt, scope);
1952         }
1953     }
1954 
1955     /*
1956      * At this point crs_range_set has all the ranges used by pci
1957      * busses *other* than PCI0.  These ranges will be excluded from
1958      * the PCI0._CRS.  Add mmconfig to the set so it will be excluded
1959      * too.
1960      */
1961     if (acpi_get_mcfg(&mcfg)) {
1962         crs_range_insert(crs_range_set.mem_ranges,
1963                          mcfg.base, mcfg.base + mcfg.size - 1);
1964     }
1965 
1966     scope = aml_scope("\\_SB.PCI0");
1967     /* build PCI0._CRS */
1968     crs = aml_resource_template();
1969     aml_append(crs,
1970         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1971                             0x0000, 0x0, root_bus_limit,
1972                             0x0000, root_bus_limit + 1));
1973     aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1974 
1975     aml_append(crs,
1976         aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1977                     AML_POS_DECODE, AML_ENTIRE_RANGE,
1978                     0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1979 
1980     crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1981     for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1982         entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1983         aml_append(crs,
1984             aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1985                         AML_POS_DECODE, AML_ENTIRE_RANGE,
1986                         0x0000, entry->base, entry->limit,
1987                         0x0000, entry->limit - entry->base + 1));
1988     }
1989 
1990     aml_append(crs,
1991         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1992                          AML_CACHEABLE, AML_READ_WRITE,
1993                          0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1994 
1995     crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1996                                  range_lob(pci_hole),
1997                                  range_upb(pci_hole));
1998     for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1999         entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2000         aml_append(crs,
2001             aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2002                              AML_NON_CACHEABLE, AML_READ_WRITE,
2003                              0, entry->base, entry->limit,
2004                              0, entry->limit - entry->base + 1));
2005     }
2006 
2007     if (!range_is_empty(pci_hole64)) {
2008         crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2009                                      range_lob(pci_hole64),
2010                                      range_upb(pci_hole64));
2011         for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2012             entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2013             aml_append(crs,
2014                        aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2015                                         AML_MAX_FIXED,
2016                                         AML_CACHEABLE, AML_READ_WRITE,
2017                                         0, entry->base, entry->limit,
2018                                         0, entry->limit - entry->base + 1));
2019         }
2020     }
2021 
2022     if (TPM_IS_TIS(tpm_find())) {
2023         aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2024                    TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2025     }
2026     aml_append(scope, aml_name_decl("_CRS", crs));
2027 
2028     /* reserve GPE0 block resources */
2029     dev = aml_device("GPE0");
2030     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2031     aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2032     /* device present, functioning, decoding, not shown in UI */
2033     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2034     crs = aml_resource_template();
2035     aml_append(crs,
2036         aml_io(
2037                AML_DECODE16,
2038                pm->fadt.gpe0_blk.address,
2039                pm->fadt.gpe0_blk.address,
2040                1,
2041                pm->fadt.gpe0_blk.bit_width / 8)
2042     );
2043     aml_append(dev, aml_name_decl("_CRS", crs));
2044     aml_append(scope, dev);
2045 
2046     crs_range_set_free(&crs_range_set);
2047 
2048     /* reserve PCIHP resources */
2049     if (pm->pcihp_io_len) {
2050         dev = aml_device("PHPR");
2051         aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2052         aml_append(dev,
2053             aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2054         /* device present, functioning, decoding, not shown in UI */
2055         aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2056         crs = aml_resource_template();
2057         aml_append(crs,
2058             aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2059                    pm->pcihp_io_len)
2060         );
2061         aml_append(dev, aml_name_decl("_CRS", crs));
2062         aml_append(scope, dev);
2063     }
2064     aml_append(dsdt, scope);
2065 
2066     /*  create S3_ / S4_ / S5_ packages if necessary */
2067     scope = aml_scope("\\");
2068     if (!pm->s3_disabled) {
2069         pkg = aml_package(4);
2070         aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2071         aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2072         aml_append(pkg, aml_int(0)); /* reserved */
2073         aml_append(pkg, aml_int(0)); /* reserved */
2074         aml_append(scope, aml_name_decl("_S3", pkg));
2075     }
2076 
2077     if (!pm->s4_disabled) {
2078         pkg = aml_package(4);
2079         aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2080         /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2081         aml_append(pkg, aml_int(pm->s4_val));
2082         aml_append(pkg, aml_int(0)); /* reserved */
2083         aml_append(pkg, aml_int(0)); /* reserved */
2084         aml_append(scope, aml_name_decl("_S4", pkg));
2085     }
2086 
2087     pkg = aml_package(4);
2088     aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2089     aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2090     aml_append(pkg, aml_int(0)); /* reserved */
2091     aml_append(pkg, aml_int(0)); /* reserved */
2092     aml_append(scope, aml_name_decl("_S5", pkg));
2093     aml_append(dsdt, scope);
2094 
2095     /* create fw_cfg node, unconditionally */
2096     {
2097         /* when using port i/o, the 8-bit data register *always* overlaps
2098          * with half of the 16-bit control register. Hence, the total size
2099          * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2100          * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2101         uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2102                                                    "dma_enabled", NULL) ?
2103                           ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2104                           FW_CFG_CTL_SIZE;
2105 
2106         scope = aml_scope("\\_SB.PCI0");
2107         dev = aml_device("FWCF");
2108 
2109         aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2110 
2111         /* device present, functioning, decoding, not shown in UI */
2112         aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2113 
2114         crs = aml_resource_template();
2115         aml_append(crs,
2116             aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2117         );
2118         aml_append(dev, aml_name_decl("_CRS", crs));
2119 
2120         aml_append(scope, dev);
2121         aml_append(dsdt, scope);
2122     }
2123 
2124     if (misc->applesmc_io_base) {
2125         scope = aml_scope("\\_SB.PCI0.ISA");
2126         dev = aml_device("SMC");
2127 
2128         aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2129         /* device present, functioning, decoding, not shown in UI */
2130         aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2131 
2132         crs = aml_resource_template();
2133         aml_append(crs,
2134             aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2135                    0x01, APPLESMC_MAX_DATA_LENGTH)
2136         );
2137         aml_append(crs, aml_irq_no_flags(6));
2138         aml_append(dev, aml_name_decl("_CRS", crs));
2139 
2140         aml_append(scope, dev);
2141         aml_append(dsdt, scope);
2142     }
2143 
2144     if (misc->pvpanic_port) {
2145         scope = aml_scope("\\_SB.PCI0.ISA");
2146 
2147         dev = aml_device("PEVT");
2148         aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2149 
2150         crs = aml_resource_template();
2151         aml_append(crs,
2152             aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2153         );
2154         aml_append(dev, aml_name_decl("_CRS", crs));
2155 
2156         aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2157                                               aml_int(misc->pvpanic_port), 1));
2158         field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2159         aml_append(field, aml_named_field("PEPT", 8));
2160         aml_append(dev, field);
2161 
2162         /* device present, functioning, decoding, shown in UI */
2163         aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2164 
2165         method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2166         aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2167         aml_append(method, aml_return(aml_local(0)));
2168         aml_append(dev, method);
2169 
2170         method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2171         aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2172         aml_append(dev, method);
2173 
2174         aml_append(scope, dev);
2175         aml_append(dsdt, scope);
2176     }
2177 
2178     sb_scope = aml_scope("\\_SB");
2179     {
2180         Object *pci_host;
2181         PCIBus *bus = NULL;
2182 
2183         pci_host = acpi_get_i386_pci_host();
2184         if (pci_host) {
2185             bus = PCI_HOST_BRIDGE(pci_host)->bus;
2186         }
2187 
2188         if (bus) {
2189             Aml *scope = aml_scope("PCI0");
2190             /* Scan all PCI buses. Generate tables to support hotplug. */
2191             build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2192 
2193             if (TPM_IS_TIS(tpm)) {
2194                 if (misc->tpm_version == TPM_VERSION_2_0) {
2195                     dev = aml_device("TPM");
2196                     aml_append(dev, aml_name_decl("_HID",
2197                                                   aml_string("MSFT0101")));
2198                 } else {
2199                     dev = aml_device("ISA.TPM");
2200                     aml_append(dev, aml_name_decl("_HID",
2201                                                   aml_eisaid("PNP0C31")));
2202                 }
2203 
2204                 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2205                 crs = aml_resource_template();
2206                 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2207                            TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2208                 /*
2209                     FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2210                     Rewrite to take IRQ from TPM device model and
2211                     fix default IRQ value there to use some unused IRQ
2212                  */
2213                 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2214                 aml_append(dev, aml_name_decl("_CRS", crs));
2215 
2216                 tpm_build_ppi_acpi(tpm, dev);
2217 
2218                 aml_append(scope, dev);
2219             }
2220 
2221             aml_append(sb_scope, scope);
2222         }
2223     }
2224 
2225     if (TPM_IS_CRB(tpm)) {
2226         dev = aml_device("TPM");
2227         aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2228         crs = aml_resource_template();
2229         aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2230                                            TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2231         aml_append(dev, aml_name_decl("_CRS", crs));
2232 
2233         method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2234         aml_append(method, aml_return(aml_int(0x0f)));
2235         aml_append(dev, method);
2236 
2237         tpm_build_ppi_acpi(tpm, dev);
2238 
2239         aml_append(sb_scope, dev);
2240     }
2241 
2242     aml_append(dsdt, sb_scope);
2243 
2244     /* copy AML table into ACPI tables blob and patch header there */
2245     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2246     build_header(linker, table_data,
2247         (void *)(table_data->data + table_data->len - dsdt->buf->len),
2248         "DSDT", dsdt->buf->len, 1, NULL, NULL);
2249     free_aml_allocator();
2250 }
2251 
2252 static void
2253 build_hpet(GArray *table_data, BIOSLinker *linker)
2254 {
2255     Acpi20Hpet *hpet;
2256 
2257     hpet = acpi_data_push(table_data, sizeof(*hpet));
2258     /* Note timer_block_id value must be kept in sync with value advertised by
2259      * emulated hpet
2260      */
2261     hpet->timer_block_id = cpu_to_le32(0x8086a201);
2262     hpet->addr.address = cpu_to_le64(HPET_BASE);
2263     build_header(linker, table_data,
2264                  (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2265 }
2266 
2267 static void
2268 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2269 {
2270     Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2271     unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2272     unsigned log_addr_offset =
2273         (char *)&tcpa->log_area_start_address - table_data->data;
2274 
2275     tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2276     tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2277     acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2278 
2279     bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2280                              false /* high memory */);
2281 
2282     /* log area start address to be filled by Guest linker */
2283     bios_linker_loader_add_pointer(linker,
2284         ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2285         ACPI_BUILD_TPMLOG_FILE, 0);
2286 
2287     build_header(linker, table_data,
2288                  (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2289 }
2290 
2291 static void
2292 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2293 {
2294     Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2295     unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2296     unsigned log_addr_offset =
2297         (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2298 
2299     tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2300     if (TPM_IS_TIS(tpm_find())) {
2301         tpm2_ptr->control_area_address = cpu_to_le64(0);
2302         tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2303     } else if (TPM_IS_CRB(tpm_find())) {
2304         tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2305         tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2306     } else {
2307         g_warn_if_reached();
2308     }
2309 
2310     tpm2_ptr->log_area_minimum_length =
2311         cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2312 
2313     /* log area start address to be filled by Guest linker */
2314     bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2315                                    log_addr_offset, log_addr_size,
2316                                    ACPI_BUILD_TPMLOG_FILE, 0);
2317     build_header(linker, table_data,
2318                  (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2319 }
2320 
2321 #define HOLE_640K_START  (640 * KiB)
2322 #define HOLE_640K_END   (1 * MiB)
2323 
2324 static void
2325 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2326 {
2327     AcpiSystemResourceAffinityTable *srat;
2328     AcpiSratMemoryAffinity *numamem;
2329 
2330     int i;
2331     int srat_start, numa_start, slots;
2332     uint64_t mem_len, mem_base, next_base;
2333     MachineClass *mc = MACHINE_GET_CLASS(machine);
2334     const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2335     PCMachineState *pcms = PC_MACHINE(machine);
2336     ram_addr_t hotplugabble_address_space_size =
2337         object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
2338                                 NULL);
2339 
2340     srat_start = table_data->len;
2341 
2342     srat = acpi_data_push(table_data, sizeof *srat);
2343     srat->reserved1 = cpu_to_le32(1);
2344 
2345     for (i = 0; i < apic_ids->len; i++) {
2346         int node_id = apic_ids->cpus[i].props.node_id;
2347         uint32_t apic_id = apic_ids->cpus[i].arch_id;
2348 
2349         if (apic_id < 255) {
2350             AcpiSratProcessorAffinity *core;
2351 
2352             core = acpi_data_push(table_data, sizeof *core);
2353             core->type = ACPI_SRAT_PROCESSOR_APIC;
2354             core->length = sizeof(*core);
2355             core->local_apic_id = apic_id;
2356             core->proximity_lo = node_id;
2357             memset(core->proximity_hi, 0, 3);
2358             core->local_sapic_eid = 0;
2359             core->flags = cpu_to_le32(1);
2360         } else {
2361             AcpiSratProcessorX2ApicAffinity *core;
2362 
2363             core = acpi_data_push(table_data, sizeof *core);
2364             core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2365             core->length = sizeof(*core);
2366             core->x2apic_id = cpu_to_le32(apic_id);
2367             core->proximity_domain = cpu_to_le32(node_id);
2368             core->flags = cpu_to_le32(1);
2369         }
2370     }
2371 
2372 
2373     /* the memory map is a bit tricky, it contains at least one hole
2374      * from 640k-1M and possibly another one from 3.5G-4G.
2375      */
2376     next_base = 0;
2377     numa_start = table_data->len;
2378 
2379     for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2380         mem_base = next_base;
2381         mem_len = pcms->node_mem[i - 1];
2382         next_base = mem_base + mem_len;
2383 
2384         /* Cut out the 640K hole */
2385         if (mem_base <= HOLE_640K_START &&
2386             next_base > HOLE_640K_START) {
2387             mem_len -= next_base - HOLE_640K_START;
2388             if (mem_len > 0) {
2389                 numamem = acpi_data_push(table_data, sizeof *numamem);
2390                 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2391                                   MEM_AFFINITY_ENABLED);
2392             }
2393 
2394             /* Check for the rare case: 640K < RAM < 1M */
2395             if (next_base <= HOLE_640K_END) {
2396                 next_base = HOLE_640K_END;
2397                 continue;
2398             }
2399             mem_base = HOLE_640K_END;
2400             mem_len = next_base - HOLE_640K_END;
2401         }
2402 
2403         /* Cut out the ACPI_PCI hole */
2404         if (mem_base <= pcms->below_4g_mem_size &&
2405             next_base > pcms->below_4g_mem_size) {
2406             mem_len -= next_base - pcms->below_4g_mem_size;
2407             if (mem_len > 0) {
2408                 numamem = acpi_data_push(table_data, sizeof *numamem);
2409                 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2410                                   MEM_AFFINITY_ENABLED);
2411             }
2412             mem_base = 1ULL << 32;
2413             mem_len = next_base - pcms->below_4g_mem_size;
2414             next_base = mem_base + mem_len;
2415         }
2416 
2417         if (mem_len > 0) {
2418             numamem = acpi_data_push(table_data, sizeof *numamem);
2419             build_srat_memory(numamem, mem_base, mem_len, i - 1,
2420                               MEM_AFFINITY_ENABLED);
2421         }
2422     }
2423     slots = (table_data->len - numa_start) / sizeof *numamem;
2424     for (; slots < pcms->numa_nodes + 2; slots++) {
2425         numamem = acpi_data_push(table_data, sizeof *numamem);
2426         build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2427     }
2428 
2429     /*
2430      * Entry is required for Windows to enable memory hotplug in OS
2431      * and for Linux to enable SWIOTLB when booted with less than
2432      * 4G of RAM. Windows works better if the entry sets proximity
2433      * to the highest NUMA node in the machine.
2434      * Memory devices may override proximity set by this entry,
2435      * providing _PXM method if necessary.
2436      */
2437     if (hotplugabble_address_space_size) {
2438         numamem = acpi_data_push(table_data, sizeof *numamem);
2439         build_srat_memory(numamem, machine->device_memory->base,
2440                           hotplugabble_address_space_size, pcms->numa_nodes - 1,
2441                           MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2442     }
2443 
2444     build_header(linker, table_data,
2445                  (void *)(table_data->data + srat_start),
2446                  "SRAT",
2447                  table_data->len - srat_start, 1, NULL, NULL);
2448 }
2449 
2450 /*
2451  * VT-d spec 8.1 DMA Remapping Reporting Structure
2452  * (version Oct. 2014 or later)
2453  */
2454 static void
2455 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2456 {
2457     int dmar_start = table_data->len;
2458 
2459     AcpiTableDmar *dmar;
2460     AcpiDmarHardwareUnit *drhd;
2461     AcpiDmarRootPortATS *atsr;
2462     uint8_t dmar_flags = 0;
2463     X86IOMMUState *iommu = x86_iommu_get_default();
2464     AcpiDmarDeviceScope *scope = NULL;
2465     /* Root complex IOAPIC use one path[0] only */
2466     size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2467     IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2468 
2469     assert(iommu);
2470     if (x86_iommu_ir_supported(iommu)) {
2471         dmar_flags |= 0x1;      /* Flags: 0x1: INT_REMAP */
2472     }
2473 
2474     dmar = acpi_data_push(table_data, sizeof(*dmar));
2475     dmar->host_address_width = intel_iommu->aw_bits - 1;
2476     dmar->flags = dmar_flags;
2477 
2478     /* DMAR Remapping Hardware Unit Definition structure */
2479     drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2480     drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2481     drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2482     drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2483     drhd->pci_segment = cpu_to_le16(0);
2484     drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2485 
2486     /* Scope definition for the root-complex IOAPIC. See VT-d spec
2487      * 8.3.1 (version Oct. 2014 or later). */
2488     scope = &drhd->scope[0];
2489     scope->entry_type = 0x03;   /* Type: 0x03 for IOAPIC */
2490     scope->length = ioapic_scope_size;
2491     scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2492     scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2493     scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2494     scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2495 
2496     if (iommu->dt_supported) {
2497         atsr = acpi_data_push(table_data, sizeof(*atsr));
2498         atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2499         atsr->length = cpu_to_le16(sizeof(*atsr));
2500         atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2501         atsr->pci_segment = cpu_to_le16(0);
2502     }
2503 
2504     build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2505                  "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2506 }
2507 /*
2508  *   IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2509  *   accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2510  */
2511 #define IOAPIC_SB_DEVID   (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2512 
2513 static void
2514 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2515 {
2516     int ivhd_table_len = 28;
2517     int iommu_start = table_data->len;
2518     AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2519 
2520     /* IVRS header */
2521     acpi_data_push(table_data, sizeof(AcpiTableHeader));
2522     /* IVinfo - IO virtualization information common to all
2523      * IOMMU units in a system
2524      */
2525     build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2526     /* reserved */
2527     build_append_int_noprefix(table_data, 0, 8);
2528 
2529     /* IVHD definition - type 10h */
2530     build_append_int_noprefix(table_data, 0x10, 1);
2531     /* virtualization flags */
2532     build_append_int_noprefix(table_data,
2533                              (1UL << 0) | /* HtTunEn      */
2534                              (1UL << 4) | /* iotblSup     */
2535                              (1UL << 6) | /* PrefSup      */
2536                              (1UL << 7),  /* PPRSup       */
2537                              1);
2538 
2539     /*
2540      * When interrupt remapping is supported, we add a special IVHD device
2541      * for type IO-APIC.
2542      */
2543     if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2544         ivhd_table_len += 8;
2545     }
2546     /* IVHD length */
2547     build_append_int_noprefix(table_data, ivhd_table_len, 2);
2548     /* DeviceID */
2549     build_append_int_noprefix(table_data, s->devid, 2);
2550     /* Capability offset */
2551     build_append_int_noprefix(table_data, s->capab_offset, 2);
2552     /* IOMMU base address */
2553     build_append_int_noprefix(table_data, s->mmio.addr, 8);
2554     /* PCI Segment Group */
2555     build_append_int_noprefix(table_data, 0, 2);
2556     /* IOMMU info */
2557     build_append_int_noprefix(table_data, 0, 2);
2558     /* IOMMU Feature Reporting */
2559     build_append_int_noprefix(table_data,
2560                              (48UL << 30) | /* HATS   */
2561                              (48UL << 28) | /* GATS   */
2562                              (1UL << 2)   | /* GTSup  */
2563                              (1UL << 6),    /* GASup  */
2564                              4);
2565     /*
2566      *   Type 1 device entry reporting all devices
2567      *   These are 4-byte device entries currently reporting the range of
2568      *   Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2569      */
2570     build_append_int_noprefix(table_data, 0x0000001, 4);
2571 
2572     /*
2573      * Add a special IVHD device type.
2574      * Refer to spec - Table 95: IVHD device entry type codes
2575      *
2576      * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2577      * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2578      */
2579     if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2580         build_append_int_noprefix(table_data,
2581                                  (0x1ull << 56) |           /* type IOAPIC */
2582                                  (IOAPIC_SB_DEVID << 40) |  /* IOAPIC devid */
2583                                  0x48,                      /* special device */
2584                                  8);
2585     }
2586 
2587     build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2588                  "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2589 }
2590 
2591 typedef
2592 struct AcpiBuildState {
2593     /* Copy of table in RAM (for patching). */
2594     MemoryRegion *table_mr;
2595     /* Is table patched? */
2596     uint8_t patched;
2597     void *rsdp;
2598     MemoryRegion *rsdp_mr;
2599     MemoryRegion *linker_mr;
2600 } AcpiBuildState;
2601 
2602 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2603 {
2604     Object *pci_host;
2605     QObject *o;
2606 
2607     pci_host = acpi_get_i386_pci_host();
2608     g_assert(pci_host);
2609 
2610     o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2611     if (!o) {
2612         return false;
2613     }
2614     mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2615     qobject_unref(o);
2616     if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2617         return false;
2618     }
2619 
2620     o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2621     assert(o);
2622     mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2623     qobject_unref(o);
2624     return true;
2625 }
2626 
2627 static
2628 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2629 {
2630     PCMachineState *pcms = PC_MACHINE(machine);
2631     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2632     GArray *table_offsets;
2633     unsigned facs, dsdt, rsdt, fadt;
2634     AcpiPmInfo pm;
2635     AcpiMiscInfo misc;
2636     AcpiMcfgInfo mcfg;
2637     Range pci_hole, pci_hole64;
2638     uint8_t *u;
2639     size_t aml_len = 0;
2640     GArray *tables_blob = tables->table_data;
2641     AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2642     Object *vmgenid_dev;
2643 
2644     acpi_get_pm_info(machine, &pm);
2645     acpi_get_misc_info(&misc);
2646     acpi_get_pci_holes(&pci_hole, &pci_hole64);
2647     acpi_get_slic_oem(&slic_oem);
2648 
2649     table_offsets = g_array_new(false, true /* clear */,
2650                                         sizeof(uint32_t));
2651     ACPI_BUILD_DPRINTF("init ACPI tables\n");
2652 
2653     bios_linker_loader_alloc(tables->linker,
2654                              ACPI_BUILD_TABLE_FILE, tables_blob,
2655                              64 /* Ensure FACS is aligned */,
2656                              false /* high memory */);
2657 
2658     /*
2659      * FACS is pointed to by FADT.
2660      * We place it first since it's the only table that has alignment
2661      * requirements.
2662      */
2663     facs = tables_blob->len;
2664     build_facs(tables_blob);
2665 
2666     /* DSDT is pointed to by FADT */
2667     dsdt = tables_blob->len;
2668     build_dsdt(tables_blob, tables->linker, &pm, &misc,
2669                &pci_hole, &pci_hole64, machine);
2670 
2671     /* Count the size of the DSDT and SSDT, we will need it for legacy
2672      * sizing of ACPI tables.
2673      */
2674     aml_len += tables_blob->len - dsdt;
2675 
2676     /* ACPI tables pointed to by RSDT */
2677     fadt = tables_blob->len;
2678     acpi_add_table(table_offsets, tables_blob);
2679     pm.fadt.facs_tbl_offset = &facs;
2680     pm.fadt.dsdt_tbl_offset = &dsdt;
2681     pm.fadt.xdsdt_tbl_offset = &dsdt;
2682     build_fadt(tables_blob, tables->linker, &pm.fadt,
2683                slic_oem.id, slic_oem.table_id);
2684     aml_len += tables_blob->len - fadt;
2685 
2686     acpi_add_table(table_offsets, tables_blob);
2687     build_madt(tables_blob, tables->linker, pcms);
2688 
2689     vmgenid_dev = find_vmgenid_dev();
2690     if (vmgenid_dev) {
2691         acpi_add_table(table_offsets, tables_blob);
2692         vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2693                            tables->vmgenid, tables->linker);
2694     }
2695 
2696     if (misc.has_hpet) {
2697         acpi_add_table(table_offsets, tables_blob);
2698         build_hpet(tables_blob, tables->linker);
2699     }
2700     if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2701         acpi_add_table(table_offsets, tables_blob);
2702         build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2703 
2704         if (misc.tpm_version == TPM_VERSION_2_0) {
2705             acpi_add_table(table_offsets, tables_blob);
2706             build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2707         }
2708     }
2709     if (pcms->numa_nodes) {
2710         acpi_add_table(table_offsets, tables_blob);
2711         build_srat(tables_blob, tables->linker, machine);
2712         if (machine->numa_state->have_numa_distance) {
2713             acpi_add_table(table_offsets, tables_blob);
2714             build_slit(tables_blob, tables->linker, machine);
2715         }
2716     }
2717     if (acpi_get_mcfg(&mcfg)) {
2718         acpi_add_table(table_offsets, tables_blob);
2719         build_mcfg(tables_blob, tables->linker, &mcfg);
2720     }
2721     if (x86_iommu_get_default()) {
2722         IommuType IOMMUType = x86_iommu_get_type();
2723         if (IOMMUType == TYPE_AMD) {
2724             acpi_add_table(table_offsets, tables_blob);
2725             build_amd_iommu(tables_blob, tables->linker);
2726         } else if (IOMMUType == TYPE_INTEL) {
2727             acpi_add_table(table_offsets, tables_blob);
2728             build_dmar_q35(tables_blob, tables->linker);
2729         }
2730     }
2731     if (machine->nvdimms_state->is_enabled) {
2732         nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2733                           machine->nvdimms_state, machine->ram_slots);
2734     }
2735 
2736     /* Add tables supplied by user (if any) */
2737     for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2738         unsigned len = acpi_table_len(u);
2739 
2740         acpi_add_table(table_offsets, tables_blob);
2741         g_array_append_vals(tables_blob, u, len);
2742     }
2743 
2744     /* RSDT is pointed to by RSDP */
2745     rsdt = tables_blob->len;
2746     build_rsdt(tables_blob, tables->linker, table_offsets,
2747                slic_oem.id, slic_oem.table_id);
2748 
2749     /* RSDP is in FSEG memory, so allocate it separately */
2750     {
2751         AcpiRsdpData rsdp_data = {
2752             .revision = 0,
2753             .oem_id = ACPI_BUILD_APPNAME6,
2754             .xsdt_tbl_offset = NULL,
2755             .rsdt_tbl_offset = &rsdt,
2756         };
2757         build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2758         if (!pcmc->rsdp_in_ram) {
2759             /* We used to allocate some extra space for RSDP revision 2 but
2760              * only used the RSDP revision 0 space. The extra bytes were
2761              * zeroed out and not used.
2762              * Here we continue wasting those extra 16 bytes to make sure we
2763              * don't break migration for machine types 2.2 and older due to
2764              * RSDP blob size mismatch.
2765              */
2766             build_append_int_noprefix(tables->rsdp, 0, 16);
2767         }
2768     }
2769 
2770     /* We'll expose it all to Guest so we want to reduce
2771      * chance of size changes.
2772      *
2773      * We used to align the tables to 4k, but of course this would
2774      * too simple to be enough.  4k turned out to be too small an
2775      * alignment very soon, and in fact it is almost impossible to
2776      * keep the table size stable for all (max_cpus, max_memory_slots)
2777      * combinations.  So the table size is always 64k for pc-i440fx-2.1
2778      * and we give an error if the table grows beyond that limit.
2779      *
2780      * We still have the problem of migrating from "-M pc-i440fx-2.0".  For
2781      * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2782      * than 2.0 and we can always pad the smaller tables with zeros.  We can
2783      * then use the exact size of the 2.0 tables.
2784      *
2785      * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2786      */
2787     if (pcmc->legacy_acpi_table_size) {
2788         /* Subtracting aml_len gives the size of fixed tables.  Then add the
2789          * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2790          */
2791         int legacy_aml_len =
2792             pcmc->legacy_acpi_table_size +
2793             ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2794         int legacy_table_size =
2795             ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2796                      ACPI_BUILD_ALIGN_SIZE);
2797         if (tables_blob->len > legacy_table_size) {
2798             /* Should happen only with PCI bridges and -M pc-i440fx-2.0.  */
2799             warn_report("ACPI table size %u exceeds %d bytes,"
2800                         " migration may not work",
2801                         tables_blob->len, legacy_table_size);
2802             error_printf("Try removing CPUs, NUMA nodes, memory slots"
2803                          " or PCI bridges.");
2804         }
2805         g_array_set_size(tables_blob, legacy_table_size);
2806     } else {
2807         /* Make sure we have a buffer in case we need to resize the tables. */
2808         if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2809             /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots.  */
2810             warn_report("ACPI table size %u exceeds %d bytes,"
2811                         " migration may not work",
2812                         tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2813             error_printf("Try removing CPUs, NUMA nodes, memory slots"
2814                          " or PCI bridges.");
2815         }
2816         acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2817     }
2818 
2819     acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2820 
2821     /* Cleanup memory that's no longer used. */
2822     g_array_free(table_offsets, true);
2823 }
2824 
2825 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2826 {
2827     uint32_t size = acpi_data_len(data);
2828 
2829     /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2830     memory_region_ram_resize(mr, size, &error_abort);
2831 
2832     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2833     memory_region_set_dirty(mr, 0, size);
2834 }
2835 
2836 static void acpi_build_update(void *build_opaque)
2837 {
2838     AcpiBuildState *build_state = build_opaque;
2839     AcpiBuildTables tables;
2840 
2841     /* No state to update or already patched? Nothing to do. */
2842     if (!build_state || build_state->patched) {
2843         return;
2844     }
2845     build_state->patched = 1;
2846 
2847     acpi_build_tables_init(&tables);
2848 
2849     acpi_build(&tables, MACHINE(qdev_get_machine()));
2850 
2851     acpi_ram_update(build_state->table_mr, tables.table_data);
2852 
2853     if (build_state->rsdp) {
2854         memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2855     } else {
2856         acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2857     }
2858 
2859     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2860     acpi_build_tables_cleanup(&tables, true);
2861 }
2862 
2863 static void acpi_build_reset(void *build_opaque)
2864 {
2865     AcpiBuildState *build_state = build_opaque;
2866     build_state->patched = 0;
2867 }
2868 
2869 static const VMStateDescription vmstate_acpi_build = {
2870     .name = "acpi_build",
2871     .version_id = 1,
2872     .minimum_version_id = 1,
2873     .fields = (VMStateField[]) {
2874         VMSTATE_UINT8(patched, AcpiBuildState),
2875         VMSTATE_END_OF_LIST()
2876     },
2877 };
2878 
2879 void acpi_setup(void)
2880 {
2881     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2882     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2883     AcpiBuildTables tables;
2884     AcpiBuildState *build_state;
2885     Object *vmgenid_dev;
2886     TPMIf *tpm;
2887     static FwCfgTPMConfig tpm_config;
2888 
2889     if (!pcms->fw_cfg) {
2890         ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2891         return;
2892     }
2893 
2894     if (!pcms->acpi_build_enabled) {
2895         ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2896         return;
2897     }
2898 
2899     if (!acpi_enabled) {
2900         ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2901         return;
2902     }
2903 
2904     build_state = g_malloc0(sizeof *build_state);
2905 
2906     acpi_build_tables_init(&tables);
2907     acpi_build(&tables, MACHINE(pcms));
2908 
2909     /* Now expose it all to Guest */
2910     build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2911                                               build_state, tables.table_data,
2912                                               ACPI_BUILD_TABLE_FILE,
2913                                               ACPI_BUILD_TABLE_MAX_SIZE);
2914     assert(build_state->table_mr != NULL);
2915 
2916     build_state->linker_mr =
2917         acpi_add_rom_blob(acpi_build_update, build_state,
2918                           tables.linker->cmd_blob, "etc/table-loader", 0);
2919 
2920     fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2921                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2922 
2923     tpm = tpm_find();
2924     if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2925         tpm_config = (FwCfgTPMConfig) {
2926             .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2927             .tpm_version = tpm_get_version(tpm),
2928             .tpmppi_version = TPM_PPI_VERSION_1_30
2929         };
2930         fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config",
2931                         &tpm_config, sizeof tpm_config);
2932     }
2933 
2934     vmgenid_dev = find_vmgenid_dev();
2935     if (vmgenid_dev) {
2936         vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2937                            tables.vmgenid);
2938     }
2939 
2940     if (!pcmc->rsdp_in_ram) {
2941         /*
2942          * Keep for compatibility with old machine types.
2943          * Though RSDP is small, its contents isn't immutable, so
2944          * we'll update it along with the rest of tables on guest access.
2945          */
2946         uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2947 
2948         build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2949         fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2950                                  acpi_build_update, NULL, build_state,
2951                                  build_state->rsdp, rsdp_size, true);
2952         build_state->rsdp_mr = NULL;
2953     } else {
2954         build_state->rsdp = NULL;
2955         build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2956                                                  build_state, tables.rsdp,
2957                                                  ACPI_BUILD_RSDP_FILE, 0);
2958     }
2959 
2960     qemu_register_reset(acpi_build_reset, build_state);
2961     acpi_build_reset(build_state);
2962     vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2963 
2964     /* Cleanup tables but don't free the memory: we track it
2965      * in build_state.
2966      */
2967     acpi_build_tables_cleanup(&tables, false);
2968 }
2969