1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "qemu-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "qom/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/block/fdc.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "sysemu/tpm.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/vmgenid.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/timer/mc146818rtc_regs.h" 49 #include "sysemu/numa.h" 50 51 /* Supported chipsets: */ 52 #include "hw/acpi/piix4.h" 53 #include "hw/acpi/pcihp.h" 54 #include "hw/i386/ich9.h" 55 #include "hw/pci/pci_bus.h" 56 #include "hw/pci-host/q35.h" 57 #include "hw/i386/x86-iommu.h" 58 59 #include "hw/acpi/aml-build.h" 60 61 #include "qom/qom-qobject.h" 62 #include "hw/i386/amd_iommu.h" 63 #include "hw/i386/intel_iommu.h" 64 65 #include "hw/acpi/ipmi.h" 66 67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 69 * a little bit, there should be plenty of free space since the DSDT 70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 71 */ 72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 73 #define ACPI_BUILD_ALIGN_SIZE 0x1000 74 75 #define ACPI_BUILD_TABLE_SIZE 0x20000 76 77 /* #define DEBUG_ACPI_BUILD */ 78 #ifdef DEBUG_ACPI_BUILD 79 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 81 #else 82 #define ACPI_BUILD_DPRINTF(fmt, ...) 83 #endif 84 85 /* Default IOAPIC ID */ 86 #define ACPI_BUILD_IOAPIC_ID 0x0 87 88 typedef struct AcpiMcfgInfo { 89 uint64_t mcfg_base; 90 uint32_t mcfg_size; 91 } AcpiMcfgInfo; 92 93 typedef struct AcpiPmInfo { 94 bool s3_disabled; 95 bool s4_disabled; 96 bool pcihp_bridge_en; 97 uint8_t s4_val; 98 AcpiFadtData fadt; 99 uint16_t cpu_hp_io_base; 100 uint16_t pcihp_io_base; 101 uint16_t pcihp_io_len; 102 } AcpiPmInfo; 103 104 typedef struct AcpiMiscInfo { 105 bool is_piix4; 106 bool has_hpet; 107 TPMVersion tpm_version; 108 const unsigned char *dsdt_code; 109 unsigned dsdt_size; 110 uint16_t pvpanic_port; 111 uint16_t applesmc_io_base; 112 } AcpiMiscInfo; 113 114 typedef struct AcpiBuildPciBusHotplugState { 115 GArray *device_table; 116 GArray *notify_table; 117 struct AcpiBuildPciBusHotplugState *parent; 118 bool pcihp_bridge_en; 119 } AcpiBuildPciBusHotplugState; 120 121 static void init_common_fadt_data(Object *o, AcpiFadtData *data) 122 { 123 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 124 AmlAddressSpace as = AML_AS_SYSTEM_IO; 125 AcpiFadtData fadt = { 126 .rev = 3, 127 .flags = 128 (1 << ACPI_FADT_F_WBINVD) | 129 (1 << ACPI_FADT_F_PROC_C1) | 130 (1 << ACPI_FADT_F_SLP_BUTTON) | 131 (1 << ACPI_FADT_F_RTC_S4) | 132 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 133 /* APIC destination mode ("Flat Logical") has an upper limit of 8 134 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 135 * used 136 */ 137 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 138 .int_model = 1 /* Multiple APIC */, 139 .rtc_century = RTC_CENTURY, 140 .plvl2_lat = 0xfff /* C2 state not supported */, 141 .plvl3_lat = 0xfff /* C3 state not supported */, 142 .smi_cmd = ACPI_PORT_SMI_CMD, 143 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 144 .acpi_enable_cmd = 145 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 146 .acpi_disable_cmd = 147 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 148 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 149 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 150 .address = io + 0x04 }, 151 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 152 .gpe0_blk = { .space_id = as, .bit_width = 153 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 154 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 155 }, 156 }; 157 *data = fadt; 158 } 159 160 static void acpi_get_pm_info(AcpiPmInfo *pm) 161 { 162 Object *piix = piix4_pm_find(); 163 Object *lpc = ich9_lpc_find(); 164 Object *obj = piix ? piix : lpc; 165 QObject *o; 166 pm->cpu_hp_io_base = 0; 167 pm->pcihp_io_base = 0; 168 pm->pcihp_io_len = 0; 169 170 init_common_fadt_data(obj, &pm->fadt); 171 if (piix) { 172 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 173 pm->fadt.rev = 1; 174 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 175 pm->pcihp_io_base = 176 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 177 pm->pcihp_io_len = 178 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 179 } 180 if (lpc) { 181 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 182 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 183 pm->fadt.reset_reg = r; 184 pm->fadt.reset_val = 0xf; 185 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 186 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 187 } 188 assert(obj); 189 190 /* The above need not be conditional on machine type because the reset port 191 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 192 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); 193 194 /* Fill in optional s3/s4 related properties */ 195 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 196 if (o) { 197 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 198 } else { 199 pm->s3_disabled = false; 200 } 201 qobject_decref(o); 202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 203 if (o) { 204 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 205 } else { 206 pm->s4_disabled = false; 207 } 208 qobject_decref(o); 209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 210 if (o) { 211 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 212 } else { 213 pm->s4_val = false; 214 } 215 qobject_decref(o); 216 217 pm->pcihp_bridge_en = 218 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 219 NULL); 220 } 221 222 static void acpi_get_misc_info(AcpiMiscInfo *info) 223 { 224 Object *piix = piix4_pm_find(); 225 Object *lpc = ich9_lpc_find(); 226 assert(!!piix != !!lpc); 227 228 if (piix) { 229 info->is_piix4 = true; 230 } 231 if (lpc) { 232 info->is_piix4 = false; 233 } 234 235 info->has_hpet = hpet_find(); 236 info->tpm_version = tpm_get_version(tpm_find()); 237 info->pvpanic_port = pvpanic_port(); 238 info->applesmc_io_base = applesmc_port(); 239 } 240 241 /* 242 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 243 * On i386 arch we only have two pci hosts, so we can look only for them. 244 */ 245 static Object *acpi_get_i386_pci_host(void) 246 { 247 PCIHostState *host; 248 249 host = OBJECT_CHECK(PCIHostState, 250 object_resolve_path("/machine/i440fx", NULL), 251 TYPE_PCI_HOST_BRIDGE); 252 if (!host) { 253 host = OBJECT_CHECK(PCIHostState, 254 object_resolve_path("/machine/q35", NULL), 255 TYPE_PCI_HOST_BRIDGE); 256 } 257 258 return OBJECT(host); 259 } 260 261 static void acpi_get_pci_holes(Range *hole, Range *hole64) 262 { 263 Object *pci_host; 264 265 pci_host = acpi_get_i386_pci_host(); 266 g_assert(pci_host); 267 268 range_set_bounds1(hole, 269 object_property_get_uint(pci_host, 270 PCI_HOST_PROP_PCI_HOLE_START, 271 NULL), 272 object_property_get_uint(pci_host, 273 PCI_HOST_PROP_PCI_HOLE_END, 274 NULL)); 275 range_set_bounds1(hole64, 276 object_property_get_uint(pci_host, 277 PCI_HOST_PROP_PCI_HOLE64_START, 278 NULL), 279 object_property_get_uint(pci_host, 280 PCI_HOST_PROP_PCI_HOLE64_END, 281 NULL)); 282 } 283 284 static void acpi_align_size(GArray *blob, unsigned align) 285 { 286 /* Align size to multiple of given size. This reduces the chance 287 * we need to change size in the future (breaking cross version migration). 288 */ 289 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 290 } 291 292 /* FACS */ 293 static void 294 build_facs(GArray *table_data, BIOSLinker *linker) 295 { 296 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 297 memcpy(&facs->signature, "FACS", 4); 298 facs->length = cpu_to_le32(sizeof(*facs)); 299 } 300 301 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 302 const CPUArchIdList *apic_ids, GArray *entry) 303 { 304 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 305 306 /* ACPI spec says that LAPIC entry for non present 307 * CPU may be omitted from MADT or it must be marked 308 * as disabled. However omitting non present CPU from 309 * MADT breaks hotplug on linux. So possible CPUs 310 * should be put in MADT but kept disabled. 311 */ 312 if (apic_id < 255) { 313 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 314 315 apic->type = ACPI_APIC_PROCESSOR; 316 apic->length = sizeof(*apic); 317 apic->processor_id = uid; 318 apic->local_apic_id = apic_id; 319 if (apic_ids->cpus[uid].cpu != NULL) { 320 apic->flags = cpu_to_le32(1); 321 } else { 322 apic->flags = cpu_to_le32(0); 323 } 324 } else { 325 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 326 327 apic->type = ACPI_APIC_LOCAL_X2APIC; 328 apic->length = sizeof(*apic); 329 apic->uid = cpu_to_le32(uid); 330 apic->x2apic_id = cpu_to_le32(apic_id); 331 if (apic_ids->cpus[uid].cpu != NULL) { 332 apic->flags = cpu_to_le32(1); 333 } else { 334 apic->flags = cpu_to_le32(0); 335 } 336 } 337 } 338 339 static void 340 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 341 { 342 MachineClass *mc = MACHINE_GET_CLASS(pcms); 343 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 344 int madt_start = table_data->len; 345 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 346 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 347 bool x2apic_mode = false; 348 349 AcpiMultipleApicTable *madt; 350 AcpiMadtIoApic *io_apic; 351 AcpiMadtIntsrcovr *intsrcovr; 352 int i; 353 354 madt = acpi_data_push(table_data, sizeof *madt); 355 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 356 madt->flags = cpu_to_le32(1); 357 358 for (i = 0; i < apic_ids->len; i++) { 359 adevc->madt_cpu(adev, i, apic_ids, table_data); 360 if (apic_ids->cpus[i].arch_id > 254) { 361 x2apic_mode = true; 362 } 363 } 364 365 io_apic = acpi_data_push(table_data, sizeof *io_apic); 366 io_apic->type = ACPI_APIC_IO; 367 io_apic->length = sizeof(*io_apic); 368 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 369 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 370 io_apic->interrupt = cpu_to_le32(0); 371 372 if (pcms->apic_xrupt_override) { 373 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 374 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 375 intsrcovr->length = sizeof(*intsrcovr); 376 intsrcovr->source = 0; 377 intsrcovr->gsi = cpu_to_le32(2); 378 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 379 } 380 for (i = 1; i < 16; i++) { 381 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 382 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 383 /* No need for a INT source override structure. */ 384 continue; 385 } 386 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 387 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 388 intsrcovr->length = sizeof(*intsrcovr); 389 intsrcovr->source = i; 390 intsrcovr->gsi = cpu_to_le32(i); 391 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 392 } 393 394 if (x2apic_mode) { 395 AcpiMadtLocalX2ApicNmi *local_nmi; 396 397 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 398 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 399 local_nmi->length = sizeof(*local_nmi); 400 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 401 local_nmi->flags = cpu_to_le16(0); 402 local_nmi->lint = 1; /* ACPI_LINT1 */ 403 } else { 404 AcpiMadtLocalNmi *local_nmi; 405 406 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 407 local_nmi->type = ACPI_APIC_LOCAL_NMI; 408 local_nmi->length = sizeof(*local_nmi); 409 local_nmi->processor_id = 0xff; /* all processors */ 410 local_nmi->flags = cpu_to_le16(0); 411 local_nmi->lint = 1; /* ACPI_LINT1 */ 412 } 413 414 build_header(linker, table_data, 415 (void *)(table_data->data + madt_start), "APIC", 416 table_data->len - madt_start, 1, NULL, NULL); 417 } 418 419 static void build_append_pcihp_notify_entry(Aml *method, int slot) 420 { 421 Aml *if_ctx; 422 int32_t devfn = PCI_DEVFN(slot, 0); 423 424 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 425 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 426 aml_append(method, if_ctx); 427 } 428 429 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 430 bool pcihp_bridge_en) 431 { 432 Aml *dev, *notify_method = NULL, *method; 433 QObject *bsel; 434 PCIBus *sec; 435 int i; 436 437 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 438 if (bsel) { 439 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 440 441 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 442 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 443 } 444 445 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 446 DeviceClass *dc; 447 PCIDeviceClass *pc; 448 PCIDevice *pdev = bus->devices[i]; 449 int slot = PCI_SLOT(i); 450 bool hotplug_enabled_dev; 451 bool bridge_in_acpi; 452 453 if (!pdev) { 454 if (bsel) { /* add hotplug slots for non present devices */ 455 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 456 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 457 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 458 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 459 aml_append(method, 460 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 461 ); 462 aml_append(dev, method); 463 aml_append(parent_scope, dev); 464 465 build_append_pcihp_notify_entry(notify_method, slot); 466 } 467 continue; 468 } 469 470 pc = PCI_DEVICE_GET_CLASS(pdev); 471 dc = DEVICE_GET_CLASS(pdev); 472 473 /* When hotplug for bridges is enabled, bridges are 474 * described in ACPI separately (see build_pci_bus_end). 475 * In this case they aren't themselves hot-pluggable. 476 * Hotplugged bridges *are* hot-pluggable. 477 */ 478 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 479 !DEVICE(pdev)->hotplugged; 480 481 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 482 483 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 484 continue; 485 } 486 487 /* start to compose PCI slot descriptor */ 488 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 489 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 490 491 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 492 /* add VGA specific AML methods */ 493 int s3d; 494 495 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 496 s3d = 3; 497 } else { 498 s3d = 0; 499 } 500 501 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 502 aml_append(method, aml_return(aml_int(0))); 503 aml_append(dev, method); 504 505 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 506 aml_append(method, aml_return(aml_int(0))); 507 aml_append(dev, method); 508 509 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 510 aml_append(method, aml_return(aml_int(s3d))); 511 aml_append(dev, method); 512 } else if (hotplug_enabled_dev) { 513 /* add _SUN/_EJ0 to make slot hotpluggable */ 514 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 515 516 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 517 aml_append(method, 518 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 519 ); 520 aml_append(dev, method); 521 522 if (bsel) { 523 build_append_pcihp_notify_entry(notify_method, slot); 524 } 525 } else if (bridge_in_acpi) { 526 /* 527 * device is coldplugged bridge, 528 * add child device descriptions into its scope 529 */ 530 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 531 532 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 533 } 534 /* slot descriptor has been composed, add it into parent context */ 535 aml_append(parent_scope, dev); 536 } 537 538 if (bsel) { 539 aml_append(parent_scope, notify_method); 540 } 541 542 /* Append PCNT method to notify about events on local and child buses. 543 * Add unconditionally for root since DSDT expects it. 544 */ 545 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 546 547 /* If bus supports hotplug select it and notify about local events */ 548 if (bsel) { 549 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 550 551 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 552 aml_append(method, 553 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 554 ); 555 aml_append(method, 556 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 557 ); 558 } 559 560 /* Notify about child bus events in any case */ 561 if (pcihp_bridge_en) { 562 QLIST_FOREACH(sec, &bus->child, sibling) { 563 int32_t devfn = sec->parent_dev->devfn; 564 565 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 566 continue; 567 } 568 569 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 570 } 571 } 572 aml_append(parent_scope, method); 573 qobject_decref(bsel); 574 } 575 576 /** 577 * build_prt_entry: 578 * @link_name: link name for PCI route entry 579 * 580 * build AML package containing a PCI route entry for @link_name 581 */ 582 static Aml *build_prt_entry(const char *link_name) 583 { 584 Aml *a_zero = aml_int(0); 585 Aml *pkg = aml_package(4); 586 aml_append(pkg, a_zero); 587 aml_append(pkg, a_zero); 588 aml_append(pkg, aml_name("%s", link_name)); 589 aml_append(pkg, a_zero); 590 return pkg; 591 } 592 593 /* 594 * initialize_route - Initialize the interrupt routing rule 595 * through a specific LINK: 596 * if (lnk_idx == idx) 597 * route using link 'link_name' 598 */ 599 static Aml *initialize_route(Aml *route, const char *link_name, 600 Aml *lnk_idx, int idx) 601 { 602 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 603 Aml *pkg = build_prt_entry(link_name); 604 605 aml_append(if_ctx, aml_store(pkg, route)); 606 607 return if_ctx; 608 } 609 610 /* 611 * build_prt - Define interrupt rounting rules 612 * 613 * Returns an array of 128 routes, one for each device, 614 * based on device location. 615 * The main goal is to equaly distribute the interrupts 616 * over the 4 existing ACPI links (works only for i440fx). 617 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 618 * 619 */ 620 static Aml *build_prt(bool is_pci0_prt) 621 { 622 Aml *method, *while_ctx, *pin, *res; 623 624 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 625 res = aml_local(0); 626 pin = aml_local(1); 627 aml_append(method, aml_store(aml_package(128), res)); 628 aml_append(method, aml_store(aml_int(0), pin)); 629 630 /* while (pin < 128) */ 631 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 632 { 633 Aml *slot = aml_local(2); 634 Aml *lnk_idx = aml_local(3); 635 Aml *route = aml_local(4); 636 637 /* slot = pin >> 2 */ 638 aml_append(while_ctx, 639 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 640 /* lnk_idx = (slot + pin) & 3 */ 641 aml_append(while_ctx, 642 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 643 lnk_idx)); 644 645 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 646 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 647 if (is_pci0_prt) { 648 Aml *if_device_1, *if_pin_4, *else_pin_4; 649 650 /* device 1 is the power-management device, needs SCI */ 651 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 652 { 653 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 654 { 655 aml_append(if_pin_4, 656 aml_store(build_prt_entry("LNKS"), route)); 657 } 658 aml_append(if_device_1, if_pin_4); 659 else_pin_4 = aml_else(); 660 { 661 aml_append(else_pin_4, 662 aml_store(build_prt_entry("LNKA"), route)); 663 } 664 aml_append(if_device_1, else_pin_4); 665 } 666 aml_append(while_ctx, if_device_1); 667 } else { 668 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 669 } 670 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 671 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 672 673 /* route[0] = 0x[slot]FFFF */ 674 aml_append(while_ctx, 675 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 676 NULL), 677 aml_index(route, aml_int(0)))); 678 /* route[1] = pin & 3 */ 679 aml_append(while_ctx, 680 aml_store(aml_and(pin, aml_int(3), NULL), 681 aml_index(route, aml_int(1)))); 682 /* res[pin] = route */ 683 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 684 /* pin++ */ 685 aml_append(while_ctx, aml_increment(pin)); 686 } 687 aml_append(method, while_ctx); 688 /* return res*/ 689 aml_append(method, aml_return(res)); 690 691 return method; 692 } 693 694 typedef struct CrsRangeEntry { 695 uint64_t base; 696 uint64_t limit; 697 } CrsRangeEntry; 698 699 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 700 { 701 CrsRangeEntry *entry; 702 703 entry = g_malloc(sizeof(*entry)); 704 entry->base = base; 705 entry->limit = limit; 706 707 g_ptr_array_add(ranges, entry); 708 } 709 710 static void crs_range_free(gpointer data) 711 { 712 CrsRangeEntry *entry = (CrsRangeEntry *)data; 713 g_free(entry); 714 } 715 716 typedef struct CrsRangeSet { 717 GPtrArray *io_ranges; 718 GPtrArray *mem_ranges; 719 GPtrArray *mem_64bit_ranges; 720 } CrsRangeSet; 721 722 static void crs_range_set_init(CrsRangeSet *range_set) 723 { 724 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 725 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 726 range_set->mem_64bit_ranges = 727 g_ptr_array_new_with_free_func(crs_range_free); 728 } 729 730 static void crs_range_set_free(CrsRangeSet *range_set) 731 { 732 g_ptr_array_free(range_set->io_ranges, true); 733 g_ptr_array_free(range_set->mem_ranges, true); 734 g_ptr_array_free(range_set->mem_64bit_ranges, true); 735 } 736 737 static gint crs_range_compare(gconstpointer a, gconstpointer b) 738 { 739 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 740 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 741 742 return (int64_t)entry_a->base - (int64_t)entry_b->base; 743 } 744 745 /* 746 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 747 * interval, computes the 'free' ranges from the same interval. 748 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 749 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 750 */ 751 static void crs_replace_with_free_ranges(GPtrArray *ranges, 752 uint64_t start, uint64_t end) 753 { 754 GPtrArray *free_ranges = g_ptr_array_new(); 755 uint64_t free_base = start; 756 int i; 757 758 g_ptr_array_sort(ranges, crs_range_compare); 759 for (i = 0; i < ranges->len; i++) { 760 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 761 762 if (free_base < used->base) { 763 crs_range_insert(free_ranges, free_base, used->base - 1); 764 } 765 766 free_base = used->limit + 1; 767 } 768 769 if (free_base < end) { 770 crs_range_insert(free_ranges, free_base, end); 771 } 772 773 g_ptr_array_set_size(ranges, 0); 774 for (i = 0; i < free_ranges->len; i++) { 775 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 776 } 777 778 g_ptr_array_free(free_ranges, true); 779 } 780 781 /* 782 * crs_range_merge - merges adjacent ranges in the given array. 783 * Array elements are deleted and replaced with the merged ranges. 784 */ 785 static void crs_range_merge(GPtrArray *range) 786 { 787 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 788 CrsRangeEntry *entry; 789 uint64_t range_base, range_limit; 790 int i; 791 792 if (!range->len) { 793 return; 794 } 795 796 g_ptr_array_sort(range, crs_range_compare); 797 798 entry = g_ptr_array_index(range, 0); 799 range_base = entry->base; 800 range_limit = entry->limit; 801 for (i = 1; i < range->len; i++) { 802 entry = g_ptr_array_index(range, i); 803 if (entry->base - 1 == range_limit) { 804 range_limit = entry->limit; 805 } else { 806 crs_range_insert(tmp, range_base, range_limit); 807 range_base = entry->base; 808 range_limit = entry->limit; 809 } 810 } 811 crs_range_insert(tmp, range_base, range_limit); 812 813 g_ptr_array_set_size(range, 0); 814 for (i = 0; i < tmp->len; i++) { 815 entry = g_ptr_array_index(tmp, i); 816 crs_range_insert(range, entry->base, entry->limit); 817 } 818 g_ptr_array_free(tmp, true); 819 } 820 821 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 822 { 823 Aml *crs = aml_resource_template(); 824 CrsRangeSet temp_range_set; 825 CrsRangeEntry *entry; 826 uint8_t max_bus = pci_bus_num(host->bus); 827 uint8_t type; 828 int devfn; 829 int i; 830 831 crs_range_set_init(&temp_range_set); 832 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 833 uint64_t range_base, range_limit; 834 PCIDevice *dev = host->bus->devices[devfn]; 835 836 if (!dev) { 837 continue; 838 } 839 840 for (i = 0; i < PCI_NUM_REGIONS; i++) { 841 PCIIORegion *r = &dev->io_regions[i]; 842 843 range_base = r->addr; 844 range_limit = r->addr + r->size - 1; 845 846 /* 847 * Work-around for old bioses 848 * that do not support multiple root buses 849 */ 850 if (!range_base || range_base > range_limit) { 851 continue; 852 } 853 854 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 855 crs_range_insert(temp_range_set.io_ranges, 856 range_base, range_limit); 857 } else { /* "memory" */ 858 crs_range_insert(temp_range_set.mem_ranges, 859 range_base, range_limit); 860 } 861 } 862 863 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 864 if (type == PCI_HEADER_TYPE_BRIDGE) { 865 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 866 if (subordinate > max_bus) { 867 max_bus = subordinate; 868 } 869 870 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 871 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 872 873 /* 874 * Work-around for old bioses 875 * that do not support multiple root buses 876 */ 877 if (range_base && range_base <= range_limit) { 878 crs_range_insert(temp_range_set.io_ranges, 879 range_base, range_limit); 880 } 881 882 range_base = 883 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 884 range_limit = 885 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 886 887 /* 888 * Work-around for old bioses 889 * that do not support multiple root buses 890 */ 891 if (range_base && range_base <= range_limit) { 892 uint64_t length = range_limit - range_base + 1; 893 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 894 crs_range_insert(temp_range_set.mem_ranges, 895 range_base, range_limit); 896 } else { 897 crs_range_insert(temp_range_set.mem_64bit_ranges, 898 range_base, range_limit); 899 } 900 } 901 902 range_base = 903 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 904 range_limit = 905 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 906 907 /* 908 * Work-around for old bioses 909 * that do not support multiple root buses 910 */ 911 if (range_base && range_base <= range_limit) { 912 uint64_t length = range_limit - range_base + 1; 913 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 914 crs_range_insert(temp_range_set.mem_ranges, 915 range_base, range_limit); 916 } else { 917 crs_range_insert(temp_range_set.mem_64bit_ranges, 918 range_base, range_limit); 919 } 920 } 921 } 922 } 923 924 crs_range_merge(temp_range_set.io_ranges); 925 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 926 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 927 aml_append(crs, 928 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 929 AML_POS_DECODE, AML_ENTIRE_RANGE, 930 0, entry->base, entry->limit, 0, 931 entry->limit - entry->base + 1)); 932 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 933 } 934 935 crs_range_merge(temp_range_set.mem_ranges); 936 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 937 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 938 aml_append(crs, 939 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 940 AML_MAX_FIXED, AML_NON_CACHEABLE, 941 AML_READ_WRITE, 942 0, entry->base, entry->limit, 0, 943 entry->limit - entry->base + 1)); 944 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 945 } 946 947 crs_range_merge(temp_range_set.mem_64bit_ranges); 948 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 949 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 950 aml_append(crs, 951 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 952 AML_MAX_FIXED, AML_NON_CACHEABLE, 953 AML_READ_WRITE, 954 0, entry->base, entry->limit, 0, 955 entry->limit - entry->base + 1)); 956 crs_range_insert(range_set->mem_64bit_ranges, 957 entry->base, entry->limit); 958 } 959 960 crs_range_set_free(&temp_range_set); 961 962 aml_append(crs, 963 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 964 0, 965 pci_bus_num(host->bus), 966 max_bus, 967 0, 968 max_bus - pci_bus_num(host->bus) + 1)); 969 970 return crs; 971 } 972 973 static void build_hpet_aml(Aml *table) 974 { 975 Aml *crs; 976 Aml *field; 977 Aml *method; 978 Aml *if_ctx; 979 Aml *scope = aml_scope("_SB"); 980 Aml *dev = aml_device("HPET"); 981 Aml *zero = aml_int(0); 982 Aml *id = aml_local(0); 983 Aml *period = aml_local(1); 984 985 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 986 aml_append(dev, aml_name_decl("_UID", zero)); 987 988 aml_append(dev, 989 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 990 HPET_LEN)); 991 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 992 aml_append(field, aml_named_field("VEND", 32)); 993 aml_append(field, aml_named_field("PRD", 32)); 994 aml_append(dev, field); 995 996 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 997 aml_append(method, aml_store(aml_name("VEND"), id)); 998 aml_append(method, aml_store(aml_name("PRD"), period)); 999 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1000 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1001 aml_equal(id, aml_int(0xffff)))); 1002 { 1003 aml_append(if_ctx, aml_return(zero)); 1004 } 1005 aml_append(method, if_ctx); 1006 1007 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1008 aml_lgreater(period, aml_int(100000000)))); 1009 { 1010 aml_append(if_ctx, aml_return(zero)); 1011 } 1012 aml_append(method, if_ctx); 1013 1014 aml_append(method, aml_return(aml_int(0x0F))); 1015 aml_append(dev, method); 1016 1017 crs = aml_resource_template(); 1018 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1019 aml_append(dev, aml_name_decl("_CRS", crs)); 1020 1021 aml_append(scope, dev); 1022 aml_append(table, scope); 1023 } 1024 1025 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1026 { 1027 Aml *dev, *fdi; 1028 uint8_t maxc, maxh, maxs; 1029 1030 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1031 1032 dev = aml_device("FLP%c", 'A' + idx); 1033 1034 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1035 1036 fdi = aml_package(16); 1037 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1038 aml_append(fdi, 1039 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1040 /* 1041 * the values below are the limits of the drive, and are thus independent 1042 * of the inserted media 1043 */ 1044 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1045 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1046 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1047 /* 1048 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1049 * the drive type, so shall we 1050 */ 1051 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1052 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1053 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1054 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1055 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1056 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1057 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1058 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1059 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1060 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1061 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1062 1063 aml_append(dev, aml_name_decl("_FDI", fdi)); 1064 return dev; 1065 } 1066 1067 static Aml *build_fdc_device_aml(ISADevice *fdc) 1068 { 1069 int i; 1070 Aml *dev; 1071 Aml *crs; 1072 1073 #define ACPI_FDE_MAX_FD 4 1074 uint32_t fde_buf[5] = { 1075 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1076 cpu_to_le32(2) /* tape presence (2 == never present) */ 1077 }; 1078 1079 dev = aml_device("FDC0"); 1080 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1081 1082 crs = aml_resource_template(); 1083 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1084 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1085 aml_append(crs, aml_irq_no_flags(6)); 1086 aml_append(crs, 1087 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1088 aml_append(dev, aml_name_decl("_CRS", crs)); 1089 1090 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1091 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1092 1093 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1094 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1095 aml_append(dev, build_fdinfo_aml(i, type)); 1096 } 1097 } 1098 aml_append(dev, aml_name_decl("_FDE", 1099 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1100 1101 return dev; 1102 } 1103 1104 static Aml *build_rtc_device_aml(void) 1105 { 1106 Aml *dev; 1107 Aml *crs; 1108 1109 dev = aml_device("RTC"); 1110 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1111 crs = aml_resource_template(); 1112 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1113 aml_append(crs, aml_irq_no_flags(8)); 1114 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1115 aml_append(dev, aml_name_decl("_CRS", crs)); 1116 1117 return dev; 1118 } 1119 1120 static Aml *build_kbd_device_aml(void) 1121 { 1122 Aml *dev; 1123 Aml *crs; 1124 Aml *method; 1125 1126 dev = aml_device("KBD"); 1127 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1128 1129 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1130 aml_append(method, aml_return(aml_int(0x0f))); 1131 aml_append(dev, method); 1132 1133 crs = aml_resource_template(); 1134 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1135 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1136 aml_append(crs, aml_irq_no_flags(1)); 1137 aml_append(dev, aml_name_decl("_CRS", crs)); 1138 1139 return dev; 1140 } 1141 1142 static Aml *build_mouse_device_aml(void) 1143 { 1144 Aml *dev; 1145 Aml *crs; 1146 Aml *method; 1147 1148 dev = aml_device("MOU"); 1149 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1150 1151 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1152 aml_append(method, aml_return(aml_int(0x0f))); 1153 aml_append(dev, method); 1154 1155 crs = aml_resource_template(); 1156 aml_append(crs, aml_irq_no_flags(12)); 1157 aml_append(dev, aml_name_decl("_CRS", crs)); 1158 1159 return dev; 1160 } 1161 1162 static Aml *build_lpt_device_aml(void) 1163 { 1164 Aml *dev; 1165 Aml *crs; 1166 Aml *method; 1167 Aml *if_ctx; 1168 Aml *else_ctx; 1169 Aml *zero = aml_int(0); 1170 Aml *is_present = aml_local(0); 1171 1172 dev = aml_device("LPT"); 1173 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1174 1175 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1176 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1177 if_ctx = aml_if(aml_equal(is_present, zero)); 1178 { 1179 aml_append(if_ctx, aml_return(aml_int(0x00))); 1180 } 1181 aml_append(method, if_ctx); 1182 else_ctx = aml_else(); 1183 { 1184 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1185 } 1186 aml_append(method, else_ctx); 1187 aml_append(dev, method); 1188 1189 crs = aml_resource_template(); 1190 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1191 aml_append(crs, aml_irq_no_flags(7)); 1192 aml_append(dev, aml_name_decl("_CRS", crs)); 1193 1194 return dev; 1195 } 1196 1197 static Aml *build_com_device_aml(uint8_t uid) 1198 { 1199 Aml *dev; 1200 Aml *crs; 1201 Aml *method; 1202 Aml *if_ctx; 1203 Aml *else_ctx; 1204 Aml *zero = aml_int(0); 1205 Aml *is_present = aml_local(0); 1206 const char *enabled_field = "CAEN"; 1207 uint8_t irq = 4; 1208 uint16_t io_port = 0x03F8; 1209 1210 assert(uid == 1 || uid == 2); 1211 if (uid == 2) { 1212 enabled_field = "CBEN"; 1213 irq = 3; 1214 io_port = 0x02F8; 1215 } 1216 1217 dev = aml_device("COM%d", uid); 1218 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1219 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1220 1221 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1222 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1223 if_ctx = aml_if(aml_equal(is_present, zero)); 1224 { 1225 aml_append(if_ctx, aml_return(aml_int(0x00))); 1226 } 1227 aml_append(method, if_ctx); 1228 else_ctx = aml_else(); 1229 { 1230 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1231 } 1232 aml_append(method, else_ctx); 1233 aml_append(dev, method); 1234 1235 crs = aml_resource_template(); 1236 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1237 aml_append(crs, aml_irq_no_flags(irq)); 1238 aml_append(dev, aml_name_decl("_CRS", crs)); 1239 1240 return dev; 1241 } 1242 1243 static void build_isa_devices_aml(Aml *table) 1244 { 1245 ISADevice *fdc = pc_find_fdc0(); 1246 bool ambiguous; 1247 1248 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1249 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1250 1251 aml_append(scope, build_rtc_device_aml()); 1252 aml_append(scope, build_kbd_device_aml()); 1253 aml_append(scope, build_mouse_device_aml()); 1254 if (fdc) { 1255 aml_append(scope, build_fdc_device_aml(fdc)); 1256 } 1257 aml_append(scope, build_lpt_device_aml()); 1258 aml_append(scope, build_com_device_aml(1)); 1259 aml_append(scope, build_com_device_aml(2)); 1260 1261 if (ambiguous) { 1262 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1263 } else if (!obj) { 1264 error_report("No ISA bus, unable to define IPMI ACPI data"); 1265 } else { 1266 build_acpi_ipmi_devices(scope, BUS(obj)); 1267 } 1268 1269 aml_append(table, scope); 1270 } 1271 1272 static void build_dbg_aml(Aml *table) 1273 { 1274 Aml *field; 1275 Aml *method; 1276 Aml *while_ctx; 1277 Aml *scope = aml_scope("\\"); 1278 Aml *buf = aml_local(0); 1279 Aml *len = aml_local(1); 1280 Aml *idx = aml_local(2); 1281 1282 aml_append(scope, 1283 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1284 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1285 aml_append(field, aml_named_field("DBGB", 8)); 1286 aml_append(scope, field); 1287 1288 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1289 1290 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1291 aml_append(method, aml_to_buffer(buf, buf)); 1292 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1293 aml_append(method, aml_store(aml_int(0), idx)); 1294 1295 while_ctx = aml_while(aml_lless(idx, len)); 1296 aml_append(while_ctx, 1297 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1298 aml_append(while_ctx, aml_increment(idx)); 1299 aml_append(method, while_ctx); 1300 1301 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1302 aml_append(scope, method); 1303 1304 aml_append(table, scope); 1305 } 1306 1307 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1308 { 1309 Aml *dev; 1310 Aml *crs; 1311 Aml *method; 1312 uint32_t irqs[] = {5, 10, 11}; 1313 1314 dev = aml_device("%s", name); 1315 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1316 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1317 1318 crs = aml_resource_template(); 1319 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1320 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1321 aml_append(dev, aml_name_decl("_PRS", crs)); 1322 1323 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1324 aml_append(method, aml_return(aml_call1("IQST", reg))); 1325 aml_append(dev, method); 1326 1327 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1328 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1329 aml_append(dev, method); 1330 1331 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1332 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1333 aml_append(dev, method); 1334 1335 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1336 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1337 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1338 aml_append(dev, method); 1339 1340 return dev; 1341 } 1342 1343 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1344 { 1345 Aml *dev; 1346 Aml *crs; 1347 Aml *method; 1348 uint32_t irqs; 1349 1350 dev = aml_device("%s", name); 1351 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1352 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1353 1354 crs = aml_resource_template(); 1355 irqs = gsi; 1356 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1357 AML_SHARED, &irqs, 1)); 1358 aml_append(dev, aml_name_decl("_PRS", crs)); 1359 1360 aml_append(dev, aml_name_decl("_CRS", crs)); 1361 1362 /* 1363 * _DIS can be no-op because the interrupt cannot be disabled. 1364 */ 1365 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1366 aml_append(dev, method); 1367 1368 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1369 aml_append(dev, method); 1370 1371 return dev; 1372 } 1373 1374 /* _CRS method - get current settings */ 1375 static Aml *build_iqcr_method(bool is_piix4) 1376 { 1377 Aml *if_ctx; 1378 uint32_t irqs; 1379 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1380 Aml *crs = aml_resource_template(); 1381 1382 irqs = 0; 1383 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1384 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1385 aml_append(method, aml_name_decl("PRR0", crs)); 1386 1387 aml_append(method, 1388 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1389 1390 if (is_piix4) { 1391 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1392 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1393 aml_append(method, if_ctx); 1394 } else { 1395 aml_append(method, 1396 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1397 aml_name("PRRI"))); 1398 } 1399 1400 aml_append(method, aml_return(aml_name("PRR0"))); 1401 return method; 1402 } 1403 1404 /* _STA method - get status */ 1405 static Aml *build_irq_status_method(void) 1406 { 1407 Aml *if_ctx; 1408 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1409 1410 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1411 aml_append(if_ctx, aml_return(aml_int(0x09))); 1412 aml_append(method, if_ctx); 1413 aml_append(method, aml_return(aml_int(0x0B))); 1414 return method; 1415 } 1416 1417 static void build_piix4_pci0_int(Aml *table) 1418 { 1419 Aml *dev; 1420 Aml *crs; 1421 Aml *field; 1422 Aml *method; 1423 uint32_t irqs; 1424 Aml *sb_scope = aml_scope("_SB"); 1425 Aml *pci0_scope = aml_scope("PCI0"); 1426 1427 aml_append(pci0_scope, build_prt(true)); 1428 aml_append(sb_scope, pci0_scope); 1429 1430 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1431 aml_append(field, aml_named_field("PRQ0", 8)); 1432 aml_append(field, aml_named_field("PRQ1", 8)); 1433 aml_append(field, aml_named_field("PRQ2", 8)); 1434 aml_append(field, aml_named_field("PRQ3", 8)); 1435 aml_append(sb_scope, field); 1436 1437 aml_append(sb_scope, build_irq_status_method()); 1438 aml_append(sb_scope, build_iqcr_method(true)); 1439 1440 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1441 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1442 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1443 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1444 1445 dev = aml_device("LNKS"); 1446 { 1447 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1448 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1449 1450 crs = aml_resource_template(); 1451 irqs = 9; 1452 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1453 AML_ACTIVE_HIGH, AML_SHARED, 1454 &irqs, 1)); 1455 aml_append(dev, aml_name_decl("_PRS", crs)); 1456 1457 /* The SCI cannot be disabled and is always attached to GSI 9, 1458 * so these are no-ops. We only need this link to override the 1459 * polarity to active high and match the content of the MADT. 1460 */ 1461 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1462 aml_append(method, aml_return(aml_int(0x0b))); 1463 aml_append(dev, method); 1464 1465 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1466 aml_append(dev, method); 1467 1468 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1469 aml_append(method, aml_return(aml_name("_PRS"))); 1470 aml_append(dev, method); 1471 1472 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1473 aml_append(dev, method); 1474 } 1475 aml_append(sb_scope, dev); 1476 1477 aml_append(table, sb_scope); 1478 } 1479 1480 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1481 { 1482 int i; 1483 int head; 1484 Aml *pkg; 1485 char base = name[3] < 'E' ? 'A' : 'E'; 1486 char *s = g_strdup(name); 1487 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1488 1489 assert(strlen(s) == 4); 1490 1491 head = name[3] - base; 1492 for (i = 0; i < 4; i++) { 1493 if (head + i > 3) { 1494 head = i * -1; 1495 } 1496 s[3] = base + head + i; 1497 pkg = aml_package(4); 1498 aml_append(pkg, a_nr); 1499 aml_append(pkg, aml_int(i)); 1500 aml_append(pkg, aml_name("%s", s)); 1501 aml_append(pkg, aml_int(0)); 1502 aml_append(ctx, pkg); 1503 } 1504 g_free(s); 1505 } 1506 1507 static Aml *build_q35_routing_table(const char *str) 1508 { 1509 int i; 1510 Aml *pkg; 1511 char *name = g_strdup_printf("%s ", str); 1512 1513 pkg = aml_package(128); 1514 for (i = 0; i < 0x18; i++) { 1515 name[3] = 'E' + (i & 0x3); 1516 append_q35_prt_entry(pkg, i, name); 1517 } 1518 1519 name[3] = 'E'; 1520 append_q35_prt_entry(pkg, 0x18, name); 1521 1522 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1523 for (i = 0x0019; i < 0x1e; i++) { 1524 name[3] = 'A'; 1525 append_q35_prt_entry(pkg, i, name); 1526 } 1527 1528 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1529 name[3] = 'E'; 1530 append_q35_prt_entry(pkg, 0x1e, name); 1531 name[3] = 'A'; 1532 append_q35_prt_entry(pkg, 0x1f, name); 1533 1534 g_free(name); 1535 return pkg; 1536 } 1537 1538 static void build_q35_pci0_int(Aml *table) 1539 { 1540 Aml *field; 1541 Aml *method; 1542 Aml *sb_scope = aml_scope("_SB"); 1543 Aml *pci0_scope = aml_scope("PCI0"); 1544 1545 /* Zero => PIC mode, One => APIC Mode */ 1546 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1547 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1548 { 1549 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1550 } 1551 aml_append(table, method); 1552 1553 aml_append(pci0_scope, 1554 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1555 aml_append(pci0_scope, 1556 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1557 1558 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1559 { 1560 Aml *if_ctx; 1561 Aml *else_ctx; 1562 1563 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1564 section 6.2.8.1 */ 1565 /* Note: we provide the same info as the PCI routing 1566 table of the Bochs BIOS */ 1567 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1568 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1569 aml_append(method, if_ctx); 1570 else_ctx = aml_else(); 1571 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1572 aml_append(method, else_ctx); 1573 } 1574 aml_append(pci0_scope, method); 1575 aml_append(sb_scope, pci0_scope); 1576 1577 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1578 aml_append(field, aml_named_field("PRQA", 8)); 1579 aml_append(field, aml_named_field("PRQB", 8)); 1580 aml_append(field, aml_named_field("PRQC", 8)); 1581 aml_append(field, aml_named_field("PRQD", 8)); 1582 aml_append(field, aml_reserved_field(0x20)); 1583 aml_append(field, aml_named_field("PRQE", 8)); 1584 aml_append(field, aml_named_field("PRQF", 8)); 1585 aml_append(field, aml_named_field("PRQG", 8)); 1586 aml_append(field, aml_named_field("PRQH", 8)); 1587 aml_append(sb_scope, field); 1588 1589 aml_append(sb_scope, build_irq_status_method()); 1590 aml_append(sb_scope, build_iqcr_method(false)); 1591 1592 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1593 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1594 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1595 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1596 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1597 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1598 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1599 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1600 1601 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1602 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1603 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1604 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1605 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1606 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1607 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1608 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1609 1610 aml_append(table, sb_scope); 1611 } 1612 1613 static void build_q35_isa_bridge(Aml *table) 1614 { 1615 Aml *dev; 1616 Aml *scope; 1617 Aml *field; 1618 1619 scope = aml_scope("_SB.PCI0"); 1620 dev = aml_device("ISA"); 1621 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1622 1623 /* ICH9 PCI to ISA irq remapping */ 1624 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1625 aml_int(0x60), 0x0C)); 1626 1627 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1628 aml_int(0x80), 0x02)); 1629 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1630 aml_append(field, aml_named_field("COMA", 3)); 1631 aml_append(field, aml_reserved_field(1)); 1632 aml_append(field, aml_named_field("COMB", 3)); 1633 aml_append(field, aml_reserved_field(1)); 1634 aml_append(field, aml_named_field("LPTD", 2)); 1635 aml_append(dev, field); 1636 1637 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1638 aml_int(0x82), 0x02)); 1639 /* enable bits */ 1640 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1641 aml_append(field, aml_named_field("CAEN", 1)); 1642 aml_append(field, aml_named_field("CBEN", 1)); 1643 aml_append(field, aml_named_field("LPEN", 1)); 1644 aml_append(dev, field); 1645 1646 aml_append(scope, dev); 1647 aml_append(table, scope); 1648 } 1649 1650 static void build_piix4_pm(Aml *table) 1651 { 1652 Aml *dev; 1653 Aml *scope; 1654 1655 scope = aml_scope("_SB.PCI0"); 1656 dev = aml_device("PX13"); 1657 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1658 1659 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1660 aml_int(0x00), 0xff)); 1661 aml_append(scope, dev); 1662 aml_append(table, scope); 1663 } 1664 1665 static void build_piix4_isa_bridge(Aml *table) 1666 { 1667 Aml *dev; 1668 Aml *scope; 1669 Aml *field; 1670 1671 scope = aml_scope("_SB.PCI0"); 1672 dev = aml_device("ISA"); 1673 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1674 1675 /* PIIX PCI to ISA irq remapping */ 1676 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1677 aml_int(0x60), 0x04)); 1678 /* enable bits */ 1679 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1680 /* Offset(0x5f),, 7, */ 1681 aml_append(field, aml_reserved_field(0x2f8)); 1682 aml_append(field, aml_reserved_field(7)); 1683 aml_append(field, aml_named_field("LPEN", 1)); 1684 /* Offset(0x67),, 3, */ 1685 aml_append(field, aml_reserved_field(0x38)); 1686 aml_append(field, aml_reserved_field(3)); 1687 aml_append(field, aml_named_field("CAEN", 1)); 1688 aml_append(field, aml_reserved_field(3)); 1689 aml_append(field, aml_named_field("CBEN", 1)); 1690 aml_append(dev, field); 1691 1692 aml_append(scope, dev); 1693 aml_append(table, scope); 1694 } 1695 1696 static void build_piix4_pci_hotplug(Aml *table) 1697 { 1698 Aml *scope; 1699 Aml *field; 1700 Aml *method; 1701 1702 scope = aml_scope("_SB.PCI0"); 1703 1704 aml_append(scope, 1705 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1706 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1707 aml_append(field, aml_named_field("PCIU", 32)); 1708 aml_append(field, aml_named_field("PCID", 32)); 1709 aml_append(scope, field); 1710 1711 aml_append(scope, 1712 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1713 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1714 aml_append(field, aml_named_field("B0EJ", 32)); 1715 aml_append(scope, field); 1716 1717 aml_append(scope, 1718 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1719 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1720 aml_append(field, aml_named_field("BNUM", 32)); 1721 aml_append(scope, field); 1722 1723 aml_append(scope, aml_mutex("BLCK", 0)); 1724 1725 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1726 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1727 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1728 aml_append(method, 1729 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1730 aml_append(method, aml_release(aml_name("BLCK"))); 1731 aml_append(method, aml_return(aml_int(0))); 1732 aml_append(scope, method); 1733 1734 aml_append(table, scope); 1735 } 1736 1737 static Aml *build_q35_osc_method(void) 1738 { 1739 Aml *if_ctx; 1740 Aml *if_ctx2; 1741 Aml *else_ctx; 1742 Aml *method; 1743 Aml *a_cwd1 = aml_name("CDW1"); 1744 Aml *a_ctrl = aml_local(0); 1745 1746 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1747 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1748 1749 if_ctx = aml_if(aml_equal( 1750 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1751 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1752 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1753 1754 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1755 1756 /* 1757 * Always allow native PME, AER (no dependencies) 1758 * Allow SHPC (PCI bridges can have SHPC controller) 1759 */ 1760 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1761 1762 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1763 /* Unknown revision */ 1764 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1765 aml_append(if_ctx, if_ctx2); 1766 1767 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1768 /* Capabilities bits were masked */ 1769 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1770 aml_append(if_ctx, if_ctx2); 1771 1772 /* Update DWORD3 in the buffer */ 1773 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1774 aml_append(method, if_ctx); 1775 1776 else_ctx = aml_else(); 1777 /* Unrecognized UUID */ 1778 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1779 aml_append(method, else_ctx); 1780 1781 aml_append(method, aml_return(aml_arg(3))); 1782 return method; 1783 } 1784 1785 static void 1786 build_dsdt(GArray *table_data, BIOSLinker *linker, 1787 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1788 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1789 { 1790 CrsRangeEntry *entry; 1791 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1792 CrsRangeSet crs_range_set; 1793 PCMachineState *pcms = PC_MACHINE(machine); 1794 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1795 uint32_t nr_mem = machine->ram_slots; 1796 int root_bus_limit = 0xFF; 1797 PCIBus *bus = NULL; 1798 int i; 1799 1800 dsdt = init_aml_allocator(); 1801 1802 /* Reserve space for header */ 1803 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1804 1805 build_dbg_aml(dsdt); 1806 if (misc->is_piix4) { 1807 sb_scope = aml_scope("_SB"); 1808 dev = aml_device("PCI0"); 1809 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1810 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1811 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1812 aml_append(sb_scope, dev); 1813 aml_append(dsdt, sb_scope); 1814 1815 build_hpet_aml(dsdt); 1816 build_piix4_pm(dsdt); 1817 build_piix4_isa_bridge(dsdt); 1818 build_isa_devices_aml(dsdt); 1819 build_piix4_pci_hotplug(dsdt); 1820 build_piix4_pci0_int(dsdt); 1821 } else { 1822 sb_scope = aml_scope("_SB"); 1823 dev = aml_device("PCI0"); 1824 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1825 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1826 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1827 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1828 aml_append(dev, build_q35_osc_method()); 1829 aml_append(sb_scope, dev); 1830 aml_append(dsdt, sb_scope); 1831 1832 build_hpet_aml(dsdt); 1833 build_q35_isa_bridge(dsdt); 1834 build_isa_devices_aml(dsdt); 1835 build_q35_pci0_int(dsdt); 1836 } 1837 1838 if (pcmc->legacy_cpu_hotplug) { 1839 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1840 } else { 1841 CPUHotplugFeatures opts = { 1842 .apci_1_compatible = true, .has_legacy_cphp = true 1843 }; 1844 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1845 "\\_SB.PCI0", "\\_GPE._E02"); 1846 } 1847 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03"); 1848 1849 scope = aml_scope("_GPE"); 1850 { 1851 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1852 1853 if (misc->is_piix4) { 1854 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1855 aml_append(method, 1856 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1857 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1858 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1859 aml_append(scope, method); 1860 } 1861 1862 if (pcms->acpi_nvdimm_state.is_enabled) { 1863 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1864 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1865 aml_int(0x80))); 1866 aml_append(scope, method); 1867 } 1868 } 1869 aml_append(dsdt, scope); 1870 1871 crs_range_set_init(&crs_range_set); 1872 bus = PC_MACHINE(machine)->bus; 1873 if (bus) { 1874 QLIST_FOREACH(bus, &bus->child, sibling) { 1875 uint8_t bus_num = pci_bus_num(bus); 1876 uint8_t numa_node = pci_bus_numa_node(bus); 1877 1878 /* look only for expander root buses */ 1879 if (!pci_bus_is_root(bus)) { 1880 continue; 1881 } 1882 1883 if (bus_num < root_bus_limit) { 1884 root_bus_limit = bus_num - 1; 1885 } 1886 1887 scope = aml_scope("\\_SB"); 1888 dev = aml_device("PC%.02X", bus_num); 1889 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1890 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1891 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1892 if (pci_bus_is_express(bus)) { 1893 aml_append(dev, build_q35_osc_method()); 1894 } 1895 1896 if (numa_node != NUMA_NODE_UNASSIGNED) { 1897 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1898 } 1899 1900 aml_append(dev, build_prt(false)); 1901 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1902 aml_append(dev, aml_name_decl("_CRS", crs)); 1903 aml_append(scope, dev); 1904 aml_append(dsdt, scope); 1905 } 1906 } 1907 1908 scope = aml_scope("\\_SB.PCI0"); 1909 /* build PCI0._CRS */ 1910 crs = aml_resource_template(); 1911 aml_append(crs, 1912 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1913 0x0000, 0x0, root_bus_limit, 1914 0x0000, root_bus_limit + 1)); 1915 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1916 1917 aml_append(crs, 1918 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1919 AML_POS_DECODE, AML_ENTIRE_RANGE, 1920 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1921 1922 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1923 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1924 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1925 aml_append(crs, 1926 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1927 AML_POS_DECODE, AML_ENTIRE_RANGE, 1928 0x0000, entry->base, entry->limit, 1929 0x0000, entry->limit - entry->base + 1)); 1930 } 1931 1932 aml_append(crs, 1933 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1934 AML_CACHEABLE, AML_READ_WRITE, 1935 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1936 1937 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1938 range_lob(pci_hole), 1939 range_upb(pci_hole)); 1940 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1941 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1942 aml_append(crs, 1943 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1944 AML_NON_CACHEABLE, AML_READ_WRITE, 1945 0, entry->base, entry->limit, 1946 0, entry->limit - entry->base + 1)); 1947 } 1948 1949 if (!range_is_empty(pci_hole64)) { 1950 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1951 range_lob(pci_hole64), 1952 range_upb(pci_hole64)); 1953 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1954 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1955 aml_append(crs, 1956 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1957 AML_MAX_FIXED, 1958 AML_CACHEABLE, AML_READ_WRITE, 1959 0, entry->base, entry->limit, 1960 0, entry->limit - entry->base + 1)); 1961 } 1962 } 1963 1964 if (TPM_IS_TIS(tpm_find())) { 1965 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1966 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1967 } 1968 aml_append(scope, aml_name_decl("_CRS", crs)); 1969 1970 /* reserve GPE0 block resources */ 1971 dev = aml_device("GPE0"); 1972 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1973 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1974 /* device present, functioning, decoding, not shown in UI */ 1975 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1976 crs = aml_resource_template(); 1977 aml_append(crs, 1978 aml_io( 1979 AML_DECODE16, 1980 pm->fadt.gpe0_blk.address, 1981 pm->fadt.gpe0_blk.address, 1982 1, 1983 pm->fadt.gpe0_blk.bit_width / 8) 1984 ); 1985 aml_append(dev, aml_name_decl("_CRS", crs)); 1986 aml_append(scope, dev); 1987 1988 crs_range_set_free(&crs_range_set); 1989 1990 /* reserve PCIHP resources */ 1991 if (pm->pcihp_io_len) { 1992 dev = aml_device("PHPR"); 1993 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1994 aml_append(dev, 1995 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1996 /* device present, functioning, decoding, not shown in UI */ 1997 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1998 crs = aml_resource_template(); 1999 aml_append(crs, 2000 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2001 pm->pcihp_io_len) 2002 ); 2003 aml_append(dev, aml_name_decl("_CRS", crs)); 2004 aml_append(scope, dev); 2005 } 2006 aml_append(dsdt, scope); 2007 2008 /* create S3_ / S4_ / S5_ packages if necessary */ 2009 scope = aml_scope("\\"); 2010 if (!pm->s3_disabled) { 2011 pkg = aml_package(4); 2012 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2013 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2014 aml_append(pkg, aml_int(0)); /* reserved */ 2015 aml_append(pkg, aml_int(0)); /* reserved */ 2016 aml_append(scope, aml_name_decl("_S3", pkg)); 2017 } 2018 2019 if (!pm->s4_disabled) { 2020 pkg = aml_package(4); 2021 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2022 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2023 aml_append(pkg, aml_int(pm->s4_val)); 2024 aml_append(pkg, aml_int(0)); /* reserved */ 2025 aml_append(pkg, aml_int(0)); /* reserved */ 2026 aml_append(scope, aml_name_decl("_S4", pkg)); 2027 } 2028 2029 pkg = aml_package(4); 2030 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2031 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2032 aml_append(pkg, aml_int(0)); /* reserved */ 2033 aml_append(pkg, aml_int(0)); /* reserved */ 2034 aml_append(scope, aml_name_decl("_S5", pkg)); 2035 aml_append(dsdt, scope); 2036 2037 /* create fw_cfg node, unconditionally */ 2038 { 2039 /* when using port i/o, the 8-bit data register *always* overlaps 2040 * with half of the 16-bit control register. Hence, the total size 2041 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2042 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2043 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2044 "dma_enabled", NULL) ? 2045 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2046 FW_CFG_CTL_SIZE; 2047 2048 scope = aml_scope("\\_SB.PCI0"); 2049 dev = aml_device("FWCF"); 2050 2051 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2052 2053 /* device present, functioning, decoding, not shown in UI */ 2054 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2055 2056 crs = aml_resource_template(); 2057 aml_append(crs, 2058 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2059 ); 2060 aml_append(dev, aml_name_decl("_CRS", crs)); 2061 2062 aml_append(scope, dev); 2063 aml_append(dsdt, scope); 2064 } 2065 2066 if (misc->applesmc_io_base) { 2067 scope = aml_scope("\\_SB.PCI0.ISA"); 2068 dev = aml_device("SMC"); 2069 2070 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2071 /* device present, functioning, decoding, not shown in UI */ 2072 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2073 2074 crs = aml_resource_template(); 2075 aml_append(crs, 2076 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2077 0x01, APPLESMC_MAX_DATA_LENGTH) 2078 ); 2079 aml_append(crs, aml_irq_no_flags(6)); 2080 aml_append(dev, aml_name_decl("_CRS", crs)); 2081 2082 aml_append(scope, dev); 2083 aml_append(dsdt, scope); 2084 } 2085 2086 if (misc->pvpanic_port) { 2087 scope = aml_scope("\\_SB.PCI0.ISA"); 2088 2089 dev = aml_device("PEVT"); 2090 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2091 2092 crs = aml_resource_template(); 2093 aml_append(crs, 2094 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2095 ); 2096 aml_append(dev, aml_name_decl("_CRS", crs)); 2097 2098 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2099 aml_int(misc->pvpanic_port), 1)); 2100 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2101 aml_append(field, aml_named_field("PEPT", 8)); 2102 aml_append(dev, field); 2103 2104 /* device present, functioning, decoding, shown in UI */ 2105 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2106 2107 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2108 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2109 aml_append(method, aml_return(aml_local(0))); 2110 aml_append(dev, method); 2111 2112 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2113 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2114 aml_append(dev, method); 2115 2116 aml_append(scope, dev); 2117 aml_append(dsdt, scope); 2118 } 2119 2120 sb_scope = aml_scope("\\_SB"); 2121 { 2122 Object *pci_host; 2123 PCIBus *bus = NULL; 2124 2125 pci_host = acpi_get_i386_pci_host(); 2126 if (pci_host) { 2127 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2128 } 2129 2130 if (bus) { 2131 Aml *scope = aml_scope("PCI0"); 2132 /* Scan all PCI buses. Generate tables to support hotplug. */ 2133 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2134 2135 if (TPM_IS_TIS(tpm_find())) { 2136 dev = aml_device("ISA.TPM"); 2137 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2138 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2139 crs = aml_resource_template(); 2140 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2141 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2142 /* 2143 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2144 Rewrite to take IRQ from TPM device model and 2145 fix default IRQ value there to use some unused IRQ 2146 */ 2147 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2148 aml_append(dev, aml_name_decl("_CRS", crs)); 2149 aml_append(scope, dev); 2150 } 2151 2152 aml_append(sb_scope, scope); 2153 } 2154 } 2155 2156 if (TPM_IS_CRB(tpm_find())) { 2157 dev = aml_device("TPM"); 2158 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 2159 crs = aml_resource_template(); 2160 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 2161 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 2162 aml_append(dev, aml_name_decl("_CRS", crs)); 2163 2164 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 2165 aml_append(method, aml_return(aml_int(0x0f))); 2166 aml_append(dev, method); 2167 2168 aml_append(sb_scope, dev); 2169 } 2170 2171 aml_append(dsdt, sb_scope); 2172 2173 /* copy AML table into ACPI tables blob and patch header there */ 2174 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2175 build_header(linker, table_data, 2176 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2177 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2178 free_aml_allocator(); 2179 } 2180 2181 static void 2182 build_hpet(GArray *table_data, BIOSLinker *linker) 2183 { 2184 Acpi20Hpet *hpet; 2185 2186 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2187 /* Note timer_block_id value must be kept in sync with value advertised by 2188 * emulated hpet 2189 */ 2190 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2191 hpet->addr.address = cpu_to_le64(HPET_BASE); 2192 build_header(linker, table_data, 2193 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2194 } 2195 2196 static void 2197 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2198 { 2199 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2200 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2201 unsigned log_addr_offset = 2202 (char *)&tcpa->log_area_start_address - table_data->data; 2203 2204 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2205 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2206 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2207 2208 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2209 false /* high memory */); 2210 2211 /* log area start address to be filled by Guest linker */ 2212 bios_linker_loader_add_pointer(linker, 2213 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2214 ACPI_BUILD_TPMLOG_FILE, 0); 2215 2216 build_header(linker, table_data, 2217 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2218 } 2219 2220 static void 2221 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2222 { 2223 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2224 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address); 2225 unsigned log_addr_offset = 2226 (char *)&tpm2_ptr->log_area_start_address - table_data->data; 2227 2228 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2229 if (TPM_IS_TIS(tpm_find())) { 2230 tpm2_ptr->control_area_address = cpu_to_le64(0); 2231 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2232 } else if (TPM_IS_CRB(tpm_find())) { 2233 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL); 2234 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB); 2235 } else { 2236 g_warn_if_reached(); 2237 } 2238 2239 tpm2_ptr->log_area_minimum_length = 2240 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2241 2242 /* log area start address to be filled by Guest linker */ 2243 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2244 log_addr_offset, log_addr_size, 2245 ACPI_BUILD_TPMLOG_FILE, 0); 2246 build_header(linker, table_data, 2247 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2248 } 2249 2250 #define HOLE_640K_START (640 * 1024) 2251 #define HOLE_640K_END (1024 * 1024) 2252 2253 static void build_srat_hotpluggable_memory(GArray *table_data, uint64_t base, 2254 uint64_t len, int default_node) 2255 { 2256 MemoryDeviceInfoList *info_list = qmp_pc_dimm_device_list(); 2257 MemoryDeviceInfoList *info; 2258 MemoryDeviceInfo *mi; 2259 PCDIMMDeviceInfo *di; 2260 uint64_t end = base + len, cur, size; 2261 bool is_nvdimm; 2262 AcpiSratMemoryAffinity *numamem; 2263 MemoryAffinityFlags flags; 2264 2265 for (cur = base, info = info_list; 2266 cur < end; 2267 cur += size, info = info->next) { 2268 numamem = acpi_data_push(table_data, sizeof *numamem); 2269 2270 if (!info) { 2271 build_srat_memory(numamem, cur, end - cur, default_node, 2272 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2273 break; 2274 } 2275 2276 mi = info->value; 2277 is_nvdimm = (mi->type == MEMORY_DEVICE_INFO_KIND_NVDIMM); 2278 di = !is_nvdimm ? mi->u.dimm.data : mi->u.nvdimm.data; 2279 2280 if (cur < di->addr) { 2281 build_srat_memory(numamem, cur, di->addr - cur, default_node, 2282 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2283 numamem = acpi_data_push(table_data, sizeof *numamem); 2284 } 2285 2286 size = di->size; 2287 2288 flags = MEM_AFFINITY_ENABLED; 2289 if (di->hotpluggable) { 2290 flags |= MEM_AFFINITY_HOTPLUGGABLE; 2291 } 2292 if (is_nvdimm) { 2293 flags |= MEM_AFFINITY_NON_VOLATILE; 2294 } 2295 2296 build_srat_memory(numamem, di->addr, size, di->node, flags); 2297 } 2298 2299 qapi_free_MemoryDeviceInfoList(info_list); 2300 } 2301 2302 static void 2303 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2304 { 2305 AcpiSystemResourceAffinityTable *srat; 2306 AcpiSratMemoryAffinity *numamem; 2307 2308 int i; 2309 int srat_start, numa_start, slots; 2310 uint64_t mem_len, mem_base, next_base; 2311 MachineClass *mc = MACHINE_GET_CLASS(machine); 2312 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2313 PCMachineState *pcms = PC_MACHINE(machine); 2314 ram_addr_t hotplugabble_address_space_size = 2315 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2316 NULL); 2317 2318 srat_start = table_data->len; 2319 2320 srat = acpi_data_push(table_data, sizeof *srat); 2321 srat->reserved1 = cpu_to_le32(1); 2322 2323 for (i = 0; i < apic_ids->len; i++) { 2324 int node_id = apic_ids->cpus[i].props.node_id; 2325 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2326 2327 if (apic_id < 255) { 2328 AcpiSratProcessorAffinity *core; 2329 2330 core = acpi_data_push(table_data, sizeof *core); 2331 core->type = ACPI_SRAT_PROCESSOR_APIC; 2332 core->length = sizeof(*core); 2333 core->local_apic_id = apic_id; 2334 core->proximity_lo = node_id; 2335 memset(core->proximity_hi, 0, 3); 2336 core->local_sapic_eid = 0; 2337 core->flags = cpu_to_le32(1); 2338 } else { 2339 AcpiSratProcessorX2ApicAffinity *core; 2340 2341 core = acpi_data_push(table_data, sizeof *core); 2342 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2343 core->length = sizeof(*core); 2344 core->x2apic_id = cpu_to_le32(apic_id); 2345 core->proximity_domain = cpu_to_le32(node_id); 2346 core->flags = cpu_to_le32(1); 2347 } 2348 } 2349 2350 2351 /* the memory map is a bit tricky, it contains at least one hole 2352 * from 640k-1M and possibly another one from 3.5G-4G. 2353 */ 2354 next_base = 0; 2355 numa_start = table_data->len; 2356 2357 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2358 mem_base = next_base; 2359 mem_len = pcms->node_mem[i - 1]; 2360 next_base = mem_base + mem_len; 2361 2362 /* Cut out the 640K hole */ 2363 if (mem_base <= HOLE_640K_START && 2364 next_base > HOLE_640K_START) { 2365 mem_len -= next_base - HOLE_640K_START; 2366 if (mem_len > 0) { 2367 numamem = acpi_data_push(table_data, sizeof *numamem); 2368 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2369 MEM_AFFINITY_ENABLED); 2370 } 2371 2372 /* Check for the rare case: 640K < RAM < 1M */ 2373 if (next_base <= HOLE_640K_END) { 2374 next_base = HOLE_640K_END; 2375 continue; 2376 } 2377 mem_base = HOLE_640K_END; 2378 mem_len = next_base - HOLE_640K_END; 2379 } 2380 2381 /* Cut out the ACPI_PCI hole */ 2382 if (mem_base <= pcms->below_4g_mem_size && 2383 next_base > pcms->below_4g_mem_size) { 2384 mem_len -= next_base - pcms->below_4g_mem_size; 2385 if (mem_len > 0) { 2386 numamem = acpi_data_push(table_data, sizeof *numamem); 2387 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2388 MEM_AFFINITY_ENABLED); 2389 } 2390 mem_base = 1ULL << 32; 2391 mem_len = next_base - pcms->below_4g_mem_size; 2392 next_base = mem_base + mem_len; 2393 } 2394 numamem = acpi_data_push(table_data, sizeof *numamem); 2395 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2396 MEM_AFFINITY_ENABLED); 2397 } 2398 slots = (table_data->len - numa_start) / sizeof *numamem; 2399 for (; slots < pcms->numa_nodes + 2; slots++) { 2400 numamem = acpi_data_push(table_data, sizeof *numamem); 2401 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2402 } 2403 2404 /* 2405 * Entry is required for Windows to enable memory hotplug in OS 2406 * and for Linux to enable SWIOTLB when booted with less than 2407 * 4G of RAM. Windows works better if the entry sets proximity 2408 * to the highest NUMA node in the machine. 2409 * Memory devices may override proximity set by this entry, 2410 * providing _PXM method if necessary. 2411 */ 2412 if (hotplugabble_address_space_size) { 2413 build_srat_hotpluggable_memory(table_data, pcms->hotplug_memory.base, 2414 hotplugabble_address_space_size, 2415 pcms->numa_nodes - 1); 2416 } 2417 2418 build_header(linker, table_data, 2419 (void *)(table_data->data + srat_start), 2420 "SRAT", 2421 table_data->len - srat_start, 1, NULL, NULL); 2422 } 2423 2424 static void 2425 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) 2426 { 2427 AcpiTableMcfg *mcfg; 2428 const char *sig; 2429 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2430 2431 mcfg = acpi_data_push(table_data, len); 2432 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2433 /* Only a single allocation so no need to play with segments */ 2434 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2435 mcfg->allocation[0].start_bus_number = 0; 2436 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2437 2438 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2439 * To avoid table size changes (which create migration issues), 2440 * always create the table even if there are no allocations, 2441 * but set the signature to a reserved value in this case. 2442 * ACPI spec requires OSPMs to ignore such tables. 2443 */ 2444 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2445 /* Reserved signature: ignored by OSPM */ 2446 sig = "QEMU"; 2447 } else { 2448 sig = "MCFG"; 2449 } 2450 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL); 2451 } 2452 2453 /* 2454 * VT-d spec 8.1 DMA Remapping Reporting Structure 2455 * (version Oct. 2014 or later) 2456 */ 2457 static void 2458 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2459 { 2460 int dmar_start = table_data->len; 2461 2462 AcpiTableDmar *dmar; 2463 AcpiDmarHardwareUnit *drhd; 2464 AcpiDmarRootPortATS *atsr; 2465 uint8_t dmar_flags = 0; 2466 X86IOMMUState *iommu = x86_iommu_get_default(); 2467 AcpiDmarDeviceScope *scope = NULL; 2468 /* Root complex IOAPIC use one path[0] only */ 2469 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2470 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2471 2472 assert(iommu); 2473 if (iommu->intr_supported) { 2474 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2475 } 2476 2477 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2478 dmar->host_address_width = intel_iommu->aw_bits - 1; 2479 dmar->flags = dmar_flags; 2480 2481 /* DMAR Remapping Hardware Unit Definition structure */ 2482 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2483 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2484 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2485 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2486 drhd->pci_segment = cpu_to_le16(0); 2487 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2488 2489 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2490 * 8.3.1 (version Oct. 2014 or later). */ 2491 scope = &drhd->scope[0]; 2492 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2493 scope->length = ioapic_scope_size; 2494 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2495 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2496 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2497 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2498 2499 if (iommu->dt_supported) { 2500 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2501 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2502 atsr->length = cpu_to_le16(sizeof(*atsr)); 2503 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2504 atsr->pci_segment = cpu_to_le16(0); 2505 } 2506 2507 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2508 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2509 } 2510 /* 2511 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2512 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2513 */ 2514 static void 2515 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2516 { 2517 int iommu_start = table_data->len; 2518 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2519 2520 /* IVRS header */ 2521 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2522 /* IVinfo - IO virtualization information common to all 2523 * IOMMU units in a system 2524 */ 2525 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2526 /* reserved */ 2527 build_append_int_noprefix(table_data, 0, 8); 2528 2529 /* IVHD definition - type 10h */ 2530 build_append_int_noprefix(table_data, 0x10, 1); 2531 /* virtualization flags */ 2532 build_append_int_noprefix(table_data, 2533 (1UL << 0) | /* HtTunEn */ 2534 (1UL << 4) | /* iotblSup */ 2535 (1UL << 6) | /* PrefSup */ 2536 (1UL << 7), /* PPRSup */ 2537 1); 2538 /* IVHD length */ 2539 build_append_int_noprefix(table_data, 0x24, 2); 2540 /* DeviceID */ 2541 build_append_int_noprefix(table_data, s->devid, 2); 2542 /* Capability offset */ 2543 build_append_int_noprefix(table_data, s->capab_offset, 2); 2544 /* IOMMU base address */ 2545 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2546 /* PCI Segment Group */ 2547 build_append_int_noprefix(table_data, 0, 2); 2548 /* IOMMU info */ 2549 build_append_int_noprefix(table_data, 0, 2); 2550 /* IOMMU Feature Reporting */ 2551 build_append_int_noprefix(table_data, 2552 (48UL << 30) | /* HATS */ 2553 (48UL << 28) | /* GATS */ 2554 (1UL << 2), /* GTSup */ 2555 4); 2556 /* 2557 * Type 1 device entry reporting all devices 2558 * These are 4-byte device entries currently reporting the range of 2559 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2560 */ 2561 build_append_int_noprefix(table_data, 0x0000001, 4); 2562 2563 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2564 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2565 } 2566 2567 static GArray * 2568 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset) 2569 { 2570 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2571 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address); 2572 unsigned rsdt_pa_offset = 2573 (char *)&rsdp->rsdt_physical_address - rsdp_table->data; 2574 2575 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16, 2576 true /* fseg memory */); 2577 2578 memcpy(&rsdp->signature, "RSD PTR ", 8); 2579 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2580 /* Address to be filled by Guest linker */ 2581 bios_linker_loader_add_pointer(linker, 2582 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size, 2583 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset); 2584 2585 /* Checksum to be filled by Guest linker */ 2586 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2587 (char *)rsdp - rsdp_table->data, sizeof *rsdp, 2588 (char *)&rsdp->checksum - rsdp_table->data); 2589 2590 return rsdp_table; 2591 } 2592 2593 typedef 2594 struct AcpiBuildState { 2595 /* Copy of table in RAM (for patching). */ 2596 MemoryRegion *table_mr; 2597 /* Is table patched? */ 2598 uint8_t patched; 2599 void *rsdp; 2600 MemoryRegion *rsdp_mr; 2601 MemoryRegion *linker_mr; 2602 } AcpiBuildState; 2603 2604 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2605 { 2606 Object *pci_host; 2607 QObject *o; 2608 2609 pci_host = acpi_get_i386_pci_host(); 2610 g_assert(pci_host); 2611 2612 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2613 if (!o) { 2614 return false; 2615 } 2616 mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o)); 2617 qobject_decref(o); 2618 2619 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2620 assert(o); 2621 mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o)); 2622 qobject_decref(o); 2623 return true; 2624 } 2625 2626 static 2627 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2628 { 2629 PCMachineState *pcms = PC_MACHINE(machine); 2630 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2631 GArray *table_offsets; 2632 unsigned facs, dsdt, rsdt, fadt; 2633 AcpiPmInfo pm; 2634 AcpiMiscInfo misc; 2635 AcpiMcfgInfo mcfg; 2636 Range pci_hole, pci_hole64; 2637 uint8_t *u; 2638 size_t aml_len = 0; 2639 GArray *tables_blob = tables->table_data; 2640 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2641 Object *vmgenid_dev; 2642 2643 acpi_get_pm_info(&pm); 2644 acpi_get_misc_info(&misc); 2645 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2646 acpi_get_slic_oem(&slic_oem); 2647 2648 table_offsets = g_array_new(false, true /* clear */, 2649 sizeof(uint32_t)); 2650 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2651 2652 bios_linker_loader_alloc(tables->linker, 2653 ACPI_BUILD_TABLE_FILE, tables_blob, 2654 64 /* Ensure FACS is aligned */, 2655 false /* high memory */); 2656 2657 /* 2658 * FACS is pointed to by FADT. 2659 * We place it first since it's the only table that has alignment 2660 * requirements. 2661 */ 2662 facs = tables_blob->len; 2663 build_facs(tables_blob, tables->linker); 2664 2665 /* DSDT is pointed to by FADT */ 2666 dsdt = tables_blob->len; 2667 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2668 &pci_hole, &pci_hole64, machine); 2669 2670 /* Count the size of the DSDT and SSDT, we will need it for legacy 2671 * sizing of ACPI tables. 2672 */ 2673 aml_len += tables_blob->len - dsdt; 2674 2675 /* ACPI tables pointed to by RSDT */ 2676 fadt = tables_blob->len; 2677 acpi_add_table(table_offsets, tables_blob); 2678 pm.fadt.facs_tbl_offset = &facs; 2679 pm.fadt.dsdt_tbl_offset = &dsdt; 2680 pm.fadt.xdsdt_tbl_offset = &dsdt; 2681 build_fadt(tables_blob, tables->linker, &pm.fadt, 2682 slic_oem.id, slic_oem.table_id); 2683 aml_len += tables_blob->len - fadt; 2684 2685 acpi_add_table(table_offsets, tables_blob); 2686 build_madt(tables_blob, tables->linker, pcms); 2687 2688 vmgenid_dev = find_vmgenid_dev(); 2689 if (vmgenid_dev) { 2690 acpi_add_table(table_offsets, tables_blob); 2691 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2692 tables->vmgenid, tables->linker); 2693 } 2694 2695 if (misc.has_hpet) { 2696 acpi_add_table(table_offsets, tables_blob); 2697 build_hpet(tables_blob, tables->linker); 2698 } 2699 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2700 acpi_add_table(table_offsets, tables_blob); 2701 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2702 2703 if (misc.tpm_version == TPM_VERSION_2_0) { 2704 acpi_add_table(table_offsets, tables_blob); 2705 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2706 } 2707 } 2708 if (pcms->numa_nodes) { 2709 acpi_add_table(table_offsets, tables_blob); 2710 build_srat(tables_blob, tables->linker, machine); 2711 if (have_numa_distance) { 2712 acpi_add_table(table_offsets, tables_blob); 2713 build_slit(tables_blob, tables->linker); 2714 } 2715 } 2716 if (acpi_get_mcfg(&mcfg)) { 2717 acpi_add_table(table_offsets, tables_blob); 2718 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2719 } 2720 if (x86_iommu_get_default()) { 2721 IommuType IOMMUType = x86_iommu_get_type(); 2722 if (IOMMUType == TYPE_AMD) { 2723 acpi_add_table(table_offsets, tables_blob); 2724 build_amd_iommu(tables_blob, tables->linker); 2725 } else if (IOMMUType == TYPE_INTEL) { 2726 acpi_add_table(table_offsets, tables_blob); 2727 build_dmar_q35(tables_blob, tables->linker); 2728 } 2729 } 2730 if (pcms->acpi_nvdimm_state.is_enabled) { 2731 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2732 &pcms->acpi_nvdimm_state, machine->ram_slots); 2733 } 2734 2735 /* Add tables supplied by user (if any) */ 2736 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2737 unsigned len = acpi_table_len(u); 2738 2739 acpi_add_table(table_offsets, tables_blob); 2740 g_array_append_vals(tables_blob, u, len); 2741 } 2742 2743 /* RSDT is pointed to by RSDP */ 2744 rsdt = tables_blob->len; 2745 build_rsdt(tables_blob, tables->linker, table_offsets, 2746 slic_oem.id, slic_oem.table_id); 2747 2748 /* RSDP is in FSEG memory, so allocate it separately */ 2749 build_rsdp(tables->rsdp, tables->linker, rsdt); 2750 2751 /* We'll expose it all to Guest so we want to reduce 2752 * chance of size changes. 2753 * 2754 * We used to align the tables to 4k, but of course this would 2755 * too simple to be enough. 4k turned out to be too small an 2756 * alignment very soon, and in fact it is almost impossible to 2757 * keep the table size stable for all (max_cpus, max_memory_slots) 2758 * combinations. So the table size is always 64k for pc-i440fx-2.1 2759 * and we give an error if the table grows beyond that limit. 2760 * 2761 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2762 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2763 * than 2.0 and we can always pad the smaller tables with zeros. We can 2764 * then use the exact size of the 2.0 tables. 2765 * 2766 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2767 */ 2768 if (pcmc->legacy_acpi_table_size) { 2769 /* Subtracting aml_len gives the size of fixed tables. Then add the 2770 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2771 */ 2772 int legacy_aml_len = 2773 pcmc->legacy_acpi_table_size + 2774 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit; 2775 int legacy_table_size = 2776 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2777 ACPI_BUILD_ALIGN_SIZE); 2778 if (tables_blob->len > legacy_table_size) { 2779 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2780 warn_report("ACPI table size %u exceeds %d bytes," 2781 " migration may not work", 2782 tables_blob->len, legacy_table_size); 2783 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2784 " or PCI bridges."); 2785 } 2786 g_array_set_size(tables_blob, legacy_table_size); 2787 } else { 2788 /* Make sure we have a buffer in case we need to resize the tables. */ 2789 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2790 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2791 warn_report("ACPI table size %u exceeds %d bytes," 2792 " migration may not work", 2793 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2794 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2795 " or PCI bridges."); 2796 } 2797 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2798 } 2799 2800 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2801 2802 /* Cleanup memory that's no longer used. */ 2803 g_array_free(table_offsets, true); 2804 } 2805 2806 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2807 { 2808 uint32_t size = acpi_data_len(data); 2809 2810 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2811 memory_region_ram_resize(mr, size, &error_abort); 2812 2813 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2814 memory_region_set_dirty(mr, 0, size); 2815 } 2816 2817 static void acpi_build_update(void *build_opaque) 2818 { 2819 AcpiBuildState *build_state = build_opaque; 2820 AcpiBuildTables tables; 2821 2822 /* No state to update or already patched? Nothing to do. */ 2823 if (!build_state || build_state->patched) { 2824 return; 2825 } 2826 build_state->patched = 1; 2827 2828 acpi_build_tables_init(&tables); 2829 2830 acpi_build(&tables, MACHINE(qdev_get_machine())); 2831 2832 acpi_ram_update(build_state->table_mr, tables.table_data); 2833 2834 if (build_state->rsdp) { 2835 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2836 } else { 2837 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2838 } 2839 2840 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2841 acpi_build_tables_cleanup(&tables, true); 2842 } 2843 2844 static void acpi_build_reset(void *build_opaque) 2845 { 2846 AcpiBuildState *build_state = build_opaque; 2847 build_state->patched = 0; 2848 } 2849 2850 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2851 GArray *blob, const char *name, 2852 uint64_t max_size) 2853 { 2854 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2855 name, acpi_build_update, build_state, NULL, true); 2856 } 2857 2858 static const VMStateDescription vmstate_acpi_build = { 2859 .name = "acpi_build", 2860 .version_id = 1, 2861 .minimum_version_id = 1, 2862 .fields = (VMStateField[]) { 2863 VMSTATE_UINT8(patched, AcpiBuildState), 2864 VMSTATE_END_OF_LIST() 2865 }, 2866 }; 2867 2868 void acpi_setup(void) 2869 { 2870 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2871 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2872 AcpiBuildTables tables; 2873 AcpiBuildState *build_state; 2874 Object *vmgenid_dev; 2875 2876 if (!pcms->fw_cfg) { 2877 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2878 return; 2879 } 2880 2881 if (!pcms->acpi_build_enabled) { 2882 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2883 return; 2884 } 2885 2886 if (!acpi_enabled) { 2887 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2888 return; 2889 } 2890 2891 build_state = g_malloc0(sizeof *build_state); 2892 2893 acpi_build_tables_init(&tables); 2894 acpi_build(&tables, MACHINE(pcms)); 2895 2896 /* Now expose it all to Guest */ 2897 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2898 ACPI_BUILD_TABLE_FILE, 2899 ACPI_BUILD_TABLE_MAX_SIZE); 2900 assert(build_state->table_mr != NULL); 2901 2902 build_state->linker_mr = 2903 acpi_add_rom_blob(build_state, tables.linker->cmd_blob, 2904 "etc/table-loader", 0); 2905 2906 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2907 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2908 2909 vmgenid_dev = find_vmgenid_dev(); 2910 if (vmgenid_dev) { 2911 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, 2912 tables.vmgenid); 2913 } 2914 2915 if (!pcmc->rsdp_in_ram) { 2916 /* 2917 * Keep for compatibility with old machine types. 2918 * Though RSDP is small, its contents isn't immutable, so 2919 * we'll update it along with the rest of tables on guest access. 2920 */ 2921 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2922 2923 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2924 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2925 acpi_build_update, NULL, build_state, 2926 build_state->rsdp, rsdp_size, true); 2927 build_state->rsdp_mr = NULL; 2928 } else { 2929 build_state->rsdp = NULL; 2930 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2931 ACPI_BUILD_RSDP_FILE, 0); 2932 } 2933 2934 qemu_register_reset(acpi_build_reset, build_state); 2935 acpi_build_reset(build_state); 2936 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2937 2938 /* Cleanup tables but don't free the memory: we track it 2939 * in build_state. 2940 */ 2941 acpi_build_tables_cleanup(&tables, false); 2942 } 2943