1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/ich9.h" 59 #include "hw/southbridge/piix.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/pc.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/i440fx.h" 65 #include "hw/pci-host/q35.h" 66 #include "hw/i386/x86-iommu.h" 67 68 #include "hw/acpi/aml-build.h" 69 #include "hw/acpi/utils.h" 70 #include "hw/acpi/pci.h" 71 #include "hw/acpi/cxl.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool has_hpet; 117 #ifdef CONFIG_TPM 118 TPMVersion tpm_version; 119 #endif 120 } AcpiMiscInfo; 121 122 typedef struct FwCfgTPMConfig { 123 uint32_t tpmppi_address; 124 uint8_t tpm_version; 125 uint8_t tpmppi_version; 126 } QEMU_PACKED FwCfgTPMConfig; 127 128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 129 130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 131 .space_id = AML_AS_SYSTEM_IO, 132 .address = NVDIMM_ACPI_IO_BASE, 133 .bit_width = NVDIMM_ACPI_IO_LEN << 3 134 }; 135 136 static void init_common_fadt_data(MachineState *ms, Object *o, 137 AcpiFadtData *data) 138 { 139 X86MachineState *x86ms = X86_MACHINE(ms); 140 /* 141 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 142 * behavior for compatibility irrelevant to smm_enabled, which doesn't 143 * comforms to ACPI spec. 144 */ 145 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 146 true : x86_machine_is_smm_enabled(x86ms); 147 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 148 AmlAddressSpace as = AML_AS_SYSTEM_IO; 149 AcpiFadtData fadt = { 150 .rev = 3, 151 .flags = 152 (1 << ACPI_FADT_F_WBINVD) | 153 (1 << ACPI_FADT_F_PROC_C1) | 154 (1 << ACPI_FADT_F_SLP_BUTTON) | 155 (1 << ACPI_FADT_F_RTC_S4) | 156 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 157 /* APIC destination mode ("Flat Logical") has an upper limit of 8 158 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 159 * used 160 */ 161 ((ms->smp.max_cpus > 8) ? 162 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 163 .int_model = 1 /* Multiple APIC */, 164 .rtc_century = RTC_CENTURY, 165 .plvl2_lat = 0xfff /* C2 state not supported */, 166 .plvl3_lat = 0xfff /* C3 state not supported */, 167 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 168 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 169 .acpi_enable_cmd = 170 smm_enabled ? 171 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 172 0, 173 .acpi_disable_cmd = 174 smm_enabled ? 175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 176 0, 177 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 178 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 179 .address = io + 0x04 }, 180 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 181 .gpe0_blk = { .space_id = as, .bit_width = 182 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 183 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 184 }, 185 }; 186 187 /* 188 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 189 * Flags, bit offset 1 - 8042. 190 */ 191 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 192 193 *data = fadt; 194 } 195 196 static Object *object_resolve_type_unambiguous(const char *typename) 197 { 198 bool ambig; 199 Object *o = object_resolve_path_type("", typename, &ambig); 200 201 if (ambig || !o) { 202 return NULL; 203 } 204 return o; 205 } 206 207 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 208 { 209 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 210 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 211 Object *obj = piix ? piix : lpc; 212 QObject *o; 213 pm->cpu_hp_io_base = 0; 214 pm->pcihp_io_base = 0; 215 pm->pcihp_io_len = 0; 216 pm->smi_on_cpuhp = false; 217 pm->smi_on_cpu_unplug = false; 218 219 assert(obj); 220 init_common_fadt_data(machine, obj, &pm->fadt); 221 if (piix) { 222 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 223 pm->fadt.rev = 1; 224 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 225 } 226 if (lpc) { 227 uint64_t smi_features = object_property_get_uint(lpc, 228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 231 pm->fadt.reset_reg = r; 232 pm->fadt.reset_val = 0xf; 233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 235 pm->smi_on_cpuhp = 236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 237 pm->smi_on_cpu_unplug = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 239 } 240 pm->pcihp_io_base = 241 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 242 pm->pcihp_io_len = 243 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 244 245 /* The above need not be conditional on machine type because the reset port 246 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 247 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 248 249 /* Fill in optional s3/s4 related properties */ 250 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 251 if (o) { 252 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 253 } else { 254 pm->s3_disabled = false; 255 } 256 qobject_unref(o); 257 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 258 if (o) { 259 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 260 } else { 261 pm->s4_disabled = false; 262 } 263 qobject_unref(o); 264 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 265 if (o) { 266 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 267 } else { 268 pm->s4_val = false; 269 } 270 qobject_unref(o); 271 272 pm->pcihp_bridge_en = 273 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 274 NULL); 275 pm->pcihp_root_en = 276 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 277 NULL); 278 } 279 280 static void acpi_get_misc_info(AcpiMiscInfo *info) 281 { 282 info->has_hpet = hpet_find(); 283 #ifdef CONFIG_TPM 284 info->tpm_version = tpm_get_version(tpm_find()); 285 #endif 286 } 287 288 /* 289 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 290 * On i386 arch we only have two pci hosts, so we can look only for them. 291 */ 292 Object *acpi_get_i386_pci_host(void) 293 { 294 PCIHostState *host; 295 296 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 297 if (!host) { 298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 299 } 300 301 return OBJECT(host); 302 } 303 304 static void acpi_get_pci_holes(Range *hole, Range *hole64) 305 { 306 Object *pci_host; 307 308 pci_host = acpi_get_i386_pci_host(); 309 310 if (!pci_host) { 311 return; 312 } 313 314 range_set_bounds1(hole, 315 object_property_get_uint(pci_host, 316 PCI_HOST_PROP_PCI_HOLE_START, 317 NULL), 318 object_property_get_uint(pci_host, 319 PCI_HOST_PROP_PCI_HOLE_END, 320 NULL)); 321 range_set_bounds1(hole64, 322 object_property_get_uint(pci_host, 323 PCI_HOST_PROP_PCI_HOLE64_START, 324 NULL), 325 object_property_get_uint(pci_host, 326 PCI_HOST_PROP_PCI_HOLE64_END, 327 NULL)); 328 } 329 330 static void acpi_align_size(GArray *blob, unsigned align) 331 { 332 /* Align size to multiple of given size. This reduces the chance 333 * we need to change size in the future (breaking cross version migration). 334 */ 335 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 336 } 337 338 /* 339 * ACPI spec 1.0b, 340 * 5.2.6 Firmware ACPI Control Structure 341 */ 342 static void 343 build_facs(GArray *table_data) 344 { 345 const char *sig = "FACS"; 346 const uint8_t reserved[40] = {}; 347 348 g_array_append_vals(table_data, sig, 4); /* Signature */ 349 build_append_int_noprefix(table_data, 64, 4); /* Length */ 350 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 351 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 352 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 353 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 354 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 355 } 356 357 Aml *aml_pci_device_dsm(void) 358 { 359 Aml *method; 360 361 method = aml_method("_DSM", 4, AML_SERIALIZED); 362 { 363 Aml *params = aml_local(0); 364 Aml *pkg = aml_package(2); 365 aml_append(pkg, aml_name("BSEL")); 366 aml_append(pkg, aml_name("ASUN")); 367 aml_append(method, aml_store(pkg, params)); 368 aml_append(method, 369 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 370 aml_arg(2), aml_arg(3), params)) 371 ); 372 } 373 return method; 374 } 375 376 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) 377 { 378 Aml *UUID, *ifctx1; 379 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 380 381 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); 382 /* 383 * PCI Firmware Specification 3.1 384 * 4.6. _DSM Definitions for PCI 385 */ 386 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 387 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 388 { 389 /* call is for unsupported UUID, bail out */ 390 aml_append(ifctx1, aml_return(retvar)); 391 } 392 aml_append(ctx, ifctx1); 393 394 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2))); 395 { 396 /* call is for unsupported REV, bail out */ 397 aml_append(ifctx1, aml_return(retvar)); 398 } 399 aml_append(ctx, ifctx1); 400 } 401 402 static Aml *aml_pci_edsm(void) 403 { 404 Aml *method, *ifctx; 405 Aml *zero = aml_int(0); 406 Aml *func = aml_arg(2); 407 Aml *ret = aml_local(0); 408 Aml *aidx = aml_local(1); 409 Aml *params = aml_arg(4); 410 411 method = aml_method("EDSM", 5, AML_SERIALIZED); 412 413 /* get supported functions */ 414 ifctx = aml_if(aml_equal(func, zero)); 415 { 416 /* 1: have supported functions */ 417 /* 7: support for function 7 */ 418 const uint8_t caps = 1 | BIT(7); 419 build_append_pci_dsm_func0_common(ifctx, ret); 420 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 421 aml_append(ifctx, aml_return(ret)); 422 } 423 aml_append(method, ifctx); 424 425 /* handle specific functions requests */ 426 /* 427 * PCI Firmware Specification 3.1 428 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 429 * Operating Systems 430 */ 431 ifctx = aml_if(aml_equal(func, aml_int(7))); 432 { 433 Aml *pkg = aml_package(2); 434 aml_append(pkg, zero); 435 /* optional, if not impl. should return null string */ 436 aml_append(pkg, aml_string("%s", "")); 437 aml_append(ifctx, aml_store(pkg, ret)); 438 439 /* 440 * IASL is fine when initializing Package with computational data, 441 * however it makes guest unhappy /it fails to process such AML/. 442 * So use runtime assignment to set acpi-index after initializer 443 * to make OSPM happy. 444 */ 445 aml_append(ifctx, 446 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 447 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 448 aml_append(ifctx, aml_return(ret)); 449 } 450 aml_append(method, ifctx); 451 452 return method; 453 } 454 455 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 456 { 457 Aml *method; 458 459 g_assert(pdev->acpi_index != 0); 460 method = aml_method("_DSM", 4, AML_SERIALIZED); 461 { 462 Aml *params = aml_local(0); 463 Aml *pkg = aml_package(1); 464 aml_append(pkg, aml_int(pdev->acpi_index)); 465 aml_append(method, aml_store(pkg, params)); 466 aml_append(method, 467 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 468 aml_arg(2), aml_arg(3), params)) 469 ); 470 } 471 return method; 472 } 473 474 static void build_append_pcihp_notify_entry(Aml *method, int slot) 475 { 476 Aml *if_ctx; 477 int32_t devfn = PCI_DEVFN(slot, 0); 478 479 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 480 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 481 aml_append(method, if_ctx); 482 } 483 484 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 485 { 486 const PCIDevice *pdev = bus->devices[devfn]; 487 488 if (PCI_FUNC(devfn)) { 489 if (IS_PCI_BRIDGE(pdev)) { 490 /* 491 * Ignore only hotplugged PCI bridges on !0 functions, but 492 * allow describing cold plugged bridges on all functions 493 */ 494 if (DEVICE(pdev)->hotplugged) { 495 return true; 496 } 497 } 498 } 499 return false; 500 } 501 502 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 503 { 504 PCIDevice *pdev = bus->devices[devfn]; 505 if (pdev) { 506 return is_devfn_ignored_generic(devfn, bus) || 507 !DEVICE_GET_CLASS(pdev)->hotpluggable || 508 /* Cold plugged bridges aren't themselves hot-pluggable */ 509 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 510 } else { /* non populated slots */ 511 /* 512 * hotplug is supported only for non-multifunction device 513 * so generate device description only for function 0 514 */ 515 if (PCI_FUNC(devfn) || 516 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 517 return true; 518 } 519 } 520 return false; 521 } 522 523 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) 524 { 525 int devfn; 526 Aml *dev, *notify_method = NULL, *method; 527 QObject *bsel = object_property_get_qobject(OBJECT(bus), 528 ACPI_PCIHP_PROP_BSEL, NULL); 529 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 530 qobject_unref(bsel); 531 532 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 533 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 534 535 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 536 int slot = PCI_SLOT(devfn); 537 int adr = slot << 16 | PCI_FUNC(devfn); 538 539 if (is_devfn_ignored_hotplug(devfn, bus)) { 540 continue; 541 } 542 543 if (bus->devices[devfn]) { 544 dev = aml_scope("S%.02X", devfn); 545 } else { 546 dev = aml_device("S%.02X", devfn); 547 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 548 } 549 550 /* 551 * Can't declare _SUN here for every device as it changes 'slot' 552 * enumeration order in linux kernel, so use another variable for it 553 */ 554 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 555 aml_append(dev, aml_pci_device_dsm()); 556 557 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 558 /* add _EJ0 to make slot hotpluggable */ 559 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 560 aml_append(method, 561 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 562 ); 563 aml_append(dev, method); 564 565 build_append_pcihp_notify_entry(notify_method, slot); 566 567 /* device descriptor has been composed, add it into parent context */ 568 aml_append(parent_scope, dev); 569 } 570 aml_append(parent_scope, notify_method); 571 } 572 573 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 574 { 575 int devfn; 576 Aml *dev; 577 578 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 579 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 580 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 581 PCIDevice *pdev = bus->devices[devfn]; 582 583 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 584 continue; 585 } 586 587 /* start to compose PCI device descriptor */ 588 dev = aml_device("S%.02X", devfn); 589 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 590 591 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 592 /* add _DSM if device has acpi-index set */ 593 if (pdev->acpi_index && 594 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 595 &error_abort)) { 596 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 597 } 598 599 /* device descriptor has been composed, add it into parent context */ 600 aml_append(parent_scope, dev); 601 } 602 } 603 604 static bool build_append_notfication_callback(Aml *parent_scope, 605 const PCIBus *bus) 606 { 607 Aml *method; 608 PCIBus *sec; 609 QObject *bsel; 610 int nr_notifiers = 0; 611 GQueue *pcnt_bus_list = g_queue_new(); 612 613 QLIST_FOREACH(sec, &bus->child, sibling) { 614 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 615 if (pci_bus_is_root(sec)) { 616 continue; 617 } 618 nr_notifiers = nr_notifiers + 619 build_append_notfication_callback(br_scope, sec); 620 /* 621 * add new child scope to parent 622 * and keep track of bus that have PCNT, 623 * bus list is used later to call children PCNTs from this level PCNT 624 */ 625 if (nr_notifiers) { 626 g_queue_push_tail(pcnt_bus_list, sec); 627 aml_append(parent_scope, br_scope); 628 } 629 } 630 631 /* 632 * Append PCNT method to notify about events on local and child buses. 633 * ps: hostbridge might not have hotplug (bsel) enabled but might have 634 * child bridges that do have bsel. 635 */ 636 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 637 638 /* If bus supports hotplug select it and notify about local events */ 639 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 640 if (bsel) { 641 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 642 643 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 644 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 645 aml_int(1))); /* Device Check */ 646 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 647 aml_int(3))); /* Eject Request */ 648 nr_notifiers++; 649 } 650 651 /* Notify about child bus events in any case */ 652 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 653 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 654 } 655 656 aml_append(parent_scope, method); 657 qobject_unref(bsel); 658 g_queue_free(pcnt_bus_list); 659 return !!nr_notifiers; 660 } 661 662 static Aml *aml_pci_pdsm(void) 663 { 664 Aml *method, *ifctx, *ifctx1; 665 Aml *ret = aml_local(0); 666 Aml *caps = aml_local(1); 667 Aml *acpi_index = aml_local(2); 668 Aml *zero = aml_int(0); 669 Aml *one = aml_int(1); 670 Aml *func = aml_arg(2); 671 Aml *params = aml_arg(4); 672 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 673 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 674 675 method = aml_method("PDSM", 5, AML_SERIALIZED); 676 677 /* get supported functions */ 678 ifctx = aml_if(aml_equal(func, zero)); 679 { 680 build_append_pci_dsm_func0_common(ifctx, ret); 681 682 aml_append(ifctx, aml_store(zero, caps)); 683 aml_append(ifctx, 684 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 685 /* 686 * advertise function 7 if device has acpi-index 687 * acpi_index values: 688 * 0: not present (default value) 689 * FFFFFFFF: not supported (old QEMU without PIDX reg) 690 * other: device's acpi-index 691 */ 692 ifctx1 = aml_if(aml_lnot( 693 aml_or(aml_equal(acpi_index, zero), 694 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 695 )); 696 { 697 /* have supported functions */ 698 aml_append(ifctx1, aml_or(caps, one, caps)); 699 /* support for function 7 */ 700 aml_append(ifctx1, 701 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 702 } 703 aml_append(ifctx, ifctx1); 704 705 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 706 aml_append(ifctx, aml_return(ret)); 707 } 708 aml_append(method, ifctx); 709 710 /* handle specific functions requests */ 711 /* 712 * PCI Firmware Specification 3.1 713 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 714 * Operating Systems 715 */ 716 ifctx = aml_if(aml_equal(func, aml_int(7))); 717 { 718 Aml *pkg = aml_package(2); 719 720 aml_append(pkg, zero); 721 /* 722 * optional, if not impl. should return null string 723 */ 724 aml_append(pkg, aml_string("%s", "")); 725 aml_append(ifctx, aml_store(pkg, ret)); 726 727 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 728 /* 729 * update acpi-index to actual value 730 */ 731 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 732 aml_append(ifctx, aml_return(ret)); 733 } 734 735 aml_append(method, ifctx); 736 return method; 737 } 738 739 /** 740 * build_prt_entry: 741 * @link_name: link name for PCI route entry 742 * 743 * build AML package containing a PCI route entry for @link_name 744 */ 745 static Aml *build_prt_entry(const char *link_name) 746 { 747 Aml *a_zero = aml_int(0); 748 Aml *pkg = aml_package(4); 749 aml_append(pkg, a_zero); 750 aml_append(pkg, a_zero); 751 aml_append(pkg, aml_name("%s", link_name)); 752 aml_append(pkg, a_zero); 753 return pkg; 754 } 755 756 /* 757 * initialize_route - Initialize the interrupt routing rule 758 * through a specific LINK: 759 * if (lnk_idx == idx) 760 * route using link 'link_name' 761 */ 762 static Aml *initialize_route(Aml *route, const char *link_name, 763 Aml *lnk_idx, int idx) 764 { 765 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 766 Aml *pkg = build_prt_entry(link_name); 767 768 aml_append(if_ctx, aml_store(pkg, route)); 769 770 return if_ctx; 771 } 772 773 /* 774 * build_prt - Define interrupt rounting rules 775 * 776 * Returns an array of 128 routes, one for each device, 777 * based on device location. 778 * The main goal is to equaly distribute the interrupts 779 * over the 4 existing ACPI links (works only for i440fx). 780 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 781 * 782 */ 783 static Aml *build_prt(bool is_pci0_prt) 784 { 785 Aml *method, *while_ctx, *pin, *res; 786 787 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 788 res = aml_local(0); 789 pin = aml_local(1); 790 aml_append(method, aml_store(aml_package(128), res)); 791 aml_append(method, aml_store(aml_int(0), pin)); 792 793 /* while (pin < 128) */ 794 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 795 { 796 Aml *slot = aml_local(2); 797 Aml *lnk_idx = aml_local(3); 798 Aml *route = aml_local(4); 799 800 /* slot = pin >> 2 */ 801 aml_append(while_ctx, 802 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 803 /* lnk_idx = (slot + pin) & 3 */ 804 aml_append(while_ctx, 805 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 806 lnk_idx)); 807 808 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 809 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 810 if (is_pci0_prt) { 811 Aml *if_device_1, *if_pin_4, *else_pin_4; 812 813 /* device 1 is the power-management device, needs SCI */ 814 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 815 { 816 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 817 { 818 aml_append(if_pin_4, 819 aml_store(build_prt_entry("LNKS"), route)); 820 } 821 aml_append(if_device_1, if_pin_4); 822 else_pin_4 = aml_else(); 823 { 824 aml_append(else_pin_4, 825 aml_store(build_prt_entry("LNKA"), route)); 826 } 827 aml_append(if_device_1, else_pin_4); 828 } 829 aml_append(while_ctx, if_device_1); 830 } else { 831 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 832 } 833 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 834 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 835 836 /* route[0] = 0x[slot]FFFF */ 837 aml_append(while_ctx, 838 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 839 NULL), 840 aml_index(route, aml_int(0)))); 841 /* route[1] = pin & 3 */ 842 aml_append(while_ctx, 843 aml_store(aml_and(pin, aml_int(3), NULL), 844 aml_index(route, aml_int(1)))); 845 /* res[pin] = route */ 846 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 847 /* pin++ */ 848 aml_append(while_ctx, aml_increment(pin)); 849 } 850 aml_append(method, while_ctx); 851 /* return res*/ 852 aml_append(method, aml_return(res)); 853 854 return method; 855 } 856 857 static void build_hpet_aml(Aml *table) 858 { 859 Aml *crs; 860 Aml *field; 861 Aml *method; 862 Aml *if_ctx; 863 Aml *scope = aml_scope("_SB"); 864 Aml *dev = aml_device("HPET"); 865 Aml *zero = aml_int(0); 866 Aml *id = aml_local(0); 867 Aml *period = aml_local(1); 868 869 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 870 aml_append(dev, aml_name_decl("_UID", zero)); 871 872 aml_append(dev, 873 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 874 HPET_LEN)); 875 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 876 aml_append(field, aml_named_field("VEND", 32)); 877 aml_append(field, aml_named_field("PRD", 32)); 878 aml_append(dev, field); 879 880 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 881 aml_append(method, aml_store(aml_name("VEND"), id)); 882 aml_append(method, aml_store(aml_name("PRD"), period)); 883 aml_append(method, aml_shiftright(id, aml_int(16), id)); 884 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 885 aml_equal(id, aml_int(0xffff)))); 886 { 887 aml_append(if_ctx, aml_return(zero)); 888 } 889 aml_append(method, if_ctx); 890 891 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 892 aml_lgreater(period, aml_int(100000000)))); 893 { 894 aml_append(if_ctx, aml_return(zero)); 895 } 896 aml_append(method, if_ctx); 897 898 aml_append(method, aml_return(aml_int(0x0F))); 899 aml_append(dev, method); 900 901 crs = aml_resource_template(); 902 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 903 aml_append(dev, aml_name_decl("_CRS", crs)); 904 905 aml_append(scope, dev); 906 aml_append(table, scope); 907 } 908 909 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 910 { 911 Aml *dev; 912 Aml *method; 913 Aml *crs; 914 915 dev = aml_device("VMBS"); 916 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 917 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 918 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 919 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 920 921 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 922 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 923 aml_name("STA"))); 924 aml_append(dev, method); 925 926 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 927 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 928 aml_name("STA"))); 929 aml_append(dev, method); 930 931 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 932 aml_append(method, aml_return(aml_name("STA"))); 933 aml_append(dev, method); 934 935 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 936 937 crs = aml_resource_template(); 938 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 939 aml_append(dev, aml_name_decl("_CRS", crs)); 940 941 return dev; 942 } 943 944 static void build_dbg_aml(Aml *table) 945 { 946 Aml *field; 947 Aml *method; 948 Aml *while_ctx; 949 Aml *scope = aml_scope("\\"); 950 Aml *buf = aml_local(0); 951 Aml *len = aml_local(1); 952 Aml *idx = aml_local(2); 953 954 aml_append(scope, 955 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 956 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 957 aml_append(field, aml_named_field("DBGB", 8)); 958 aml_append(scope, field); 959 960 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 961 962 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 963 aml_append(method, aml_to_buffer(buf, buf)); 964 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 965 aml_append(method, aml_store(aml_int(0), idx)); 966 967 while_ctx = aml_while(aml_lless(idx, len)); 968 aml_append(while_ctx, 969 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 970 aml_append(while_ctx, aml_increment(idx)); 971 aml_append(method, while_ctx); 972 973 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 974 aml_append(scope, method); 975 976 aml_append(table, scope); 977 } 978 979 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 980 { 981 Aml *dev; 982 Aml *crs; 983 Aml *method; 984 uint32_t irqs[] = {5, 10, 11}; 985 986 dev = aml_device("%s", name); 987 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 988 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 989 990 crs = aml_resource_template(); 991 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 992 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 993 aml_append(dev, aml_name_decl("_PRS", crs)); 994 995 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 996 aml_append(method, aml_return(aml_call1("IQST", reg))); 997 aml_append(dev, method); 998 999 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1000 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1001 aml_append(dev, method); 1002 1003 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1004 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1005 aml_append(dev, method); 1006 1007 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1008 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1009 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1010 aml_append(dev, method); 1011 1012 return dev; 1013 } 1014 1015 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1016 { 1017 Aml *dev; 1018 Aml *crs; 1019 Aml *method; 1020 uint32_t irqs; 1021 1022 dev = aml_device("%s", name); 1023 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1024 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1025 1026 crs = aml_resource_template(); 1027 irqs = gsi; 1028 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1029 AML_SHARED, &irqs, 1)); 1030 aml_append(dev, aml_name_decl("_PRS", crs)); 1031 1032 aml_append(dev, aml_name_decl("_CRS", crs)); 1033 1034 /* 1035 * _DIS can be no-op because the interrupt cannot be disabled. 1036 */ 1037 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1038 aml_append(dev, method); 1039 1040 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1041 aml_append(dev, method); 1042 1043 return dev; 1044 } 1045 1046 /* _CRS method - get current settings */ 1047 static Aml *build_iqcr_method(bool is_piix4) 1048 { 1049 Aml *if_ctx; 1050 uint32_t irqs; 1051 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1052 Aml *crs = aml_resource_template(); 1053 1054 irqs = 0; 1055 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1056 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1057 aml_append(method, aml_name_decl("PRR0", crs)); 1058 1059 aml_append(method, 1060 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1061 1062 if (is_piix4) { 1063 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1064 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1065 aml_append(method, if_ctx); 1066 } else { 1067 aml_append(method, 1068 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1069 aml_name("PRRI"))); 1070 } 1071 1072 aml_append(method, aml_return(aml_name("PRR0"))); 1073 return method; 1074 } 1075 1076 /* _STA method - get status */ 1077 static Aml *build_irq_status_method(void) 1078 { 1079 Aml *if_ctx; 1080 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1081 1082 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1083 aml_append(if_ctx, aml_return(aml_int(0x09))); 1084 aml_append(method, if_ctx); 1085 aml_append(method, aml_return(aml_int(0x0B))); 1086 return method; 1087 } 1088 1089 static void build_piix4_pci0_int(Aml *table) 1090 { 1091 Aml *dev; 1092 Aml *crs; 1093 Aml *method; 1094 uint32_t irqs; 1095 Aml *sb_scope = aml_scope("_SB"); 1096 Aml *pci0_scope = aml_scope("PCI0"); 1097 1098 aml_append(pci0_scope, build_prt(true)); 1099 aml_append(sb_scope, pci0_scope); 1100 1101 aml_append(sb_scope, build_irq_status_method()); 1102 aml_append(sb_scope, build_iqcr_method(true)); 1103 1104 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1105 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1106 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1107 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1108 1109 dev = aml_device("LNKS"); 1110 { 1111 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1112 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1113 1114 crs = aml_resource_template(); 1115 irqs = 9; 1116 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1117 AML_ACTIVE_HIGH, AML_SHARED, 1118 &irqs, 1)); 1119 aml_append(dev, aml_name_decl("_PRS", crs)); 1120 1121 /* The SCI cannot be disabled and is always attached to GSI 9, 1122 * so these are no-ops. We only need this link to override the 1123 * polarity to active high and match the content of the MADT. 1124 */ 1125 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1126 aml_append(method, aml_return(aml_int(0x0b))); 1127 aml_append(dev, method); 1128 1129 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1130 aml_append(dev, method); 1131 1132 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1133 aml_append(method, aml_return(aml_name("_PRS"))); 1134 aml_append(dev, method); 1135 1136 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1137 aml_append(dev, method); 1138 } 1139 aml_append(sb_scope, dev); 1140 1141 aml_append(table, sb_scope); 1142 } 1143 1144 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1145 { 1146 int i; 1147 int head; 1148 Aml *pkg; 1149 char base = name[3] < 'E' ? 'A' : 'E'; 1150 char *s = g_strdup(name); 1151 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1152 1153 assert(strlen(s) == 4); 1154 1155 head = name[3] - base; 1156 for (i = 0; i < 4; i++) { 1157 if (head + i > 3) { 1158 head = i * -1; 1159 } 1160 s[3] = base + head + i; 1161 pkg = aml_package(4); 1162 aml_append(pkg, a_nr); 1163 aml_append(pkg, aml_int(i)); 1164 aml_append(pkg, aml_name("%s", s)); 1165 aml_append(pkg, aml_int(0)); 1166 aml_append(ctx, pkg); 1167 } 1168 g_free(s); 1169 } 1170 1171 static Aml *build_q35_routing_table(const char *str) 1172 { 1173 int i; 1174 Aml *pkg; 1175 char *name = g_strdup_printf("%s ", str); 1176 1177 pkg = aml_package(128); 1178 for (i = 0; i < 0x18; i++) { 1179 name[3] = 'E' + (i & 0x3); 1180 append_q35_prt_entry(pkg, i, name); 1181 } 1182 1183 name[3] = 'E'; 1184 append_q35_prt_entry(pkg, 0x18, name); 1185 1186 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1187 for (i = 0x0019; i < 0x1e; i++) { 1188 name[3] = 'A'; 1189 append_q35_prt_entry(pkg, i, name); 1190 } 1191 1192 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1193 name[3] = 'E'; 1194 append_q35_prt_entry(pkg, 0x1e, name); 1195 name[3] = 'A'; 1196 append_q35_prt_entry(pkg, 0x1f, name); 1197 1198 g_free(name); 1199 return pkg; 1200 } 1201 1202 static void build_q35_pci0_int(Aml *table) 1203 { 1204 Aml *method; 1205 Aml *sb_scope = aml_scope("_SB"); 1206 Aml *pci0_scope = aml_scope("PCI0"); 1207 1208 /* Zero => PIC mode, One => APIC Mode */ 1209 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1210 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1211 { 1212 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1213 } 1214 aml_append(table, method); 1215 1216 aml_append(pci0_scope, 1217 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1218 aml_append(pci0_scope, 1219 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1220 1221 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1222 { 1223 Aml *if_ctx; 1224 Aml *else_ctx; 1225 1226 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1227 section 6.2.8.1 */ 1228 /* Note: we provide the same info as the PCI routing 1229 table of the Bochs BIOS */ 1230 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1231 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1232 aml_append(method, if_ctx); 1233 else_ctx = aml_else(); 1234 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1235 aml_append(method, else_ctx); 1236 } 1237 aml_append(pci0_scope, method); 1238 aml_append(sb_scope, pci0_scope); 1239 1240 aml_append(sb_scope, build_irq_status_method()); 1241 aml_append(sb_scope, build_iqcr_method(false)); 1242 1243 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1244 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1245 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1246 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1247 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1248 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1249 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1250 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1251 1252 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1253 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1254 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1255 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1256 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1257 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1258 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1259 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1260 1261 aml_append(table, sb_scope); 1262 } 1263 1264 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1265 { 1266 Aml *dev; 1267 Aml *resource_template; 1268 1269 /* DRAM controller */ 1270 dev = aml_device("DRAC"); 1271 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1272 1273 resource_template = aml_resource_template(); 1274 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1275 aml_append(resource_template, 1276 aml_qword_memory(AML_POS_DECODE, 1277 AML_MIN_FIXED, 1278 AML_MAX_FIXED, 1279 AML_NON_CACHEABLE, 1280 AML_READ_WRITE, 1281 0x0000000000000000, 1282 mcfg->base, 1283 mcfg->base + mcfg->size - 1, 1284 0x0000000000000000, 1285 mcfg->size)); 1286 } else { 1287 aml_append(resource_template, 1288 aml_dword_memory(AML_POS_DECODE, 1289 AML_MIN_FIXED, 1290 AML_MAX_FIXED, 1291 AML_NON_CACHEABLE, 1292 AML_READ_WRITE, 1293 0x0000000000000000, 1294 mcfg->base, 1295 mcfg->base + mcfg->size - 1, 1296 0x0000000000000000, 1297 mcfg->size)); 1298 } 1299 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1300 1301 return dev; 1302 } 1303 1304 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1305 { 1306 Aml *scope; 1307 Aml *field; 1308 Aml *method; 1309 1310 scope = aml_scope("_SB.PCI0"); 1311 1312 aml_append(scope, 1313 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1314 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1315 aml_append(field, aml_named_field("PCIU", 32)); 1316 aml_append(field, aml_named_field("PCID", 32)); 1317 aml_append(scope, field); 1318 1319 aml_append(scope, 1320 aml_operation_region("SEJ", AML_SYSTEM_IO, 1321 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1322 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1323 aml_append(field, aml_named_field("B0EJ", 32)); 1324 aml_append(scope, field); 1325 1326 aml_append(scope, 1327 aml_operation_region("BNMR", AML_SYSTEM_IO, 1328 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1329 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1330 aml_append(field, aml_named_field("BNUM", 32)); 1331 aml_append(field, aml_named_field("PIDX", 32)); 1332 aml_append(scope, field); 1333 1334 aml_append(scope, aml_mutex("BLCK", 0)); 1335 1336 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1337 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1338 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1339 aml_append(method, 1340 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1341 aml_append(method, aml_release(aml_name("BLCK"))); 1342 aml_append(method, aml_return(aml_int(0))); 1343 aml_append(scope, method); 1344 1345 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1346 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1347 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1348 aml_append(method, 1349 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1350 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1351 aml_append(method, aml_release(aml_name("BLCK"))); 1352 aml_append(method, aml_return(aml_local(0))); 1353 aml_append(scope, method); 1354 1355 aml_append(scope, aml_pci_pdsm()); 1356 1357 aml_append(table, scope); 1358 } 1359 1360 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1361 { 1362 Aml *if_ctx; 1363 Aml *if_ctx2; 1364 Aml *else_ctx; 1365 Aml *method; 1366 Aml *a_cwd1 = aml_name("CDW1"); 1367 Aml *a_ctrl = aml_local(0); 1368 1369 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1370 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1371 1372 if_ctx = aml_if(aml_equal( 1373 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1374 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1375 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1376 1377 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1378 1379 /* 1380 * Always allow native PME, AER (no dependencies) 1381 * Allow SHPC (PCI bridges can have SHPC controller) 1382 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1383 */ 1384 aml_append(if_ctx, aml_and(a_ctrl, 1385 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1386 1387 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1388 /* Unknown revision */ 1389 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1390 aml_append(if_ctx, if_ctx2); 1391 1392 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1393 /* Capabilities bits were masked */ 1394 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1395 aml_append(if_ctx, if_ctx2); 1396 1397 /* Update DWORD3 in the buffer */ 1398 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1399 aml_append(method, if_ctx); 1400 1401 else_ctx = aml_else(); 1402 /* Unrecognized UUID */ 1403 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1404 aml_append(method, else_ctx); 1405 1406 aml_append(method, aml_return(aml_arg(3))); 1407 return method; 1408 } 1409 1410 static void build_acpi0017(Aml *table) 1411 { 1412 Aml *dev, *scope, *method; 1413 1414 scope = aml_scope("_SB"); 1415 dev = aml_device("CXLM"); 1416 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1417 1418 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1419 aml_append(method, aml_return(aml_int(0x01))); 1420 aml_append(dev, method); 1421 1422 aml_append(scope, dev); 1423 aml_append(table, scope); 1424 } 1425 1426 static void 1427 build_dsdt(GArray *table_data, BIOSLinker *linker, 1428 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1429 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1430 { 1431 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1432 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1433 CrsRangeEntry *entry; 1434 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1435 CrsRangeSet crs_range_set; 1436 PCMachineState *pcms = PC_MACHINE(machine); 1437 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1438 X86MachineState *x86ms = X86_MACHINE(machine); 1439 AcpiMcfgInfo mcfg; 1440 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1441 uint32_t nr_mem = machine->ram_slots; 1442 int root_bus_limit = 0xFF; 1443 PCIBus *bus = NULL; 1444 #ifdef CONFIG_TPM 1445 TPMIf *tpm = tpm_find(); 1446 #endif 1447 bool cxl_present = false; 1448 int i; 1449 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1450 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1451 .oem_table_id = x86ms->oem_table_id }; 1452 1453 assert(!!i440fx != !!q35); 1454 1455 acpi_table_begin(&table, table_data); 1456 dsdt = init_aml_allocator(); 1457 1458 build_dbg_aml(dsdt); 1459 if (i440fx) { 1460 sb_scope = aml_scope("_SB"); 1461 dev = aml_device("PCI0"); 1462 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1463 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1464 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1465 aml_append(dev, aml_pci_edsm()); 1466 aml_append(sb_scope, dev); 1467 aml_append(dsdt, sb_scope); 1468 1469 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1470 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1471 } 1472 build_piix4_pci0_int(dsdt); 1473 } else if (q35) { 1474 sb_scope = aml_scope("_SB"); 1475 dev = aml_device("PCI0"); 1476 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1477 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1478 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1479 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1480 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1481 aml_append(dev, aml_pci_edsm()); 1482 aml_append(sb_scope, dev); 1483 if (mcfg_valid) { 1484 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1485 } 1486 1487 if (pm->smi_on_cpuhp) { 1488 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1489 dev = aml_device("PCI0.SMI0"); 1490 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1491 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1492 crs = aml_resource_template(); 1493 aml_append(crs, 1494 aml_io( 1495 AML_DECODE16, 1496 ACPI_PORT_SMI_CMD, 1497 ACPI_PORT_SMI_CMD, 1498 1, 1499 2) 1500 ); 1501 aml_append(dev, aml_name_decl("_CRS", crs)); 1502 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1503 aml_int(ACPI_PORT_SMI_CMD), 2)); 1504 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1505 AML_WRITE_AS_ZEROS); 1506 aml_append(field, aml_named_field("SMIC", 8)); 1507 aml_append(field, aml_reserved_field(8)); 1508 aml_append(dev, field); 1509 aml_append(sb_scope, dev); 1510 } 1511 1512 aml_append(dsdt, sb_scope); 1513 1514 if (pm->pcihp_bridge_en) { 1515 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1516 } 1517 build_q35_pci0_int(dsdt); 1518 } 1519 1520 if (misc->has_hpet) { 1521 build_hpet_aml(dsdt); 1522 } 1523 1524 if (vmbus_bridge) { 1525 sb_scope = aml_scope("_SB"); 1526 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1527 aml_append(dsdt, sb_scope); 1528 } 1529 1530 scope = aml_scope("_GPE"); 1531 { 1532 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1533 if (machine->nvdimms_state->is_enabled) { 1534 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1535 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1536 aml_int(0x80))); 1537 aml_append(scope, method); 1538 } 1539 } 1540 aml_append(dsdt, scope); 1541 1542 if (pcmc->legacy_cpu_hotplug) { 1543 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1544 } else { 1545 CPUHotplugFeatures opts = { 1546 .acpi_1_compatible = true, .has_legacy_cphp = true, 1547 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1548 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1549 }; 1550 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1551 "\\_SB.PCI0", "\\_GPE._E02"); 1552 } 1553 1554 if (pcms->memhp_io_base && nr_mem) { 1555 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1556 "\\_GPE._E03", AML_SYSTEM_IO, 1557 pcms->memhp_io_base); 1558 } 1559 1560 crs_range_set_init(&crs_range_set); 1561 bus = PC_MACHINE(machine)->bus; 1562 if (bus) { 1563 QLIST_FOREACH(bus, &bus->child, sibling) { 1564 uint8_t bus_num = pci_bus_num(bus); 1565 uint8_t numa_node = pci_bus_numa_node(bus); 1566 1567 /* look only for expander root buses */ 1568 if (!pci_bus_is_root(bus)) { 1569 continue; 1570 } 1571 1572 if (bus_num < root_bus_limit) { 1573 root_bus_limit = bus_num - 1; 1574 } 1575 1576 scope = aml_scope("\\_SB"); 1577 1578 if (pci_bus_is_cxl(bus)) { 1579 dev = aml_device("CL%.02X", bus_num); 1580 } else { 1581 dev = aml_device("PC%.02X", bus_num); 1582 } 1583 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1584 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1585 if (pci_bus_is_cxl(bus)) { 1586 struct Aml *pkg = aml_package(2); 1587 1588 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1589 aml_append(pkg, aml_eisaid("PNP0A08")); 1590 aml_append(pkg, aml_eisaid("PNP0A03")); 1591 aml_append(dev, aml_name_decl("_CID", pkg)); 1592 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1593 build_cxl_osc_method(dev); 1594 } else if (pci_bus_is_express(bus)) { 1595 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1596 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1597 1598 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1599 aml_append(dev, build_q35_osc_method(true)); 1600 } else { 1601 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1602 } 1603 1604 if (numa_node != NUMA_NODE_UNASSIGNED) { 1605 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1606 } 1607 1608 aml_append(dev, build_prt(false)); 1609 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1610 0, 0, 0, 0); 1611 aml_append(dev, aml_name_decl("_CRS", crs)); 1612 aml_append(scope, dev); 1613 aml_append(dsdt, scope); 1614 1615 /* Handle the ranges for the PXB expanders */ 1616 if (pci_bus_is_cxl(bus)) { 1617 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1618 uint64_t base = mr->addr; 1619 1620 cxl_present = true; 1621 crs_range_insert(crs_range_set.mem_ranges, base, 1622 base + memory_region_size(mr) - 1); 1623 } 1624 } 1625 } 1626 1627 if (cxl_present) { 1628 build_acpi0017(dsdt); 1629 } 1630 1631 /* 1632 * At this point crs_range_set has all the ranges used by pci 1633 * busses *other* than PCI0. These ranges will be excluded from 1634 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1635 * too. 1636 */ 1637 if (mcfg_valid) { 1638 crs_range_insert(crs_range_set.mem_ranges, 1639 mcfg.base, mcfg.base + mcfg.size - 1); 1640 } 1641 1642 scope = aml_scope("\\_SB.PCI0"); 1643 /* build PCI0._CRS */ 1644 crs = aml_resource_template(); 1645 aml_append(crs, 1646 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1647 0x0000, 0x0, root_bus_limit, 1648 0x0000, root_bus_limit + 1)); 1649 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1650 1651 aml_append(crs, 1652 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1653 AML_POS_DECODE, AML_ENTIRE_RANGE, 1654 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1655 1656 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1657 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1658 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1659 aml_append(crs, 1660 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1661 AML_POS_DECODE, AML_ENTIRE_RANGE, 1662 0x0000, entry->base, entry->limit, 1663 0x0000, entry->limit - entry->base + 1)); 1664 } 1665 1666 aml_append(crs, 1667 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1668 AML_CACHEABLE, AML_READ_WRITE, 1669 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1670 1671 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1672 range_lob(pci_hole), 1673 range_upb(pci_hole)); 1674 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1675 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1676 aml_append(crs, 1677 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1678 AML_NON_CACHEABLE, AML_READ_WRITE, 1679 0, entry->base, entry->limit, 1680 0, entry->limit - entry->base + 1)); 1681 } 1682 1683 if (!range_is_empty(pci_hole64)) { 1684 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1685 range_lob(pci_hole64), 1686 range_upb(pci_hole64)); 1687 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1688 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1689 aml_append(crs, 1690 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1691 AML_MAX_FIXED, 1692 AML_CACHEABLE, AML_READ_WRITE, 1693 0, entry->base, entry->limit, 1694 0, entry->limit - entry->base + 1)); 1695 } 1696 } 1697 1698 #ifdef CONFIG_TPM 1699 if (TPM_IS_TIS_ISA(tpm_find())) { 1700 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1701 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1702 } 1703 #endif 1704 aml_append(scope, aml_name_decl("_CRS", crs)); 1705 1706 /* reserve GPE0 block resources */ 1707 dev = aml_device("GPE0"); 1708 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1709 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1710 /* device present, functioning, decoding, not shown in UI */ 1711 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1712 crs = aml_resource_template(); 1713 aml_append(crs, 1714 aml_io( 1715 AML_DECODE16, 1716 pm->fadt.gpe0_blk.address, 1717 pm->fadt.gpe0_blk.address, 1718 1, 1719 pm->fadt.gpe0_blk.bit_width / 8) 1720 ); 1721 aml_append(dev, aml_name_decl("_CRS", crs)); 1722 aml_append(scope, dev); 1723 1724 crs_range_set_free(&crs_range_set); 1725 1726 /* reserve PCIHP resources */ 1727 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1728 dev = aml_device("PHPR"); 1729 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1730 aml_append(dev, 1731 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1732 /* device present, functioning, decoding, not shown in UI */ 1733 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1734 crs = aml_resource_template(); 1735 aml_append(crs, 1736 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1737 pm->pcihp_io_len) 1738 ); 1739 aml_append(dev, aml_name_decl("_CRS", crs)); 1740 aml_append(scope, dev); 1741 } 1742 aml_append(dsdt, scope); 1743 1744 /* create S3_ / S4_ / S5_ packages if necessary */ 1745 scope = aml_scope("\\"); 1746 if (!pm->s3_disabled) { 1747 pkg = aml_package(4); 1748 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1749 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1750 aml_append(pkg, aml_int(0)); /* reserved */ 1751 aml_append(pkg, aml_int(0)); /* reserved */ 1752 aml_append(scope, aml_name_decl("_S3", pkg)); 1753 } 1754 1755 if (!pm->s4_disabled) { 1756 pkg = aml_package(4); 1757 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1758 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1759 aml_append(pkg, aml_int(pm->s4_val)); 1760 aml_append(pkg, aml_int(0)); /* reserved */ 1761 aml_append(pkg, aml_int(0)); /* reserved */ 1762 aml_append(scope, aml_name_decl("_S4", pkg)); 1763 } 1764 1765 pkg = aml_package(4); 1766 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1767 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1768 aml_append(pkg, aml_int(0)); /* reserved */ 1769 aml_append(pkg, aml_int(0)); /* reserved */ 1770 aml_append(scope, aml_name_decl("_S5", pkg)); 1771 aml_append(dsdt, scope); 1772 1773 /* create fw_cfg node, unconditionally */ 1774 { 1775 scope = aml_scope("\\_SB.PCI0"); 1776 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1777 aml_append(dsdt, scope); 1778 } 1779 1780 sb_scope = aml_scope("\\_SB"); 1781 { 1782 Object *pci_host = acpi_get_i386_pci_host(); 1783 1784 if (pci_host) { 1785 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1786 Aml *scope = aml_scope("PCI0"); 1787 /* Scan all PCI buses. Generate tables to support hotplug. */ 1788 build_append_pci_bus_devices(scope, bus); 1789 if (object_property_find(OBJECT(bus), ACPI_PCIHP_PROP_BSEL)) { 1790 build_append_pcihp_slots(scope, bus); 1791 } 1792 aml_append(sb_scope, scope); 1793 } 1794 } 1795 1796 #ifdef CONFIG_TPM 1797 if (TPM_IS_CRB(tpm)) { 1798 dev = aml_device("TPM"); 1799 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1800 aml_append(dev, aml_name_decl("_STR", 1801 aml_string("TPM 2.0 Device"))); 1802 crs = aml_resource_template(); 1803 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1804 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1805 aml_append(dev, aml_name_decl("_CRS", crs)); 1806 1807 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1808 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1809 1810 tpm_build_ppi_acpi(tpm, dev); 1811 1812 aml_append(sb_scope, dev); 1813 } 1814 #endif 1815 1816 if (pcms->sgx_epc.size != 0) { 1817 uint64_t epc_base = pcms->sgx_epc.base; 1818 uint64_t epc_size = pcms->sgx_epc.size; 1819 1820 dev = aml_device("EPC"); 1821 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1822 aml_append(dev, aml_name_decl("_STR", 1823 aml_unicode("Enclave Page Cache 1.0"))); 1824 crs = aml_resource_template(); 1825 aml_append(crs, 1826 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1827 AML_MAX_FIXED, AML_NON_CACHEABLE, 1828 AML_READ_WRITE, 0, epc_base, 1829 epc_base + epc_size - 1, 0, epc_size)); 1830 aml_append(dev, aml_name_decl("_CRS", crs)); 1831 1832 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1833 aml_append(method, aml_return(aml_int(0x0f))); 1834 aml_append(dev, method); 1835 1836 aml_append(sb_scope, dev); 1837 } 1838 aml_append(dsdt, sb_scope); 1839 1840 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1841 bool has_pcnt; 1842 1843 Object *pci_host = acpi_get_i386_pci_host(); 1844 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1845 1846 scope = aml_scope("\\_SB.PCI0"); 1847 has_pcnt = build_append_notfication_callback(scope, bus); 1848 if (has_pcnt) { 1849 aml_append(dsdt, scope); 1850 } 1851 1852 scope = aml_scope("_GPE"); 1853 { 1854 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1855 if (has_pcnt) { 1856 aml_append(method, 1857 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1858 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1859 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1860 } 1861 aml_append(scope, method); 1862 } 1863 aml_append(dsdt, scope); 1864 } 1865 1866 /* copy AML table into ACPI tables blob and patch header there */ 1867 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1868 acpi_table_end(linker, &table); 1869 free_aml_allocator(); 1870 } 1871 1872 /* 1873 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1874 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1875 */ 1876 static void 1877 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1878 const char *oem_table_id) 1879 { 1880 AcpiTable table = { .sig = "HPET", .rev = 1, 1881 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1882 1883 acpi_table_begin(&table, table_data); 1884 /* Note timer_block_id value must be kept in sync with value advertised by 1885 * emulated hpet 1886 */ 1887 /* Event Timer Block ID */ 1888 build_append_int_noprefix(table_data, 0x8086a201, 4); 1889 /* BASE_ADDRESS */ 1890 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1891 /* HPET Number */ 1892 build_append_int_noprefix(table_data, 0, 1); 1893 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1894 build_append_int_noprefix(table_data, 0, 2); 1895 /* Page Protection And OEM Attribute */ 1896 build_append_int_noprefix(table_data, 0, 1); 1897 acpi_table_end(linker, &table); 1898 } 1899 1900 #ifdef CONFIG_TPM 1901 /* 1902 * TCPA Description Table 1903 * 1904 * Following Level 00, Rev 00.37 of specs: 1905 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1906 * 7.1.2 ACPI Table Layout 1907 */ 1908 static void 1909 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1910 const char *oem_id, const char *oem_table_id) 1911 { 1912 unsigned log_addr_offset; 1913 AcpiTable table = { .sig = "TCPA", .rev = 2, 1914 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1915 1916 acpi_table_begin(&table, table_data); 1917 /* Platform Class */ 1918 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1919 /* Log Area Minimum Length (LAML) */ 1920 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1921 /* Log Area Start Address (LASA) */ 1922 log_addr_offset = table_data->len; 1923 build_append_int_noprefix(table_data, 0, 8); 1924 1925 /* allocate/reserve space for TPM log area */ 1926 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1927 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1928 false /* high memory */); 1929 /* log area start address to be filled by Guest linker */ 1930 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1931 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1932 1933 acpi_table_end(linker, &table); 1934 } 1935 #endif 1936 1937 #define HOLE_640K_START (640 * KiB) 1938 #define HOLE_640K_END (1 * MiB) 1939 1940 /* 1941 * ACPI spec, Revision 3.0 1942 * 5.2.15 System Resource Affinity Table (SRAT) 1943 */ 1944 static void 1945 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1946 { 1947 int i; 1948 int numa_mem_start, slots; 1949 uint64_t mem_len, mem_base, next_base; 1950 MachineClass *mc = MACHINE_GET_CLASS(machine); 1951 X86MachineState *x86ms = X86_MACHINE(machine); 1952 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1953 PCMachineState *pcms = PC_MACHINE(machine); 1954 int nb_numa_nodes = machine->numa_state->num_nodes; 1955 NodeInfo *numa_info = machine->numa_state->nodes; 1956 ram_addr_t hotpluggable_address_space_size = 1957 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1958 NULL); 1959 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1960 .oem_table_id = x86ms->oem_table_id }; 1961 1962 acpi_table_begin(&table, table_data); 1963 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1964 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1965 1966 for (i = 0; i < apic_ids->len; i++) { 1967 int node_id = apic_ids->cpus[i].props.node_id; 1968 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1969 1970 if (apic_id < 255) { 1971 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1972 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1973 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1974 /* Proximity Domain [7:0] */ 1975 build_append_int_noprefix(table_data, node_id, 1); 1976 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1977 /* Flags, Table 5-36 */ 1978 build_append_int_noprefix(table_data, 1, 4); 1979 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1980 /* Proximity Domain [31:8] */ 1981 build_append_int_noprefix(table_data, 0, 3); 1982 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1983 } else { 1984 /* 1985 * ACPI spec, Revision 4.0 1986 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1987 */ 1988 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1989 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1990 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1991 /* Proximity Domain */ 1992 build_append_int_noprefix(table_data, node_id, 4); 1993 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1994 /* Flags, Table 5-39 */ 1995 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1996 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1997 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1998 } 1999 } 2000 2001 /* the memory map is a bit tricky, it contains at least one hole 2002 * from 640k-1M and possibly another one from 3.5G-4G. 2003 */ 2004 next_base = 0; 2005 numa_mem_start = table_data->len; 2006 2007 for (i = 1; i < nb_numa_nodes + 1; ++i) { 2008 mem_base = next_base; 2009 mem_len = numa_info[i - 1].node_mem; 2010 next_base = mem_base + mem_len; 2011 2012 /* Cut out the 640K hole */ 2013 if (mem_base <= HOLE_640K_START && 2014 next_base > HOLE_640K_START) { 2015 mem_len -= next_base - HOLE_640K_START; 2016 if (mem_len > 0) { 2017 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2018 MEM_AFFINITY_ENABLED); 2019 } 2020 2021 /* Check for the rare case: 640K < RAM < 1M */ 2022 if (next_base <= HOLE_640K_END) { 2023 next_base = HOLE_640K_END; 2024 continue; 2025 } 2026 mem_base = HOLE_640K_END; 2027 mem_len = next_base - HOLE_640K_END; 2028 } 2029 2030 /* Cut out the ACPI_PCI hole */ 2031 if (mem_base <= x86ms->below_4g_mem_size && 2032 next_base > x86ms->below_4g_mem_size) { 2033 mem_len -= next_base - x86ms->below_4g_mem_size; 2034 if (mem_len > 0) { 2035 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2036 MEM_AFFINITY_ENABLED); 2037 } 2038 mem_base = x86ms->above_4g_mem_start; 2039 mem_len = next_base - x86ms->below_4g_mem_size; 2040 next_base = mem_base + mem_len; 2041 } 2042 2043 if (mem_len > 0) { 2044 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2045 MEM_AFFINITY_ENABLED); 2046 } 2047 } 2048 2049 if (machine->nvdimms_state->is_enabled) { 2050 nvdimm_build_srat(table_data); 2051 } 2052 2053 sgx_epc_build_srat(table_data); 2054 2055 /* 2056 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2057 * without these entries. But I recall there were issues the last time I 2058 * tried to remove it with some ancient guest OS, however I can't remember 2059 * what that was so keep this around for now 2060 */ 2061 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2062 for (; slots < nb_numa_nodes + 2; slots++) { 2063 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2064 } 2065 2066 /* 2067 * Entry is required for Windows to enable memory hotplug in OS 2068 * and for Linux to enable SWIOTLB when booted with less than 2069 * 4G of RAM. Windows works better if the entry sets proximity 2070 * to the highest NUMA node in the machine. 2071 * Memory devices may override proximity set by this entry, 2072 * providing _PXM method if necessary. 2073 */ 2074 if (hotpluggable_address_space_size) { 2075 build_srat_memory(table_data, machine->device_memory->base, 2076 hotpluggable_address_space_size, nb_numa_nodes - 1, 2077 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2078 } 2079 2080 acpi_table_end(linker, &table); 2081 } 2082 2083 /* 2084 * Insert DMAR scope for PCI bridges and endpoint devcie 2085 */ 2086 static void 2087 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2088 { 2089 const size_t device_scope_size = 6 /* device scope structure */ + 2090 2 /* 1 path entry */; 2091 GArray *scope_blob = opaque; 2092 2093 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2094 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2095 build_append_int_noprefix(scope_blob, 0x02, 1); 2096 } else { 2097 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2098 build_append_int_noprefix(scope_blob, 0x01, 1); 2099 } 2100 2101 /* length */ 2102 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2103 /* reserved */ 2104 build_append_int_noprefix(scope_blob, 0, 2); 2105 /* enumeration_id */ 2106 build_append_int_noprefix(scope_blob, 0, 1); 2107 /* bus */ 2108 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2109 /* device */ 2110 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2111 /* function */ 2112 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2113 } 2114 2115 /* For a given PCI host bridge, walk and insert DMAR scope */ 2116 static int 2117 dmar_host_bridges(Object *obj, void *opaque) 2118 { 2119 GArray *scope_blob = opaque; 2120 2121 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2122 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2123 2124 if (bus && !pci_bus_bypass_iommu(bus)) { 2125 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2126 } 2127 } 2128 2129 return 0; 2130 } 2131 2132 /* 2133 * Intel ® Virtualization Technology for Directed I/O 2134 * Architecture Specification. Revision 3.3 2135 * 8.1 DMA Remapping Reporting Structure 2136 */ 2137 static void 2138 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2139 const char *oem_table_id) 2140 { 2141 uint8_t dmar_flags = 0; 2142 uint8_t rsvd10[10] = {}; 2143 /* Root complex IOAPIC uses one path only */ 2144 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2145 2 /* 1 path entry */; 2146 X86IOMMUState *iommu = x86_iommu_get_default(); 2147 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2148 GArray *scope_blob = g_array_new(false, true, 1); 2149 2150 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2151 .oem_table_id = oem_table_id }; 2152 2153 /* 2154 * A PCI bus walk, for each PCI host bridge. 2155 * Insert scope for each PCI bridge and endpoint device which 2156 * is attached to a bus with iommu enabled. 2157 */ 2158 object_child_foreach_recursive(object_get_root(), 2159 dmar_host_bridges, scope_blob); 2160 2161 assert(iommu); 2162 if (x86_iommu_ir_supported(iommu)) { 2163 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2164 } 2165 2166 acpi_table_begin(&table, table_data); 2167 /* Host Address Width */ 2168 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2169 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2170 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2171 2172 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2173 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2174 /* Length */ 2175 build_append_int_noprefix(table_data, 2176 16 + ioapic_scope_size + scope_blob->len, 2); 2177 /* Flags */ 2178 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2179 1); 2180 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2181 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2182 /* Register Base Address */ 2183 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2184 2185 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2186 * 8.3.1 (version Oct. 2014 or later). */ 2187 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2188 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2189 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2190 /* Enumeration ID */ 2191 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2192 /* Start Bus Number */ 2193 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2194 /* Path, {Device, Function} pair */ 2195 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2196 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2197 2198 /* Add scope found above */ 2199 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2200 g_array_free(scope_blob, true); 2201 2202 if (iommu->dt_supported) { 2203 /* 8.5 Root Port ATS Capability Reporting Structure */ 2204 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2205 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2206 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2207 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2208 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2209 } 2210 2211 acpi_table_end(linker, &table); 2212 } 2213 2214 /* 2215 * Windows ACPI Emulated Devices Table 2216 * (Version 1.0 - April 6, 2009) 2217 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2218 * 2219 * Helpful to speedup Windows guests and ignored by others. 2220 */ 2221 static void 2222 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2223 const char *oem_table_id) 2224 { 2225 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2226 .oem_table_id = oem_table_id }; 2227 2228 acpi_table_begin(&table, table_data); 2229 /* 2230 * Set "ACPI PM timer good" flag. 2231 * 2232 * Tells Windows guests that our ACPI PM timer is reliable in the 2233 * sense that guest can read it only once to obtain a reliable value. 2234 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2235 */ 2236 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2237 acpi_table_end(linker, &table); 2238 } 2239 2240 /* 2241 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2242 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2243 */ 2244 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2245 2246 /* 2247 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2248 * necessary for the PCI topology. 2249 */ 2250 static void 2251 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2252 { 2253 GArray *table_data = opaque; 2254 uint32_t entry; 2255 2256 /* "Select" IVHD entry, type 0x2 */ 2257 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2258 build_append_int_noprefix(table_data, entry, 4); 2259 2260 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2261 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2262 uint8_t sec = pci_bus_num(sec_bus); 2263 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2264 2265 if (pci_bus_is_express(sec_bus)) { 2266 /* 2267 * Walk the bus if there are subordinates, otherwise use a range 2268 * to cover an entire leaf bus. We could potentially also use a 2269 * range for traversed buses, but we'd need to take care not to 2270 * create both Select and Range entries covering the same device. 2271 * This is easier and potentially more compact. 2272 * 2273 * An example bare metal system seems to use Select entries for 2274 * root ports without a slot (ie. built-ins) and Range entries 2275 * when there is a slot. The same system also only hard-codes 2276 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2277 * making no effort to support nested bridges. We attempt to 2278 * be more thorough here. 2279 */ 2280 if (sec == sub) { /* leaf bus */ 2281 /* "Start of Range" IVHD entry, type 0x3 */ 2282 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2283 build_append_int_noprefix(table_data, entry, 4); 2284 /* "End of Range" IVHD entry, type 0x4 */ 2285 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2286 build_append_int_noprefix(table_data, entry, 4); 2287 } else { 2288 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2289 } 2290 } else { 2291 /* 2292 * If the secondary bus is conventional, then we need to create an 2293 * Alias range for everything downstream. The range covers the 2294 * first devfn on the secondary bus to the last devfn on the 2295 * subordinate bus. The alias target depends on legacy versus 2296 * express bridges, just as in pci_device_iommu_address_space(). 2297 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2298 */ 2299 uint16_t dev_id_a, dev_id_b; 2300 2301 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2302 2303 if (pci_is_express(dev) && 2304 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2305 dev_id_b = dev_id_a; 2306 } else { 2307 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2308 } 2309 2310 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2311 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2312 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2313 2314 /* "End of Range" IVHD entry, type 0x4 */ 2315 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2316 build_append_int_noprefix(table_data, entry, 4); 2317 } 2318 } 2319 } 2320 2321 /* For all PCI host bridges, walk and insert IVHD entries */ 2322 static int 2323 ivrs_host_bridges(Object *obj, void *opaque) 2324 { 2325 GArray *ivhd_blob = opaque; 2326 2327 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2328 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2329 2330 if (bus && !pci_bus_bypass_iommu(bus)) { 2331 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2332 } 2333 } 2334 2335 return 0; 2336 } 2337 2338 static void 2339 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2340 const char *oem_table_id) 2341 { 2342 int ivhd_table_len = 24; 2343 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2344 GArray *ivhd_blob = g_array_new(false, true, 1); 2345 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2346 .oem_table_id = oem_table_id }; 2347 2348 acpi_table_begin(&table, table_data); 2349 /* IVinfo - IO virtualization information common to all 2350 * IOMMU units in a system 2351 */ 2352 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2353 /* reserved */ 2354 build_append_int_noprefix(table_data, 0, 8); 2355 2356 /* IVHD definition - type 10h */ 2357 build_append_int_noprefix(table_data, 0x10, 1); 2358 /* virtualization flags */ 2359 build_append_int_noprefix(table_data, 2360 (1UL << 0) | /* HtTunEn */ 2361 (1UL << 4) | /* iotblSup */ 2362 (1UL << 6) | /* PrefSup */ 2363 (1UL << 7), /* PPRSup */ 2364 1); 2365 2366 /* 2367 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2368 * complete set of IVHD entries. Do this into a separate blob so that we 2369 * can calculate the total IVRS table length here and then append the new 2370 * blob further below. Fall back to an entry covering all devices, which 2371 * is sufficient when no aliases are present. 2372 */ 2373 object_child_foreach_recursive(object_get_root(), 2374 ivrs_host_bridges, ivhd_blob); 2375 2376 if (!ivhd_blob->len) { 2377 /* 2378 * Type 1 device entry reporting all devices 2379 * These are 4-byte device entries currently reporting the range of 2380 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2381 */ 2382 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2383 } 2384 2385 ivhd_table_len += ivhd_blob->len; 2386 2387 /* 2388 * When interrupt remapping is supported, we add a special IVHD device 2389 * for type IO-APIC. 2390 */ 2391 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2392 ivhd_table_len += 8; 2393 } 2394 2395 /* IVHD length */ 2396 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2397 /* DeviceID */ 2398 build_append_int_noprefix(table_data, s->devid, 2); 2399 /* Capability offset */ 2400 build_append_int_noprefix(table_data, s->capab_offset, 2); 2401 /* IOMMU base address */ 2402 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2403 /* PCI Segment Group */ 2404 build_append_int_noprefix(table_data, 0, 2); 2405 /* IOMMU info */ 2406 build_append_int_noprefix(table_data, 0, 2); 2407 /* IOMMU Feature Reporting */ 2408 build_append_int_noprefix(table_data, 2409 (48UL << 30) | /* HATS */ 2410 (48UL << 28) | /* GATS */ 2411 (1UL << 2) | /* GTSup */ 2412 (1UL << 6), /* GASup */ 2413 4); 2414 2415 /* IVHD entries as found above */ 2416 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2417 g_array_free(ivhd_blob, TRUE); 2418 2419 /* 2420 * Add a special IVHD device type. 2421 * Refer to spec - Table 95: IVHD device entry type codes 2422 * 2423 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2424 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2425 */ 2426 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2427 build_append_int_noprefix(table_data, 2428 (0x1ull << 56) | /* type IOAPIC */ 2429 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2430 0x48, /* special device */ 2431 8); 2432 } 2433 acpi_table_end(linker, &table); 2434 } 2435 2436 typedef 2437 struct AcpiBuildState { 2438 /* Copy of table in RAM (for patching). */ 2439 MemoryRegion *table_mr; 2440 /* Is table patched? */ 2441 uint8_t patched; 2442 void *rsdp; 2443 MemoryRegion *rsdp_mr; 2444 MemoryRegion *linker_mr; 2445 } AcpiBuildState; 2446 2447 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2448 { 2449 Object *pci_host; 2450 QObject *o; 2451 2452 pci_host = acpi_get_i386_pci_host(); 2453 if (!pci_host) { 2454 return false; 2455 } 2456 2457 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2458 if (!o) { 2459 return false; 2460 } 2461 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2462 qobject_unref(o); 2463 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2464 return false; 2465 } 2466 2467 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2468 assert(o); 2469 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2470 qobject_unref(o); 2471 return true; 2472 } 2473 2474 static 2475 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2476 { 2477 PCMachineState *pcms = PC_MACHINE(machine); 2478 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2479 X86MachineState *x86ms = X86_MACHINE(machine); 2480 DeviceState *iommu = pcms->iommu; 2481 GArray *table_offsets; 2482 unsigned facs, dsdt, rsdt, fadt; 2483 AcpiPmInfo pm; 2484 AcpiMiscInfo misc; 2485 AcpiMcfgInfo mcfg; 2486 Range pci_hole = {}, pci_hole64 = {}; 2487 uint8_t *u; 2488 size_t aml_len = 0; 2489 GArray *tables_blob = tables->table_data; 2490 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2491 Object *vmgenid_dev; 2492 char *oem_id; 2493 char *oem_table_id; 2494 2495 acpi_get_pm_info(machine, &pm); 2496 acpi_get_misc_info(&misc); 2497 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2498 acpi_get_slic_oem(&slic_oem); 2499 2500 if (slic_oem.id) { 2501 oem_id = slic_oem.id; 2502 } else { 2503 oem_id = x86ms->oem_id; 2504 } 2505 2506 if (slic_oem.table_id) { 2507 oem_table_id = slic_oem.table_id; 2508 } else { 2509 oem_table_id = x86ms->oem_table_id; 2510 } 2511 2512 table_offsets = g_array_new(false, true /* clear */, 2513 sizeof(uint32_t)); 2514 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2515 2516 bios_linker_loader_alloc(tables->linker, 2517 ACPI_BUILD_TABLE_FILE, tables_blob, 2518 64 /* Ensure FACS is aligned */, 2519 false /* high memory */); 2520 2521 /* 2522 * FACS is pointed to by FADT. 2523 * We place it first since it's the only table that has alignment 2524 * requirements. 2525 */ 2526 facs = tables_blob->len; 2527 build_facs(tables_blob); 2528 2529 /* DSDT is pointed to by FADT */ 2530 dsdt = tables_blob->len; 2531 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2532 &pci_hole, &pci_hole64, machine); 2533 2534 /* Count the size of the DSDT and SSDT, we will need it for legacy 2535 * sizing of ACPI tables. 2536 */ 2537 aml_len += tables_blob->len - dsdt; 2538 2539 /* ACPI tables pointed to by RSDT */ 2540 fadt = tables_blob->len; 2541 acpi_add_table(table_offsets, tables_blob); 2542 pm.fadt.facs_tbl_offset = &facs; 2543 pm.fadt.dsdt_tbl_offset = &dsdt; 2544 pm.fadt.xdsdt_tbl_offset = &dsdt; 2545 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2546 aml_len += tables_blob->len - fadt; 2547 2548 acpi_add_table(table_offsets, tables_blob); 2549 acpi_build_madt(tables_blob, tables->linker, x86ms, 2550 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2551 x86ms->oem_table_id); 2552 2553 #ifdef CONFIG_ACPI_ERST 2554 { 2555 Object *erst_dev; 2556 erst_dev = find_erst_dev(); 2557 if (erst_dev) { 2558 acpi_add_table(table_offsets, tables_blob); 2559 build_erst(tables_blob, tables->linker, erst_dev, 2560 x86ms->oem_id, x86ms->oem_table_id); 2561 } 2562 } 2563 #endif 2564 2565 vmgenid_dev = find_vmgenid_dev(); 2566 if (vmgenid_dev) { 2567 acpi_add_table(table_offsets, tables_blob); 2568 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2569 tables->vmgenid, tables->linker, x86ms->oem_id); 2570 } 2571 2572 if (misc.has_hpet) { 2573 acpi_add_table(table_offsets, tables_blob); 2574 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2575 x86ms->oem_table_id); 2576 } 2577 #ifdef CONFIG_TPM 2578 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2579 if (misc.tpm_version == TPM_VERSION_1_2) { 2580 acpi_add_table(table_offsets, tables_blob); 2581 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2582 x86ms->oem_id, x86ms->oem_table_id); 2583 } else { /* TPM_VERSION_2_0 */ 2584 acpi_add_table(table_offsets, tables_blob); 2585 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2586 x86ms->oem_id, x86ms->oem_table_id); 2587 } 2588 } 2589 #endif 2590 if (machine->numa_state->num_nodes) { 2591 acpi_add_table(table_offsets, tables_blob); 2592 build_srat(tables_blob, tables->linker, machine); 2593 if (machine->numa_state->have_numa_distance) { 2594 acpi_add_table(table_offsets, tables_blob); 2595 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2596 x86ms->oem_table_id); 2597 } 2598 if (machine->numa_state->hmat_enabled) { 2599 acpi_add_table(table_offsets, tables_blob); 2600 build_hmat(tables_blob, tables->linker, machine->numa_state, 2601 x86ms->oem_id, x86ms->oem_table_id); 2602 } 2603 } 2604 if (acpi_get_mcfg(&mcfg)) { 2605 acpi_add_table(table_offsets, tables_blob); 2606 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2607 x86ms->oem_table_id); 2608 } 2609 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2610 acpi_add_table(table_offsets, tables_blob); 2611 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2612 x86ms->oem_table_id); 2613 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2614 acpi_add_table(table_offsets, tables_blob); 2615 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2616 x86ms->oem_table_id); 2617 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2618 PCIDevice *pdev = PCI_DEVICE(iommu); 2619 2620 acpi_add_table(table_offsets, tables_blob); 2621 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2622 x86ms->oem_id, x86ms->oem_table_id); 2623 } 2624 if (machine->nvdimms_state->is_enabled) { 2625 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2626 machine->nvdimms_state, machine->ram_slots, 2627 x86ms->oem_id, x86ms->oem_table_id); 2628 } 2629 if (pcms->cxl_devices_state.is_enabled) { 2630 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2631 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2632 } 2633 2634 acpi_add_table(table_offsets, tables_blob); 2635 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2636 2637 /* Add tables supplied by user (if any) */ 2638 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2639 unsigned len = acpi_table_len(u); 2640 2641 acpi_add_table(table_offsets, tables_blob); 2642 g_array_append_vals(tables_blob, u, len); 2643 } 2644 2645 /* RSDT is pointed to by RSDP */ 2646 rsdt = tables_blob->len; 2647 build_rsdt(tables_blob, tables->linker, table_offsets, 2648 oem_id, oem_table_id); 2649 2650 /* RSDP is in FSEG memory, so allocate it separately */ 2651 { 2652 AcpiRsdpData rsdp_data = { 2653 .revision = 0, 2654 .oem_id = x86ms->oem_id, 2655 .xsdt_tbl_offset = NULL, 2656 .rsdt_tbl_offset = &rsdt, 2657 }; 2658 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2659 if (!pcmc->rsdp_in_ram) { 2660 /* We used to allocate some extra space for RSDP revision 2 but 2661 * only used the RSDP revision 0 space. The extra bytes were 2662 * zeroed out and not used. 2663 * Here we continue wasting those extra 16 bytes to make sure we 2664 * don't break migration for machine types 2.2 and older due to 2665 * RSDP blob size mismatch. 2666 */ 2667 build_append_int_noprefix(tables->rsdp, 0, 16); 2668 } 2669 } 2670 2671 /* We'll expose it all to Guest so we want to reduce 2672 * chance of size changes. 2673 * 2674 * We used to align the tables to 4k, but of course this would 2675 * too simple to be enough. 4k turned out to be too small an 2676 * alignment very soon, and in fact it is almost impossible to 2677 * keep the table size stable for all (max_cpus, max_memory_slots) 2678 * combinations. So the table size is always 64k for pc-i440fx-2.1 2679 * and we give an error if the table grows beyond that limit. 2680 * 2681 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2682 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2683 * than 2.0 and we can always pad the smaller tables with zeros. We can 2684 * then use the exact size of the 2.0 tables. 2685 * 2686 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2687 */ 2688 if (pcmc->legacy_acpi_table_size) { 2689 /* Subtracting aml_len gives the size of fixed tables. Then add the 2690 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2691 */ 2692 int legacy_aml_len = 2693 pcmc->legacy_acpi_table_size + 2694 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2695 int legacy_table_size = 2696 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2697 ACPI_BUILD_ALIGN_SIZE); 2698 if (tables_blob->len > legacy_table_size) { 2699 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2700 warn_report("ACPI table size %u exceeds %d bytes," 2701 " migration may not work", 2702 tables_blob->len, legacy_table_size); 2703 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2704 " or PCI bridges."); 2705 } 2706 g_array_set_size(tables_blob, legacy_table_size); 2707 } else { 2708 /* Make sure we have a buffer in case we need to resize the tables. */ 2709 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2710 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2711 warn_report("ACPI table size %u exceeds %d bytes," 2712 " migration may not work", 2713 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2714 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2715 " or PCI bridges."); 2716 } 2717 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2718 } 2719 2720 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2721 2722 /* Cleanup memory that's no longer used. */ 2723 g_array_free(table_offsets, true); 2724 g_free(slic_oem.id); 2725 g_free(slic_oem.table_id); 2726 } 2727 2728 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2729 { 2730 uint32_t size = acpi_data_len(data); 2731 2732 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2733 memory_region_ram_resize(mr, size, &error_abort); 2734 2735 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2736 memory_region_set_dirty(mr, 0, size); 2737 } 2738 2739 static void acpi_build_update(void *build_opaque) 2740 { 2741 AcpiBuildState *build_state = build_opaque; 2742 AcpiBuildTables tables; 2743 2744 /* No state to update or already patched? Nothing to do. */ 2745 if (!build_state || build_state->patched) { 2746 return; 2747 } 2748 build_state->patched = 1; 2749 2750 acpi_build_tables_init(&tables); 2751 2752 acpi_build(&tables, MACHINE(qdev_get_machine())); 2753 2754 acpi_ram_update(build_state->table_mr, tables.table_data); 2755 2756 if (build_state->rsdp) { 2757 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2758 } else { 2759 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2760 } 2761 2762 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2763 acpi_build_tables_cleanup(&tables, true); 2764 } 2765 2766 static void acpi_build_reset(void *build_opaque) 2767 { 2768 AcpiBuildState *build_state = build_opaque; 2769 build_state->patched = 0; 2770 } 2771 2772 static const VMStateDescription vmstate_acpi_build = { 2773 .name = "acpi_build", 2774 .version_id = 1, 2775 .minimum_version_id = 1, 2776 .fields = (VMStateField[]) { 2777 VMSTATE_UINT8(patched, AcpiBuildState), 2778 VMSTATE_END_OF_LIST() 2779 }, 2780 }; 2781 2782 void acpi_setup(void) 2783 { 2784 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2785 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2786 X86MachineState *x86ms = X86_MACHINE(pcms); 2787 AcpiBuildTables tables; 2788 AcpiBuildState *build_state; 2789 Object *vmgenid_dev; 2790 #ifdef CONFIG_TPM 2791 TPMIf *tpm; 2792 static FwCfgTPMConfig tpm_config; 2793 #endif 2794 2795 if (!x86ms->fw_cfg) { 2796 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2797 return; 2798 } 2799 2800 if (!pcms->acpi_build_enabled) { 2801 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2802 return; 2803 } 2804 2805 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2806 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2807 return; 2808 } 2809 2810 build_state = g_malloc0(sizeof *build_state); 2811 2812 acpi_build_tables_init(&tables); 2813 acpi_build(&tables, MACHINE(pcms)); 2814 2815 /* Now expose it all to Guest */ 2816 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2817 build_state, tables.table_data, 2818 ACPI_BUILD_TABLE_FILE); 2819 assert(build_state->table_mr != NULL); 2820 2821 build_state->linker_mr = 2822 acpi_add_rom_blob(acpi_build_update, build_state, 2823 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2824 2825 #ifdef CONFIG_TPM 2826 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2827 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2828 2829 tpm = tpm_find(); 2830 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2831 tpm_config = (FwCfgTPMConfig) { 2832 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2833 .tpm_version = tpm_get_version(tpm), 2834 .tpmppi_version = TPM_PPI_VERSION_1_30 2835 }; 2836 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2837 &tpm_config, sizeof tpm_config); 2838 } 2839 #endif 2840 2841 vmgenid_dev = find_vmgenid_dev(); 2842 if (vmgenid_dev) { 2843 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2844 tables.vmgenid); 2845 } 2846 2847 if (!pcmc->rsdp_in_ram) { 2848 /* 2849 * Keep for compatibility with old machine types. 2850 * Though RSDP is small, its contents isn't immutable, so 2851 * we'll update it along with the rest of tables on guest access. 2852 */ 2853 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2854 2855 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2856 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2857 acpi_build_update, NULL, build_state, 2858 build_state->rsdp, rsdp_size, true); 2859 build_state->rsdp_mr = NULL; 2860 } else { 2861 build_state->rsdp = NULL; 2862 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2863 build_state, tables.rsdp, 2864 ACPI_BUILD_RSDP_FILE); 2865 } 2866 2867 qemu_register_reset(acpi_build_reset, build_state); 2868 acpi_build_reset(build_state); 2869 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2870 2871 /* Cleanup tables but don't free the memory: we track it 2872 * in build_state. 2873 */ 2874 acpi_build_tables_cleanup(&tables, false); 2875 } 2876