1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qobject/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "system/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/vmclock.h" 47 #include "hw/acpi/erst.h" 48 #include "hw/acpi/piix4.h" 49 #include "system/tpm_backend.h" 50 #include "hw/rtc/mc146818rtc_regs.h" 51 #include "migration/vmstate.h" 52 #include "hw/mem/memory-device.h" 53 #include "hw/mem/nvdimm.h" 54 #include "system/numa.h" 55 #include "system/reset.h" 56 #include "hw/hyperv/vmbus-bridge.h" 57 58 /* Supported chipsets: */ 59 #include "hw/southbridge/ich9.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/pc.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/i440fx.h" 65 #include "hw/pci-host/q35.h" 66 #include "hw/i386/x86-iommu.h" 67 68 #include "hw/acpi/aml-build.h" 69 #include "hw/acpi/utils.h" 70 #include "hw/acpi/pci.h" 71 #include "hw/acpi/cxl.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_ALIGN_SIZE 0x1000 89 90 #define ACPI_BUILD_TABLE_SIZE 0x20000 91 92 /* #define DEBUG_ACPI_BUILD */ 93 #ifdef DEBUG_ACPI_BUILD 94 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 96 #else 97 #define ACPI_BUILD_DPRINTF(fmt, ...) 98 #endif 99 100 typedef struct AcpiPmInfo { 101 bool s3_disabled; 102 bool s4_disabled; 103 bool pcihp_bridge_en; 104 bool smi_on_cpuhp; 105 bool smi_on_cpu_unplug; 106 bool pcihp_root_en; 107 uint8_t s4_val; 108 AcpiFadtData fadt; 109 uint16_t cpu_hp_io_base; 110 uint16_t pcihp_io_base; 111 uint16_t pcihp_io_len; 112 } AcpiPmInfo; 113 114 typedef struct AcpiMiscInfo { 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 } AcpiMiscInfo; 120 121 typedef struct FwCfgTPMConfig { 122 uint32_t tpmppi_address; 123 uint8_t tpm_version; 124 uint8_t tpmppi_version; 125 } QEMU_PACKED FwCfgTPMConfig; 126 127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 128 129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 130 .space_id = AML_AS_SYSTEM_IO, 131 .address = NVDIMM_ACPI_IO_BASE, 132 .bit_width = NVDIMM_ACPI_IO_LEN << 3 133 }; 134 135 static void init_common_fadt_data(MachineState *ms, Object *o, 136 AcpiFadtData *data) 137 { 138 X86MachineState *x86ms = X86_MACHINE(ms); 139 /* 140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 141 * behavior for compatibility irrelevant to smm_enabled, which doesn't 142 * conform to the ACPI spec. 143 */ 144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 145 true : x86_machine_is_smm_enabled(x86ms); 146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 147 AmlAddressSpace as = AML_AS_SYSTEM_IO; 148 AcpiFadtData fadt = { 149 .rev = 3, 150 .flags = 151 (1 << ACPI_FADT_F_WBINVD) | 152 (1 << ACPI_FADT_F_PROC_C1) | 153 (1 << ACPI_FADT_F_SLP_BUTTON) | 154 (1 << ACPI_FADT_F_RTC_S4) | 155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 156 /* APIC destination mode ("Flat Logical") has an upper limit of 8 157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 158 * used 159 */ 160 ((ms->smp.max_cpus > 8) ? 161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 162 .int_model = 1 /* Multiple APIC */, 163 .rtc_century = RTC_CENTURY, 164 .plvl2_lat = 0xfff /* C2 state not supported */, 165 .plvl3_lat = 0xfff /* C3 state not supported */, 166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 168 .acpi_enable_cmd = 169 smm_enabled ? 170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 171 0, 172 .acpi_disable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 175 0, 176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 178 .address = io + 0x04 }, 179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 180 .gpe0_blk = { .space_id = as, .bit_width = 181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 183 }, 184 }; 185 186 /* 187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 188 * Flags, bit offset 1 - 8042. 189 */ 190 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 191 192 *data = fadt; 193 } 194 195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 196 { 197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL); 198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL); 199 Object *obj = piix ? piix : lpc; 200 QObject *o; 201 pm->cpu_hp_io_base = 0; 202 pm->pcihp_io_base = 0; 203 pm->pcihp_io_len = 0; 204 pm->smi_on_cpuhp = false; 205 pm->smi_on_cpu_unplug = false; 206 207 assert(obj); 208 init_common_fadt_data(machine, obj, &pm->fadt); 209 if (piix) { 210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 211 pm->fadt.rev = 1; 212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 213 } 214 if (lpc) { 215 uint64_t smi_features = object_property_get_uint(lpc, 216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 219 pm->fadt.reset_reg = r; 220 pm->fadt.reset_val = 0xf; 221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 223 pm->smi_on_cpuhp = 224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 225 pm->smi_on_cpu_unplug = 226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 227 } 228 pm->pcihp_io_base = 229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 230 pm->pcihp_io_len = 231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 232 233 /* Fill in optional s3/s4 related properties */ 234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 235 if (o) { 236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 237 } else { 238 pm->s3_disabled = false; 239 } 240 qobject_unref(o); 241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 242 if (o) { 243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 244 } else { 245 pm->s4_disabled = false; 246 } 247 qobject_unref(o); 248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 249 if (o) { 250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 251 } else { 252 pm->s4_val = false; 253 } 254 qobject_unref(o); 255 256 pm->pcihp_bridge_en = 257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 258 NULL); 259 pm->pcihp_root_en = 260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 261 NULL); 262 } 263 264 static void acpi_get_misc_info(AcpiMiscInfo *info) 265 { 266 info->has_hpet = hpet_find(); 267 #ifdef CONFIG_TPM 268 info->tpm_version = tpm_get_version(tpm_find()); 269 #endif 270 } 271 272 /* 273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 274 * On i386 arch we only have two pci hosts, so we can look only for them. 275 */ 276 Object *acpi_get_i386_pci_host(void) 277 { 278 PCIHostState *host; 279 280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 281 if (!host) { 282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 283 } 284 285 return OBJECT(host); 286 } 287 288 static void acpi_get_pci_holes(Range *hole, Range *hole64) 289 { 290 Object *pci_host; 291 292 pci_host = acpi_get_i386_pci_host(); 293 294 if (!pci_host) { 295 return; 296 } 297 298 range_set_bounds1(hole, 299 object_property_get_uint(pci_host, 300 PCI_HOST_PROP_PCI_HOLE_START, 301 NULL), 302 object_property_get_uint(pci_host, 303 PCI_HOST_PROP_PCI_HOLE_END, 304 NULL)); 305 range_set_bounds1(hole64, 306 object_property_get_uint(pci_host, 307 PCI_HOST_PROP_PCI_HOLE64_START, 308 NULL), 309 object_property_get_uint(pci_host, 310 PCI_HOST_PROP_PCI_HOLE64_END, 311 NULL)); 312 } 313 314 static void acpi_align_size(GArray *blob, unsigned align) 315 { 316 /* Align size to multiple of given size. This reduces the chance 317 * we need to change size in the future (breaking cross version migration). 318 */ 319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 320 } 321 322 /* 323 * ACPI spec 1.0b, 324 * 5.2.6 Firmware ACPI Control Structure 325 */ 326 static void 327 build_facs(GArray *table_data) 328 { 329 const char *sig = "FACS"; 330 const uint8_t reserved[40] = {}; 331 332 g_array_append_vals(table_data, sig, 4); /* Signature */ 333 build_append_int_noprefix(table_data, 64, 4); /* Length */ 334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 337 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 338 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 339 } 340 341 static Aml *aml_pci_edsm(void) 342 { 343 Aml *method, *ifctx; 344 Aml *zero = aml_int(0); 345 Aml *func = aml_arg(2); 346 Aml *ret = aml_local(0); 347 Aml *aidx = aml_local(1); 348 Aml *params = aml_arg(4); 349 350 method = aml_method("EDSM", 5, AML_SERIALIZED); 351 352 /* get supported functions */ 353 ifctx = aml_if(aml_equal(func, zero)); 354 { 355 /* 1: have supported functions */ 356 /* 7: support for function 7 */ 357 const uint8_t caps = 1 | BIT(7); 358 build_append_pci_dsm_func0_common(ifctx, ret); 359 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 360 aml_append(ifctx, aml_return(ret)); 361 } 362 aml_append(method, ifctx); 363 364 /* handle specific functions requests */ 365 /* 366 * PCI Firmware Specification 3.1 367 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 368 * Operating Systems 369 */ 370 ifctx = aml_if(aml_equal(func, aml_int(7))); 371 { 372 Aml *pkg = aml_package(2); 373 aml_append(pkg, zero); 374 /* optional, if not impl. should return null string */ 375 aml_append(pkg, aml_string("%s", "")); 376 aml_append(ifctx, aml_store(pkg, ret)); 377 378 /* 379 * IASL is fine when initializing Package with computational data, 380 * however it makes guest unhappy /it fails to process such AML/. 381 * So use runtime assignment to set acpi-index after initializer 382 * to make OSPM happy. 383 */ 384 aml_append(ifctx, 385 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 386 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 387 aml_append(ifctx, aml_return(ret)); 388 } 389 aml_append(method, ifctx); 390 391 return method; 392 } 393 394 /* 395 * build_prt - Define interrupt routing rules 396 * 397 * Returns an array of 128 routes, one for each device, 398 * based on device location. 399 * The main goal is to equally distribute the interrupts 400 * over the 4 existing ACPI links (works only for i440fx). 401 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]". 402 * 403 */ 404 static Aml *build_prt(bool is_pci0_prt) 405 { 406 const int nroutes = 128; 407 Aml *rt_pkg, *method; 408 int pin; 409 410 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 411 assert(nroutes < 256); 412 rt_pkg = aml_package(nroutes); 413 414 for (pin = 0; pin < nroutes; pin++) { 415 Aml *pkg = aml_package(4); 416 int slot = pin >> 2; 417 418 aml_append(pkg, aml_int((slot << 16) | 0xFFFF)); 419 aml_append(pkg, aml_int(pin & 3)); 420 /* device 1 is the power-management device, needs SCI */ 421 if (is_pci0_prt && pin == 4) { 422 aml_append(pkg, aml_name("%s", "LNKS")); 423 } else { 424 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"}; 425 int hash = (slot + pin) & 3; 426 aml_append(pkg, aml_name("%s", link_name[hash])); 427 } 428 aml_append(pkg, aml_int(0)); 429 aml_append(rt_pkg, pkg); 430 } 431 432 aml_append(method, aml_return(rt_pkg)); 433 434 return method; 435 } 436 437 static void build_hpet_aml(Aml *table) 438 { 439 Aml *crs; 440 Aml *field; 441 Aml *method; 442 Aml *if_ctx; 443 Aml *scope = aml_scope("_SB"); 444 Aml *dev = aml_device("HPET"); 445 Aml *zero = aml_int(0); 446 Aml *id = aml_local(0); 447 Aml *period = aml_local(1); 448 449 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 450 aml_append(dev, aml_name_decl("_UID", zero)); 451 452 aml_append(dev, 453 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 454 HPET_LEN)); 455 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 456 aml_append(field, aml_named_field("VEND", 32)); 457 aml_append(field, aml_named_field("PRD", 32)); 458 aml_append(dev, field); 459 460 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 461 aml_append(method, aml_store(aml_name("VEND"), id)); 462 aml_append(method, aml_store(aml_name("PRD"), period)); 463 aml_append(method, aml_shiftright(id, aml_int(16), id)); 464 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 465 aml_equal(id, aml_int(0xffff)))); 466 { 467 aml_append(if_ctx, aml_return(zero)); 468 } 469 aml_append(method, if_ctx); 470 471 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 472 aml_lgreater(period, aml_int(100000000)))); 473 { 474 aml_append(if_ctx, aml_return(zero)); 475 } 476 aml_append(method, if_ctx); 477 478 aml_append(method, aml_return(aml_int(0x0F))); 479 aml_append(dev, method); 480 481 crs = aml_resource_template(); 482 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 483 aml_append(dev, aml_name_decl("_CRS", crs)); 484 485 aml_append(scope, dev); 486 aml_append(table, scope); 487 } 488 489 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 490 { 491 Aml *dev; 492 Aml *method; 493 Aml *crs; 494 495 dev = aml_device("VMBS"); 496 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 497 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 498 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 499 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 500 501 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 502 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 503 aml_name("STA"))); 504 aml_append(dev, method); 505 506 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 507 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 508 aml_name("STA"))); 509 aml_append(dev, method); 510 511 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 512 aml_append(method, aml_return(aml_name("STA"))); 513 aml_append(dev, method); 514 515 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 516 517 crs = aml_resource_template(); 518 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 519 aml_append(dev, aml_name_decl("_CRS", crs)); 520 521 return dev; 522 } 523 524 static void build_dbg_aml(Aml *table) 525 { 526 Aml *field; 527 Aml *method; 528 Aml *while_ctx; 529 Aml *scope = aml_scope("\\"); 530 Aml *buf = aml_local(0); 531 Aml *len = aml_local(1); 532 Aml *idx = aml_local(2); 533 534 aml_append(scope, 535 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 536 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 537 aml_append(field, aml_named_field("DBGB", 8)); 538 aml_append(scope, field); 539 540 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 541 542 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 543 aml_append(method, aml_to_buffer(buf, buf)); 544 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 545 aml_append(method, aml_store(aml_int(0), idx)); 546 547 while_ctx = aml_while(aml_lless(idx, len)); 548 aml_append(while_ctx, 549 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 550 aml_append(while_ctx, aml_increment(idx)); 551 aml_append(method, while_ctx); 552 553 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 554 aml_append(scope, method); 555 556 aml_append(table, scope); 557 } 558 559 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 560 { 561 Aml *dev; 562 Aml *crs; 563 Aml *method; 564 uint32_t irqs[] = {5, 10, 11}; 565 566 dev = aml_device("%s", name); 567 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 568 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 569 570 crs = aml_resource_template(); 571 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 572 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 573 aml_append(dev, aml_name_decl("_PRS", crs)); 574 575 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 576 aml_append(method, aml_return(aml_call1("IQST", reg))); 577 aml_append(dev, method); 578 579 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 580 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 581 aml_append(dev, method); 582 583 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 584 aml_append(method, aml_return(aml_call1("IQCR", reg))); 585 aml_append(dev, method); 586 587 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 588 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 589 aml_append(method, aml_store(aml_name("PRRI"), reg)); 590 aml_append(dev, method); 591 592 return dev; 593 } 594 595 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 596 { 597 Aml *dev; 598 Aml *crs; 599 Aml *method; 600 uint32_t irqs; 601 602 dev = aml_device("%s", name); 603 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 604 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 605 606 crs = aml_resource_template(); 607 irqs = gsi; 608 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 609 AML_SHARED, &irqs, 1)); 610 aml_append(dev, aml_name_decl("_PRS", crs)); 611 612 aml_append(dev, aml_name_decl("_CRS", crs)); 613 614 /* 615 * _DIS can be no-op because the interrupt cannot be disabled. 616 */ 617 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 618 aml_append(dev, method); 619 620 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 621 aml_append(dev, method); 622 623 return dev; 624 } 625 626 /* _CRS method - get current settings */ 627 static Aml *build_iqcr_method(bool is_piix4) 628 { 629 Aml *if_ctx; 630 uint32_t irqs; 631 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 632 Aml *crs = aml_resource_template(); 633 634 irqs = 0; 635 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 636 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 637 aml_append(method, aml_name_decl("PRR0", crs)); 638 639 aml_append(method, 640 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 641 642 if (is_piix4) { 643 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 644 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 645 aml_append(method, if_ctx); 646 } else { 647 aml_append(method, 648 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 649 aml_name("PRRI"))); 650 } 651 652 aml_append(method, aml_return(aml_name("PRR0"))); 653 return method; 654 } 655 656 /* _STA method - get status */ 657 static Aml *build_irq_status_method(void) 658 { 659 Aml *if_ctx; 660 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 661 662 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 663 aml_append(if_ctx, aml_return(aml_int(0x09))); 664 aml_append(method, if_ctx); 665 aml_append(method, aml_return(aml_int(0x0B))); 666 return method; 667 } 668 669 static void build_piix4_pci0_int(Aml *table) 670 { 671 Aml *dev; 672 Aml *crs; 673 Aml *method; 674 uint32_t irqs; 675 Aml *sb_scope = aml_scope("_SB"); 676 Aml *pci0_scope = aml_scope("PCI0"); 677 678 aml_append(pci0_scope, build_prt(true)); 679 aml_append(sb_scope, pci0_scope); 680 681 aml_append(sb_scope, build_irq_status_method()); 682 aml_append(sb_scope, build_iqcr_method(true)); 683 684 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 685 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 686 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 687 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 688 689 dev = aml_device("LNKS"); 690 { 691 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 692 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 693 694 crs = aml_resource_template(); 695 irqs = 9; 696 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 697 AML_ACTIVE_HIGH, AML_SHARED, 698 &irqs, 1)); 699 aml_append(dev, aml_name_decl("_PRS", crs)); 700 701 /* The SCI cannot be disabled and is always attached to GSI 9, 702 * so these are no-ops. We only need this link to override the 703 * polarity to active high and match the content of the MADT. 704 */ 705 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 706 aml_append(method, aml_return(aml_int(0x0b))); 707 aml_append(dev, method); 708 709 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 710 aml_append(dev, method); 711 712 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 713 aml_append(method, aml_return(aml_name("_PRS"))); 714 aml_append(dev, method); 715 716 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 717 aml_append(dev, method); 718 } 719 aml_append(sb_scope, dev); 720 721 aml_append(table, sb_scope); 722 } 723 724 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 725 { 726 int i; 727 int head; 728 Aml *pkg; 729 char base = name[3] < 'E' ? 'A' : 'E'; 730 char *s = g_strdup(name); 731 Aml *a_nr = aml_int((nr << 16) | 0xffff); 732 733 assert(strlen(s) == 4); 734 735 head = name[3] - base; 736 for (i = 0; i < 4; i++) { 737 if (head + i > 3) { 738 head = i * -1; 739 } 740 s[3] = base + head + i; 741 pkg = aml_package(4); 742 aml_append(pkg, a_nr); 743 aml_append(pkg, aml_int(i)); 744 aml_append(pkg, aml_name("%s", s)); 745 aml_append(pkg, aml_int(0)); 746 aml_append(ctx, pkg); 747 } 748 g_free(s); 749 } 750 751 static Aml *build_q35_routing_table(const char *str) 752 { 753 int i; 754 Aml *pkg; 755 char *name = g_strdup_printf("%s ", str); 756 757 pkg = aml_package(128); 758 for (i = 0; i < 0x18; i++) { 759 name[3] = 'E' + (i & 0x3); 760 append_q35_prt_entry(pkg, i, name); 761 } 762 763 name[3] = 'E'; 764 append_q35_prt_entry(pkg, 0x18, name); 765 766 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 767 for (i = 0x0019; i < 0x1e; i++) { 768 name[3] = 'A'; 769 append_q35_prt_entry(pkg, i, name); 770 } 771 772 /* PCIe->PCI bridge. use PIRQ[E-H] */ 773 name[3] = 'E'; 774 append_q35_prt_entry(pkg, 0x1e, name); 775 name[3] = 'A'; 776 append_q35_prt_entry(pkg, 0x1f, name); 777 778 g_free(name); 779 return pkg; 780 } 781 782 static void build_q35_pci0_int(Aml *table) 783 { 784 Aml *method; 785 Aml *sb_scope = aml_scope("_SB"); 786 Aml *pci0_scope = aml_scope("PCI0"); 787 788 /* Zero => PIC mode, One => APIC Mode */ 789 aml_append(table, aml_name_decl("PICF", aml_int(0))); 790 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 791 { 792 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 793 } 794 aml_append(table, method); 795 796 aml_append(pci0_scope, 797 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 798 aml_append(pci0_scope, 799 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 800 801 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 802 { 803 Aml *if_ctx; 804 Aml *else_ctx; 805 806 /* PCI IRQ routing table, example from ACPI 2.0a specification, 807 section 6.2.8.1 */ 808 /* Note: we provide the same info as the PCI routing 809 table of the Bochs BIOS */ 810 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 811 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 812 aml_append(method, if_ctx); 813 else_ctx = aml_else(); 814 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 815 aml_append(method, else_ctx); 816 } 817 aml_append(pci0_scope, method); 818 aml_append(sb_scope, pci0_scope); 819 820 aml_append(sb_scope, build_irq_status_method()); 821 aml_append(sb_scope, build_iqcr_method(false)); 822 823 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 824 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 825 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 826 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 827 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 828 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 829 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 830 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 831 832 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 833 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 834 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 835 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 836 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 837 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 838 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 839 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 840 841 aml_append(table, sb_scope); 842 } 843 844 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 845 { 846 Aml *dev; 847 Aml *resource_template; 848 849 /* DRAM controller */ 850 dev = aml_device("DRAC"); 851 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 852 853 resource_template = aml_resource_template(); 854 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 855 aml_append(resource_template, 856 aml_qword_memory(AML_POS_DECODE, 857 AML_MIN_FIXED, 858 AML_MAX_FIXED, 859 AML_NON_CACHEABLE, 860 AML_READ_WRITE, 861 0x0000000000000000, 862 mcfg->base, 863 mcfg->base + mcfg->size - 1, 864 0x0000000000000000, 865 mcfg->size)); 866 } else { 867 aml_append(resource_template, 868 aml_dword_memory(AML_POS_DECODE, 869 AML_MIN_FIXED, 870 AML_MAX_FIXED, 871 AML_NON_CACHEABLE, 872 AML_READ_WRITE, 873 0x0000000000000000, 874 mcfg->base, 875 mcfg->base + mcfg->size - 1, 876 0x0000000000000000, 877 mcfg->size)); 878 } 879 aml_append(dev, aml_name_decl("_CRS", resource_template)); 880 881 return dev; 882 } 883 884 static void build_acpi0017(Aml *table) 885 { 886 Aml *dev, *scope, *method; 887 888 scope = aml_scope("_SB"); 889 dev = aml_device("CXLM"); 890 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 891 892 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 893 aml_append(method, aml_return(aml_int(0x0B))); 894 aml_append(dev, method); 895 build_cxl_dsm_method(dev); 896 897 aml_append(scope, dev); 898 aml_append(table, scope); 899 } 900 901 static void 902 build_dsdt(GArray *table_data, BIOSLinker *linker, 903 AcpiPmInfo *pm, AcpiMiscInfo *misc, 904 Range *pci_hole, Range *pci_hole64, MachineState *machine) 905 { 906 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE, 907 NULL); 908 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL); 909 CrsRangeEntry *entry; 910 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 911 CrsRangeSet crs_range_set; 912 PCMachineState *pcms = PC_MACHINE(machine); 913 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 914 X86MachineState *x86ms = X86_MACHINE(machine); 915 AcpiMcfgInfo mcfg; 916 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 917 uint32_t nr_mem = machine->ram_slots; 918 int root_bus_limit = 0xFF; 919 PCIBus *bus = NULL; 920 #ifdef CONFIG_TPM 921 TPMIf *tpm = tpm_find(); 922 #endif 923 bool cxl_present = false; 924 int i; 925 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 926 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 927 .oem_table_id = x86ms->oem_table_id }; 928 929 assert(!!i440fx != !!q35); 930 931 acpi_table_begin(&table, table_data); 932 dsdt = init_aml_allocator(); 933 934 build_dbg_aml(dsdt); 935 if (i440fx) { 936 sb_scope = aml_scope("_SB"); 937 dev = aml_device("PCI0"); 938 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 939 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 940 aml_append(dev, aml_pci_edsm()); 941 aml_append(sb_scope, dev); 942 aml_append(dsdt, sb_scope); 943 944 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 945 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); 946 } 947 build_piix4_pci0_int(dsdt); 948 } else if (q35) { 949 sb_scope = aml_scope("_SB"); 950 dev = aml_device("PCI0"); 951 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 952 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 953 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 954 aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en)); 955 aml_append(dev, aml_pci_edsm()); 956 aml_append(sb_scope, dev); 957 if (mcfg_valid) { 958 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 959 } 960 961 if (pm->smi_on_cpuhp) { 962 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 963 dev = aml_device("PCI0.SMI0"); 964 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 965 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 966 crs = aml_resource_template(); 967 aml_append(crs, 968 aml_io( 969 AML_DECODE16, 970 pm->fadt.smi_cmd, 971 pm->fadt.smi_cmd, 972 1, 973 2) 974 ); 975 aml_append(dev, aml_name_decl("_CRS", crs)); 976 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 977 aml_int(pm->fadt.smi_cmd), 2)); 978 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 979 AML_WRITE_AS_ZEROS); 980 aml_append(field, aml_named_field("SMIC", 8)); 981 aml_append(field, aml_reserved_field(8)); 982 aml_append(dev, field); 983 aml_append(sb_scope, dev); 984 } 985 986 aml_append(dsdt, sb_scope); 987 988 if (pm->pcihp_bridge_en) { 989 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); 990 } 991 build_q35_pci0_int(dsdt); 992 } 993 994 if (misc->has_hpet) { 995 build_hpet_aml(dsdt); 996 } 997 998 if (vmbus_bridge) { 999 sb_scope = aml_scope("_SB"); 1000 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1001 aml_append(dsdt, sb_scope); 1002 } 1003 1004 scope = aml_scope("_GPE"); 1005 { 1006 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1007 if (machine->nvdimms_state->is_enabled) { 1008 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1009 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1010 aml_int(0x80))); 1011 aml_append(scope, method); 1012 } 1013 } 1014 aml_append(dsdt, scope); 1015 1016 if (pcmc->legacy_cpu_hotplug) { 1017 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1018 } else { 1019 CPUHotplugFeatures opts = { 1020 .acpi_1_compatible = true, .has_legacy_cphp = true, 1021 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1022 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1023 }; 1024 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, 1025 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", 1026 AML_SYSTEM_IO); 1027 } 1028 1029 if (pcms->memhp_io_base && nr_mem) { 1030 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1031 "\\_GPE._E03", AML_SYSTEM_IO, 1032 pcms->memhp_io_base); 1033 } 1034 1035 crs_range_set_init(&crs_range_set); 1036 bus = PC_MACHINE(machine)->pcibus; 1037 if (bus) { 1038 QLIST_FOREACH(bus, &bus->child, sibling) { 1039 uint8_t bus_num = pci_bus_num(bus); 1040 uint8_t numa_node = pci_bus_numa_node(bus); 1041 uint32_t uid; 1042 1043 /* look only for expander root buses */ 1044 if (!pci_bus_is_root(bus)) { 1045 continue; 1046 } 1047 1048 if (bus_num < root_bus_limit) { 1049 root_bus_limit = bus_num - 1; 1050 } 1051 1052 uid = object_property_get_uint(OBJECT(bus), "acpi_uid", 1053 &error_fatal); 1054 scope = aml_scope("\\_SB"); 1055 1056 if (pci_bus_is_cxl(bus)) { 1057 dev = aml_device("CL%.02X", bus_num); 1058 } else { 1059 dev = aml_device("PC%.02X", bus_num); 1060 } 1061 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1062 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1063 if (pci_bus_is_cxl(bus)) { 1064 struct Aml *aml_pkg = aml_package(2); 1065 1066 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1067 aml_append(aml_pkg, aml_eisaid("PNP0A08")); 1068 aml_append(aml_pkg, aml_eisaid("PNP0A03")); 1069 aml_append(dev, aml_name_decl("_CID", aml_pkg)); 1070 build_cxl_osc_method(dev); 1071 } else if (pci_bus_is_express(bus)) { 1072 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1073 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1074 1075 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1076 aml_append(dev, build_pci_host_bridge_osc_method(true)); 1077 } else { 1078 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1079 } 1080 1081 if (numa_node != NUMA_NODE_UNASSIGNED) { 1082 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1083 } 1084 1085 aml_append(dev, build_prt(false)); 1086 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1087 0, 0, 0, 0); 1088 aml_append(dev, aml_name_decl("_CRS", crs)); 1089 aml_append(scope, dev); 1090 aml_append(dsdt, scope); 1091 1092 /* Handle the ranges for the PXB expanders */ 1093 if (pci_bus_is_cxl(bus)) { 1094 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1095 uint64_t base = mr->addr; 1096 1097 cxl_present = true; 1098 crs_range_insert(crs_range_set.mem_ranges, base, 1099 base + memory_region_size(mr) - 1); 1100 } 1101 } 1102 } 1103 1104 if (cxl_present) { 1105 build_acpi0017(dsdt); 1106 } 1107 1108 /* 1109 * At this point crs_range_set has all the ranges used by pci 1110 * busses *other* than PCI0. These ranges will be excluded from 1111 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1112 * too. 1113 */ 1114 if (mcfg_valid) { 1115 crs_range_insert(crs_range_set.mem_ranges, 1116 mcfg.base, mcfg.base + mcfg.size - 1); 1117 } 1118 1119 scope = aml_scope("\\_SB.PCI0"); 1120 /* build PCI0._CRS */ 1121 crs = aml_resource_template(); 1122 aml_append(crs, 1123 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1124 0x0000, 0x0, root_bus_limit, 1125 0x0000, root_bus_limit + 1)); 1126 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1127 1128 aml_append(crs, 1129 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1130 AML_POS_DECODE, AML_ENTIRE_RANGE, 1131 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1132 1133 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1134 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1135 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1136 aml_append(crs, 1137 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1138 AML_POS_DECODE, AML_ENTIRE_RANGE, 1139 0x0000, entry->base, entry->limit, 1140 0x0000, entry->limit - entry->base + 1)); 1141 } 1142 1143 aml_append(crs, 1144 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1145 AML_CACHEABLE, AML_READ_WRITE, 1146 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1147 1148 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1149 range_lob(pci_hole), 1150 range_upb(pci_hole)); 1151 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1152 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1153 aml_append(crs, 1154 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1155 AML_NON_CACHEABLE, AML_READ_WRITE, 1156 0, entry->base, entry->limit, 1157 0, entry->limit - entry->base + 1)); 1158 } 1159 1160 if (!range_is_empty(pci_hole64)) { 1161 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1162 range_lob(pci_hole64), 1163 range_upb(pci_hole64)); 1164 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1165 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1166 aml_append(crs, 1167 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1168 AML_MAX_FIXED, 1169 AML_CACHEABLE, AML_READ_WRITE, 1170 0, entry->base, entry->limit, 1171 0, entry->limit - entry->base + 1)); 1172 } 1173 } 1174 1175 #ifdef CONFIG_TPM 1176 if (TPM_IS_TIS_ISA(tpm_find())) { 1177 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1178 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1179 } 1180 #endif 1181 aml_append(scope, aml_name_decl("_CRS", crs)); 1182 1183 /* reserve GPE0 block resources */ 1184 dev = aml_device("GPE0"); 1185 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1186 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1187 /* device present, functioning, decoding, not shown in UI */ 1188 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1189 crs = aml_resource_template(); 1190 aml_append(crs, 1191 aml_io( 1192 AML_DECODE16, 1193 pm->fadt.gpe0_blk.address, 1194 pm->fadt.gpe0_blk.address, 1195 1, 1196 pm->fadt.gpe0_blk.bit_width / 8) 1197 ); 1198 aml_append(dev, aml_name_decl("_CRS", crs)); 1199 aml_append(scope, dev); 1200 1201 crs_range_set_free(&crs_range_set); 1202 1203 /* reserve PCIHP resources */ 1204 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1205 build_append_pcihp_resources(scope, 1206 pm->pcihp_io_base, pm->pcihp_io_len); 1207 } 1208 aml_append(dsdt, scope); 1209 1210 /* create S3_ / S4_ / S5_ packages if necessary */ 1211 scope = aml_scope("\\"); 1212 if (!pm->s3_disabled) { 1213 pkg = aml_package(4); 1214 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1215 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1216 aml_append(pkg, aml_int(0)); /* reserved */ 1217 aml_append(pkg, aml_int(0)); /* reserved */ 1218 aml_append(scope, aml_name_decl("_S3", pkg)); 1219 } 1220 1221 if (!pm->s4_disabled) { 1222 pkg = aml_package(4); 1223 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1224 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1225 aml_append(pkg, aml_int(pm->s4_val)); 1226 aml_append(pkg, aml_int(0)); /* reserved */ 1227 aml_append(pkg, aml_int(0)); /* reserved */ 1228 aml_append(scope, aml_name_decl("_S4", pkg)); 1229 } 1230 1231 pkg = aml_package(4); 1232 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1233 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1234 aml_append(pkg, aml_int(0)); /* reserved */ 1235 aml_append(pkg, aml_int(0)); /* reserved */ 1236 aml_append(scope, aml_name_decl("_S5", pkg)); 1237 aml_append(dsdt, scope); 1238 1239 /* create fw_cfg node, unconditionally */ 1240 { 1241 scope = aml_scope("\\_SB.PCI0"); 1242 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1243 aml_append(dsdt, scope); 1244 } 1245 1246 sb_scope = aml_scope("\\_SB"); 1247 { 1248 Object *pci_host = acpi_get_i386_pci_host(); 1249 1250 if (pci_host) { 1251 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; 1252 Aml *ascope = aml_scope("PCI0"); 1253 /* Scan all PCI buses. Generate tables to support hotplug. */ 1254 build_append_pci_bus_devices(ascope, pbus); 1255 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) { 1256 build_append_pcihp_slots(ascope, pbus); 1257 } 1258 aml_append(sb_scope, ascope); 1259 } 1260 } 1261 1262 #ifdef CONFIG_TPM 1263 if (TPM_IS_CRB(tpm)) { 1264 dev = aml_device("TPM"); 1265 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1266 aml_append(dev, aml_name_decl("_STR", 1267 aml_string("TPM 2.0 Device"))); 1268 crs = aml_resource_template(); 1269 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1270 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1271 aml_append(dev, aml_name_decl("_CRS", crs)); 1272 1273 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1274 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1275 1276 tpm_build_ppi_acpi(tpm, dev); 1277 1278 aml_append(sb_scope, dev); 1279 } 1280 #endif 1281 1282 if (pcms->sgx_epc.size != 0) { 1283 uint64_t epc_base = pcms->sgx_epc.base; 1284 uint64_t epc_size = pcms->sgx_epc.size; 1285 1286 dev = aml_device("EPC"); 1287 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1288 aml_append(dev, aml_name_decl("_STR", 1289 aml_unicode("Enclave Page Cache 1.0"))); 1290 crs = aml_resource_template(); 1291 aml_append(crs, 1292 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1293 AML_MAX_FIXED, AML_NON_CACHEABLE, 1294 AML_READ_WRITE, 0, epc_base, 1295 epc_base + epc_size - 1, 0, epc_size)); 1296 aml_append(dev, aml_name_decl("_CRS", crs)); 1297 1298 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1299 aml_append(method, aml_return(aml_int(0x0f))); 1300 aml_append(dev, method); 1301 1302 aml_append(sb_scope, dev); 1303 } 1304 aml_append(dsdt, sb_scope); 1305 1306 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1307 bool has_pcnt; 1308 1309 Object *pci_host = acpi_get_i386_pci_host(); 1310 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; 1311 1312 scope = aml_scope("\\_SB.PCI0"); 1313 has_pcnt = build_append_notification_callback(scope, b); 1314 if (has_pcnt) { 1315 aml_append(dsdt, scope); 1316 } 1317 1318 scope = aml_scope("_GPE"); 1319 { 1320 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1321 if (has_pcnt) { 1322 aml_append(method, 1323 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1324 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1325 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1326 } 1327 aml_append(scope, method); 1328 } 1329 aml_append(dsdt, scope); 1330 } 1331 1332 /* copy AML table into ACPI tables blob and patch header there */ 1333 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1334 acpi_table_end(linker, &table); 1335 free_aml_allocator(); 1336 } 1337 1338 /* 1339 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1340 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1341 */ 1342 static void 1343 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1344 const char *oem_table_id) 1345 { 1346 AcpiTable table = { .sig = "HPET", .rev = 1, 1347 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1348 1349 acpi_table_begin(&table, table_data); 1350 /* Note timer_block_id value must be kept in sync with value advertised by 1351 * emulated hpet 1352 */ 1353 /* Event Timer Block ID */ 1354 build_append_int_noprefix(table_data, 0x8086a201, 4); 1355 /* BASE_ADDRESS */ 1356 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1357 /* HPET Number */ 1358 build_append_int_noprefix(table_data, 0, 1); 1359 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1360 build_append_int_noprefix(table_data, 0, 2); 1361 /* Page Protection And OEM Attribute */ 1362 build_append_int_noprefix(table_data, 0, 1); 1363 acpi_table_end(linker, &table); 1364 } 1365 1366 #ifdef CONFIG_TPM 1367 /* 1368 * TCPA Description Table 1369 * 1370 * Following Level 00, Rev 00.37 of specs: 1371 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1372 * 7.1.2 ACPI Table Layout 1373 */ 1374 static void 1375 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1376 const char *oem_id, const char *oem_table_id) 1377 { 1378 unsigned log_addr_offset; 1379 AcpiTable table = { .sig = "TCPA", .rev = 2, 1380 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1381 1382 acpi_table_begin(&table, table_data); 1383 /* Platform Class */ 1384 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1385 /* Log Area Minimum Length (LAML) */ 1386 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1387 /* Log Area Start Address (LASA) */ 1388 log_addr_offset = table_data->len; 1389 build_append_int_noprefix(table_data, 0, 8); 1390 1391 /* allocate/reserve space for TPM log area */ 1392 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1393 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1394 false /* high memory */); 1395 /* log area start address to be filled by Guest linker */ 1396 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1397 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1398 1399 acpi_table_end(linker, &table); 1400 } 1401 #endif 1402 1403 #define HOLE_640K_START (640 * KiB) 1404 #define HOLE_640K_END (1 * MiB) 1405 1406 /* 1407 * ACPI spec, Revision 3.0 1408 * 5.2.15 System Resource Affinity Table (SRAT) 1409 */ 1410 static void 1411 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1412 { 1413 int i; 1414 int numa_mem_start, slots; 1415 uint64_t mem_len, mem_base, next_base; 1416 MachineClass *mc = MACHINE_GET_CLASS(machine); 1417 X86MachineState *x86ms = X86_MACHINE(machine); 1418 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1419 int nb_numa_nodes = machine->numa_state->num_nodes; 1420 NodeInfo *numa_info = machine->numa_state->nodes; 1421 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1422 .oem_table_id = x86ms->oem_table_id }; 1423 1424 acpi_table_begin(&table, table_data); 1425 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1426 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1427 1428 for (i = 0; i < apic_ids->len; i++) { 1429 int node_id = apic_ids->cpus[i].props.node_id; 1430 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1431 1432 if (apic_id < 255) { 1433 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1434 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1435 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1436 /* Proximity Domain [7:0] */ 1437 build_append_int_noprefix(table_data, node_id, 1); 1438 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1439 /* Flags, Table 5-36 */ 1440 build_append_int_noprefix(table_data, 1, 4); 1441 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1442 /* Proximity Domain [31:8] */ 1443 build_append_int_noprefix(table_data, 0, 3); 1444 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1445 } else { 1446 /* 1447 * ACPI spec, Revision 4.0 1448 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1449 */ 1450 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1451 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1452 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1453 /* Proximity Domain */ 1454 build_append_int_noprefix(table_data, node_id, 4); 1455 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1456 /* Flags, Table 5-39 */ 1457 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1458 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1459 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1460 } 1461 } 1462 1463 /* the memory map is a bit tricky, it contains at least one hole 1464 * from 640k-1M and possibly another one from 3.5G-4G. 1465 */ 1466 next_base = 0; 1467 numa_mem_start = table_data->len; 1468 1469 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1470 mem_base = next_base; 1471 mem_len = numa_info[i - 1].node_mem; 1472 next_base = mem_base + mem_len; 1473 1474 /* Cut out the 640K hole */ 1475 if (mem_base <= HOLE_640K_START && 1476 next_base > HOLE_640K_START) { 1477 mem_len -= next_base - HOLE_640K_START; 1478 if (mem_len > 0) { 1479 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1480 MEM_AFFINITY_ENABLED); 1481 } 1482 1483 /* Check for the rare case: 640K < RAM < 1M */ 1484 if (next_base <= HOLE_640K_END) { 1485 next_base = HOLE_640K_END; 1486 continue; 1487 } 1488 mem_base = HOLE_640K_END; 1489 mem_len = next_base - HOLE_640K_END; 1490 } 1491 1492 /* Cut out the ACPI_PCI hole */ 1493 if (mem_base <= x86ms->below_4g_mem_size && 1494 next_base > x86ms->below_4g_mem_size) { 1495 mem_len -= next_base - x86ms->below_4g_mem_size; 1496 if (mem_len > 0) { 1497 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1498 MEM_AFFINITY_ENABLED); 1499 } 1500 mem_base = x86ms->above_4g_mem_start; 1501 mem_len = next_base - x86ms->below_4g_mem_size; 1502 next_base = mem_base + mem_len; 1503 } 1504 1505 if (mem_len > 0) { 1506 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1507 MEM_AFFINITY_ENABLED); 1508 } 1509 } 1510 1511 if (machine->nvdimms_state->is_enabled) { 1512 nvdimm_build_srat(table_data); 1513 } 1514 1515 sgx_epc_build_srat(table_data); 1516 1517 /* 1518 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1519 * without these entries. But I recall there were issues the last time I 1520 * tried to remove it with some ancient guest OS, however I can't remember 1521 * what that was so keep this around for now 1522 */ 1523 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1524 for (; slots < nb_numa_nodes + 2; slots++) { 1525 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1526 } 1527 1528 build_srat_generic_affinity_structures(table_data); 1529 1530 /* 1531 * Entry is required for Windows to enable memory hotplug in OS 1532 * and for Linux to enable SWIOTLB when booted with less than 1533 * 4G of RAM. Windows works better if the entry sets proximity 1534 * to the highest NUMA node in the machine. 1535 * Memory devices may override proximity set by this entry, 1536 * providing _PXM method if necessary. 1537 */ 1538 if (machine->device_memory) { 1539 build_srat_memory(table_data, machine->device_memory->base, 1540 memory_region_size(&machine->device_memory->mr), 1541 nb_numa_nodes - 1, 1542 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1543 } 1544 1545 acpi_table_end(linker, &table); 1546 } 1547 1548 /* 1549 * Insert DMAR scope for PCI bridges and endpoint devices 1550 */ 1551 static void 1552 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1553 { 1554 const size_t device_scope_size = 6 /* device scope structure */ + 1555 2 /* 1 path entry */; 1556 GArray *scope_blob = opaque; 1557 1558 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1559 /* Dmar Scope Type: 0x02 for PCI Bridge */ 1560 build_append_int_noprefix(scope_blob, 0x02, 1); 1561 } else { 1562 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 1563 build_append_int_noprefix(scope_blob, 0x01, 1); 1564 } 1565 1566 /* length */ 1567 build_append_int_noprefix(scope_blob, device_scope_size, 1); 1568 /* reserved */ 1569 build_append_int_noprefix(scope_blob, 0, 2); 1570 /* enumeration_id */ 1571 build_append_int_noprefix(scope_blob, 0, 1); 1572 /* bus */ 1573 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 1574 /* device */ 1575 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 1576 /* function */ 1577 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 1578 } 1579 1580 /* For a given PCI host bridge, walk and insert DMAR scope */ 1581 static int 1582 dmar_host_bridges(Object *obj, void *opaque) 1583 { 1584 GArray *scope_blob = opaque; 1585 1586 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1587 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 1588 1589 if (bus && !pci_bus_bypass_iommu(bus)) { 1590 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 1591 } 1592 } 1593 1594 return 0; 1595 } 1596 1597 /* 1598 * Intel ® Virtualization Technology for Directed I/O 1599 * Architecture Specification. Revision 3.3 1600 * 8.1 DMA Remapping Reporting Structure 1601 */ 1602 static void 1603 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1604 const char *oem_table_id) 1605 { 1606 uint8_t dmar_flags = 0; 1607 uint8_t rsvd10[10] = {}; 1608 /* Root complex IOAPIC uses one path only */ 1609 const size_t ioapic_scope_size = 6 /* device scope structure */ + 1610 2 /* 1 path entry */; 1611 X86IOMMUState *iommu = x86_iommu_get_default(); 1612 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1613 GArray *scope_blob = g_array_new(false, true, 1); 1614 1615 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 1616 .oem_table_id = oem_table_id }; 1617 1618 /* 1619 * A PCI bus walk, for each PCI host bridge. 1620 * Insert scope for each PCI bridge and endpoint device which 1621 * is attached to a bus with iommu enabled. 1622 */ 1623 object_child_foreach_recursive(object_get_root(), 1624 dmar_host_bridges, scope_blob); 1625 1626 assert(iommu); 1627 if (x86_iommu_ir_supported(iommu)) { 1628 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 1629 } 1630 1631 acpi_table_begin(&table, table_data); 1632 /* Host Address Width */ 1633 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 1634 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 1635 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 1636 1637 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 1638 build_append_int_noprefix(table_data, 0, 2); /* Type */ 1639 /* Length */ 1640 build_append_int_noprefix(table_data, 1641 16 + ioapic_scope_size + scope_blob->len, 2); 1642 /* Flags */ 1643 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 1644 1); 1645 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 1646 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 1647 /* Register Base Address */ 1648 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 1649 1650 /* Scope definition for the root-complex IOAPIC. See VT-d spec 1651 * 8.3.1 (version Oct. 2014 or later). */ 1652 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 1653 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 1654 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1655 /* Enumeration ID */ 1656 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 1657 /* Start Bus Number */ 1658 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 1659 /* Path, {Device, Function} pair */ 1660 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 1661 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 1662 1663 /* Add scope found above */ 1664 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 1665 g_array_free(scope_blob, true); 1666 1667 if (iommu->dt_supported) { 1668 /* 8.5 Root Port ATS Capability Reporting Structure */ 1669 build_append_int_noprefix(table_data, 2, 2); /* Type */ 1670 build_append_int_noprefix(table_data, 8, 2); /* Length */ 1671 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 1672 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 1673 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 1674 } 1675 1676 acpi_table_end(linker, &table); 1677 } 1678 1679 /* 1680 * Windows ACPI Emulated Devices Table 1681 * (Version 1.0 - April 6, 2009) 1682 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 1683 * 1684 * Helpful to speedup Windows guests and ignored by others. 1685 */ 1686 static void 1687 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1688 const char *oem_table_id) 1689 { 1690 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 1691 .oem_table_id = oem_table_id }; 1692 1693 acpi_table_begin(&table, table_data); 1694 /* 1695 * Set "ACPI PM timer good" flag. 1696 * 1697 * Tells Windows guests that our ACPI PM timer is reliable in the 1698 * sense that guest can read it only once to obtain a reliable value. 1699 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 1700 */ 1701 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 1702 acpi_table_end(linker, &table); 1703 } 1704 1705 /* 1706 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 1707 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 1708 */ 1709 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 1710 1711 /* 1712 * Insert IVHD entry for device and recurse, insert alias, or insert range as 1713 * necessary for the PCI topology. 1714 */ 1715 static void 1716 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 1717 { 1718 GArray *table_data = opaque; 1719 uint32_t entry; 1720 1721 /* "Select" IVHD entry, type 0x2 */ 1722 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 1723 build_append_int_noprefix(table_data, entry, 4); 1724 1725 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1726 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1727 uint8_t sec = pci_bus_num(sec_bus); 1728 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 1729 1730 if (pci_bus_is_express(sec_bus)) { 1731 /* 1732 * Walk the bus if there are subordinates, otherwise use a range 1733 * to cover an entire leaf bus. We could potentially also use a 1734 * range for traversed buses, but we'd need to take care not to 1735 * create both Select and Range entries covering the same device. 1736 * This is easier and potentially more compact. 1737 * 1738 * An example bare metal system seems to use Select entries for 1739 * root ports without a slot (ie. built-ins) and Range entries 1740 * when there is a slot. The same system also only hard-codes 1741 * the alias range for an onboard PCIe-to-PCI bridge, apparently 1742 * making no effort to support nested bridges. We attempt to 1743 * be more thorough here. 1744 */ 1745 if (sec == sub) { /* leaf bus */ 1746 /* "Start of Range" IVHD entry, type 0x3 */ 1747 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 1748 build_append_int_noprefix(table_data, entry, 4); 1749 /* "End of Range" IVHD entry, type 0x4 */ 1750 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 1751 build_append_int_noprefix(table_data, entry, 4); 1752 } else { 1753 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 1754 } 1755 } else { 1756 /* 1757 * If the secondary bus is conventional, then we need to create an 1758 * Alias range for everything downstream. The range covers the 1759 * first devfn on the secondary bus to the last devfn on the 1760 * subordinate bus. The alias target depends on legacy versus 1761 * express bridges, just as in pci_device_iommu_address_space(). 1762 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 1763 */ 1764 uint16_t dev_id_a, dev_id_b; 1765 1766 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 1767 1768 if (pci_is_express(dev) && 1769 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 1770 dev_id_b = dev_id_a; 1771 } else { 1772 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 1773 } 1774 1775 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 1776 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 1777 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 1778 1779 /* "End of Range" IVHD entry, type 0x4 */ 1780 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 1781 build_append_int_noprefix(table_data, entry, 4); 1782 } 1783 } 1784 } 1785 1786 /* For all PCI host bridges, walk and insert IVHD entries */ 1787 static int 1788 ivrs_host_bridges(Object *obj, void *opaque) 1789 { 1790 GArray *ivhd_blob = opaque; 1791 1792 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1793 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 1794 1795 if (bus && !pci_bus_bypass_iommu(bus)) { 1796 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 1797 } 1798 } 1799 1800 return 0; 1801 } 1802 1803 static void 1804 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1805 const char *oem_table_id) 1806 { 1807 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 1808 GArray *ivhd_blob = g_array_new(false, true, 1); 1809 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 1810 .oem_table_id = oem_table_id }; 1811 uint64_t feature_report; 1812 1813 acpi_table_begin(&table, table_data); 1814 /* IVinfo - IO virtualization information common to all 1815 * IOMMU units in a system 1816 */ 1817 build_append_int_noprefix(table_data, 1818 (1UL << 0) | /* EFRSup */ 1819 (40UL << 8), /* PASize */ 1820 4); 1821 /* reserved */ 1822 build_append_int_noprefix(table_data, 0, 8); 1823 1824 /* 1825 * A PCI bus walk, for each PCI host bridge, is necessary to create a 1826 * complete set of IVHD entries. Do this into a separate blob so that we 1827 * can calculate the total IVRS table length here and then append the new 1828 * blob further below. Fall back to an entry covering all devices, which 1829 * is sufficient when no aliases are present. 1830 */ 1831 object_child_foreach_recursive(object_get_root(), 1832 ivrs_host_bridges, ivhd_blob); 1833 1834 if (!ivhd_blob->len) { 1835 /* 1836 * Type 1 device entry reporting all devices 1837 * These are 4-byte device entries currently reporting the range of 1838 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 1839 */ 1840 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 1841 } 1842 1843 /* 1844 * When interrupt remapping is supported, we add a special IVHD device 1845 * for type IO-APIC 1846 * Refer to spec - Table 95: IVHD device entry type codes 1847 * 1848 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 1849 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 1850 */ 1851 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 1852 build_append_int_noprefix(ivhd_blob, 1853 (0x1ull << 56) | /* type IOAPIC */ 1854 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 1855 0x48, /* special device */ 1856 8); 1857 } 1858 1859 /* IVHD definition - type 10h */ 1860 build_append_int_noprefix(table_data, 0x10, 1); 1861 /* virtualization flags */ 1862 build_append_int_noprefix(table_data, 1863 (1UL << 0) | /* HtTunEn */ 1864 (1UL << 4) | /* iotblSup */ 1865 (1UL << 6) | /* PrefSup */ 1866 (1UL << 7), /* PPRSup */ 1867 1); 1868 1869 /* IVHD length */ 1870 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); 1871 /* DeviceID */ 1872 build_append_int_noprefix(table_data, 1873 object_property_get_int(OBJECT(s->pci), "addr", 1874 &error_abort), 2); 1875 /* Capability offset */ 1876 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); 1877 /* IOMMU base address */ 1878 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 1879 /* PCI Segment Group */ 1880 build_append_int_noprefix(table_data, 0, 2); 1881 /* IOMMU info */ 1882 build_append_int_noprefix(table_data, 0, 2); 1883 /* IOMMU Feature Reporting */ 1884 feature_report = (48UL << 30) | /* HATS */ 1885 (48UL << 28) | /* GATS */ 1886 (1UL << 2) | /* GTSup */ 1887 (1UL << 6); /* GASup */ 1888 if (s->xtsup) { 1889 feature_report |= (1UL << 0); /* XTSup */ 1890 } 1891 build_append_int_noprefix(table_data, feature_report, 4); 1892 1893 /* IVHD entries as found above */ 1894 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 1895 1896 /* IVHD definition - type 11h */ 1897 build_append_int_noprefix(table_data, 0x11, 1); 1898 /* virtualization flags */ 1899 build_append_int_noprefix(table_data, 1900 (1UL << 0) | /* HtTunEn */ 1901 (1UL << 4), /* iotblSup */ 1902 1); 1903 1904 /* IVHD length */ 1905 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); 1906 /* DeviceID */ 1907 build_append_int_noprefix(table_data, 1908 object_property_get_int(OBJECT(s->pci), "addr", 1909 &error_abort), 2); 1910 /* Capability offset */ 1911 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); 1912 /* IOMMU base address */ 1913 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 1914 /* PCI Segment Group */ 1915 build_append_int_noprefix(table_data, 0, 2); 1916 /* IOMMU info */ 1917 build_append_int_noprefix(table_data, 0, 2); 1918 /* IOMMU Attributes */ 1919 build_append_int_noprefix(table_data, 0, 4); 1920 /* EFR Register Image */ 1921 build_append_int_noprefix(table_data, 1922 amdvi_extended_feature_register(s), 1923 8); 1924 /* EFR Register Image 2 */ 1925 build_append_int_noprefix(table_data, 0, 8); 1926 1927 /* IVHD entries as found above */ 1928 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 1929 1930 g_array_free(ivhd_blob, TRUE); 1931 acpi_table_end(linker, &table); 1932 } 1933 1934 typedef 1935 struct AcpiBuildState { 1936 /* Copy of table in RAM (for patching). */ 1937 MemoryRegion *table_mr; 1938 /* Is table patched? */ 1939 uint8_t patched; 1940 MemoryRegion *rsdp_mr; 1941 MemoryRegion *linker_mr; 1942 } AcpiBuildState; 1943 1944 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1945 { 1946 Object *pci_host; 1947 QObject *o; 1948 1949 pci_host = acpi_get_i386_pci_host(); 1950 if (!pci_host) { 1951 return false; 1952 } 1953 1954 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1955 if (!o) { 1956 return false; 1957 } 1958 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 1959 qobject_unref(o); 1960 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 1961 return false; 1962 } 1963 1964 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1965 assert(o); 1966 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 1967 qobject_unref(o); 1968 return true; 1969 } 1970 1971 static 1972 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 1973 { 1974 PCMachineState *pcms = PC_MACHINE(machine); 1975 X86MachineState *x86ms = X86_MACHINE(machine); 1976 DeviceState *iommu = pcms->iommu; 1977 GArray *table_offsets; 1978 unsigned facs, dsdt, rsdt; 1979 AcpiPmInfo pm; 1980 AcpiMiscInfo misc; 1981 AcpiMcfgInfo mcfg; 1982 Range pci_hole = {}, pci_hole64 = {}; 1983 uint8_t *u; 1984 GArray *tables_blob = tables->table_data; 1985 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 1986 Object *vmgenid_dev, *vmclock_dev; 1987 char *oem_id; 1988 char *oem_table_id; 1989 1990 acpi_get_pm_info(machine, &pm); 1991 acpi_get_misc_info(&misc); 1992 acpi_get_pci_holes(&pci_hole, &pci_hole64); 1993 acpi_get_slic_oem(&slic_oem); 1994 1995 if (slic_oem.id) { 1996 oem_id = slic_oem.id; 1997 } else { 1998 oem_id = x86ms->oem_id; 1999 } 2000 2001 if (slic_oem.table_id) { 2002 oem_table_id = slic_oem.table_id; 2003 } else { 2004 oem_table_id = x86ms->oem_table_id; 2005 } 2006 2007 table_offsets = g_array_new(false, true /* clear */, 2008 sizeof(uint32_t)); 2009 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2010 2011 bios_linker_loader_alloc(tables->linker, 2012 ACPI_BUILD_TABLE_FILE, tables_blob, 2013 64 /* Ensure FACS is aligned */, 2014 false /* high memory */); 2015 2016 /* 2017 * FACS is pointed to by FADT. 2018 * We place it first since it's the only table that has alignment 2019 * requirements. 2020 */ 2021 facs = tables_blob->len; 2022 build_facs(tables_blob); 2023 2024 /* DSDT is pointed to by FADT */ 2025 dsdt = tables_blob->len; 2026 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2027 &pci_hole, &pci_hole64, machine); 2028 2029 /* ACPI tables pointed to by RSDT */ 2030 acpi_add_table(table_offsets, tables_blob); 2031 pm.fadt.facs_tbl_offset = &facs; 2032 pm.fadt.dsdt_tbl_offset = &dsdt; 2033 pm.fadt.xdsdt_tbl_offset = &dsdt; 2034 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2035 2036 acpi_add_table(table_offsets, tables_blob); 2037 acpi_build_madt(tables_blob, tables->linker, x86ms, 2038 x86ms->oem_id, x86ms->oem_table_id); 2039 2040 #ifdef CONFIG_ACPI_ERST 2041 { 2042 Object *erst_dev; 2043 erst_dev = find_erst_dev(); 2044 if (erst_dev) { 2045 acpi_add_table(table_offsets, tables_blob); 2046 build_erst(tables_blob, tables->linker, erst_dev, 2047 x86ms->oem_id, x86ms->oem_table_id); 2048 } 2049 } 2050 #endif 2051 2052 vmgenid_dev = find_vmgenid_dev(); 2053 if (vmgenid_dev) { 2054 acpi_add_table(table_offsets, tables_blob); 2055 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2056 tables->vmgenid, tables->linker, x86ms->oem_id); 2057 } 2058 2059 vmclock_dev = find_vmclock_dev(); 2060 if (vmclock_dev) { 2061 acpi_add_table(table_offsets, tables_blob); 2062 vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker, 2063 x86ms->oem_id); 2064 } 2065 2066 if (misc.has_hpet) { 2067 acpi_add_table(table_offsets, tables_blob); 2068 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2069 x86ms->oem_table_id); 2070 } 2071 #ifdef CONFIG_TPM 2072 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2073 if (misc.tpm_version == TPM_VERSION_1_2) { 2074 acpi_add_table(table_offsets, tables_blob); 2075 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2076 x86ms->oem_id, x86ms->oem_table_id); 2077 } else { /* TPM_VERSION_2_0 */ 2078 acpi_add_table(table_offsets, tables_blob); 2079 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2080 x86ms->oem_id, x86ms->oem_table_id); 2081 } 2082 } 2083 #endif 2084 if (machine->numa_state->num_nodes) { 2085 acpi_add_table(table_offsets, tables_blob); 2086 build_srat(tables_blob, tables->linker, machine); 2087 if (machine->numa_state->have_numa_distance) { 2088 acpi_add_table(table_offsets, tables_blob); 2089 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2090 x86ms->oem_table_id); 2091 } 2092 if (machine->numa_state->hmat_enabled) { 2093 acpi_add_table(table_offsets, tables_blob); 2094 build_hmat(tables_blob, tables->linker, machine->numa_state, 2095 x86ms->oem_id, x86ms->oem_table_id); 2096 } 2097 } 2098 if (acpi_get_mcfg(&mcfg)) { 2099 acpi_add_table(table_offsets, tables_blob); 2100 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2101 x86ms->oem_table_id); 2102 } 2103 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2104 acpi_add_table(table_offsets, tables_blob); 2105 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2106 x86ms->oem_table_id); 2107 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2108 acpi_add_table(table_offsets, tables_blob); 2109 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2110 x86ms->oem_table_id); 2111 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2112 PCIDevice *pdev = PCI_DEVICE(iommu); 2113 2114 acpi_add_table(table_offsets, tables_blob); 2115 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2116 x86ms->oem_id, x86ms->oem_table_id); 2117 } 2118 if (machine->nvdimms_state->is_enabled) { 2119 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2120 machine->nvdimms_state, machine->ram_slots, 2121 x86ms->oem_id, x86ms->oem_table_id); 2122 } 2123 if (pcms->cxl_devices_state.is_enabled) { 2124 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2125 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2126 } 2127 2128 acpi_add_table(table_offsets, tables_blob); 2129 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2130 2131 /* Add tables supplied by user (if any) */ 2132 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2133 unsigned len = acpi_table_len(u); 2134 2135 acpi_add_table(table_offsets, tables_blob); 2136 g_array_append_vals(tables_blob, u, len); 2137 } 2138 2139 /* RSDT is pointed to by RSDP */ 2140 rsdt = tables_blob->len; 2141 build_rsdt(tables_blob, tables->linker, table_offsets, 2142 oem_id, oem_table_id); 2143 2144 /* RSDP is in FSEG memory, so allocate it separately */ 2145 { 2146 AcpiRsdpData rsdp_data = { 2147 .revision = 0, 2148 .oem_id = x86ms->oem_id, 2149 .xsdt_tbl_offset = NULL, 2150 .rsdt_tbl_offset = &rsdt, 2151 }; 2152 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2153 } 2154 2155 /* We'll expose it all to Guest so we want to reduce 2156 * chance of size changes. 2157 * 2158 * We used to align the tables to 4k, but of course this would 2159 * too simple to be enough. 4k turned out to be too small an 2160 * alignment very soon, and in fact it is almost impossible to 2161 * keep the table size stable for all (max_cpus, max_memory_slots) 2162 * combinations. 2163 */ 2164 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2165 2166 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2167 2168 /* Cleanup memory that's no longer used. */ 2169 g_array_free(table_offsets, true); 2170 g_free(slic_oem.id); 2171 g_free(slic_oem.table_id); 2172 } 2173 2174 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2175 { 2176 uint32_t size = acpi_data_len(data); 2177 2178 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2179 memory_region_ram_resize(mr, size, &error_abort); 2180 2181 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2182 memory_region_set_dirty(mr, 0, size); 2183 } 2184 2185 static void acpi_build_update(void *build_opaque) 2186 { 2187 AcpiBuildState *build_state = build_opaque; 2188 AcpiBuildTables tables; 2189 2190 /* No state to update or already patched? Nothing to do. */ 2191 if (!build_state || build_state->patched) { 2192 return; 2193 } 2194 build_state->patched = 1; 2195 2196 acpi_build_tables_init(&tables); 2197 2198 acpi_build(&tables, MACHINE(qdev_get_machine())); 2199 2200 acpi_ram_update(build_state->table_mr, tables.table_data); 2201 2202 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2203 2204 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2205 acpi_build_tables_cleanup(&tables, true); 2206 } 2207 2208 static void acpi_build_reset(void *build_opaque) 2209 { 2210 AcpiBuildState *build_state = build_opaque; 2211 build_state->patched = 0; 2212 } 2213 2214 static const VMStateDescription vmstate_acpi_build = { 2215 .name = "acpi_build", 2216 .version_id = 1, 2217 .minimum_version_id = 1, 2218 .fields = (const VMStateField[]) { 2219 VMSTATE_UINT8(patched, AcpiBuildState), 2220 VMSTATE_END_OF_LIST() 2221 }, 2222 }; 2223 2224 void acpi_setup(void) 2225 { 2226 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2227 X86MachineState *x86ms = X86_MACHINE(pcms); 2228 AcpiBuildTables tables; 2229 AcpiBuildState *build_state; 2230 Object *vmgenid_dev; 2231 #ifdef CONFIG_TPM 2232 TPMIf *tpm; 2233 static FwCfgTPMConfig tpm_config; 2234 #endif 2235 2236 if (!x86ms->fw_cfg) { 2237 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2238 return; 2239 } 2240 2241 if (!pcms->acpi_build_enabled) { 2242 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2243 return; 2244 } 2245 2246 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2247 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2248 return; 2249 } 2250 2251 build_state = g_malloc0(sizeof *build_state); 2252 2253 acpi_build_tables_init(&tables); 2254 acpi_build(&tables, MACHINE(pcms)); 2255 2256 /* Now expose it all to Guest */ 2257 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2258 build_state, tables.table_data, 2259 ACPI_BUILD_TABLE_FILE); 2260 assert(build_state->table_mr != NULL); 2261 2262 build_state->linker_mr = 2263 acpi_add_rom_blob(acpi_build_update, build_state, 2264 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2265 2266 #ifdef CONFIG_TPM 2267 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2268 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2269 2270 tpm = tpm_find(); 2271 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2272 tpm_config = (FwCfgTPMConfig) { 2273 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2274 .tpm_version = tpm_get_version(tpm), 2275 .tpmppi_version = TPM_PPI_VERSION_1_30 2276 }; 2277 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2278 &tpm_config, sizeof tpm_config); 2279 } 2280 #endif 2281 2282 vmgenid_dev = find_vmgenid_dev(); 2283 if (vmgenid_dev) { 2284 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2285 tables.vmgenid); 2286 } 2287 2288 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2289 build_state, tables.rsdp, 2290 ACPI_BUILD_RSDP_FILE); 2291 2292 qemu_register_reset(acpi_build_reset, build_state); 2293 acpi_build_reset(build_state); 2294 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2295 2296 /* Cleanup tables but don't free the memory: we track it 2297 * in build_state. 2298 */ 2299 acpi_build_tables_cleanup(&tables, false); 2300 } 2301