1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/piix.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/ich9.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 #include "hw/acpi/cxl.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool has_hpet; 117 #ifdef CONFIG_TPM 118 TPMVersion tpm_version; 119 #endif 120 const unsigned char *dsdt_code; 121 unsigned dsdt_size; 122 } AcpiMiscInfo; 123 124 typedef struct FwCfgTPMConfig { 125 uint32_t tpmppi_address; 126 uint8_t tpm_version; 127 uint8_t tpmppi_version; 128 } QEMU_PACKED FwCfgTPMConfig; 129 130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 131 132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 133 .space_id = AML_AS_SYSTEM_IO, 134 .address = NVDIMM_ACPI_IO_BASE, 135 .bit_width = NVDIMM_ACPI_IO_LEN << 3 136 }; 137 138 static void init_common_fadt_data(MachineState *ms, Object *o, 139 AcpiFadtData *data) 140 { 141 X86MachineState *x86ms = X86_MACHINE(ms); 142 /* 143 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 144 * behavior for compatibility irrelevant to smm_enabled, which doesn't 145 * comforms to ACPI spec. 146 */ 147 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 148 true : x86_machine_is_smm_enabled(x86ms); 149 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 150 AmlAddressSpace as = AML_AS_SYSTEM_IO; 151 AcpiFadtData fadt = { 152 .rev = 3, 153 .flags = 154 (1 << ACPI_FADT_F_WBINVD) | 155 (1 << ACPI_FADT_F_PROC_C1) | 156 (1 << ACPI_FADT_F_SLP_BUTTON) | 157 (1 << ACPI_FADT_F_RTC_S4) | 158 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 159 /* APIC destination mode ("Flat Logical") has an upper limit of 8 160 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 161 * used 162 */ 163 ((ms->smp.max_cpus > 8) ? 164 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 165 .int_model = 1 /* Multiple APIC */, 166 .rtc_century = RTC_CENTURY, 167 .plvl2_lat = 0xfff /* C2 state not supported */, 168 .plvl3_lat = 0xfff /* C3 state not supported */, 169 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 170 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 171 .acpi_enable_cmd = 172 smm_enabled ? 173 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 174 0, 175 .acpi_disable_cmd = 176 smm_enabled ? 177 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 178 0, 179 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 180 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 181 .address = io + 0x04 }, 182 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 183 .gpe0_blk = { .space_id = as, .bit_width = 184 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 185 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 186 }, 187 }; 188 189 /* 190 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 191 * Flags, bit offset 1 - 8042. 192 */ 193 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 194 195 *data = fadt; 196 } 197 198 static Object *object_resolve_type_unambiguous(const char *typename) 199 { 200 bool ambig; 201 Object *o = object_resolve_path_type("", typename, &ambig); 202 203 if (ambig || !o) { 204 return NULL; 205 } 206 return o; 207 } 208 209 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 210 { 211 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 212 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 213 Object *obj = piix ? piix : lpc; 214 QObject *o; 215 pm->cpu_hp_io_base = 0; 216 pm->pcihp_io_base = 0; 217 pm->pcihp_io_len = 0; 218 pm->smi_on_cpuhp = false; 219 pm->smi_on_cpu_unplug = false; 220 221 assert(obj); 222 init_common_fadt_data(machine, obj, &pm->fadt); 223 if (piix) { 224 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 225 pm->fadt.rev = 1; 226 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 227 } 228 if (lpc) { 229 uint64_t smi_features = object_property_get_uint(lpc, 230 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 231 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 232 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 233 pm->fadt.reset_reg = r; 234 pm->fadt.reset_val = 0xf; 235 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 236 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 237 pm->smi_on_cpuhp = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 239 pm->smi_on_cpu_unplug = 240 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 241 } 242 pm->pcihp_io_base = 243 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 244 pm->pcihp_io_len = 245 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 246 247 /* The above need not be conditional on machine type because the reset port 248 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 249 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 250 251 /* Fill in optional s3/s4 related properties */ 252 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 253 if (o) { 254 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 255 } else { 256 pm->s3_disabled = false; 257 } 258 qobject_unref(o); 259 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 260 if (o) { 261 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 262 } else { 263 pm->s4_disabled = false; 264 } 265 qobject_unref(o); 266 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 267 if (o) { 268 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 269 } else { 270 pm->s4_val = false; 271 } 272 qobject_unref(o); 273 274 pm->pcihp_bridge_en = 275 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 276 NULL); 277 pm->pcihp_root_en = 278 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 279 NULL); 280 } 281 282 static void acpi_get_misc_info(AcpiMiscInfo *info) 283 { 284 info->has_hpet = hpet_find(); 285 #ifdef CONFIG_TPM 286 info->tpm_version = tpm_get_version(tpm_find()); 287 #endif 288 } 289 290 /* 291 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 292 * On i386 arch we only have two pci hosts, so we can look only for them. 293 */ 294 Object *acpi_get_i386_pci_host(void) 295 { 296 PCIHostState *host; 297 298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 299 if (!host) { 300 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 301 } 302 303 return OBJECT(host); 304 } 305 306 static void acpi_get_pci_holes(Range *hole, Range *hole64) 307 { 308 Object *pci_host; 309 310 pci_host = acpi_get_i386_pci_host(); 311 312 if (!pci_host) { 313 return; 314 } 315 316 range_set_bounds1(hole, 317 object_property_get_uint(pci_host, 318 PCI_HOST_PROP_PCI_HOLE_START, 319 NULL), 320 object_property_get_uint(pci_host, 321 PCI_HOST_PROP_PCI_HOLE_END, 322 NULL)); 323 range_set_bounds1(hole64, 324 object_property_get_uint(pci_host, 325 PCI_HOST_PROP_PCI_HOLE64_START, 326 NULL), 327 object_property_get_uint(pci_host, 328 PCI_HOST_PROP_PCI_HOLE64_END, 329 NULL)); 330 } 331 332 static void acpi_align_size(GArray *blob, unsigned align) 333 { 334 /* Align size to multiple of given size. This reduces the chance 335 * we need to change size in the future (breaking cross version migration). 336 */ 337 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 338 } 339 340 /* 341 * ACPI spec 1.0b, 342 * 5.2.6 Firmware ACPI Control Structure 343 */ 344 static void 345 build_facs(GArray *table_data) 346 { 347 const char *sig = "FACS"; 348 const uint8_t reserved[40] = {}; 349 350 g_array_append_vals(table_data, sig, 4); /* Signature */ 351 build_append_int_noprefix(table_data, 64, 4); /* Length */ 352 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 353 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 354 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 355 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 356 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 357 } 358 359 Aml *aml_pci_device_dsm(void) 360 { 361 Aml *method; 362 363 method = aml_method("_DSM", 4, AML_SERIALIZED); 364 { 365 Aml *params = aml_local(0); 366 Aml *pkg = aml_package(2); 367 aml_append(pkg, aml_name("BSEL")); 368 aml_append(pkg, aml_name("ASUN")); 369 aml_append(method, aml_store(pkg, params)); 370 aml_append(method, 371 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 372 aml_arg(2), aml_arg(3), params)) 373 ); 374 } 375 return method; 376 } 377 378 static void build_append_pcihp_notify_entry(Aml *method, int slot) 379 { 380 Aml *if_ctx; 381 int32_t devfn = PCI_DEVFN(slot, 0); 382 383 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 384 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 385 aml_append(method, if_ctx); 386 } 387 388 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 389 bool pcihp_bridge_en) 390 { 391 Aml *dev, *notify_method = NULL, *method; 392 QObject *bsel; 393 PCIBus *sec; 394 int devfn; 395 396 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 397 if (bsel) { 398 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 399 400 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 401 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 402 } 403 404 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 405 DeviceClass *dc; 406 PCIDeviceClass *pc; 407 PCIDevice *pdev = bus->devices[devfn]; 408 int slot = PCI_SLOT(devfn); 409 int func = PCI_FUNC(devfn); 410 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 411 int adr = slot << 16 | func; 412 bool hotpluggbale_slot = false; 413 bool bridge_in_acpi = false; 414 bool cold_plugged_bridge = false; 415 416 if (pdev) { 417 pc = PCI_DEVICE_GET_CLASS(pdev); 418 dc = DEVICE_GET_CLASS(pdev); 419 420 /* 421 * Cold plugged bridges aren't themselves hot-pluggable. 422 * Hotplugged bridges *are* hot-pluggable. 423 */ 424 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 425 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 426 427 hotpluggbale_slot = bsel && dc->hotpluggable && 428 !cold_plugged_bridge; 429 430 /* 431 * allow describing coldplugged bridges in ACPI even if they are not 432 * on function 0, as they are not unpluggable, for all other devices 433 * generate description only for function 0 per slot, and for other 434 * functions if device on function provides its own AML 435 */ 436 if (func && !bridge_in_acpi && !get_dev_aml_func(DEVICE(pdev))) { 437 continue; 438 } 439 } else { 440 /* 441 * hotplug is supported only for non-multifunction device 442 * so generate device description only for function 0 443 */ 444 if (bsel && !func) { 445 if (pci_bus_is_express(bus) && slot > 0) { 446 break; 447 } 448 /* mark it as empty hotpluggable slot */ 449 hotpluggbale_slot = true; 450 } else { 451 continue; 452 } 453 } 454 455 /* start to compose PCI device descriptor */ 456 dev = aml_device("S%.02X", devfn); 457 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 458 459 if (bsel) { 460 /* 461 * Can't declare _SUN here for every device as it changes 'slot' 462 * enumeration order in linux kernel, so use another variable for it 463 */ 464 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 465 aml_append(dev, aml_pci_device_dsm()); 466 } 467 468 call_dev_aml_func(DEVICE(pdev), dev); 469 470 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 471 if (bridge_in_acpi) { 472 /* 473 * device is coldplugged bridge, 474 * add child device descriptions into its scope 475 */ 476 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 477 478 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 479 } 480 481 if (hotpluggbale_slot) { 482 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 483 /* add _EJ0 to make slot hotpluggable */ 484 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 485 aml_append(method, 486 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 487 ); 488 aml_append(dev, method); 489 490 build_append_pcihp_notify_entry(notify_method, slot); 491 } 492 493 /* device descriptor has been composed, add it into parent context */ 494 aml_append(parent_scope, dev); 495 } 496 497 if (bsel) { 498 aml_append(parent_scope, notify_method); 499 } 500 501 /* Append PCNT method to notify about events on local and child buses. 502 * Add this method for root bus only when hotplug is enabled since DSDT 503 * expects it. 504 */ 505 if (bsel || pcihp_bridge_en) { 506 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 507 508 /* If bus supports hotplug select it and notify about local events */ 509 if (bsel) { 510 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 511 512 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 513 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 514 aml_int(1))); /* Device Check */ 515 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 516 aml_int(3))); /* Eject Request */ 517 } 518 519 /* Notify about child bus events in any case */ 520 if (pcihp_bridge_en) { 521 QLIST_FOREACH(sec, &bus->child, sibling) { 522 if (pci_bus_is_root(sec)) { 523 continue; 524 } 525 526 aml_append(method, aml_name("^S%.02X.PCNT", 527 sec->parent_dev->devfn)); 528 } 529 } 530 531 aml_append(parent_scope, method); 532 } 533 qobject_unref(bsel); 534 } 535 536 static Aml *aml_pci_pdsm(void) 537 { 538 Aml *method, *UUID, *ifctx, *ifctx1; 539 Aml *ret = aml_local(0); 540 Aml *caps = aml_local(1); 541 Aml *acpi_index = aml_local(2); 542 Aml *zero = aml_int(0); 543 Aml *one = aml_int(1); 544 Aml *func = aml_arg(2); 545 Aml *rev = aml_arg(1); 546 Aml *params = aml_arg(4); 547 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 548 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 549 550 method = aml_method("PDSM", 5, AML_SERIALIZED); 551 552 /* get supported functions */ 553 ifctx = aml_if(aml_equal(func, zero)); 554 { 555 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 556 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); 557 aml_append(ifctx, aml_store(zero, caps)); 558 559 /* 560 * PCI Firmware Specification 3.1 561 * 4.6. _DSM Definitions for PCI 562 */ 563 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 564 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 565 { 566 /* call is for unsupported UUID, bail out */ 567 aml_append(ifctx1, aml_return(ret)); 568 } 569 aml_append(ifctx, ifctx1); 570 571 ifctx1 = aml_if(aml_lless(rev, aml_int(2))); 572 { 573 /* call is for unsupported REV, bail out */ 574 aml_append(ifctx1, aml_return(ret)); 575 } 576 aml_append(ifctx, ifctx1); 577 578 aml_append(ifctx, 579 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 580 /* 581 * advertise function 7 if device has acpi-index 582 * acpi_index values: 583 * 0: not present (default value) 584 * FFFFFFFF: not supported (old QEMU without PIDX reg) 585 * other: device's acpi-index 586 */ 587 ifctx1 = aml_if(aml_lnot( 588 aml_or(aml_equal(acpi_index, zero), 589 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 590 )); 591 { 592 /* have supported functions */ 593 aml_append(ifctx1, aml_or(caps, one, caps)); 594 /* support for function 7 */ 595 aml_append(ifctx1, 596 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 597 } 598 aml_append(ifctx, ifctx1); 599 600 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 601 aml_append(ifctx, aml_return(ret)); 602 } 603 aml_append(method, ifctx); 604 605 /* handle specific functions requests */ 606 /* 607 * PCI Firmware Specification 3.1 608 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 609 * Operating Systems 610 */ 611 ifctx = aml_if(aml_equal(func, aml_int(7))); 612 { 613 Aml *pkg = aml_package(2); 614 615 aml_append(pkg, zero); 616 /* 617 * optional, if not impl. should return null string 618 */ 619 aml_append(pkg, aml_string("%s", "")); 620 aml_append(ifctx, aml_store(pkg, ret)); 621 622 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 623 /* 624 * update acpi-index to actual value 625 */ 626 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 627 aml_append(ifctx, aml_return(ret)); 628 } 629 630 aml_append(method, ifctx); 631 return method; 632 } 633 634 /** 635 * build_prt_entry: 636 * @link_name: link name for PCI route entry 637 * 638 * build AML package containing a PCI route entry for @link_name 639 */ 640 static Aml *build_prt_entry(const char *link_name) 641 { 642 Aml *a_zero = aml_int(0); 643 Aml *pkg = aml_package(4); 644 aml_append(pkg, a_zero); 645 aml_append(pkg, a_zero); 646 aml_append(pkg, aml_name("%s", link_name)); 647 aml_append(pkg, a_zero); 648 return pkg; 649 } 650 651 /* 652 * initialize_route - Initialize the interrupt routing rule 653 * through a specific LINK: 654 * if (lnk_idx == idx) 655 * route using link 'link_name' 656 */ 657 static Aml *initialize_route(Aml *route, const char *link_name, 658 Aml *lnk_idx, int idx) 659 { 660 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 661 Aml *pkg = build_prt_entry(link_name); 662 663 aml_append(if_ctx, aml_store(pkg, route)); 664 665 return if_ctx; 666 } 667 668 /* 669 * build_prt - Define interrupt rounting rules 670 * 671 * Returns an array of 128 routes, one for each device, 672 * based on device location. 673 * The main goal is to equaly distribute the interrupts 674 * over the 4 existing ACPI links (works only for i440fx). 675 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 676 * 677 */ 678 static Aml *build_prt(bool is_pci0_prt) 679 { 680 Aml *method, *while_ctx, *pin, *res; 681 682 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 683 res = aml_local(0); 684 pin = aml_local(1); 685 aml_append(method, aml_store(aml_package(128), res)); 686 aml_append(method, aml_store(aml_int(0), pin)); 687 688 /* while (pin < 128) */ 689 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 690 { 691 Aml *slot = aml_local(2); 692 Aml *lnk_idx = aml_local(3); 693 Aml *route = aml_local(4); 694 695 /* slot = pin >> 2 */ 696 aml_append(while_ctx, 697 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 698 /* lnk_idx = (slot + pin) & 3 */ 699 aml_append(while_ctx, 700 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 701 lnk_idx)); 702 703 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 704 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 705 if (is_pci0_prt) { 706 Aml *if_device_1, *if_pin_4, *else_pin_4; 707 708 /* device 1 is the power-management device, needs SCI */ 709 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 710 { 711 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 712 { 713 aml_append(if_pin_4, 714 aml_store(build_prt_entry("LNKS"), route)); 715 } 716 aml_append(if_device_1, if_pin_4); 717 else_pin_4 = aml_else(); 718 { 719 aml_append(else_pin_4, 720 aml_store(build_prt_entry("LNKA"), route)); 721 } 722 aml_append(if_device_1, else_pin_4); 723 } 724 aml_append(while_ctx, if_device_1); 725 } else { 726 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 727 } 728 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 729 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 730 731 /* route[0] = 0x[slot]FFFF */ 732 aml_append(while_ctx, 733 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 734 NULL), 735 aml_index(route, aml_int(0)))); 736 /* route[1] = pin & 3 */ 737 aml_append(while_ctx, 738 aml_store(aml_and(pin, aml_int(3), NULL), 739 aml_index(route, aml_int(1)))); 740 /* res[pin] = route */ 741 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 742 /* pin++ */ 743 aml_append(while_ctx, aml_increment(pin)); 744 } 745 aml_append(method, while_ctx); 746 /* return res*/ 747 aml_append(method, aml_return(res)); 748 749 return method; 750 } 751 752 static void build_hpet_aml(Aml *table) 753 { 754 Aml *crs; 755 Aml *field; 756 Aml *method; 757 Aml *if_ctx; 758 Aml *scope = aml_scope("_SB"); 759 Aml *dev = aml_device("HPET"); 760 Aml *zero = aml_int(0); 761 Aml *id = aml_local(0); 762 Aml *period = aml_local(1); 763 764 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 765 aml_append(dev, aml_name_decl("_UID", zero)); 766 767 aml_append(dev, 768 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 769 HPET_LEN)); 770 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 771 aml_append(field, aml_named_field("VEND", 32)); 772 aml_append(field, aml_named_field("PRD", 32)); 773 aml_append(dev, field); 774 775 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 776 aml_append(method, aml_store(aml_name("VEND"), id)); 777 aml_append(method, aml_store(aml_name("PRD"), period)); 778 aml_append(method, aml_shiftright(id, aml_int(16), id)); 779 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 780 aml_equal(id, aml_int(0xffff)))); 781 { 782 aml_append(if_ctx, aml_return(zero)); 783 } 784 aml_append(method, if_ctx); 785 786 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 787 aml_lgreater(period, aml_int(100000000)))); 788 { 789 aml_append(if_ctx, aml_return(zero)); 790 } 791 aml_append(method, if_ctx); 792 793 aml_append(method, aml_return(aml_int(0x0F))); 794 aml_append(dev, method); 795 796 crs = aml_resource_template(); 797 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 798 aml_append(dev, aml_name_decl("_CRS", crs)); 799 800 aml_append(scope, dev); 801 aml_append(table, scope); 802 } 803 804 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 805 { 806 Aml *dev; 807 Aml *method; 808 Aml *crs; 809 810 dev = aml_device("VMBS"); 811 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 812 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 813 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 814 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 815 816 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 817 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 818 aml_name("STA"))); 819 aml_append(dev, method); 820 821 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 822 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 823 aml_name("STA"))); 824 aml_append(dev, method); 825 826 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 827 aml_append(method, aml_return(aml_name("STA"))); 828 aml_append(dev, method); 829 830 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 831 832 crs = aml_resource_template(); 833 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 834 aml_append(dev, aml_name_decl("_CRS", crs)); 835 836 return dev; 837 } 838 839 static void build_dbg_aml(Aml *table) 840 { 841 Aml *field; 842 Aml *method; 843 Aml *while_ctx; 844 Aml *scope = aml_scope("\\"); 845 Aml *buf = aml_local(0); 846 Aml *len = aml_local(1); 847 Aml *idx = aml_local(2); 848 849 aml_append(scope, 850 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 851 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 852 aml_append(field, aml_named_field("DBGB", 8)); 853 aml_append(scope, field); 854 855 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 856 857 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 858 aml_append(method, aml_to_buffer(buf, buf)); 859 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 860 aml_append(method, aml_store(aml_int(0), idx)); 861 862 while_ctx = aml_while(aml_lless(idx, len)); 863 aml_append(while_ctx, 864 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 865 aml_append(while_ctx, aml_increment(idx)); 866 aml_append(method, while_ctx); 867 868 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 869 aml_append(scope, method); 870 871 aml_append(table, scope); 872 } 873 874 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 875 { 876 Aml *dev; 877 Aml *crs; 878 Aml *method; 879 uint32_t irqs[] = {5, 10, 11}; 880 881 dev = aml_device("%s", name); 882 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 883 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 884 885 crs = aml_resource_template(); 886 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 887 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 888 aml_append(dev, aml_name_decl("_PRS", crs)); 889 890 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 891 aml_append(method, aml_return(aml_call1("IQST", reg))); 892 aml_append(dev, method); 893 894 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 895 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 896 aml_append(dev, method); 897 898 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 899 aml_append(method, aml_return(aml_call1("IQCR", reg))); 900 aml_append(dev, method); 901 902 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 903 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 904 aml_append(method, aml_store(aml_name("PRRI"), reg)); 905 aml_append(dev, method); 906 907 return dev; 908 } 909 910 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 911 { 912 Aml *dev; 913 Aml *crs; 914 Aml *method; 915 uint32_t irqs; 916 917 dev = aml_device("%s", name); 918 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 919 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 920 921 crs = aml_resource_template(); 922 irqs = gsi; 923 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 924 AML_SHARED, &irqs, 1)); 925 aml_append(dev, aml_name_decl("_PRS", crs)); 926 927 aml_append(dev, aml_name_decl("_CRS", crs)); 928 929 /* 930 * _DIS can be no-op because the interrupt cannot be disabled. 931 */ 932 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 933 aml_append(dev, method); 934 935 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 936 aml_append(dev, method); 937 938 return dev; 939 } 940 941 /* _CRS method - get current settings */ 942 static Aml *build_iqcr_method(bool is_piix4) 943 { 944 Aml *if_ctx; 945 uint32_t irqs; 946 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 947 Aml *crs = aml_resource_template(); 948 949 irqs = 0; 950 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 951 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 952 aml_append(method, aml_name_decl("PRR0", crs)); 953 954 aml_append(method, 955 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 956 957 if (is_piix4) { 958 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 959 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 960 aml_append(method, if_ctx); 961 } else { 962 aml_append(method, 963 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 964 aml_name("PRRI"))); 965 } 966 967 aml_append(method, aml_return(aml_name("PRR0"))); 968 return method; 969 } 970 971 /* _STA method - get status */ 972 static Aml *build_irq_status_method(void) 973 { 974 Aml *if_ctx; 975 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 976 977 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 978 aml_append(if_ctx, aml_return(aml_int(0x09))); 979 aml_append(method, if_ctx); 980 aml_append(method, aml_return(aml_int(0x0B))); 981 return method; 982 } 983 984 static void build_piix4_pci0_int(Aml *table) 985 { 986 Aml *dev; 987 Aml *crs; 988 Aml *method; 989 uint32_t irqs; 990 Aml *sb_scope = aml_scope("_SB"); 991 Aml *pci0_scope = aml_scope("PCI0"); 992 993 aml_append(pci0_scope, build_prt(true)); 994 aml_append(sb_scope, pci0_scope); 995 996 aml_append(sb_scope, build_irq_status_method()); 997 aml_append(sb_scope, build_iqcr_method(true)); 998 999 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1000 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1001 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1002 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1003 1004 dev = aml_device("LNKS"); 1005 { 1006 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1007 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1008 1009 crs = aml_resource_template(); 1010 irqs = 9; 1011 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1012 AML_ACTIVE_HIGH, AML_SHARED, 1013 &irqs, 1)); 1014 aml_append(dev, aml_name_decl("_PRS", crs)); 1015 1016 /* The SCI cannot be disabled and is always attached to GSI 9, 1017 * so these are no-ops. We only need this link to override the 1018 * polarity to active high and match the content of the MADT. 1019 */ 1020 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1021 aml_append(method, aml_return(aml_int(0x0b))); 1022 aml_append(dev, method); 1023 1024 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1025 aml_append(dev, method); 1026 1027 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1028 aml_append(method, aml_return(aml_name("_PRS"))); 1029 aml_append(dev, method); 1030 1031 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1032 aml_append(dev, method); 1033 } 1034 aml_append(sb_scope, dev); 1035 1036 aml_append(table, sb_scope); 1037 } 1038 1039 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1040 { 1041 int i; 1042 int head; 1043 Aml *pkg; 1044 char base = name[3] < 'E' ? 'A' : 'E'; 1045 char *s = g_strdup(name); 1046 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1047 1048 assert(strlen(s) == 4); 1049 1050 head = name[3] - base; 1051 for (i = 0; i < 4; i++) { 1052 if (head + i > 3) { 1053 head = i * -1; 1054 } 1055 s[3] = base + head + i; 1056 pkg = aml_package(4); 1057 aml_append(pkg, a_nr); 1058 aml_append(pkg, aml_int(i)); 1059 aml_append(pkg, aml_name("%s", s)); 1060 aml_append(pkg, aml_int(0)); 1061 aml_append(ctx, pkg); 1062 } 1063 g_free(s); 1064 } 1065 1066 static Aml *build_q35_routing_table(const char *str) 1067 { 1068 int i; 1069 Aml *pkg; 1070 char *name = g_strdup_printf("%s ", str); 1071 1072 pkg = aml_package(128); 1073 for (i = 0; i < 0x18; i++) { 1074 name[3] = 'E' + (i & 0x3); 1075 append_q35_prt_entry(pkg, i, name); 1076 } 1077 1078 name[3] = 'E'; 1079 append_q35_prt_entry(pkg, 0x18, name); 1080 1081 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1082 for (i = 0x0019; i < 0x1e; i++) { 1083 name[3] = 'A'; 1084 append_q35_prt_entry(pkg, i, name); 1085 } 1086 1087 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1088 name[3] = 'E'; 1089 append_q35_prt_entry(pkg, 0x1e, name); 1090 name[3] = 'A'; 1091 append_q35_prt_entry(pkg, 0x1f, name); 1092 1093 g_free(name); 1094 return pkg; 1095 } 1096 1097 static void build_q35_pci0_int(Aml *table) 1098 { 1099 Aml *method; 1100 Aml *sb_scope = aml_scope("_SB"); 1101 Aml *pci0_scope = aml_scope("PCI0"); 1102 1103 /* Zero => PIC mode, One => APIC Mode */ 1104 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1105 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1106 { 1107 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1108 } 1109 aml_append(table, method); 1110 1111 aml_append(pci0_scope, 1112 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1113 aml_append(pci0_scope, 1114 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1115 1116 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1117 { 1118 Aml *if_ctx; 1119 Aml *else_ctx; 1120 1121 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1122 section 6.2.8.1 */ 1123 /* Note: we provide the same info as the PCI routing 1124 table of the Bochs BIOS */ 1125 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1126 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1127 aml_append(method, if_ctx); 1128 else_ctx = aml_else(); 1129 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1130 aml_append(method, else_ctx); 1131 } 1132 aml_append(pci0_scope, method); 1133 aml_append(sb_scope, pci0_scope); 1134 1135 aml_append(sb_scope, build_irq_status_method()); 1136 aml_append(sb_scope, build_iqcr_method(false)); 1137 1138 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1139 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1140 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1141 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1142 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1143 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1144 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1145 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1146 1147 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1148 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1149 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1150 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1151 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1152 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1153 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1154 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1155 1156 aml_append(table, sb_scope); 1157 } 1158 1159 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1160 { 1161 Aml *dev; 1162 Aml *resource_template; 1163 1164 /* DRAM controller */ 1165 dev = aml_device("DRAC"); 1166 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1167 1168 resource_template = aml_resource_template(); 1169 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1170 aml_append(resource_template, 1171 aml_qword_memory(AML_POS_DECODE, 1172 AML_MIN_FIXED, 1173 AML_MAX_FIXED, 1174 AML_NON_CACHEABLE, 1175 AML_READ_WRITE, 1176 0x0000000000000000, 1177 mcfg->base, 1178 mcfg->base + mcfg->size - 1, 1179 0x0000000000000000, 1180 mcfg->size)); 1181 } else { 1182 aml_append(resource_template, 1183 aml_dword_memory(AML_POS_DECODE, 1184 AML_MIN_FIXED, 1185 AML_MAX_FIXED, 1186 AML_NON_CACHEABLE, 1187 AML_READ_WRITE, 1188 0x0000000000000000, 1189 mcfg->base, 1190 mcfg->base + mcfg->size - 1, 1191 0x0000000000000000, 1192 mcfg->size)); 1193 } 1194 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1195 1196 return dev; 1197 } 1198 1199 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1200 { 1201 Aml *scope; 1202 Aml *field; 1203 Aml *method; 1204 1205 scope = aml_scope("_SB.PCI0"); 1206 1207 aml_append(scope, 1208 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1209 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1210 aml_append(field, aml_named_field("PCIU", 32)); 1211 aml_append(field, aml_named_field("PCID", 32)); 1212 aml_append(scope, field); 1213 1214 aml_append(scope, 1215 aml_operation_region("SEJ", AML_SYSTEM_IO, 1216 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1217 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1218 aml_append(field, aml_named_field("B0EJ", 32)); 1219 aml_append(scope, field); 1220 1221 aml_append(scope, 1222 aml_operation_region("BNMR", AML_SYSTEM_IO, 1223 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1224 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1225 aml_append(field, aml_named_field("BNUM", 32)); 1226 aml_append(field, aml_named_field("PIDX", 32)); 1227 aml_append(scope, field); 1228 1229 aml_append(scope, aml_mutex("BLCK", 0)); 1230 1231 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1232 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1233 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1234 aml_append(method, 1235 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1236 aml_append(method, aml_release(aml_name("BLCK"))); 1237 aml_append(method, aml_return(aml_int(0))); 1238 aml_append(scope, method); 1239 1240 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1241 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1242 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1243 aml_append(method, 1244 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1245 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1246 aml_append(method, aml_release(aml_name("BLCK"))); 1247 aml_append(method, aml_return(aml_local(0))); 1248 aml_append(scope, method); 1249 1250 aml_append(scope, aml_pci_pdsm()); 1251 1252 aml_append(table, scope); 1253 } 1254 1255 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1256 { 1257 Aml *if_ctx; 1258 Aml *if_ctx2; 1259 Aml *else_ctx; 1260 Aml *method; 1261 Aml *a_cwd1 = aml_name("CDW1"); 1262 Aml *a_ctrl = aml_local(0); 1263 1264 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1265 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1266 1267 if_ctx = aml_if(aml_equal( 1268 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1269 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1270 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1271 1272 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1273 1274 /* 1275 * Always allow native PME, AER (no dependencies) 1276 * Allow SHPC (PCI bridges can have SHPC controller) 1277 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1278 */ 1279 aml_append(if_ctx, aml_and(a_ctrl, 1280 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1281 1282 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1283 /* Unknown revision */ 1284 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1285 aml_append(if_ctx, if_ctx2); 1286 1287 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1288 /* Capabilities bits were masked */ 1289 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1290 aml_append(if_ctx, if_ctx2); 1291 1292 /* Update DWORD3 in the buffer */ 1293 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1294 aml_append(method, if_ctx); 1295 1296 else_ctx = aml_else(); 1297 /* Unrecognized UUID */ 1298 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1299 aml_append(method, else_ctx); 1300 1301 aml_append(method, aml_return(aml_arg(3))); 1302 return method; 1303 } 1304 1305 static void build_acpi0017(Aml *table) 1306 { 1307 Aml *dev, *scope, *method; 1308 1309 scope = aml_scope("_SB"); 1310 dev = aml_device("CXLM"); 1311 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1312 1313 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1314 aml_append(method, aml_return(aml_int(0x01))); 1315 aml_append(dev, method); 1316 1317 aml_append(scope, dev); 1318 aml_append(table, scope); 1319 } 1320 1321 static void 1322 build_dsdt(GArray *table_data, BIOSLinker *linker, 1323 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1324 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1325 { 1326 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1327 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1328 CrsRangeEntry *entry; 1329 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1330 CrsRangeSet crs_range_set; 1331 PCMachineState *pcms = PC_MACHINE(machine); 1332 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1333 X86MachineState *x86ms = X86_MACHINE(machine); 1334 AcpiMcfgInfo mcfg; 1335 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1336 uint32_t nr_mem = machine->ram_slots; 1337 int root_bus_limit = 0xFF; 1338 PCIBus *bus = NULL; 1339 #ifdef CONFIG_TPM 1340 TPMIf *tpm = tpm_find(); 1341 #endif 1342 bool cxl_present = false; 1343 int i; 1344 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1345 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1346 .oem_table_id = x86ms->oem_table_id }; 1347 1348 assert(!!i440fx != !!q35); 1349 1350 acpi_table_begin(&table, table_data); 1351 dsdt = init_aml_allocator(); 1352 1353 build_dbg_aml(dsdt); 1354 if (i440fx) { 1355 sb_scope = aml_scope("_SB"); 1356 dev = aml_device("PCI0"); 1357 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1358 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1359 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1360 aml_append(sb_scope, dev); 1361 aml_append(dsdt, sb_scope); 1362 1363 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1364 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1365 } 1366 build_piix4_pci0_int(dsdt); 1367 } else if (q35) { 1368 sb_scope = aml_scope("_SB"); 1369 dev = aml_device("PCI0"); 1370 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1371 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1372 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1373 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1374 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1375 aml_append(sb_scope, dev); 1376 if (mcfg_valid) { 1377 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1378 } 1379 1380 if (pm->smi_on_cpuhp) { 1381 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1382 dev = aml_device("PCI0.SMI0"); 1383 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1384 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1385 crs = aml_resource_template(); 1386 aml_append(crs, 1387 aml_io( 1388 AML_DECODE16, 1389 ACPI_PORT_SMI_CMD, 1390 ACPI_PORT_SMI_CMD, 1391 1, 1392 2) 1393 ); 1394 aml_append(dev, aml_name_decl("_CRS", crs)); 1395 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1396 aml_int(ACPI_PORT_SMI_CMD), 2)); 1397 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1398 AML_WRITE_AS_ZEROS); 1399 aml_append(field, aml_named_field("SMIC", 8)); 1400 aml_append(field, aml_reserved_field(8)); 1401 aml_append(dev, field); 1402 aml_append(sb_scope, dev); 1403 } 1404 1405 aml_append(dsdt, sb_scope); 1406 1407 if (pm->pcihp_bridge_en) { 1408 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1409 } 1410 build_q35_pci0_int(dsdt); 1411 } 1412 1413 if (misc->has_hpet) { 1414 build_hpet_aml(dsdt); 1415 } 1416 1417 if (vmbus_bridge) { 1418 sb_scope = aml_scope("_SB"); 1419 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1420 aml_append(dsdt, sb_scope); 1421 } 1422 1423 scope = aml_scope("_GPE"); 1424 { 1425 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1426 if (machine->nvdimms_state->is_enabled) { 1427 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1428 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1429 aml_int(0x80))); 1430 aml_append(scope, method); 1431 } 1432 } 1433 aml_append(dsdt, scope); 1434 1435 if (pcmc->legacy_cpu_hotplug) { 1436 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1437 } else { 1438 CPUHotplugFeatures opts = { 1439 .acpi_1_compatible = true, .has_legacy_cphp = true, 1440 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1441 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1442 }; 1443 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1444 "\\_SB.PCI0", "\\_GPE._E02"); 1445 } 1446 1447 if (pcms->memhp_io_base && nr_mem) { 1448 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1449 "\\_GPE._E03", AML_SYSTEM_IO, 1450 pcms->memhp_io_base); 1451 } 1452 1453 crs_range_set_init(&crs_range_set); 1454 bus = PC_MACHINE(machine)->bus; 1455 if (bus) { 1456 QLIST_FOREACH(bus, &bus->child, sibling) { 1457 uint8_t bus_num = pci_bus_num(bus); 1458 uint8_t numa_node = pci_bus_numa_node(bus); 1459 1460 /* look only for expander root buses */ 1461 if (!pci_bus_is_root(bus)) { 1462 continue; 1463 } 1464 1465 if (bus_num < root_bus_limit) { 1466 root_bus_limit = bus_num - 1; 1467 } 1468 1469 scope = aml_scope("\\_SB"); 1470 1471 if (pci_bus_is_cxl(bus)) { 1472 dev = aml_device("CL%.02X", bus_num); 1473 } else { 1474 dev = aml_device("PC%.02X", bus_num); 1475 } 1476 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1477 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1478 if (pci_bus_is_cxl(bus)) { 1479 struct Aml *pkg = aml_package(2); 1480 1481 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1482 aml_append(pkg, aml_eisaid("PNP0A08")); 1483 aml_append(pkg, aml_eisaid("PNP0A03")); 1484 aml_append(dev, aml_name_decl("_CID", pkg)); 1485 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1486 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1487 build_cxl_osc_method(dev); 1488 } else if (pci_bus_is_express(bus)) { 1489 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1490 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1491 1492 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1493 aml_append(dev, build_q35_osc_method(true)); 1494 } else { 1495 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1496 } 1497 1498 if (numa_node != NUMA_NODE_UNASSIGNED) { 1499 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1500 } 1501 1502 aml_append(dev, build_prt(false)); 1503 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1504 0, 0, 0, 0); 1505 aml_append(dev, aml_name_decl("_CRS", crs)); 1506 aml_append(scope, dev); 1507 aml_append(dsdt, scope); 1508 1509 /* Handle the ranges for the PXB expanders */ 1510 if (pci_bus_is_cxl(bus)) { 1511 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1512 uint64_t base = mr->addr; 1513 1514 cxl_present = true; 1515 crs_range_insert(crs_range_set.mem_ranges, base, 1516 base + memory_region_size(mr) - 1); 1517 } 1518 } 1519 } 1520 1521 if (cxl_present) { 1522 build_acpi0017(dsdt); 1523 } 1524 1525 /* 1526 * At this point crs_range_set has all the ranges used by pci 1527 * busses *other* than PCI0. These ranges will be excluded from 1528 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1529 * too. 1530 */ 1531 if (mcfg_valid) { 1532 crs_range_insert(crs_range_set.mem_ranges, 1533 mcfg.base, mcfg.base + mcfg.size - 1); 1534 } 1535 1536 scope = aml_scope("\\_SB.PCI0"); 1537 /* build PCI0._CRS */ 1538 crs = aml_resource_template(); 1539 aml_append(crs, 1540 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1541 0x0000, 0x0, root_bus_limit, 1542 0x0000, root_bus_limit + 1)); 1543 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1544 1545 aml_append(crs, 1546 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1547 AML_POS_DECODE, AML_ENTIRE_RANGE, 1548 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1549 1550 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1551 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1552 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1553 aml_append(crs, 1554 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1555 AML_POS_DECODE, AML_ENTIRE_RANGE, 1556 0x0000, entry->base, entry->limit, 1557 0x0000, entry->limit - entry->base + 1)); 1558 } 1559 1560 aml_append(crs, 1561 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1562 AML_CACHEABLE, AML_READ_WRITE, 1563 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1564 1565 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1566 range_lob(pci_hole), 1567 range_upb(pci_hole)); 1568 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1569 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1570 aml_append(crs, 1571 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1572 AML_NON_CACHEABLE, AML_READ_WRITE, 1573 0, entry->base, entry->limit, 1574 0, entry->limit - entry->base + 1)); 1575 } 1576 1577 if (!range_is_empty(pci_hole64)) { 1578 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1579 range_lob(pci_hole64), 1580 range_upb(pci_hole64)); 1581 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1582 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1583 aml_append(crs, 1584 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1585 AML_MAX_FIXED, 1586 AML_CACHEABLE, AML_READ_WRITE, 1587 0, entry->base, entry->limit, 1588 0, entry->limit - entry->base + 1)); 1589 } 1590 } 1591 1592 #ifdef CONFIG_TPM 1593 if (TPM_IS_TIS_ISA(tpm_find())) { 1594 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1595 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1596 } 1597 #endif 1598 aml_append(scope, aml_name_decl("_CRS", crs)); 1599 1600 /* reserve GPE0 block resources */ 1601 dev = aml_device("GPE0"); 1602 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1603 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1604 /* device present, functioning, decoding, not shown in UI */ 1605 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1606 crs = aml_resource_template(); 1607 aml_append(crs, 1608 aml_io( 1609 AML_DECODE16, 1610 pm->fadt.gpe0_blk.address, 1611 pm->fadt.gpe0_blk.address, 1612 1, 1613 pm->fadt.gpe0_blk.bit_width / 8) 1614 ); 1615 aml_append(dev, aml_name_decl("_CRS", crs)); 1616 aml_append(scope, dev); 1617 1618 crs_range_set_free(&crs_range_set); 1619 1620 /* reserve PCIHP resources */ 1621 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1622 dev = aml_device("PHPR"); 1623 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1624 aml_append(dev, 1625 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1626 /* device present, functioning, decoding, not shown in UI */ 1627 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1628 crs = aml_resource_template(); 1629 aml_append(crs, 1630 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1631 pm->pcihp_io_len) 1632 ); 1633 aml_append(dev, aml_name_decl("_CRS", crs)); 1634 aml_append(scope, dev); 1635 } 1636 aml_append(dsdt, scope); 1637 1638 /* create S3_ / S4_ / S5_ packages if necessary */ 1639 scope = aml_scope("\\"); 1640 if (!pm->s3_disabled) { 1641 pkg = aml_package(4); 1642 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1643 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1644 aml_append(pkg, aml_int(0)); /* reserved */ 1645 aml_append(pkg, aml_int(0)); /* reserved */ 1646 aml_append(scope, aml_name_decl("_S3", pkg)); 1647 } 1648 1649 if (!pm->s4_disabled) { 1650 pkg = aml_package(4); 1651 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1652 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1653 aml_append(pkg, aml_int(pm->s4_val)); 1654 aml_append(pkg, aml_int(0)); /* reserved */ 1655 aml_append(pkg, aml_int(0)); /* reserved */ 1656 aml_append(scope, aml_name_decl("_S4", pkg)); 1657 } 1658 1659 pkg = aml_package(4); 1660 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1661 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1662 aml_append(pkg, aml_int(0)); /* reserved */ 1663 aml_append(pkg, aml_int(0)); /* reserved */ 1664 aml_append(scope, aml_name_decl("_S5", pkg)); 1665 aml_append(dsdt, scope); 1666 1667 /* create fw_cfg node, unconditionally */ 1668 { 1669 scope = aml_scope("\\_SB.PCI0"); 1670 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1671 aml_append(dsdt, scope); 1672 } 1673 1674 sb_scope = aml_scope("\\_SB"); 1675 { 1676 Object *pci_host = acpi_get_i386_pci_host(); 1677 1678 if (pci_host) { 1679 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1680 Aml *scope = aml_scope("PCI0"); 1681 /* Scan all PCI buses. Generate tables to support hotplug. */ 1682 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1683 aml_append(sb_scope, scope); 1684 } 1685 } 1686 1687 #ifdef CONFIG_TPM 1688 if (TPM_IS_CRB(tpm)) { 1689 dev = aml_device("TPM"); 1690 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1691 aml_append(dev, aml_name_decl("_STR", 1692 aml_string("TPM 2.0 Device"))); 1693 crs = aml_resource_template(); 1694 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1695 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1696 aml_append(dev, aml_name_decl("_CRS", crs)); 1697 1698 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1699 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1700 1701 tpm_build_ppi_acpi(tpm, dev); 1702 1703 aml_append(sb_scope, dev); 1704 } 1705 #endif 1706 1707 if (pcms->sgx_epc.size != 0) { 1708 uint64_t epc_base = pcms->sgx_epc.base; 1709 uint64_t epc_size = pcms->sgx_epc.size; 1710 1711 dev = aml_device("EPC"); 1712 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1713 aml_append(dev, aml_name_decl("_STR", 1714 aml_unicode("Enclave Page Cache 1.0"))); 1715 crs = aml_resource_template(); 1716 aml_append(crs, 1717 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1718 AML_MAX_FIXED, AML_NON_CACHEABLE, 1719 AML_READ_WRITE, 0, epc_base, 1720 epc_base + epc_size - 1, 0, epc_size)); 1721 aml_append(dev, aml_name_decl("_CRS", crs)); 1722 1723 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1724 aml_append(method, aml_return(aml_int(0x0f))); 1725 aml_append(dev, method); 1726 1727 aml_append(sb_scope, dev); 1728 } 1729 aml_append(dsdt, sb_scope); 1730 1731 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1732 scope = aml_scope("_GPE"); 1733 { 1734 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1735 aml_append(method, 1736 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1737 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1738 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1739 aml_append(scope, method); 1740 } 1741 aml_append(dsdt, scope); 1742 } 1743 1744 /* copy AML table into ACPI tables blob and patch header there */ 1745 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1746 acpi_table_end(linker, &table); 1747 free_aml_allocator(); 1748 } 1749 1750 /* 1751 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1752 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1753 */ 1754 static void 1755 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1756 const char *oem_table_id) 1757 { 1758 AcpiTable table = { .sig = "HPET", .rev = 1, 1759 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1760 1761 acpi_table_begin(&table, table_data); 1762 /* Note timer_block_id value must be kept in sync with value advertised by 1763 * emulated hpet 1764 */ 1765 /* Event Timer Block ID */ 1766 build_append_int_noprefix(table_data, 0x8086a201, 4); 1767 /* BASE_ADDRESS */ 1768 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1769 /* HPET Number */ 1770 build_append_int_noprefix(table_data, 0, 1); 1771 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1772 build_append_int_noprefix(table_data, 0, 2); 1773 /* Page Protection And OEM Attribute */ 1774 build_append_int_noprefix(table_data, 0, 1); 1775 acpi_table_end(linker, &table); 1776 } 1777 1778 #ifdef CONFIG_TPM 1779 /* 1780 * TCPA Description Table 1781 * 1782 * Following Level 00, Rev 00.37 of specs: 1783 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1784 * 7.1.2 ACPI Table Layout 1785 */ 1786 static void 1787 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1788 const char *oem_id, const char *oem_table_id) 1789 { 1790 unsigned log_addr_offset; 1791 AcpiTable table = { .sig = "TCPA", .rev = 2, 1792 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1793 1794 acpi_table_begin(&table, table_data); 1795 /* Platform Class */ 1796 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1797 /* Log Area Minimum Length (LAML) */ 1798 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1799 /* Log Area Start Address (LASA) */ 1800 log_addr_offset = table_data->len; 1801 build_append_int_noprefix(table_data, 0, 8); 1802 1803 /* allocate/reserve space for TPM log area */ 1804 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1805 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1806 false /* high memory */); 1807 /* log area start address to be filled by Guest linker */ 1808 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1809 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1810 1811 acpi_table_end(linker, &table); 1812 } 1813 #endif 1814 1815 #define HOLE_640K_START (640 * KiB) 1816 #define HOLE_640K_END (1 * MiB) 1817 1818 /* 1819 * ACPI spec, Revision 3.0 1820 * 5.2.15 System Resource Affinity Table (SRAT) 1821 */ 1822 static void 1823 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1824 { 1825 int i; 1826 int numa_mem_start, slots; 1827 uint64_t mem_len, mem_base, next_base; 1828 MachineClass *mc = MACHINE_GET_CLASS(machine); 1829 X86MachineState *x86ms = X86_MACHINE(machine); 1830 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1831 PCMachineState *pcms = PC_MACHINE(machine); 1832 int nb_numa_nodes = machine->numa_state->num_nodes; 1833 NodeInfo *numa_info = machine->numa_state->nodes; 1834 ram_addr_t hotpluggable_address_space_size = 1835 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1836 NULL); 1837 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1838 .oem_table_id = x86ms->oem_table_id }; 1839 1840 acpi_table_begin(&table, table_data); 1841 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1842 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1843 1844 for (i = 0; i < apic_ids->len; i++) { 1845 int node_id = apic_ids->cpus[i].props.node_id; 1846 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1847 1848 if (apic_id < 255) { 1849 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1850 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1851 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1852 /* Proximity Domain [7:0] */ 1853 build_append_int_noprefix(table_data, node_id, 1); 1854 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1855 /* Flags, Table 5-36 */ 1856 build_append_int_noprefix(table_data, 1, 4); 1857 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1858 /* Proximity Domain [31:8] */ 1859 build_append_int_noprefix(table_data, 0, 3); 1860 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1861 } else { 1862 /* 1863 * ACPI spec, Revision 4.0 1864 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1865 */ 1866 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1867 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1868 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1869 /* Proximity Domain */ 1870 build_append_int_noprefix(table_data, node_id, 4); 1871 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1872 /* Flags, Table 5-39 */ 1873 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1874 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1875 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1876 } 1877 } 1878 1879 /* the memory map is a bit tricky, it contains at least one hole 1880 * from 640k-1M and possibly another one from 3.5G-4G. 1881 */ 1882 next_base = 0; 1883 numa_mem_start = table_data->len; 1884 1885 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1886 mem_base = next_base; 1887 mem_len = numa_info[i - 1].node_mem; 1888 next_base = mem_base + mem_len; 1889 1890 /* Cut out the 640K hole */ 1891 if (mem_base <= HOLE_640K_START && 1892 next_base > HOLE_640K_START) { 1893 mem_len -= next_base - HOLE_640K_START; 1894 if (mem_len > 0) { 1895 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1896 MEM_AFFINITY_ENABLED); 1897 } 1898 1899 /* Check for the rare case: 640K < RAM < 1M */ 1900 if (next_base <= HOLE_640K_END) { 1901 next_base = HOLE_640K_END; 1902 continue; 1903 } 1904 mem_base = HOLE_640K_END; 1905 mem_len = next_base - HOLE_640K_END; 1906 } 1907 1908 /* Cut out the ACPI_PCI hole */ 1909 if (mem_base <= x86ms->below_4g_mem_size && 1910 next_base > x86ms->below_4g_mem_size) { 1911 mem_len -= next_base - x86ms->below_4g_mem_size; 1912 if (mem_len > 0) { 1913 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1914 MEM_AFFINITY_ENABLED); 1915 } 1916 mem_base = x86ms->above_4g_mem_start; 1917 mem_len = next_base - x86ms->below_4g_mem_size; 1918 next_base = mem_base + mem_len; 1919 } 1920 1921 if (mem_len > 0) { 1922 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1923 MEM_AFFINITY_ENABLED); 1924 } 1925 } 1926 1927 if (machine->nvdimms_state->is_enabled) { 1928 nvdimm_build_srat(table_data); 1929 } 1930 1931 sgx_epc_build_srat(table_data); 1932 1933 /* 1934 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1935 * without these entries. But I recall there were issues the last time I 1936 * tried to remove it with some ancient guest OS, however I can't remember 1937 * what that was so keep this around for now 1938 */ 1939 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1940 for (; slots < nb_numa_nodes + 2; slots++) { 1941 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1942 } 1943 1944 /* 1945 * Entry is required for Windows to enable memory hotplug in OS 1946 * and for Linux to enable SWIOTLB when booted with less than 1947 * 4G of RAM. Windows works better if the entry sets proximity 1948 * to the highest NUMA node in the machine. 1949 * Memory devices may override proximity set by this entry, 1950 * providing _PXM method if necessary. 1951 */ 1952 if (hotpluggable_address_space_size) { 1953 build_srat_memory(table_data, machine->device_memory->base, 1954 hotpluggable_address_space_size, nb_numa_nodes - 1, 1955 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1956 } 1957 1958 acpi_table_end(linker, &table); 1959 } 1960 1961 /* 1962 * Insert DMAR scope for PCI bridges and endpoint devcie 1963 */ 1964 static void 1965 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1966 { 1967 const size_t device_scope_size = 6 /* device scope structure */ + 1968 2 /* 1 path entry */; 1969 GArray *scope_blob = opaque; 1970 1971 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1972 /* Dmar Scope Type: 0x02 for PCI Bridge */ 1973 build_append_int_noprefix(scope_blob, 0x02, 1); 1974 } else { 1975 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 1976 build_append_int_noprefix(scope_blob, 0x01, 1); 1977 } 1978 1979 /* length */ 1980 build_append_int_noprefix(scope_blob, device_scope_size, 1); 1981 /* reserved */ 1982 build_append_int_noprefix(scope_blob, 0, 2); 1983 /* enumeration_id */ 1984 build_append_int_noprefix(scope_blob, 0, 1); 1985 /* bus */ 1986 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 1987 /* device */ 1988 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 1989 /* function */ 1990 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 1991 } 1992 1993 /* For a given PCI host bridge, walk and insert DMAR scope */ 1994 static int 1995 dmar_host_bridges(Object *obj, void *opaque) 1996 { 1997 GArray *scope_blob = opaque; 1998 1999 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2000 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2001 2002 if (bus && !pci_bus_bypass_iommu(bus)) { 2003 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2004 } 2005 } 2006 2007 return 0; 2008 } 2009 2010 /* 2011 * Intel ® Virtualization Technology for Directed I/O 2012 * Architecture Specification. Revision 3.3 2013 * 8.1 DMA Remapping Reporting Structure 2014 */ 2015 static void 2016 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2017 const char *oem_table_id) 2018 { 2019 uint8_t dmar_flags = 0; 2020 uint8_t rsvd10[10] = {}; 2021 /* Root complex IOAPIC uses one path only */ 2022 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2023 2 /* 1 path entry */; 2024 X86IOMMUState *iommu = x86_iommu_get_default(); 2025 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2026 GArray *scope_blob = g_array_new(false, true, 1); 2027 2028 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2029 .oem_table_id = oem_table_id }; 2030 2031 /* 2032 * A PCI bus walk, for each PCI host bridge. 2033 * Insert scope for each PCI bridge and endpoint device which 2034 * is attached to a bus with iommu enabled. 2035 */ 2036 object_child_foreach_recursive(object_get_root(), 2037 dmar_host_bridges, scope_blob); 2038 2039 assert(iommu); 2040 if (x86_iommu_ir_supported(iommu)) { 2041 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2042 } 2043 2044 acpi_table_begin(&table, table_data); 2045 /* Host Address Width */ 2046 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2047 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2048 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2049 2050 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2051 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2052 /* Length */ 2053 build_append_int_noprefix(table_data, 2054 16 + ioapic_scope_size + scope_blob->len, 2); 2055 /* Flags */ 2056 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2057 1); 2058 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2059 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2060 /* Register Base Address */ 2061 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2062 2063 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2064 * 8.3.1 (version Oct. 2014 or later). */ 2065 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2066 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2067 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2068 /* Enumeration ID */ 2069 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2070 /* Start Bus Number */ 2071 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2072 /* Path, {Device, Function} pair */ 2073 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2074 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2075 2076 /* Add scope found above */ 2077 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2078 g_array_free(scope_blob, true); 2079 2080 if (iommu->dt_supported) { 2081 /* 8.5 Root Port ATS Capability Reporting Structure */ 2082 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2083 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2084 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2085 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2086 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2087 } 2088 2089 acpi_table_end(linker, &table); 2090 } 2091 2092 /* 2093 * Windows ACPI Emulated Devices Table 2094 * (Version 1.0 - April 6, 2009) 2095 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2096 * 2097 * Helpful to speedup Windows guests and ignored by others. 2098 */ 2099 static void 2100 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2101 const char *oem_table_id) 2102 { 2103 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2104 .oem_table_id = oem_table_id }; 2105 2106 acpi_table_begin(&table, table_data); 2107 /* 2108 * Set "ACPI PM timer good" flag. 2109 * 2110 * Tells Windows guests that our ACPI PM timer is reliable in the 2111 * sense that guest can read it only once to obtain a reliable value. 2112 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2113 */ 2114 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2115 acpi_table_end(linker, &table); 2116 } 2117 2118 /* 2119 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2120 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2121 */ 2122 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2123 2124 /* 2125 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2126 * necessary for the PCI topology. 2127 */ 2128 static void 2129 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2130 { 2131 GArray *table_data = opaque; 2132 uint32_t entry; 2133 2134 /* "Select" IVHD entry, type 0x2 */ 2135 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2136 build_append_int_noprefix(table_data, entry, 4); 2137 2138 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2139 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2140 uint8_t sec = pci_bus_num(sec_bus); 2141 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2142 2143 if (pci_bus_is_express(sec_bus)) { 2144 /* 2145 * Walk the bus if there are subordinates, otherwise use a range 2146 * to cover an entire leaf bus. We could potentially also use a 2147 * range for traversed buses, but we'd need to take care not to 2148 * create both Select and Range entries covering the same device. 2149 * This is easier and potentially more compact. 2150 * 2151 * An example bare metal system seems to use Select entries for 2152 * root ports without a slot (ie. built-ins) and Range entries 2153 * when there is a slot. The same system also only hard-codes 2154 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2155 * making no effort to support nested bridges. We attempt to 2156 * be more thorough here. 2157 */ 2158 if (sec == sub) { /* leaf bus */ 2159 /* "Start of Range" IVHD entry, type 0x3 */ 2160 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2161 build_append_int_noprefix(table_data, entry, 4); 2162 /* "End of Range" IVHD entry, type 0x4 */ 2163 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2164 build_append_int_noprefix(table_data, entry, 4); 2165 } else { 2166 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2167 } 2168 } else { 2169 /* 2170 * If the secondary bus is conventional, then we need to create an 2171 * Alias range for everything downstream. The range covers the 2172 * first devfn on the secondary bus to the last devfn on the 2173 * subordinate bus. The alias target depends on legacy versus 2174 * express bridges, just as in pci_device_iommu_address_space(). 2175 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2176 */ 2177 uint16_t dev_id_a, dev_id_b; 2178 2179 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2180 2181 if (pci_is_express(dev) && 2182 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2183 dev_id_b = dev_id_a; 2184 } else { 2185 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2186 } 2187 2188 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2189 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2190 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2191 2192 /* "End of Range" IVHD entry, type 0x4 */ 2193 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2194 build_append_int_noprefix(table_data, entry, 4); 2195 } 2196 } 2197 } 2198 2199 /* For all PCI host bridges, walk and insert IVHD entries */ 2200 static int 2201 ivrs_host_bridges(Object *obj, void *opaque) 2202 { 2203 GArray *ivhd_blob = opaque; 2204 2205 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2206 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2207 2208 if (bus && !pci_bus_bypass_iommu(bus)) { 2209 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2210 } 2211 } 2212 2213 return 0; 2214 } 2215 2216 static void 2217 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2218 const char *oem_table_id) 2219 { 2220 int ivhd_table_len = 24; 2221 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2222 GArray *ivhd_blob = g_array_new(false, true, 1); 2223 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2224 .oem_table_id = oem_table_id }; 2225 2226 acpi_table_begin(&table, table_data); 2227 /* IVinfo - IO virtualization information common to all 2228 * IOMMU units in a system 2229 */ 2230 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2231 /* reserved */ 2232 build_append_int_noprefix(table_data, 0, 8); 2233 2234 /* IVHD definition - type 10h */ 2235 build_append_int_noprefix(table_data, 0x10, 1); 2236 /* virtualization flags */ 2237 build_append_int_noprefix(table_data, 2238 (1UL << 0) | /* HtTunEn */ 2239 (1UL << 4) | /* iotblSup */ 2240 (1UL << 6) | /* PrefSup */ 2241 (1UL << 7), /* PPRSup */ 2242 1); 2243 2244 /* 2245 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2246 * complete set of IVHD entries. Do this into a separate blob so that we 2247 * can calculate the total IVRS table length here and then append the new 2248 * blob further below. Fall back to an entry covering all devices, which 2249 * is sufficient when no aliases are present. 2250 */ 2251 object_child_foreach_recursive(object_get_root(), 2252 ivrs_host_bridges, ivhd_blob); 2253 2254 if (!ivhd_blob->len) { 2255 /* 2256 * Type 1 device entry reporting all devices 2257 * These are 4-byte device entries currently reporting the range of 2258 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2259 */ 2260 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2261 } 2262 2263 ivhd_table_len += ivhd_blob->len; 2264 2265 /* 2266 * When interrupt remapping is supported, we add a special IVHD device 2267 * for type IO-APIC. 2268 */ 2269 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2270 ivhd_table_len += 8; 2271 } 2272 2273 /* IVHD length */ 2274 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2275 /* DeviceID */ 2276 build_append_int_noprefix(table_data, s->devid, 2); 2277 /* Capability offset */ 2278 build_append_int_noprefix(table_data, s->capab_offset, 2); 2279 /* IOMMU base address */ 2280 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2281 /* PCI Segment Group */ 2282 build_append_int_noprefix(table_data, 0, 2); 2283 /* IOMMU info */ 2284 build_append_int_noprefix(table_data, 0, 2); 2285 /* IOMMU Feature Reporting */ 2286 build_append_int_noprefix(table_data, 2287 (48UL << 30) | /* HATS */ 2288 (48UL << 28) | /* GATS */ 2289 (1UL << 2) | /* GTSup */ 2290 (1UL << 6), /* GASup */ 2291 4); 2292 2293 /* IVHD entries as found above */ 2294 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2295 g_array_free(ivhd_blob, TRUE); 2296 2297 /* 2298 * Add a special IVHD device type. 2299 * Refer to spec - Table 95: IVHD device entry type codes 2300 * 2301 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2302 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2303 */ 2304 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2305 build_append_int_noprefix(table_data, 2306 (0x1ull << 56) | /* type IOAPIC */ 2307 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2308 0x48, /* special device */ 2309 8); 2310 } 2311 acpi_table_end(linker, &table); 2312 } 2313 2314 typedef 2315 struct AcpiBuildState { 2316 /* Copy of table in RAM (for patching). */ 2317 MemoryRegion *table_mr; 2318 /* Is table patched? */ 2319 uint8_t patched; 2320 void *rsdp; 2321 MemoryRegion *rsdp_mr; 2322 MemoryRegion *linker_mr; 2323 } AcpiBuildState; 2324 2325 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2326 { 2327 Object *pci_host; 2328 QObject *o; 2329 2330 pci_host = acpi_get_i386_pci_host(); 2331 if (!pci_host) { 2332 return false; 2333 } 2334 2335 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2336 if (!o) { 2337 return false; 2338 } 2339 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2340 qobject_unref(o); 2341 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2342 return false; 2343 } 2344 2345 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2346 assert(o); 2347 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2348 qobject_unref(o); 2349 return true; 2350 } 2351 2352 static 2353 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2354 { 2355 PCMachineState *pcms = PC_MACHINE(machine); 2356 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2357 X86MachineState *x86ms = X86_MACHINE(machine); 2358 DeviceState *iommu = pcms->iommu; 2359 GArray *table_offsets; 2360 unsigned facs, dsdt, rsdt, fadt; 2361 AcpiPmInfo pm; 2362 AcpiMiscInfo misc; 2363 AcpiMcfgInfo mcfg; 2364 Range pci_hole = {}, pci_hole64 = {}; 2365 uint8_t *u; 2366 size_t aml_len = 0; 2367 GArray *tables_blob = tables->table_data; 2368 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2369 Object *vmgenid_dev; 2370 char *oem_id; 2371 char *oem_table_id; 2372 2373 acpi_get_pm_info(machine, &pm); 2374 acpi_get_misc_info(&misc); 2375 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2376 acpi_get_slic_oem(&slic_oem); 2377 2378 if (slic_oem.id) { 2379 oem_id = slic_oem.id; 2380 } else { 2381 oem_id = x86ms->oem_id; 2382 } 2383 2384 if (slic_oem.table_id) { 2385 oem_table_id = slic_oem.table_id; 2386 } else { 2387 oem_table_id = x86ms->oem_table_id; 2388 } 2389 2390 table_offsets = g_array_new(false, true /* clear */, 2391 sizeof(uint32_t)); 2392 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2393 2394 bios_linker_loader_alloc(tables->linker, 2395 ACPI_BUILD_TABLE_FILE, tables_blob, 2396 64 /* Ensure FACS is aligned */, 2397 false /* high memory */); 2398 2399 /* 2400 * FACS is pointed to by FADT. 2401 * We place it first since it's the only table that has alignment 2402 * requirements. 2403 */ 2404 facs = tables_blob->len; 2405 build_facs(tables_blob); 2406 2407 /* DSDT is pointed to by FADT */ 2408 dsdt = tables_blob->len; 2409 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2410 &pci_hole, &pci_hole64, machine); 2411 2412 /* Count the size of the DSDT and SSDT, we will need it for legacy 2413 * sizing of ACPI tables. 2414 */ 2415 aml_len += tables_blob->len - dsdt; 2416 2417 /* ACPI tables pointed to by RSDT */ 2418 fadt = tables_blob->len; 2419 acpi_add_table(table_offsets, tables_blob); 2420 pm.fadt.facs_tbl_offset = &facs; 2421 pm.fadt.dsdt_tbl_offset = &dsdt; 2422 pm.fadt.xdsdt_tbl_offset = &dsdt; 2423 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2424 aml_len += tables_blob->len - fadt; 2425 2426 acpi_add_table(table_offsets, tables_blob); 2427 acpi_build_madt(tables_blob, tables->linker, x86ms, 2428 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2429 x86ms->oem_table_id); 2430 2431 #ifdef CONFIG_ACPI_ERST 2432 { 2433 Object *erst_dev; 2434 erst_dev = find_erst_dev(); 2435 if (erst_dev) { 2436 acpi_add_table(table_offsets, tables_blob); 2437 build_erst(tables_blob, tables->linker, erst_dev, 2438 x86ms->oem_id, x86ms->oem_table_id); 2439 } 2440 } 2441 #endif 2442 2443 vmgenid_dev = find_vmgenid_dev(); 2444 if (vmgenid_dev) { 2445 acpi_add_table(table_offsets, tables_blob); 2446 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2447 tables->vmgenid, tables->linker, x86ms->oem_id); 2448 } 2449 2450 if (misc.has_hpet) { 2451 acpi_add_table(table_offsets, tables_blob); 2452 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2453 x86ms->oem_table_id); 2454 } 2455 #ifdef CONFIG_TPM 2456 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2457 if (misc.tpm_version == TPM_VERSION_1_2) { 2458 acpi_add_table(table_offsets, tables_blob); 2459 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2460 x86ms->oem_id, x86ms->oem_table_id); 2461 } else { /* TPM_VERSION_2_0 */ 2462 acpi_add_table(table_offsets, tables_blob); 2463 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2464 x86ms->oem_id, x86ms->oem_table_id); 2465 } 2466 } 2467 #endif 2468 if (machine->numa_state->num_nodes) { 2469 acpi_add_table(table_offsets, tables_blob); 2470 build_srat(tables_blob, tables->linker, machine); 2471 if (machine->numa_state->have_numa_distance) { 2472 acpi_add_table(table_offsets, tables_blob); 2473 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2474 x86ms->oem_table_id); 2475 } 2476 if (machine->numa_state->hmat_enabled) { 2477 acpi_add_table(table_offsets, tables_blob); 2478 build_hmat(tables_blob, tables->linker, machine->numa_state, 2479 x86ms->oem_id, x86ms->oem_table_id); 2480 } 2481 } 2482 if (acpi_get_mcfg(&mcfg)) { 2483 acpi_add_table(table_offsets, tables_blob); 2484 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2485 x86ms->oem_table_id); 2486 } 2487 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2488 acpi_add_table(table_offsets, tables_blob); 2489 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2490 x86ms->oem_table_id); 2491 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2492 acpi_add_table(table_offsets, tables_blob); 2493 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2494 x86ms->oem_table_id); 2495 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2496 PCIDevice *pdev = PCI_DEVICE(iommu); 2497 2498 acpi_add_table(table_offsets, tables_blob); 2499 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2500 x86ms->oem_id, x86ms->oem_table_id); 2501 } 2502 if (machine->nvdimms_state->is_enabled) { 2503 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2504 machine->nvdimms_state, machine->ram_slots, 2505 x86ms->oem_id, x86ms->oem_table_id); 2506 } 2507 if (pcms->cxl_devices_state.is_enabled) { 2508 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2509 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2510 } 2511 2512 acpi_add_table(table_offsets, tables_blob); 2513 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2514 2515 /* Add tables supplied by user (if any) */ 2516 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2517 unsigned len = acpi_table_len(u); 2518 2519 acpi_add_table(table_offsets, tables_blob); 2520 g_array_append_vals(tables_blob, u, len); 2521 } 2522 2523 /* RSDT is pointed to by RSDP */ 2524 rsdt = tables_blob->len; 2525 build_rsdt(tables_blob, tables->linker, table_offsets, 2526 oem_id, oem_table_id); 2527 2528 /* RSDP is in FSEG memory, so allocate it separately */ 2529 { 2530 AcpiRsdpData rsdp_data = { 2531 .revision = 0, 2532 .oem_id = x86ms->oem_id, 2533 .xsdt_tbl_offset = NULL, 2534 .rsdt_tbl_offset = &rsdt, 2535 }; 2536 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2537 if (!pcmc->rsdp_in_ram) { 2538 /* We used to allocate some extra space for RSDP revision 2 but 2539 * only used the RSDP revision 0 space. The extra bytes were 2540 * zeroed out and not used. 2541 * Here we continue wasting those extra 16 bytes to make sure we 2542 * don't break migration for machine types 2.2 and older due to 2543 * RSDP blob size mismatch. 2544 */ 2545 build_append_int_noprefix(tables->rsdp, 0, 16); 2546 } 2547 } 2548 2549 /* We'll expose it all to Guest so we want to reduce 2550 * chance of size changes. 2551 * 2552 * We used to align the tables to 4k, but of course this would 2553 * too simple to be enough. 4k turned out to be too small an 2554 * alignment very soon, and in fact it is almost impossible to 2555 * keep the table size stable for all (max_cpus, max_memory_slots) 2556 * combinations. So the table size is always 64k for pc-i440fx-2.1 2557 * and we give an error if the table grows beyond that limit. 2558 * 2559 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2560 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2561 * than 2.0 and we can always pad the smaller tables with zeros. We can 2562 * then use the exact size of the 2.0 tables. 2563 * 2564 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2565 */ 2566 if (pcmc->legacy_acpi_table_size) { 2567 /* Subtracting aml_len gives the size of fixed tables. Then add the 2568 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2569 */ 2570 int legacy_aml_len = 2571 pcmc->legacy_acpi_table_size + 2572 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2573 int legacy_table_size = 2574 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2575 ACPI_BUILD_ALIGN_SIZE); 2576 if (tables_blob->len > legacy_table_size) { 2577 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2578 warn_report("ACPI table size %u exceeds %d bytes," 2579 " migration may not work", 2580 tables_blob->len, legacy_table_size); 2581 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2582 " or PCI bridges."); 2583 } 2584 g_array_set_size(tables_blob, legacy_table_size); 2585 } else { 2586 /* Make sure we have a buffer in case we need to resize the tables. */ 2587 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2588 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2589 warn_report("ACPI table size %u exceeds %d bytes," 2590 " migration may not work", 2591 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2592 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2593 " or PCI bridges."); 2594 } 2595 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2596 } 2597 2598 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2599 2600 /* Cleanup memory that's no longer used. */ 2601 g_array_free(table_offsets, true); 2602 g_free(slic_oem.id); 2603 g_free(slic_oem.table_id); 2604 } 2605 2606 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2607 { 2608 uint32_t size = acpi_data_len(data); 2609 2610 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2611 memory_region_ram_resize(mr, size, &error_abort); 2612 2613 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2614 memory_region_set_dirty(mr, 0, size); 2615 } 2616 2617 static void acpi_build_update(void *build_opaque) 2618 { 2619 AcpiBuildState *build_state = build_opaque; 2620 AcpiBuildTables tables; 2621 2622 /* No state to update or already patched? Nothing to do. */ 2623 if (!build_state || build_state->patched) { 2624 return; 2625 } 2626 build_state->patched = 1; 2627 2628 acpi_build_tables_init(&tables); 2629 2630 acpi_build(&tables, MACHINE(qdev_get_machine())); 2631 2632 acpi_ram_update(build_state->table_mr, tables.table_data); 2633 2634 if (build_state->rsdp) { 2635 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2636 } else { 2637 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2638 } 2639 2640 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2641 acpi_build_tables_cleanup(&tables, true); 2642 } 2643 2644 static void acpi_build_reset(void *build_opaque) 2645 { 2646 AcpiBuildState *build_state = build_opaque; 2647 build_state->patched = 0; 2648 } 2649 2650 static const VMStateDescription vmstate_acpi_build = { 2651 .name = "acpi_build", 2652 .version_id = 1, 2653 .minimum_version_id = 1, 2654 .fields = (VMStateField[]) { 2655 VMSTATE_UINT8(patched, AcpiBuildState), 2656 VMSTATE_END_OF_LIST() 2657 }, 2658 }; 2659 2660 void acpi_setup(void) 2661 { 2662 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2663 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2664 X86MachineState *x86ms = X86_MACHINE(pcms); 2665 AcpiBuildTables tables; 2666 AcpiBuildState *build_state; 2667 Object *vmgenid_dev; 2668 #ifdef CONFIG_TPM 2669 TPMIf *tpm; 2670 static FwCfgTPMConfig tpm_config; 2671 #endif 2672 2673 if (!x86ms->fw_cfg) { 2674 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2675 return; 2676 } 2677 2678 if (!pcms->acpi_build_enabled) { 2679 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2680 return; 2681 } 2682 2683 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2684 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2685 return; 2686 } 2687 2688 build_state = g_malloc0(sizeof *build_state); 2689 2690 acpi_build_tables_init(&tables); 2691 acpi_build(&tables, MACHINE(pcms)); 2692 2693 /* Now expose it all to Guest */ 2694 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2695 build_state, tables.table_data, 2696 ACPI_BUILD_TABLE_FILE); 2697 assert(build_state->table_mr != NULL); 2698 2699 build_state->linker_mr = 2700 acpi_add_rom_blob(acpi_build_update, build_state, 2701 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2702 2703 #ifdef CONFIG_TPM 2704 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2705 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2706 2707 tpm = tpm_find(); 2708 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2709 tpm_config = (FwCfgTPMConfig) { 2710 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2711 .tpm_version = tpm_get_version(tpm), 2712 .tpmppi_version = TPM_PPI_VERSION_1_30 2713 }; 2714 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2715 &tpm_config, sizeof tpm_config); 2716 } 2717 #endif 2718 2719 vmgenid_dev = find_vmgenid_dev(); 2720 if (vmgenid_dev) { 2721 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2722 tables.vmgenid); 2723 } 2724 2725 if (!pcmc->rsdp_in_ram) { 2726 /* 2727 * Keep for compatibility with old machine types. 2728 * Though RSDP is small, its contents isn't immutable, so 2729 * we'll update it along with the rest of tables on guest access. 2730 */ 2731 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2732 2733 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2734 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2735 acpi_build_update, NULL, build_state, 2736 build_state->rsdp, rsdp_size, true); 2737 build_state->rsdp_mr = NULL; 2738 } else { 2739 build_state->rsdp = NULL; 2740 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2741 build_state, tables.rsdp, 2742 ACPI_BUILD_RSDP_FILE); 2743 } 2744 2745 qemu_register_reset(acpi_build_reset, build_state); 2746 acpi_build_reset(build_state); 2747 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2748 2749 /* Cleanup tables but don't free the memory: we track it 2750 * in build_state. 2751 */ 2752 acpi_build_tables_cleanup(&tables, false); 2753 } 2754