1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qobject/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "system/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/vmclock.h" 47 #include "hw/acpi/erst.h" 48 #include "hw/acpi/piix4.h" 49 #include "system/tpm_backend.h" 50 #include "hw/rtc/mc146818rtc_regs.h" 51 #include "migration/vmstate.h" 52 #include "hw/mem/memory-device.h" 53 #include "hw/mem/nvdimm.h" 54 #include "system/numa.h" 55 #include "system/reset.h" 56 #include "hw/hyperv/vmbus-bridge.h" 57 58 /* Supported chipsets: */ 59 #include "hw/southbridge/ich9.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/pc.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/i440fx.h" 65 #include "hw/pci-host/q35.h" 66 #include "hw/i386/x86-iommu.h" 67 68 #include "hw/acpi/aml-build.h" 69 #include "hw/acpi/utils.h" 70 #include "hw/acpi/pci.h" 71 #include "hw/acpi/cxl.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_ALIGN_SIZE 0x1000 89 90 #define ACPI_BUILD_TABLE_SIZE 0x20000 91 92 /* #define DEBUG_ACPI_BUILD */ 93 #ifdef DEBUG_ACPI_BUILD 94 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 96 #else 97 #define ACPI_BUILD_DPRINTF(fmt, ...) 98 #endif 99 100 typedef struct AcpiPmInfo { 101 bool s3_disabled; 102 bool s4_disabled; 103 bool pcihp_bridge_en; 104 bool smi_on_cpuhp; 105 bool smi_on_cpu_unplug; 106 bool pcihp_root_en; 107 uint8_t s4_val; 108 AcpiFadtData fadt; 109 uint16_t cpu_hp_io_base; 110 uint16_t pcihp_io_base; 111 uint16_t pcihp_io_len; 112 } AcpiPmInfo; 113 114 typedef struct AcpiMiscInfo { 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 } AcpiMiscInfo; 120 121 typedef struct FwCfgTPMConfig { 122 uint32_t tpmppi_address; 123 uint8_t tpm_version; 124 uint8_t tpmppi_version; 125 } QEMU_PACKED FwCfgTPMConfig; 126 127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 128 129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 130 .space_id = AML_AS_SYSTEM_IO, 131 .address = NVDIMM_ACPI_IO_BASE, 132 .bit_width = NVDIMM_ACPI_IO_LEN << 3 133 }; 134 135 static void init_common_fadt_data(MachineState *ms, Object *o, 136 AcpiFadtData *data) 137 { 138 X86MachineState *x86ms = X86_MACHINE(ms); 139 /* 140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 141 * behavior for compatibility irrelevant to smm_enabled, which doesn't 142 * conform to the ACPI spec. 143 */ 144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 145 true : x86_machine_is_smm_enabled(x86ms); 146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 147 AmlAddressSpace as = AML_AS_SYSTEM_IO; 148 AcpiFadtData fadt = { 149 .rev = 3, 150 .flags = 151 (1 << ACPI_FADT_F_WBINVD) | 152 (1 << ACPI_FADT_F_PROC_C1) | 153 (1 << ACPI_FADT_F_SLP_BUTTON) | 154 (1 << ACPI_FADT_F_RTC_S4) | 155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 156 /* APIC destination mode ("Flat Logical") has an upper limit of 8 157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 158 * used 159 */ 160 ((ms->smp.max_cpus > 8) ? 161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 162 .int_model = 1 /* Multiple APIC */, 163 .rtc_century = RTC_CENTURY, 164 .plvl2_lat = 0xfff /* C2 state not supported */, 165 .plvl3_lat = 0xfff /* C3 state not supported */, 166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 168 .acpi_enable_cmd = 169 smm_enabled ? 170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 171 0, 172 .acpi_disable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 175 0, 176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 178 .address = io + 0x04 }, 179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 180 .gpe0_blk = { .space_id = as, .bit_width = 181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 183 }, 184 }; 185 186 /* 187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 188 * Flags, bit offset 1 - 8042. 189 */ 190 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 191 192 *data = fadt; 193 } 194 195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 196 { 197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL); 198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL); 199 Object *obj = piix ? piix : lpc; 200 QObject *o; 201 pm->cpu_hp_io_base = 0; 202 pm->pcihp_io_base = 0; 203 pm->pcihp_io_len = 0; 204 pm->smi_on_cpuhp = false; 205 pm->smi_on_cpu_unplug = false; 206 207 assert(obj); 208 init_common_fadt_data(machine, obj, &pm->fadt); 209 if (piix) { 210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 211 pm->fadt.rev = 1; 212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 213 } 214 if (lpc) { 215 uint64_t smi_features = object_property_get_uint(lpc, 216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 219 pm->fadt.reset_reg = r; 220 pm->fadt.reset_val = 0xf; 221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 223 pm->smi_on_cpuhp = 224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 225 pm->smi_on_cpu_unplug = 226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 227 } 228 pm->pcihp_io_base = 229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 230 pm->pcihp_io_len = 231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 232 233 /* Fill in optional s3/s4 related properties */ 234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 235 if (o) { 236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 237 } else { 238 pm->s3_disabled = false; 239 } 240 qobject_unref(o); 241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 242 if (o) { 243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 244 } else { 245 pm->s4_disabled = false; 246 } 247 qobject_unref(o); 248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 249 if (o) { 250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 251 } else { 252 pm->s4_val = false; 253 } 254 qobject_unref(o); 255 256 pm->pcihp_bridge_en = 257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 258 NULL); 259 pm->pcihp_root_en = 260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 261 NULL); 262 } 263 264 static void acpi_get_misc_info(AcpiMiscInfo *info) 265 { 266 info->has_hpet = hpet_find(); 267 #ifdef CONFIG_TPM 268 info->tpm_version = tpm_get_version(tpm_find()); 269 #endif 270 } 271 272 /* 273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 274 * On i386 arch we only have two pci hosts, so we can look only for them. 275 */ 276 Object *acpi_get_i386_pci_host(void) 277 { 278 PCIHostState *host; 279 280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 281 if (!host) { 282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 283 } 284 285 return OBJECT(host); 286 } 287 288 static void acpi_get_pci_holes(Range *hole, Range *hole64) 289 { 290 Object *pci_host; 291 292 pci_host = acpi_get_i386_pci_host(); 293 294 if (!pci_host) { 295 return; 296 } 297 298 range_set_bounds1(hole, 299 object_property_get_uint(pci_host, 300 PCI_HOST_PROP_PCI_HOLE_START, 301 NULL), 302 object_property_get_uint(pci_host, 303 PCI_HOST_PROP_PCI_HOLE_END, 304 NULL)); 305 range_set_bounds1(hole64, 306 object_property_get_uint(pci_host, 307 PCI_HOST_PROP_PCI_HOLE64_START, 308 NULL), 309 object_property_get_uint(pci_host, 310 PCI_HOST_PROP_PCI_HOLE64_END, 311 NULL)); 312 } 313 314 static void acpi_align_size(GArray *blob, unsigned align) 315 { 316 /* Align size to multiple of given size. This reduces the chance 317 * we need to change size in the future (breaking cross version migration). 318 */ 319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 320 } 321 322 /* 323 * ACPI spec 1.0b, 324 * 5.2.6 Firmware ACPI Control Structure 325 */ 326 static void 327 build_facs(GArray *table_data) 328 { 329 const char *sig = "FACS"; 330 const uint8_t reserved[40] = {}; 331 332 g_array_append_vals(table_data, sig, 4); /* Signature */ 333 build_append_int_noprefix(table_data, 64, 4); /* Length */ 334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 337 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 338 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 339 } 340 341 static Aml *aml_pci_device_dsm(void) 342 { 343 Aml *method; 344 345 method = aml_method("_DSM", 4, AML_SERIALIZED); 346 { 347 Aml *params = aml_local(0); 348 Aml *pkg = aml_package(2); 349 aml_append(pkg, aml_int(0)); 350 aml_append(pkg, aml_int(0)); 351 aml_append(method, aml_store(pkg, params)); 352 aml_append(method, 353 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); 354 aml_append(method, 355 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); 356 aml_append(method, 357 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 358 aml_arg(2), aml_arg(3), params)) 359 ); 360 } 361 return method; 362 } 363 364 static Aml *aml_pci_edsm(void) 365 { 366 Aml *method, *ifctx; 367 Aml *zero = aml_int(0); 368 Aml *func = aml_arg(2); 369 Aml *ret = aml_local(0); 370 Aml *aidx = aml_local(1); 371 Aml *params = aml_arg(4); 372 373 method = aml_method("EDSM", 5, AML_SERIALIZED); 374 375 /* get supported functions */ 376 ifctx = aml_if(aml_equal(func, zero)); 377 { 378 /* 1: have supported functions */ 379 /* 7: support for function 7 */ 380 const uint8_t caps = 1 | BIT(7); 381 build_append_pci_dsm_func0_common(ifctx, ret); 382 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 383 aml_append(ifctx, aml_return(ret)); 384 } 385 aml_append(method, ifctx); 386 387 /* handle specific functions requests */ 388 /* 389 * PCI Firmware Specification 3.1 390 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 391 * Operating Systems 392 */ 393 ifctx = aml_if(aml_equal(func, aml_int(7))); 394 { 395 Aml *pkg = aml_package(2); 396 aml_append(pkg, zero); 397 /* optional, if not impl. should return null string */ 398 aml_append(pkg, aml_string("%s", "")); 399 aml_append(ifctx, aml_store(pkg, ret)); 400 401 /* 402 * IASL is fine when initializing Package with computational data, 403 * however it makes guest unhappy /it fails to process such AML/. 404 * So use runtime assignment to set acpi-index after initializer 405 * to make OSPM happy. 406 */ 407 aml_append(ifctx, 408 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 409 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 410 aml_append(ifctx, aml_return(ret)); 411 } 412 aml_append(method, ifctx); 413 414 return method; 415 } 416 417 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 418 { 419 Aml *method; 420 421 g_assert(pdev->acpi_index != 0); 422 method = aml_method("_DSM", 4, AML_SERIALIZED); 423 { 424 Aml *params = aml_local(0); 425 Aml *pkg = aml_package(1); 426 aml_append(pkg, aml_int(pdev->acpi_index)); 427 aml_append(method, aml_store(pkg, params)); 428 aml_append(method, 429 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 430 aml_arg(2), aml_arg(3), params)) 431 ); 432 } 433 return method; 434 } 435 436 static void build_append_pcihp_notify_entry(Aml *method, int slot) 437 { 438 Aml *if_ctx; 439 int32_t devfn = PCI_DEVFN(slot, 0); 440 441 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 442 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 443 aml_append(method, if_ctx); 444 } 445 446 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 447 { 448 const PCIDevice *pdev = bus->devices[devfn]; 449 450 if (PCI_FUNC(devfn)) { 451 if (IS_PCI_BRIDGE(pdev)) { 452 /* 453 * Ignore only hotplugged PCI bridges on !0 functions, but 454 * allow describing cold plugged bridges on all functions 455 */ 456 if (DEVICE(pdev)->hotplugged) { 457 return true; 458 } 459 } 460 } 461 return false; 462 } 463 464 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 465 { 466 PCIDevice *pdev = bus->devices[devfn]; 467 if (pdev) { 468 return is_devfn_ignored_generic(devfn, bus) || 469 !DEVICE_GET_CLASS(pdev)->hotpluggable || 470 /* Cold plugged bridges aren't themselves hot-pluggable */ 471 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 472 } else { /* non populated slots */ 473 /* 474 * hotplug is supported only for non-multifunction device 475 * so generate device description only for function 0 476 */ 477 if (PCI_FUNC(devfn) || 478 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 479 return true; 480 } 481 } 482 return false; 483 } 484 485 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) 486 { 487 int devfn; 488 Aml *dev, *notify_method = NULL, *method; 489 QObject *bsel = object_property_get_qobject(OBJECT(bus), 490 ACPI_PCIHP_PROP_BSEL, NULL); 491 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 492 qobject_unref(bsel); 493 494 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 495 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 496 497 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 498 int slot = PCI_SLOT(devfn); 499 int adr = slot << 16 | PCI_FUNC(devfn); 500 501 if (is_devfn_ignored_hotplug(devfn, bus)) { 502 continue; 503 } 504 505 if (bus->devices[devfn]) { 506 dev = aml_scope("S%.02X", devfn); 507 } else { 508 dev = aml_device("S%.02X", devfn); 509 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 510 } 511 512 /* 513 * Can't declare _SUN here for every device as it changes 'slot' 514 * enumeration order in linux kernel, so use another variable for it 515 */ 516 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 517 aml_append(dev, aml_pci_device_dsm()); 518 519 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 520 /* add _EJ0 to make slot hotpluggable */ 521 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 522 aml_append(method, 523 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 524 ); 525 aml_append(dev, method); 526 527 build_append_pcihp_notify_entry(notify_method, slot); 528 529 /* device descriptor has been composed, add it into parent context */ 530 aml_append(parent_scope, dev); 531 } 532 aml_append(parent_scope, notify_method); 533 } 534 535 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 536 { 537 int devfn; 538 Aml *dev; 539 540 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 541 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 542 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 543 PCIDevice *pdev = bus->devices[devfn]; 544 545 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 546 continue; 547 } 548 549 /* start to compose PCI device descriptor */ 550 dev = aml_device("S%.02X", devfn); 551 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 552 553 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 554 /* add _DSM if device has acpi-index set */ 555 if (pdev->acpi_index && 556 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 557 &error_abort)) { 558 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 559 } 560 561 /* device descriptor has been composed, add it into parent context */ 562 aml_append(parent_scope, dev); 563 } 564 } 565 566 /* 567 * build_prt - Define interrupt routing rules 568 * 569 * Returns an array of 128 routes, one for each device, 570 * based on device location. 571 * The main goal is to equally distribute the interrupts 572 * over the 4 existing ACPI links (works only for i440fx). 573 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]". 574 * 575 */ 576 static Aml *build_prt(bool is_pci0_prt) 577 { 578 const int nroutes = 128; 579 Aml *rt_pkg, *method; 580 int pin; 581 582 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 583 assert(nroutes < 256); 584 rt_pkg = aml_package(nroutes); 585 586 for (pin = 0; pin < nroutes; pin++) { 587 Aml *pkg = aml_package(4); 588 int slot = pin >> 2; 589 590 aml_append(pkg, aml_int((slot << 16) | 0xFFFF)); 591 aml_append(pkg, aml_int(pin & 3)); 592 /* device 1 is the power-management device, needs SCI */ 593 if (is_pci0_prt && pin == 4) { 594 aml_append(pkg, aml_name("%s", "LNKS")); 595 } else { 596 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"}; 597 int hash = (slot + pin) & 3; 598 aml_append(pkg, aml_name("%s", link_name[hash])); 599 } 600 aml_append(pkg, aml_int(0)); 601 aml_append(rt_pkg, pkg); 602 } 603 604 aml_append(method, aml_return(rt_pkg)); 605 606 return method; 607 } 608 609 static void build_hpet_aml(Aml *table) 610 { 611 Aml *crs; 612 Aml *field; 613 Aml *method; 614 Aml *if_ctx; 615 Aml *scope = aml_scope("_SB"); 616 Aml *dev = aml_device("HPET"); 617 Aml *zero = aml_int(0); 618 Aml *id = aml_local(0); 619 Aml *period = aml_local(1); 620 621 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 622 aml_append(dev, aml_name_decl("_UID", zero)); 623 624 aml_append(dev, 625 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 626 HPET_LEN)); 627 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 628 aml_append(field, aml_named_field("VEND", 32)); 629 aml_append(field, aml_named_field("PRD", 32)); 630 aml_append(dev, field); 631 632 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 633 aml_append(method, aml_store(aml_name("VEND"), id)); 634 aml_append(method, aml_store(aml_name("PRD"), period)); 635 aml_append(method, aml_shiftright(id, aml_int(16), id)); 636 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 637 aml_equal(id, aml_int(0xffff)))); 638 { 639 aml_append(if_ctx, aml_return(zero)); 640 } 641 aml_append(method, if_ctx); 642 643 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 644 aml_lgreater(period, aml_int(100000000)))); 645 { 646 aml_append(if_ctx, aml_return(zero)); 647 } 648 aml_append(method, if_ctx); 649 650 aml_append(method, aml_return(aml_int(0x0F))); 651 aml_append(dev, method); 652 653 crs = aml_resource_template(); 654 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 655 aml_append(dev, aml_name_decl("_CRS", crs)); 656 657 aml_append(scope, dev); 658 aml_append(table, scope); 659 } 660 661 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 662 { 663 Aml *dev; 664 Aml *method; 665 Aml *crs; 666 667 dev = aml_device("VMBS"); 668 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 669 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 670 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 671 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 672 673 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 674 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 675 aml_name("STA"))); 676 aml_append(dev, method); 677 678 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 679 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 680 aml_name("STA"))); 681 aml_append(dev, method); 682 683 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 684 aml_append(method, aml_return(aml_name("STA"))); 685 aml_append(dev, method); 686 687 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 688 689 crs = aml_resource_template(); 690 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 691 aml_append(dev, aml_name_decl("_CRS", crs)); 692 693 return dev; 694 } 695 696 static void build_dbg_aml(Aml *table) 697 { 698 Aml *field; 699 Aml *method; 700 Aml *while_ctx; 701 Aml *scope = aml_scope("\\"); 702 Aml *buf = aml_local(0); 703 Aml *len = aml_local(1); 704 Aml *idx = aml_local(2); 705 706 aml_append(scope, 707 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 708 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 709 aml_append(field, aml_named_field("DBGB", 8)); 710 aml_append(scope, field); 711 712 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 713 714 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 715 aml_append(method, aml_to_buffer(buf, buf)); 716 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 717 aml_append(method, aml_store(aml_int(0), idx)); 718 719 while_ctx = aml_while(aml_lless(idx, len)); 720 aml_append(while_ctx, 721 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 722 aml_append(while_ctx, aml_increment(idx)); 723 aml_append(method, while_ctx); 724 725 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 726 aml_append(scope, method); 727 728 aml_append(table, scope); 729 } 730 731 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 732 { 733 Aml *dev; 734 Aml *crs; 735 Aml *method; 736 uint32_t irqs[] = {5, 10, 11}; 737 738 dev = aml_device("%s", name); 739 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 740 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 741 742 crs = aml_resource_template(); 743 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 744 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 745 aml_append(dev, aml_name_decl("_PRS", crs)); 746 747 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 748 aml_append(method, aml_return(aml_call1("IQST", reg))); 749 aml_append(dev, method); 750 751 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 752 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 753 aml_append(dev, method); 754 755 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 756 aml_append(method, aml_return(aml_call1("IQCR", reg))); 757 aml_append(dev, method); 758 759 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 760 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 761 aml_append(method, aml_store(aml_name("PRRI"), reg)); 762 aml_append(dev, method); 763 764 return dev; 765 } 766 767 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 768 { 769 Aml *dev; 770 Aml *crs; 771 Aml *method; 772 uint32_t irqs; 773 774 dev = aml_device("%s", name); 775 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 776 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 777 778 crs = aml_resource_template(); 779 irqs = gsi; 780 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 781 AML_SHARED, &irqs, 1)); 782 aml_append(dev, aml_name_decl("_PRS", crs)); 783 784 aml_append(dev, aml_name_decl("_CRS", crs)); 785 786 /* 787 * _DIS can be no-op because the interrupt cannot be disabled. 788 */ 789 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 790 aml_append(dev, method); 791 792 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 793 aml_append(dev, method); 794 795 return dev; 796 } 797 798 /* _CRS method - get current settings */ 799 static Aml *build_iqcr_method(bool is_piix4) 800 { 801 Aml *if_ctx; 802 uint32_t irqs; 803 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 804 Aml *crs = aml_resource_template(); 805 806 irqs = 0; 807 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 808 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 809 aml_append(method, aml_name_decl("PRR0", crs)); 810 811 aml_append(method, 812 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 813 814 if (is_piix4) { 815 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 816 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 817 aml_append(method, if_ctx); 818 } else { 819 aml_append(method, 820 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 821 aml_name("PRRI"))); 822 } 823 824 aml_append(method, aml_return(aml_name("PRR0"))); 825 return method; 826 } 827 828 /* _STA method - get status */ 829 static Aml *build_irq_status_method(void) 830 { 831 Aml *if_ctx; 832 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 833 834 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 835 aml_append(if_ctx, aml_return(aml_int(0x09))); 836 aml_append(method, if_ctx); 837 aml_append(method, aml_return(aml_int(0x0B))); 838 return method; 839 } 840 841 static void build_piix4_pci0_int(Aml *table) 842 { 843 Aml *dev; 844 Aml *crs; 845 Aml *method; 846 uint32_t irqs; 847 Aml *sb_scope = aml_scope("_SB"); 848 Aml *pci0_scope = aml_scope("PCI0"); 849 850 aml_append(pci0_scope, build_prt(true)); 851 aml_append(sb_scope, pci0_scope); 852 853 aml_append(sb_scope, build_irq_status_method()); 854 aml_append(sb_scope, build_iqcr_method(true)); 855 856 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 857 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 858 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 859 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 860 861 dev = aml_device("LNKS"); 862 { 863 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 864 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 865 866 crs = aml_resource_template(); 867 irqs = 9; 868 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 869 AML_ACTIVE_HIGH, AML_SHARED, 870 &irqs, 1)); 871 aml_append(dev, aml_name_decl("_PRS", crs)); 872 873 /* The SCI cannot be disabled and is always attached to GSI 9, 874 * so these are no-ops. We only need this link to override the 875 * polarity to active high and match the content of the MADT. 876 */ 877 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 878 aml_append(method, aml_return(aml_int(0x0b))); 879 aml_append(dev, method); 880 881 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 882 aml_append(dev, method); 883 884 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 885 aml_append(method, aml_return(aml_name("_PRS"))); 886 aml_append(dev, method); 887 888 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 889 aml_append(dev, method); 890 } 891 aml_append(sb_scope, dev); 892 893 aml_append(table, sb_scope); 894 } 895 896 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 897 { 898 int i; 899 int head; 900 Aml *pkg; 901 char base = name[3] < 'E' ? 'A' : 'E'; 902 char *s = g_strdup(name); 903 Aml *a_nr = aml_int((nr << 16) | 0xffff); 904 905 assert(strlen(s) == 4); 906 907 head = name[3] - base; 908 for (i = 0; i < 4; i++) { 909 if (head + i > 3) { 910 head = i * -1; 911 } 912 s[3] = base + head + i; 913 pkg = aml_package(4); 914 aml_append(pkg, a_nr); 915 aml_append(pkg, aml_int(i)); 916 aml_append(pkg, aml_name("%s", s)); 917 aml_append(pkg, aml_int(0)); 918 aml_append(ctx, pkg); 919 } 920 g_free(s); 921 } 922 923 static Aml *build_q35_routing_table(const char *str) 924 { 925 int i; 926 Aml *pkg; 927 char *name = g_strdup_printf("%s ", str); 928 929 pkg = aml_package(128); 930 for (i = 0; i < 0x18; i++) { 931 name[3] = 'E' + (i & 0x3); 932 append_q35_prt_entry(pkg, i, name); 933 } 934 935 name[3] = 'E'; 936 append_q35_prt_entry(pkg, 0x18, name); 937 938 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 939 for (i = 0x0019; i < 0x1e; i++) { 940 name[3] = 'A'; 941 append_q35_prt_entry(pkg, i, name); 942 } 943 944 /* PCIe->PCI bridge. use PIRQ[E-H] */ 945 name[3] = 'E'; 946 append_q35_prt_entry(pkg, 0x1e, name); 947 name[3] = 'A'; 948 append_q35_prt_entry(pkg, 0x1f, name); 949 950 g_free(name); 951 return pkg; 952 } 953 954 static void build_q35_pci0_int(Aml *table) 955 { 956 Aml *method; 957 Aml *sb_scope = aml_scope("_SB"); 958 Aml *pci0_scope = aml_scope("PCI0"); 959 960 /* Zero => PIC mode, One => APIC Mode */ 961 aml_append(table, aml_name_decl("PICF", aml_int(0))); 962 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 963 { 964 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 965 } 966 aml_append(table, method); 967 968 aml_append(pci0_scope, 969 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 970 aml_append(pci0_scope, 971 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 972 973 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 974 { 975 Aml *if_ctx; 976 Aml *else_ctx; 977 978 /* PCI IRQ routing table, example from ACPI 2.0a specification, 979 section 6.2.8.1 */ 980 /* Note: we provide the same info as the PCI routing 981 table of the Bochs BIOS */ 982 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 983 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 984 aml_append(method, if_ctx); 985 else_ctx = aml_else(); 986 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 987 aml_append(method, else_ctx); 988 } 989 aml_append(pci0_scope, method); 990 aml_append(sb_scope, pci0_scope); 991 992 aml_append(sb_scope, build_irq_status_method()); 993 aml_append(sb_scope, build_iqcr_method(false)); 994 995 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 996 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 997 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 998 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 999 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1000 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1001 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1002 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1003 1004 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1005 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1006 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1007 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1008 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1009 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1010 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1011 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1012 1013 aml_append(table, sb_scope); 1014 } 1015 1016 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1017 { 1018 Aml *dev; 1019 Aml *resource_template; 1020 1021 /* DRAM controller */ 1022 dev = aml_device("DRAC"); 1023 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1024 1025 resource_template = aml_resource_template(); 1026 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1027 aml_append(resource_template, 1028 aml_qword_memory(AML_POS_DECODE, 1029 AML_MIN_FIXED, 1030 AML_MAX_FIXED, 1031 AML_NON_CACHEABLE, 1032 AML_READ_WRITE, 1033 0x0000000000000000, 1034 mcfg->base, 1035 mcfg->base + mcfg->size - 1, 1036 0x0000000000000000, 1037 mcfg->size)); 1038 } else { 1039 aml_append(resource_template, 1040 aml_dword_memory(AML_POS_DECODE, 1041 AML_MIN_FIXED, 1042 AML_MAX_FIXED, 1043 AML_NON_CACHEABLE, 1044 AML_READ_WRITE, 1045 0x0000000000000000, 1046 mcfg->base, 1047 mcfg->base + mcfg->size - 1, 1048 0x0000000000000000, 1049 mcfg->size)); 1050 } 1051 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1052 1053 return dev; 1054 } 1055 1056 static void build_acpi0017(Aml *table) 1057 { 1058 Aml *dev, *scope, *method; 1059 1060 scope = aml_scope("_SB"); 1061 dev = aml_device("CXLM"); 1062 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1063 1064 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1065 aml_append(method, aml_return(aml_int(0x0B))); 1066 aml_append(dev, method); 1067 build_cxl_dsm_method(dev); 1068 1069 aml_append(scope, dev); 1070 aml_append(table, scope); 1071 } 1072 1073 static void 1074 build_dsdt(GArray *table_data, BIOSLinker *linker, 1075 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1076 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1077 { 1078 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE, 1079 NULL); 1080 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL); 1081 CrsRangeEntry *entry; 1082 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1083 CrsRangeSet crs_range_set; 1084 PCMachineState *pcms = PC_MACHINE(machine); 1085 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1086 X86MachineState *x86ms = X86_MACHINE(machine); 1087 AcpiMcfgInfo mcfg; 1088 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1089 uint32_t nr_mem = machine->ram_slots; 1090 int root_bus_limit = 0xFF; 1091 PCIBus *bus = NULL; 1092 #ifdef CONFIG_TPM 1093 TPMIf *tpm = tpm_find(); 1094 #endif 1095 bool cxl_present = false; 1096 int i; 1097 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1098 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1099 .oem_table_id = x86ms->oem_table_id }; 1100 1101 assert(!!i440fx != !!q35); 1102 1103 acpi_table_begin(&table, table_data); 1104 dsdt = init_aml_allocator(); 1105 1106 build_dbg_aml(dsdt); 1107 if (i440fx) { 1108 sb_scope = aml_scope("_SB"); 1109 dev = aml_device("PCI0"); 1110 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1111 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1112 aml_append(dev, aml_pci_edsm()); 1113 aml_append(sb_scope, dev); 1114 aml_append(dsdt, sb_scope); 1115 1116 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1117 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); 1118 } 1119 build_piix4_pci0_int(dsdt); 1120 } else if (q35) { 1121 sb_scope = aml_scope("_SB"); 1122 dev = aml_device("PCI0"); 1123 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1124 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1125 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1126 aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en)); 1127 aml_append(dev, aml_pci_edsm()); 1128 aml_append(sb_scope, dev); 1129 if (mcfg_valid) { 1130 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1131 } 1132 1133 if (pm->smi_on_cpuhp) { 1134 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1135 dev = aml_device("PCI0.SMI0"); 1136 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1137 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1138 crs = aml_resource_template(); 1139 aml_append(crs, 1140 aml_io( 1141 AML_DECODE16, 1142 pm->fadt.smi_cmd, 1143 pm->fadt.smi_cmd, 1144 1, 1145 2) 1146 ); 1147 aml_append(dev, aml_name_decl("_CRS", crs)); 1148 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1149 aml_int(pm->fadt.smi_cmd), 2)); 1150 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1151 AML_WRITE_AS_ZEROS); 1152 aml_append(field, aml_named_field("SMIC", 8)); 1153 aml_append(field, aml_reserved_field(8)); 1154 aml_append(dev, field); 1155 aml_append(sb_scope, dev); 1156 } 1157 1158 aml_append(dsdt, sb_scope); 1159 1160 if (pm->pcihp_bridge_en) { 1161 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); 1162 } 1163 build_q35_pci0_int(dsdt); 1164 } 1165 1166 if (misc->has_hpet) { 1167 build_hpet_aml(dsdt); 1168 } 1169 1170 if (vmbus_bridge) { 1171 sb_scope = aml_scope("_SB"); 1172 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1173 aml_append(dsdt, sb_scope); 1174 } 1175 1176 scope = aml_scope("_GPE"); 1177 { 1178 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1179 if (machine->nvdimms_state->is_enabled) { 1180 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1181 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1182 aml_int(0x80))); 1183 aml_append(scope, method); 1184 } 1185 } 1186 aml_append(dsdt, scope); 1187 1188 if (pcmc->legacy_cpu_hotplug) { 1189 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1190 } else { 1191 CPUHotplugFeatures opts = { 1192 .acpi_1_compatible = true, .has_legacy_cphp = true, 1193 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1194 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1195 }; 1196 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, 1197 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", 1198 AML_SYSTEM_IO); 1199 } 1200 1201 if (pcms->memhp_io_base && nr_mem) { 1202 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1203 "\\_GPE._E03", AML_SYSTEM_IO, 1204 pcms->memhp_io_base); 1205 } 1206 1207 crs_range_set_init(&crs_range_set); 1208 bus = PC_MACHINE(machine)->pcibus; 1209 if (bus) { 1210 QLIST_FOREACH(bus, &bus->child, sibling) { 1211 uint8_t bus_num = pci_bus_num(bus); 1212 uint8_t numa_node = pci_bus_numa_node(bus); 1213 uint32_t uid; 1214 1215 /* look only for expander root buses */ 1216 if (!pci_bus_is_root(bus)) { 1217 continue; 1218 } 1219 1220 if (bus_num < root_bus_limit) { 1221 root_bus_limit = bus_num - 1; 1222 } 1223 1224 uid = object_property_get_uint(OBJECT(bus), "acpi_uid", 1225 &error_fatal); 1226 scope = aml_scope("\\_SB"); 1227 1228 if (pci_bus_is_cxl(bus)) { 1229 dev = aml_device("CL%.02X", bus_num); 1230 } else { 1231 dev = aml_device("PC%.02X", bus_num); 1232 } 1233 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1234 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1235 if (pci_bus_is_cxl(bus)) { 1236 struct Aml *aml_pkg = aml_package(2); 1237 1238 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1239 aml_append(aml_pkg, aml_eisaid("PNP0A08")); 1240 aml_append(aml_pkg, aml_eisaid("PNP0A03")); 1241 aml_append(dev, aml_name_decl("_CID", aml_pkg)); 1242 build_cxl_osc_method(dev); 1243 } else if (pci_bus_is_express(bus)) { 1244 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1245 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1246 1247 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1248 aml_append(dev, build_pci_host_bridge_osc_method(true)); 1249 } else { 1250 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1251 } 1252 1253 if (numa_node != NUMA_NODE_UNASSIGNED) { 1254 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1255 } 1256 1257 aml_append(dev, build_prt(false)); 1258 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1259 0, 0, 0, 0); 1260 aml_append(dev, aml_name_decl("_CRS", crs)); 1261 aml_append(scope, dev); 1262 aml_append(dsdt, scope); 1263 1264 /* Handle the ranges for the PXB expanders */ 1265 if (pci_bus_is_cxl(bus)) { 1266 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1267 uint64_t base = mr->addr; 1268 1269 cxl_present = true; 1270 crs_range_insert(crs_range_set.mem_ranges, base, 1271 base + memory_region_size(mr) - 1); 1272 } 1273 } 1274 } 1275 1276 if (cxl_present) { 1277 build_acpi0017(dsdt); 1278 } 1279 1280 /* 1281 * At this point crs_range_set has all the ranges used by pci 1282 * busses *other* than PCI0. These ranges will be excluded from 1283 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1284 * too. 1285 */ 1286 if (mcfg_valid) { 1287 crs_range_insert(crs_range_set.mem_ranges, 1288 mcfg.base, mcfg.base + mcfg.size - 1); 1289 } 1290 1291 scope = aml_scope("\\_SB.PCI0"); 1292 /* build PCI0._CRS */ 1293 crs = aml_resource_template(); 1294 aml_append(crs, 1295 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1296 0x0000, 0x0, root_bus_limit, 1297 0x0000, root_bus_limit + 1)); 1298 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1299 1300 aml_append(crs, 1301 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1302 AML_POS_DECODE, AML_ENTIRE_RANGE, 1303 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1304 1305 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1306 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1307 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1308 aml_append(crs, 1309 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1310 AML_POS_DECODE, AML_ENTIRE_RANGE, 1311 0x0000, entry->base, entry->limit, 1312 0x0000, entry->limit - entry->base + 1)); 1313 } 1314 1315 aml_append(crs, 1316 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1317 AML_CACHEABLE, AML_READ_WRITE, 1318 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1319 1320 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1321 range_lob(pci_hole), 1322 range_upb(pci_hole)); 1323 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1324 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1325 aml_append(crs, 1326 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1327 AML_NON_CACHEABLE, AML_READ_WRITE, 1328 0, entry->base, entry->limit, 1329 0, entry->limit - entry->base + 1)); 1330 } 1331 1332 if (!range_is_empty(pci_hole64)) { 1333 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1334 range_lob(pci_hole64), 1335 range_upb(pci_hole64)); 1336 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1337 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1338 aml_append(crs, 1339 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1340 AML_MAX_FIXED, 1341 AML_CACHEABLE, AML_READ_WRITE, 1342 0, entry->base, entry->limit, 1343 0, entry->limit - entry->base + 1)); 1344 } 1345 } 1346 1347 #ifdef CONFIG_TPM 1348 if (TPM_IS_TIS_ISA(tpm_find())) { 1349 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1350 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1351 } 1352 #endif 1353 aml_append(scope, aml_name_decl("_CRS", crs)); 1354 1355 /* reserve GPE0 block resources */ 1356 dev = aml_device("GPE0"); 1357 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1358 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1359 /* device present, functioning, decoding, not shown in UI */ 1360 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1361 crs = aml_resource_template(); 1362 aml_append(crs, 1363 aml_io( 1364 AML_DECODE16, 1365 pm->fadt.gpe0_blk.address, 1366 pm->fadt.gpe0_blk.address, 1367 1, 1368 pm->fadt.gpe0_blk.bit_width / 8) 1369 ); 1370 aml_append(dev, aml_name_decl("_CRS", crs)); 1371 aml_append(scope, dev); 1372 1373 crs_range_set_free(&crs_range_set); 1374 1375 /* reserve PCIHP resources */ 1376 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1377 build_append_pcihp_resources(scope, 1378 pm->pcihp_io_base, pm->pcihp_io_len); 1379 } 1380 aml_append(dsdt, scope); 1381 1382 /* create S3_ / S4_ / S5_ packages if necessary */ 1383 scope = aml_scope("\\"); 1384 if (!pm->s3_disabled) { 1385 pkg = aml_package(4); 1386 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1387 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1388 aml_append(pkg, aml_int(0)); /* reserved */ 1389 aml_append(pkg, aml_int(0)); /* reserved */ 1390 aml_append(scope, aml_name_decl("_S3", pkg)); 1391 } 1392 1393 if (!pm->s4_disabled) { 1394 pkg = aml_package(4); 1395 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1396 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1397 aml_append(pkg, aml_int(pm->s4_val)); 1398 aml_append(pkg, aml_int(0)); /* reserved */ 1399 aml_append(pkg, aml_int(0)); /* reserved */ 1400 aml_append(scope, aml_name_decl("_S4", pkg)); 1401 } 1402 1403 pkg = aml_package(4); 1404 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1405 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1406 aml_append(pkg, aml_int(0)); /* reserved */ 1407 aml_append(pkg, aml_int(0)); /* reserved */ 1408 aml_append(scope, aml_name_decl("_S5", pkg)); 1409 aml_append(dsdt, scope); 1410 1411 /* create fw_cfg node, unconditionally */ 1412 { 1413 scope = aml_scope("\\_SB.PCI0"); 1414 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1415 aml_append(dsdt, scope); 1416 } 1417 1418 sb_scope = aml_scope("\\_SB"); 1419 { 1420 Object *pci_host = acpi_get_i386_pci_host(); 1421 1422 if (pci_host) { 1423 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; 1424 Aml *ascope = aml_scope("PCI0"); 1425 /* Scan all PCI buses. Generate tables to support hotplug. */ 1426 build_append_pci_bus_devices(ascope, pbus); 1427 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) { 1428 build_append_pcihp_slots(ascope, pbus); 1429 } 1430 aml_append(sb_scope, ascope); 1431 } 1432 } 1433 1434 #ifdef CONFIG_TPM 1435 if (TPM_IS_CRB(tpm)) { 1436 dev = aml_device("TPM"); 1437 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1438 aml_append(dev, aml_name_decl("_STR", 1439 aml_string("TPM 2.0 Device"))); 1440 crs = aml_resource_template(); 1441 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1442 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1443 aml_append(dev, aml_name_decl("_CRS", crs)); 1444 1445 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1446 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1447 1448 tpm_build_ppi_acpi(tpm, dev); 1449 1450 aml_append(sb_scope, dev); 1451 } 1452 #endif 1453 1454 if (pcms->sgx_epc.size != 0) { 1455 uint64_t epc_base = pcms->sgx_epc.base; 1456 uint64_t epc_size = pcms->sgx_epc.size; 1457 1458 dev = aml_device("EPC"); 1459 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1460 aml_append(dev, aml_name_decl("_STR", 1461 aml_unicode("Enclave Page Cache 1.0"))); 1462 crs = aml_resource_template(); 1463 aml_append(crs, 1464 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1465 AML_MAX_FIXED, AML_NON_CACHEABLE, 1466 AML_READ_WRITE, 0, epc_base, 1467 epc_base + epc_size - 1, 0, epc_size)); 1468 aml_append(dev, aml_name_decl("_CRS", crs)); 1469 1470 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1471 aml_append(method, aml_return(aml_int(0x0f))); 1472 aml_append(dev, method); 1473 1474 aml_append(sb_scope, dev); 1475 } 1476 aml_append(dsdt, sb_scope); 1477 1478 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1479 bool has_pcnt; 1480 1481 Object *pci_host = acpi_get_i386_pci_host(); 1482 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; 1483 1484 scope = aml_scope("\\_SB.PCI0"); 1485 has_pcnt = build_append_notification_callback(scope, b); 1486 if (has_pcnt) { 1487 aml_append(dsdt, scope); 1488 } 1489 1490 scope = aml_scope("_GPE"); 1491 { 1492 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1493 if (has_pcnt) { 1494 aml_append(method, 1495 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1496 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1497 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1498 } 1499 aml_append(scope, method); 1500 } 1501 aml_append(dsdt, scope); 1502 } 1503 1504 /* copy AML table into ACPI tables blob and patch header there */ 1505 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1506 acpi_table_end(linker, &table); 1507 free_aml_allocator(); 1508 } 1509 1510 /* 1511 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1512 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1513 */ 1514 static void 1515 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1516 const char *oem_table_id) 1517 { 1518 AcpiTable table = { .sig = "HPET", .rev = 1, 1519 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1520 1521 acpi_table_begin(&table, table_data); 1522 /* Note timer_block_id value must be kept in sync with value advertised by 1523 * emulated hpet 1524 */ 1525 /* Event Timer Block ID */ 1526 build_append_int_noprefix(table_data, 0x8086a201, 4); 1527 /* BASE_ADDRESS */ 1528 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1529 /* HPET Number */ 1530 build_append_int_noprefix(table_data, 0, 1); 1531 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1532 build_append_int_noprefix(table_data, 0, 2); 1533 /* Page Protection And OEM Attribute */ 1534 build_append_int_noprefix(table_data, 0, 1); 1535 acpi_table_end(linker, &table); 1536 } 1537 1538 #ifdef CONFIG_TPM 1539 /* 1540 * TCPA Description Table 1541 * 1542 * Following Level 00, Rev 00.37 of specs: 1543 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1544 * 7.1.2 ACPI Table Layout 1545 */ 1546 static void 1547 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1548 const char *oem_id, const char *oem_table_id) 1549 { 1550 unsigned log_addr_offset; 1551 AcpiTable table = { .sig = "TCPA", .rev = 2, 1552 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1553 1554 acpi_table_begin(&table, table_data); 1555 /* Platform Class */ 1556 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1557 /* Log Area Minimum Length (LAML) */ 1558 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1559 /* Log Area Start Address (LASA) */ 1560 log_addr_offset = table_data->len; 1561 build_append_int_noprefix(table_data, 0, 8); 1562 1563 /* allocate/reserve space for TPM log area */ 1564 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1565 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1566 false /* high memory */); 1567 /* log area start address to be filled by Guest linker */ 1568 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1569 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1570 1571 acpi_table_end(linker, &table); 1572 } 1573 #endif 1574 1575 #define HOLE_640K_START (640 * KiB) 1576 #define HOLE_640K_END (1 * MiB) 1577 1578 /* 1579 * ACPI spec, Revision 3.0 1580 * 5.2.15 System Resource Affinity Table (SRAT) 1581 */ 1582 static void 1583 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1584 { 1585 int i; 1586 int numa_mem_start, slots; 1587 uint64_t mem_len, mem_base, next_base; 1588 MachineClass *mc = MACHINE_GET_CLASS(machine); 1589 X86MachineState *x86ms = X86_MACHINE(machine); 1590 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1591 int nb_numa_nodes = machine->numa_state->num_nodes; 1592 NodeInfo *numa_info = machine->numa_state->nodes; 1593 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1594 .oem_table_id = x86ms->oem_table_id }; 1595 1596 acpi_table_begin(&table, table_data); 1597 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1598 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1599 1600 for (i = 0; i < apic_ids->len; i++) { 1601 int node_id = apic_ids->cpus[i].props.node_id; 1602 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1603 1604 if (apic_id < 255) { 1605 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1606 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1607 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1608 /* Proximity Domain [7:0] */ 1609 build_append_int_noprefix(table_data, node_id, 1); 1610 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1611 /* Flags, Table 5-36 */ 1612 build_append_int_noprefix(table_data, 1, 4); 1613 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1614 /* Proximity Domain [31:8] */ 1615 build_append_int_noprefix(table_data, 0, 3); 1616 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1617 } else { 1618 /* 1619 * ACPI spec, Revision 4.0 1620 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1621 */ 1622 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1623 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1624 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1625 /* Proximity Domain */ 1626 build_append_int_noprefix(table_data, node_id, 4); 1627 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1628 /* Flags, Table 5-39 */ 1629 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1630 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1631 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1632 } 1633 } 1634 1635 /* the memory map is a bit tricky, it contains at least one hole 1636 * from 640k-1M and possibly another one from 3.5G-4G. 1637 */ 1638 next_base = 0; 1639 numa_mem_start = table_data->len; 1640 1641 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1642 mem_base = next_base; 1643 mem_len = numa_info[i - 1].node_mem; 1644 next_base = mem_base + mem_len; 1645 1646 /* Cut out the 640K hole */ 1647 if (mem_base <= HOLE_640K_START && 1648 next_base > HOLE_640K_START) { 1649 mem_len -= next_base - HOLE_640K_START; 1650 if (mem_len > 0) { 1651 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1652 MEM_AFFINITY_ENABLED); 1653 } 1654 1655 /* Check for the rare case: 640K < RAM < 1M */ 1656 if (next_base <= HOLE_640K_END) { 1657 next_base = HOLE_640K_END; 1658 continue; 1659 } 1660 mem_base = HOLE_640K_END; 1661 mem_len = next_base - HOLE_640K_END; 1662 } 1663 1664 /* Cut out the ACPI_PCI hole */ 1665 if (mem_base <= x86ms->below_4g_mem_size && 1666 next_base > x86ms->below_4g_mem_size) { 1667 mem_len -= next_base - x86ms->below_4g_mem_size; 1668 if (mem_len > 0) { 1669 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1670 MEM_AFFINITY_ENABLED); 1671 } 1672 mem_base = x86ms->above_4g_mem_start; 1673 mem_len = next_base - x86ms->below_4g_mem_size; 1674 next_base = mem_base + mem_len; 1675 } 1676 1677 if (mem_len > 0) { 1678 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1679 MEM_AFFINITY_ENABLED); 1680 } 1681 } 1682 1683 if (machine->nvdimms_state->is_enabled) { 1684 nvdimm_build_srat(table_data); 1685 } 1686 1687 sgx_epc_build_srat(table_data); 1688 1689 /* 1690 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1691 * without these entries. But I recall there were issues the last time I 1692 * tried to remove it with some ancient guest OS, however I can't remember 1693 * what that was so keep this around for now 1694 */ 1695 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1696 for (; slots < nb_numa_nodes + 2; slots++) { 1697 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1698 } 1699 1700 build_srat_generic_affinity_structures(table_data); 1701 1702 /* 1703 * Entry is required for Windows to enable memory hotplug in OS 1704 * and for Linux to enable SWIOTLB when booted with less than 1705 * 4G of RAM. Windows works better if the entry sets proximity 1706 * to the highest NUMA node in the machine. 1707 * Memory devices may override proximity set by this entry, 1708 * providing _PXM method if necessary. 1709 */ 1710 if (machine->device_memory) { 1711 build_srat_memory(table_data, machine->device_memory->base, 1712 memory_region_size(&machine->device_memory->mr), 1713 nb_numa_nodes - 1, 1714 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1715 } 1716 1717 acpi_table_end(linker, &table); 1718 } 1719 1720 /* 1721 * Insert DMAR scope for PCI bridges and endpoint devices 1722 */ 1723 static void 1724 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1725 { 1726 const size_t device_scope_size = 6 /* device scope structure */ + 1727 2 /* 1 path entry */; 1728 GArray *scope_blob = opaque; 1729 1730 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1731 /* Dmar Scope Type: 0x02 for PCI Bridge */ 1732 build_append_int_noprefix(scope_blob, 0x02, 1); 1733 } else { 1734 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 1735 build_append_int_noprefix(scope_blob, 0x01, 1); 1736 } 1737 1738 /* length */ 1739 build_append_int_noprefix(scope_blob, device_scope_size, 1); 1740 /* reserved */ 1741 build_append_int_noprefix(scope_blob, 0, 2); 1742 /* enumeration_id */ 1743 build_append_int_noprefix(scope_blob, 0, 1); 1744 /* bus */ 1745 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 1746 /* device */ 1747 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 1748 /* function */ 1749 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 1750 } 1751 1752 /* For a given PCI host bridge, walk and insert DMAR scope */ 1753 static int 1754 dmar_host_bridges(Object *obj, void *opaque) 1755 { 1756 GArray *scope_blob = opaque; 1757 1758 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1759 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 1760 1761 if (bus && !pci_bus_bypass_iommu(bus)) { 1762 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 1763 } 1764 } 1765 1766 return 0; 1767 } 1768 1769 /* 1770 * Intel ® Virtualization Technology for Directed I/O 1771 * Architecture Specification. Revision 3.3 1772 * 8.1 DMA Remapping Reporting Structure 1773 */ 1774 static void 1775 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1776 const char *oem_table_id) 1777 { 1778 uint8_t dmar_flags = 0; 1779 uint8_t rsvd10[10] = {}; 1780 /* Root complex IOAPIC uses one path only */ 1781 const size_t ioapic_scope_size = 6 /* device scope structure */ + 1782 2 /* 1 path entry */; 1783 X86IOMMUState *iommu = x86_iommu_get_default(); 1784 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1785 GArray *scope_blob = g_array_new(false, true, 1); 1786 1787 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 1788 .oem_table_id = oem_table_id }; 1789 1790 /* 1791 * A PCI bus walk, for each PCI host bridge. 1792 * Insert scope for each PCI bridge and endpoint device which 1793 * is attached to a bus with iommu enabled. 1794 */ 1795 object_child_foreach_recursive(object_get_root(), 1796 dmar_host_bridges, scope_blob); 1797 1798 assert(iommu); 1799 if (x86_iommu_ir_supported(iommu)) { 1800 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 1801 } 1802 1803 acpi_table_begin(&table, table_data); 1804 /* Host Address Width */ 1805 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 1806 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 1807 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 1808 1809 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 1810 build_append_int_noprefix(table_data, 0, 2); /* Type */ 1811 /* Length */ 1812 build_append_int_noprefix(table_data, 1813 16 + ioapic_scope_size + scope_blob->len, 2); 1814 /* Flags */ 1815 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 1816 1); 1817 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 1818 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 1819 /* Register Base Address */ 1820 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 1821 1822 /* Scope definition for the root-complex IOAPIC. See VT-d spec 1823 * 8.3.1 (version Oct. 2014 or later). */ 1824 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 1825 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 1826 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1827 /* Enumeration ID */ 1828 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 1829 /* Start Bus Number */ 1830 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 1831 /* Path, {Device, Function} pair */ 1832 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 1833 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 1834 1835 /* Add scope found above */ 1836 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 1837 g_array_free(scope_blob, true); 1838 1839 if (iommu->dt_supported) { 1840 /* 8.5 Root Port ATS Capability Reporting Structure */ 1841 build_append_int_noprefix(table_data, 2, 2); /* Type */ 1842 build_append_int_noprefix(table_data, 8, 2); /* Length */ 1843 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 1844 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 1845 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 1846 } 1847 1848 acpi_table_end(linker, &table); 1849 } 1850 1851 /* 1852 * Windows ACPI Emulated Devices Table 1853 * (Version 1.0 - April 6, 2009) 1854 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 1855 * 1856 * Helpful to speedup Windows guests and ignored by others. 1857 */ 1858 static void 1859 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1860 const char *oem_table_id) 1861 { 1862 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 1863 .oem_table_id = oem_table_id }; 1864 1865 acpi_table_begin(&table, table_data); 1866 /* 1867 * Set "ACPI PM timer good" flag. 1868 * 1869 * Tells Windows guests that our ACPI PM timer is reliable in the 1870 * sense that guest can read it only once to obtain a reliable value. 1871 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 1872 */ 1873 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 1874 acpi_table_end(linker, &table); 1875 } 1876 1877 /* 1878 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 1879 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 1880 */ 1881 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 1882 1883 /* 1884 * Insert IVHD entry for device and recurse, insert alias, or insert range as 1885 * necessary for the PCI topology. 1886 */ 1887 static void 1888 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 1889 { 1890 GArray *table_data = opaque; 1891 uint32_t entry; 1892 1893 /* "Select" IVHD entry, type 0x2 */ 1894 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 1895 build_append_int_noprefix(table_data, entry, 4); 1896 1897 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1898 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1899 uint8_t sec = pci_bus_num(sec_bus); 1900 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 1901 1902 if (pci_bus_is_express(sec_bus)) { 1903 /* 1904 * Walk the bus if there are subordinates, otherwise use a range 1905 * to cover an entire leaf bus. We could potentially also use a 1906 * range for traversed buses, but we'd need to take care not to 1907 * create both Select and Range entries covering the same device. 1908 * This is easier and potentially more compact. 1909 * 1910 * An example bare metal system seems to use Select entries for 1911 * root ports without a slot (ie. built-ins) and Range entries 1912 * when there is a slot. The same system also only hard-codes 1913 * the alias range for an onboard PCIe-to-PCI bridge, apparently 1914 * making no effort to support nested bridges. We attempt to 1915 * be more thorough here. 1916 */ 1917 if (sec == sub) { /* leaf bus */ 1918 /* "Start of Range" IVHD entry, type 0x3 */ 1919 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 1920 build_append_int_noprefix(table_data, entry, 4); 1921 /* "End of Range" IVHD entry, type 0x4 */ 1922 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 1923 build_append_int_noprefix(table_data, entry, 4); 1924 } else { 1925 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 1926 } 1927 } else { 1928 /* 1929 * If the secondary bus is conventional, then we need to create an 1930 * Alias range for everything downstream. The range covers the 1931 * first devfn on the secondary bus to the last devfn on the 1932 * subordinate bus. The alias target depends on legacy versus 1933 * express bridges, just as in pci_device_iommu_address_space(). 1934 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 1935 */ 1936 uint16_t dev_id_a, dev_id_b; 1937 1938 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 1939 1940 if (pci_is_express(dev) && 1941 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 1942 dev_id_b = dev_id_a; 1943 } else { 1944 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 1945 } 1946 1947 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 1948 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 1949 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 1950 1951 /* "End of Range" IVHD entry, type 0x4 */ 1952 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 1953 build_append_int_noprefix(table_data, entry, 4); 1954 } 1955 } 1956 } 1957 1958 /* For all PCI host bridges, walk and insert IVHD entries */ 1959 static int 1960 ivrs_host_bridges(Object *obj, void *opaque) 1961 { 1962 GArray *ivhd_blob = opaque; 1963 1964 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1965 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 1966 1967 if (bus && !pci_bus_bypass_iommu(bus)) { 1968 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 1969 } 1970 } 1971 1972 return 0; 1973 } 1974 1975 static void 1976 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1977 const char *oem_table_id) 1978 { 1979 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 1980 GArray *ivhd_blob = g_array_new(false, true, 1); 1981 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 1982 .oem_table_id = oem_table_id }; 1983 uint64_t feature_report; 1984 1985 acpi_table_begin(&table, table_data); 1986 /* IVinfo - IO virtualization information common to all 1987 * IOMMU units in a system 1988 */ 1989 build_append_int_noprefix(table_data, 1990 (1UL << 0) | /* EFRSup */ 1991 (40UL << 8), /* PASize */ 1992 4); 1993 /* reserved */ 1994 build_append_int_noprefix(table_data, 0, 8); 1995 1996 /* 1997 * A PCI bus walk, for each PCI host bridge, is necessary to create a 1998 * complete set of IVHD entries. Do this into a separate blob so that we 1999 * can calculate the total IVRS table length here and then append the new 2000 * blob further below. Fall back to an entry covering all devices, which 2001 * is sufficient when no aliases are present. 2002 */ 2003 object_child_foreach_recursive(object_get_root(), 2004 ivrs_host_bridges, ivhd_blob); 2005 2006 if (!ivhd_blob->len) { 2007 /* 2008 * Type 1 device entry reporting all devices 2009 * These are 4-byte device entries currently reporting the range of 2010 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2011 */ 2012 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2013 } 2014 2015 /* 2016 * When interrupt remapping is supported, we add a special IVHD device 2017 * for type IO-APIC 2018 * Refer to spec - Table 95: IVHD device entry type codes 2019 * 2020 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2021 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2022 */ 2023 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2024 build_append_int_noprefix(ivhd_blob, 2025 (0x1ull << 56) | /* type IOAPIC */ 2026 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2027 0x48, /* special device */ 2028 8); 2029 } 2030 2031 /* IVHD definition - type 10h */ 2032 build_append_int_noprefix(table_data, 0x10, 1); 2033 /* virtualization flags */ 2034 build_append_int_noprefix(table_data, 2035 (1UL << 0) | /* HtTunEn */ 2036 (1UL << 4) | /* iotblSup */ 2037 (1UL << 6) | /* PrefSup */ 2038 (1UL << 7), /* PPRSup */ 2039 1); 2040 2041 /* IVHD length */ 2042 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); 2043 /* DeviceID */ 2044 build_append_int_noprefix(table_data, 2045 object_property_get_int(OBJECT(s->pci), "addr", 2046 &error_abort), 2); 2047 /* Capability offset */ 2048 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); 2049 /* IOMMU base address */ 2050 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 2051 /* PCI Segment Group */ 2052 build_append_int_noprefix(table_data, 0, 2); 2053 /* IOMMU info */ 2054 build_append_int_noprefix(table_data, 0, 2); 2055 /* IOMMU Feature Reporting */ 2056 feature_report = (48UL << 30) | /* HATS */ 2057 (48UL << 28) | /* GATS */ 2058 (1UL << 2) | /* GTSup */ 2059 (1UL << 6); /* GASup */ 2060 if (s->xtsup) { 2061 feature_report |= (1UL << 0); /* XTSup */ 2062 } 2063 build_append_int_noprefix(table_data, feature_report, 4); 2064 2065 /* IVHD entries as found above */ 2066 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2067 2068 /* IVHD definition - type 11h */ 2069 build_append_int_noprefix(table_data, 0x11, 1); 2070 /* virtualization flags */ 2071 build_append_int_noprefix(table_data, 2072 (1UL << 0) | /* HtTunEn */ 2073 (1UL << 4), /* iotblSup */ 2074 1); 2075 2076 /* IVHD length */ 2077 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); 2078 /* DeviceID */ 2079 build_append_int_noprefix(table_data, 2080 object_property_get_int(OBJECT(s->pci), "addr", 2081 &error_abort), 2); 2082 /* Capability offset */ 2083 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); 2084 /* IOMMU base address */ 2085 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 2086 /* PCI Segment Group */ 2087 build_append_int_noprefix(table_data, 0, 2); 2088 /* IOMMU info */ 2089 build_append_int_noprefix(table_data, 0, 2); 2090 /* IOMMU Attributes */ 2091 build_append_int_noprefix(table_data, 0, 4); 2092 /* EFR Register Image */ 2093 build_append_int_noprefix(table_data, 2094 amdvi_extended_feature_register(s), 2095 8); 2096 /* EFR Register Image 2 */ 2097 build_append_int_noprefix(table_data, 0, 8); 2098 2099 /* IVHD entries as found above */ 2100 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2101 2102 g_array_free(ivhd_blob, TRUE); 2103 acpi_table_end(linker, &table); 2104 } 2105 2106 typedef 2107 struct AcpiBuildState { 2108 /* Copy of table in RAM (for patching). */ 2109 MemoryRegion *table_mr; 2110 /* Is table patched? */ 2111 uint8_t patched; 2112 MemoryRegion *rsdp_mr; 2113 MemoryRegion *linker_mr; 2114 } AcpiBuildState; 2115 2116 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2117 { 2118 Object *pci_host; 2119 QObject *o; 2120 2121 pci_host = acpi_get_i386_pci_host(); 2122 if (!pci_host) { 2123 return false; 2124 } 2125 2126 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2127 if (!o) { 2128 return false; 2129 } 2130 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2131 qobject_unref(o); 2132 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2133 return false; 2134 } 2135 2136 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2137 assert(o); 2138 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2139 qobject_unref(o); 2140 return true; 2141 } 2142 2143 static 2144 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2145 { 2146 PCMachineState *pcms = PC_MACHINE(machine); 2147 X86MachineState *x86ms = X86_MACHINE(machine); 2148 DeviceState *iommu = pcms->iommu; 2149 GArray *table_offsets; 2150 unsigned facs, dsdt, rsdt; 2151 AcpiPmInfo pm; 2152 AcpiMiscInfo misc; 2153 AcpiMcfgInfo mcfg; 2154 Range pci_hole = {}, pci_hole64 = {}; 2155 uint8_t *u; 2156 GArray *tables_blob = tables->table_data; 2157 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2158 Object *vmgenid_dev, *vmclock_dev; 2159 char *oem_id; 2160 char *oem_table_id; 2161 2162 acpi_get_pm_info(machine, &pm); 2163 acpi_get_misc_info(&misc); 2164 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2165 acpi_get_slic_oem(&slic_oem); 2166 2167 if (slic_oem.id) { 2168 oem_id = slic_oem.id; 2169 } else { 2170 oem_id = x86ms->oem_id; 2171 } 2172 2173 if (slic_oem.table_id) { 2174 oem_table_id = slic_oem.table_id; 2175 } else { 2176 oem_table_id = x86ms->oem_table_id; 2177 } 2178 2179 table_offsets = g_array_new(false, true /* clear */, 2180 sizeof(uint32_t)); 2181 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2182 2183 bios_linker_loader_alloc(tables->linker, 2184 ACPI_BUILD_TABLE_FILE, tables_blob, 2185 64 /* Ensure FACS is aligned */, 2186 false /* high memory */); 2187 2188 /* 2189 * FACS is pointed to by FADT. 2190 * We place it first since it's the only table that has alignment 2191 * requirements. 2192 */ 2193 facs = tables_blob->len; 2194 build_facs(tables_blob); 2195 2196 /* DSDT is pointed to by FADT */ 2197 dsdt = tables_blob->len; 2198 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2199 &pci_hole, &pci_hole64, machine); 2200 2201 /* ACPI tables pointed to by RSDT */ 2202 acpi_add_table(table_offsets, tables_blob); 2203 pm.fadt.facs_tbl_offset = &facs; 2204 pm.fadt.dsdt_tbl_offset = &dsdt; 2205 pm.fadt.xdsdt_tbl_offset = &dsdt; 2206 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2207 2208 acpi_add_table(table_offsets, tables_blob); 2209 acpi_build_madt(tables_blob, tables->linker, x86ms, 2210 x86ms->oem_id, x86ms->oem_table_id); 2211 2212 #ifdef CONFIG_ACPI_ERST 2213 { 2214 Object *erst_dev; 2215 erst_dev = find_erst_dev(); 2216 if (erst_dev) { 2217 acpi_add_table(table_offsets, tables_blob); 2218 build_erst(tables_blob, tables->linker, erst_dev, 2219 x86ms->oem_id, x86ms->oem_table_id); 2220 } 2221 } 2222 #endif 2223 2224 vmgenid_dev = find_vmgenid_dev(); 2225 if (vmgenid_dev) { 2226 acpi_add_table(table_offsets, tables_blob); 2227 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2228 tables->vmgenid, tables->linker, x86ms->oem_id); 2229 } 2230 2231 vmclock_dev = find_vmclock_dev(); 2232 if (vmclock_dev) { 2233 acpi_add_table(table_offsets, tables_blob); 2234 vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker, 2235 x86ms->oem_id); 2236 } 2237 2238 if (misc.has_hpet) { 2239 acpi_add_table(table_offsets, tables_blob); 2240 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2241 x86ms->oem_table_id); 2242 } 2243 #ifdef CONFIG_TPM 2244 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2245 if (misc.tpm_version == TPM_VERSION_1_2) { 2246 acpi_add_table(table_offsets, tables_blob); 2247 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2248 x86ms->oem_id, x86ms->oem_table_id); 2249 } else { /* TPM_VERSION_2_0 */ 2250 acpi_add_table(table_offsets, tables_blob); 2251 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2252 x86ms->oem_id, x86ms->oem_table_id); 2253 } 2254 } 2255 #endif 2256 if (machine->numa_state->num_nodes) { 2257 acpi_add_table(table_offsets, tables_blob); 2258 build_srat(tables_blob, tables->linker, machine); 2259 if (machine->numa_state->have_numa_distance) { 2260 acpi_add_table(table_offsets, tables_blob); 2261 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2262 x86ms->oem_table_id); 2263 } 2264 if (machine->numa_state->hmat_enabled) { 2265 acpi_add_table(table_offsets, tables_blob); 2266 build_hmat(tables_blob, tables->linker, machine->numa_state, 2267 x86ms->oem_id, x86ms->oem_table_id); 2268 } 2269 } 2270 if (acpi_get_mcfg(&mcfg)) { 2271 acpi_add_table(table_offsets, tables_blob); 2272 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2273 x86ms->oem_table_id); 2274 } 2275 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2276 acpi_add_table(table_offsets, tables_blob); 2277 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2278 x86ms->oem_table_id); 2279 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2280 acpi_add_table(table_offsets, tables_blob); 2281 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2282 x86ms->oem_table_id); 2283 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2284 PCIDevice *pdev = PCI_DEVICE(iommu); 2285 2286 acpi_add_table(table_offsets, tables_blob); 2287 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2288 x86ms->oem_id, x86ms->oem_table_id); 2289 } 2290 if (machine->nvdimms_state->is_enabled) { 2291 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2292 machine->nvdimms_state, machine->ram_slots, 2293 x86ms->oem_id, x86ms->oem_table_id); 2294 } 2295 if (pcms->cxl_devices_state.is_enabled) { 2296 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2297 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2298 } 2299 2300 acpi_add_table(table_offsets, tables_blob); 2301 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2302 2303 /* Add tables supplied by user (if any) */ 2304 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2305 unsigned len = acpi_table_len(u); 2306 2307 acpi_add_table(table_offsets, tables_blob); 2308 g_array_append_vals(tables_blob, u, len); 2309 } 2310 2311 /* RSDT is pointed to by RSDP */ 2312 rsdt = tables_blob->len; 2313 build_rsdt(tables_blob, tables->linker, table_offsets, 2314 oem_id, oem_table_id); 2315 2316 /* RSDP is in FSEG memory, so allocate it separately */ 2317 { 2318 AcpiRsdpData rsdp_data = { 2319 .revision = 0, 2320 .oem_id = x86ms->oem_id, 2321 .xsdt_tbl_offset = NULL, 2322 .rsdt_tbl_offset = &rsdt, 2323 }; 2324 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2325 } 2326 2327 /* We'll expose it all to Guest so we want to reduce 2328 * chance of size changes. 2329 * 2330 * We used to align the tables to 4k, but of course this would 2331 * too simple to be enough. 4k turned out to be too small an 2332 * alignment very soon, and in fact it is almost impossible to 2333 * keep the table size stable for all (max_cpus, max_memory_slots) 2334 * combinations. 2335 */ 2336 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2337 2338 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2339 2340 /* Cleanup memory that's no longer used. */ 2341 g_array_free(table_offsets, true); 2342 g_free(slic_oem.id); 2343 g_free(slic_oem.table_id); 2344 } 2345 2346 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2347 { 2348 uint32_t size = acpi_data_len(data); 2349 2350 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2351 memory_region_ram_resize(mr, size, &error_abort); 2352 2353 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2354 memory_region_set_dirty(mr, 0, size); 2355 } 2356 2357 static void acpi_build_update(void *build_opaque) 2358 { 2359 AcpiBuildState *build_state = build_opaque; 2360 AcpiBuildTables tables; 2361 2362 /* No state to update or already patched? Nothing to do. */ 2363 if (!build_state || build_state->patched) { 2364 return; 2365 } 2366 build_state->patched = 1; 2367 2368 acpi_build_tables_init(&tables); 2369 2370 acpi_build(&tables, MACHINE(qdev_get_machine())); 2371 2372 acpi_ram_update(build_state->table_mr, tables.table_data); 2373 2374 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2375 2376 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2377 acpi_build_tables_cleanup(&tables, true); 2378 } 2379 2380 static void acpi_build_reset(void *build_opaque) 2381 { 2382 AcpiBuildState *build_state = build_opaque; 2383 build_state->patched = 0; 2384 } 2385 2386 static const VMStateDescription vmstate_acpi_build = { 2387 .name = "acpi_build", 2388 .version_id = 1, 2389 .minimum_version_id = 1, 2390 .fields = (const VMStateField[]) { 2391 VMSTATE_UINT8(patched, AcpiBuildState), 2392 VMSTATE_END_OF_LIST() 2393 }, 2394 }; 2395 2396 void acpi_setup(void) 2397 { 2398 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2399 X86MachineState *x86ms = X86_MACHINE(pcms); 2400 AcpiBuildTables tables; 2401 AcpiBuildState *build_state; 2402 Object *vmgenid_dev; 2403 #ifdef CONFIG_TPM 2404 TPMIf *tpm; 2405 static FwCfgTPMConfig tpm_config; 2406 #endif 2407 2408 if (!x86ms->fw_cfg) { 2409 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2410 return; 2411 } 2412 2413 if (!pcms->acpi_build_enabled) { 2414 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2415 return; 2416 } 2417 2418 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2419 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2420 return; 2421 } 2422 2423 build_state = g_malloc0(sizeof *build_state); 2424 2425 acpi_build_tables_init(&tables); 2426 acpi_build(&tables, MACHINE(pcms)); 2427 2428 /* Now expose it all to Guest */ 2429 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2430 build_state, tables.table_data, 2431 ACPI_BUILD_TABLE_FILE); 2432 assert(build_state->table_mr != NULL); 2433 2434 build_state->linker_mr = 2435 acpi_add_rom_blob(acpi_build_update, build_state, 2436 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2437 2438 #ifdef CONFIG_TPM 2439 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2440 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2441 2442 tpm = tpm_find(); 2443 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2444 tpm_config = (FwCfgTPMConfig) { 2445 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2446 .tpm_version = tpm_get_version(tpm), 2447 .tpmppi_version = TPM_PPI_VERSION_1_30 2448 }; 2449 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2450 &tpm_config, sizeof tpm_config); 2451 } 2452 #endif 2453 2454 vmgenid_dev = find_vmgenid_dev(); 2455 if (vmgenid_dev) { 2456 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2457 tables.vmgenid); 2458 } 2459 2460 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2461 build_state, tables.rsdp, 2462 ACPI_BUILD_RSDP_FILE); 2463 2464 qemu_register_reset(acpi_build_reset, build_state); 2465 acpi_build_reset(build_state); 2466 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2467 2468 /* Cleanup tables but don't free the memory: we track it 2469 * in build_state. 2470 */ 2471 acpi_build_tables_cleanup(&tables, false); 2472 } 2473