1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/misc/pvpanic.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/acpi/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/acpi/cpu.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/acpi/bios-linker-loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/input/i8042.h" 43 #include "hw/block/fdc.h" 44 #include "hw/acpi/memory_hotplug.h" 45 #include "sysemu/tpm.h" 46 #include "hw/acpi/tpm.h" 47 #include "hw/acpi/vmgenid.h" 48 #include "hw/acpi/erst.h" 49 #include "sysemu/tpm_backend.h" 50 #include "hw/rtc/mc146818rtc_regs.h" 51 #include "migration/vmstate.h" 52 #include "hw/mem/memory-device.h" 53 #include "hw/mem/nvdimm.h" 54 #include "sysemu/numa.h" 55 #include "sysemu/reset.h" 56 #include "hw/hyperv/vmbus-bridge.h" 57 58 /* Supported chipsets: */ 59 #include "hw/southbridge/piix.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/ich9.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/ipmi.h" 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 #include "hw/acpi/cxl.h" 81 82 #include CONFIG_DEVICES 83 84 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 85 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 86 * a little bit, there should be plenty of free space since the DSDT 87 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 88 */ 89 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 90 #define ACPI_BUILD_ALIGN_SIZE 0x1000 91 92 #define ACPI_BUILD_TABLE_SIZE 0x20000 93 94 /* #define DEBUG_ACPI_BUILD */ 95 #ifdef DEBUG_ACPI_BUILD 96 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 97 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 98 #else 99 #define ACPI_BUILD_DPRINTF(fmt, ...) 100 #endif 101 102 typedef struct AcpiPmInfo { 103 bool s3_disabled; 104 bool s4_disabled; 105 bool pcihp_bridge_en; 106 bool smi_on_cpuhp; 107 bool smi_on_cpu_unplug; 108 bool pcihp_root_en; 109 uint8_t s4_val; 110 AcpiFadtData fadt; 111 uint16_t cpu_hp_io_base; 112 uint16_t pcihp_io_base; 113 uint16_t pcihp_io_len; 114 } AcpiPmInfo; 115 116 typedef struct AcpiMiscInfo { 117 bool is_piix4; 118 bool has_hpet; 119 #ifdef CONFIG_TPM 120 TPMVersion tpm_version; 121 #endif 122 const unsigned char *dsdt_code; 123 unsigned dsdt_size; 124 uint16_t pvpanic_port; 125 uint16_t applesmc_io_base; 126 } AcpiMiscInfo; 127 128 typedef struct AcpiBuildPciBusHotplugState { 129 GArray *device_table; 130 GArray *notify_table; 131 struct AcpiBuildPciBusHotplugState *parent; 132 bool pcihp_bridge_en; 133 } AcpiBuildPciBusHotplugState; 134 135 typedef struct FwCfgTPMConfig { 136 uint32_t tpmppi_address; 137 uint8_t tpm_version; 138 uint8_t tpmppi_version; 139 } QEMU_PACKED FwCfgTPMConfig; 140 141 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 142 143 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 144 .space_id = AML_AS_SYSTEM_IO, 145 .address = NVDIMM_ACPI_IO_BASE, 146 .bit_width = NVDIMM_ACPI_IO_LEN << 3 147 }; 148 149 static void init_common_fadt_data(MachineState *ms, Object *o, 150 AcpiFadtData *data) 151 { 152 X86MachineState *x86ms = X86_MACHINE(ms); 153 /* 154 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 155 * behavior for compatibility irrelevant to smm_enabled, which doesn't 156 * comforms to ACPI spec. 157 */ 158 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 159 true : x86_machine_is_smm_enabled(x86ms); 160 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 161 AmlAddressSpace as = AML_AS_SYSTEM_IO; 162 AcpiFadtData fadt = { 163 .rev = 3, 164 .flags = 165 (1 << ACPI_FADT_F_WBINVD) | 166 (1 << ACPI_FADT_F_PROC_C1) | 167 (1 << ACPI_FADT_F_SLP_BUTTON) | 168 (1 << ACPI_FADT_F_RTC_S4) | 169 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 170 /* APIC destination mode ("Flat Logical") has an upper limit of 8 171 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 172 * used 173 */ 174 ((ms->smp.max_cpus > 8) ? 175 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 176 .int_model = 1 /* Multiple APIC */, 177 .rtc_century = RTC_CENTURY, 178 .plvl2_lat = 0xfff /* C2 state not supported */, 179 .plvl3_lat = 0xfff /* C3 state not supported */, 180 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 181 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 182 .acpi_enable_cmd = 183 smm_enabled ? 184 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 185 0, 186 .acpi_disable_cmd = 187 smm_enabled ? 188 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 189 0, 190 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 191 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 192 .address = io + 0x04 }, 193 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 194 .gpe0_blk = { .space_id = as, .bit_width = 195 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 196 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 197 }, 198 }; 199 200 /* 201 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 202 * Flags, bit offset 1 - 8042. 203 */ 204 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 205 206 *data = fadt; 207 } 208 209 static Object *object_resolve_type_unambiguous(const char *typename) 210 { 211 bool ambig; 212 Object *o = object_resolve_path_type("", typename, &ambig); 213 214 if (ambig || !o) { 215 return NULL; 216 } 217 return o; 218 } 219 220 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 221 { 222 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 223 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 224 Object *obj = piix ? piix : lpc; 225 QObject *o; 226 pm->cpu_hp_io_base = 0; 227 pm->pcihp_io_base = 0; 228 pm->pcihp_io_len = 0; 229 pm->smi_on_cpuhp = false; 230 pm->smi_on_cpu_unplug = false; 231 232 assert(obj); 233 init_common_fadt_data(machine, obj, &pm->fadt); 234 if (piix) { 235 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 236 pm->fadt.rev = 1; 237 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 238 } 239 if (lpc) { 240 uint64_t smi_features = object_property_get_uint(lpc, 241 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 242 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 243 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 244 pm->fadt.reset_reg = r; 245 pm->fadt.reset_val = 0xf; 246 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 247 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 248 pm->smi_on_cpuhp = 249 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 250 pm->smi_on_cpu_unplug = 251 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 252 } 253 pm->pcihp_io_base = 254 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 255 pm->pcihp_io_len = 256 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 257 258 /* The above need not be conditional on machine type because the reset port 259 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 260 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 261 262 /* Fill in optional s3/s4 related properties */ 263 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 264 if (o) { 265 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 266 } else { 267 pm->s3_disabled = false; 268 } 269 qobject_unref(o); 270 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 271 if (o) { 272 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 273 } else { 274 pm->s4_disabled = false; 275 } 276 qobject_unref(o); 277 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 278 if (o) { 279 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 280 } else { 281 pm->s4_val = false; 282 } 283 qobject_unref(o); 284 285 pm->pcihp_bridge_en = 286 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 287 NULL); 288 pm->pcihp_root_en = 289 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 290 NULL); 291 } 292 293 static void acpi_get_misc_info(AcpiMiscInfo *info) 294 { 295 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 296 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 297 assert(!!piix != !!lpc); 298 299 if (piix) { 300 info->is_piix4 = true; 301 } 302 if (lpc) { 303 info->is_piix4 = false; 304 } 305 306 info->has_hpet = hpet_find(); 307 #ifdef CONFIG_TPM 308 info->tpm_version = tpm_get_version(tpm_find()); 309 #endif 310 info->pvpanic_port = pvpanic_port(); 311 info->applesmc_io_base = applesmc_port(); 312 } 313 314 /* 315 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 316 * On i386 arch we only have two pci hosts, so we can look only for them. 317 */ 318 Object *acpi_get_i386_pci_host(void) 319 { 320 PCIHostState *host; 321 322 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 323 if (!host) { 324 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 325 } 326 327 return OBJECT(host); 328 } 329 330 static void acpi_get_pci_holes(Range *hole, Range *hole64) 331 { 332 Object *pci_host; 333 334 pci_host = acpi_get_i386_pci_host(); 335 336 if (!pci_host) { 337 return; 338 } 339 340 range_set_bounds1(hole, 341 object_property_get_uint(pci_host, 342 PCI_HOST_PROP_PCI_HOLE_START, 343 NULL), 344 object_property_get_uint(pci_host, 345 PCI_HOST_PROP_PCI_HOLE_END, 346 NULL)); 347 range_set_bounds1(hole64, 348 object_property_get_uint(pci_host, 349 PCI_HOST_PROP_PCI_HOLE64_START, 350 NULL), 351 object_property_get_uint(pci_host, 352 PCI_HOST_PROP_PCI_HOLE64_END, 353 NULL)); 354 } 355 356 static void acpi_align_size(GArray *blob, unsigned align) 357 { 358 /* Align size to multiple of given size. This reduces the chance 359 * we need to change size in the future (breaking cross version migration). 360 */ 361 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 362 } 363 364 /* 365 * ACPI spec 1.0b, 366 * 5.2.6 Firmware ACPI Control Structure 367 */ 368 static void 369 build_facs(GArray *table_data) 370 { 371 const char *sig = "FACS"; 372 const uint8_t reserved[40] = {}; 373 374 g_array_append_vals(table_data, sig, 4); /* Signature */ 375 build_append_int_noprefix(table_data, 64, 4); /* Length */ 376 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 377 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 378 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 379 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 380 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 381 } 382 383 static void build_append_pcihp_notify_entry(Aml *method, int slot) 384 { 385 Aml *if_ctx; 386 int32_t devfn = PCI_DEVFN(slot, 0); 387 388 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 389 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 390 aml_append(method, if_ctx); 391 } 392 393 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 394 bool pcihp_bridge_en) 395 { 396 Aml *dev, *notify_method = NULL, *method; 397 QObject *bsel; 398 PCIBus *sec; 399 int devfn; 400 401 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 402 if (bsel) { 403 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 404 405 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 406 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 407 } 408 409 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 410 DeviceClass *dc; 411 PCIDeviceClass *pc; 412 PCIDevice *pdev = bus->devices[devfn]; 413 int slot = PCI_SLOT(devfn); 414 int func = PCI_FUNC(devfn); 415 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 416 int adr = slot << 16 | func; 417 bool hotplug_enabled_dev; 418 bool bridge_in_acpi; 419 bool cold_plugged_bridge; 420 421 if (!pdev) { 422 /* 423 * add hotplug slots for non present devices. 424 * hotplug is supported only for non-multifunction device 425 * so generate device description only for function 0 426 */ 427 if (bsel && !func) { 428 if (pci_bus_is_express(bus) && slot > 0) { 429 break; 430 } 431 dev = aml_device("S%.02X", devfn); 432 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 433 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 434 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 435 aml_append(method, 436 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 437 ); 438 aml_append(dev, method); 439 method = aml_method("_DSM", 4, AML_SERIALIZED); 440 aml_append(method, 441 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), 442 aml_arg(2), aml_arg(3), 443 aml_name("BSEL"), aml_name("_SUN"))) 444 ); 445 aml_append(dev, method); 446 aml_append(parent_scope, dev); 447 448 build_append_pcihp_notify_entry(notify_method, slot); 449 } 450 continue; 451 } 452 453 pc = PCI_DEVICE_GET_CLASS(pdev); 454 dc = DEVICE_GET_CLASS(pdev); 455 456 /* 457 * Cold plugged bridges aren't themselves hot-pluggable. 458 * Hotplugged bridges *are* hot-pluggable. 459 */ 460 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 461 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 462 463 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 464 465 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 466 continue; 467 } 468 469 /* 470 * allow describing coldplugged bridges in ACPI even if they are not 471 * on function 0, as they are not unpluggable, for all other devices 472 * generate description only for function 0 per slot 473 */ 474 if (func && !bridge_in_acpi) { 475 continue; 476 } 477 478 /* start to compose PCI device descriptor */ 479 dev = aml_device("S%.02X", devfn); 480 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 481 482 if (bsel) { 483 /* 484 * Can't declare _SUN here for every device as it changes 'slot' 485 * enumeration order in linux kernel, so use another variable for it 486 */ 487 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 488 method = aml_method("_DSM", 4, AML_SERIALIZED); 489 aml_append(method, aml_return( 490 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), 491 aml_arg(3), aml_name("BSEL"), aml_name("ASUN")) 492 )); 493 aml_append(dev, method); 494 } 495 496 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 497 /* add VGA specific AML methods */ 498 int s3d; 499 500 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 501 s3d = 3; 502 } else { 503 s3d = 0; 504 } 505 506 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 507 aml_append(method, aml_return(aml_int(0))); 508 aml_append(dev, method); 509 510 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 511 aml_append(method, aml_return(aml_int(0))); 512 aml_append(dev, method); 513 514 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 515 aml_append(method, aml_return(aml_int(s3d))); 516 aml_append(dev, method); 517 } else if (hotplug_enabled_dev) { 518 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 519 /* add _EJ0 to make slot hotpluggable */ 520 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 521 aml_append(method, 522 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 523 ); 524 aml_append(dev, method); 525 526 if (bsel) { 527 build_append_pcihp_notify_entry(notify_method, slot); 528 } 529 } else if (bridge_in_acpi) { 530 /* 531 * device is coldplugged bridge, 532 * add child device descriptions into its scope 533 */ 534 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 535 536 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 537 } 538 /* device descriptor has been composed, add it into parent context */ 539 aml_append(parent_scope, dev); 540 } 541 542 if (bsel) { 543 aml_append(parent_scope, notify_method); 544 } 545 546 /* Append PCNT method to notify about events on local and child buses. 547 * Add this method for root bus only when hotplug is enabled since DSDT 548 * expects it. 549 */ 550 if (bsel || pcihp_bridge_en) { 551 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 552 553 /* If bus supports hotplug select it and notify about local events */ 554 if (bsel) { 555 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 556 557 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 558 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 559 aml_int(1))); /* Device Check */ 560 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 561 aml_int(3))); /* Eject Request */ 562 } 563 564 /* Notify about child bus events in any case */ 565 if (pcihp_bridge_en) { 566 QLIST_FOREACH(sec, &bus->child, sibling) { 567 if (pci_bus_is_root(sec)) { 568 continue; 569 } 570 571 aml_append(method, aml_name("^S%.02X.PCNT", 572 sec->parent_dev->devfn)); 573 } 574 } 575 576 aml_append(parent_scope, method); 577 } 578 qobject_unref(bsel); 579 } 580 581 Aml *aml_pci_device_dsm(void) 582 { 583 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; 584 Aml *acpi_index = aml_local(0); 585 Aml *zero = aml_int(0); 586 Aml *bnum = aml_arg(4); 587 Aml *func = aml_arg(2); 588 Aml *rev = aml_arg(1); 589 Aml *sunum = aml_arg(5); 590 591 method = aml_method("PDSM", 6, AML_SERIALIZED); 592 593 /* 594 * PCI Firmware Specification 3.1 595 * 4.6. _DSM Definitions for PCI 596 */ 597 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 598 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 599 { 600 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 601 ifctx1 = aml_if(aml_equal(func, zero)); 602 { 603 uint8_t byte_list[1]; 604 605 ifctx2 = aml_if(aml_equal(rev, aml_int(2))); 606 { 607 /* 608 * advertise function 7 if device has acpi-index 609 * acpi_index values: 610 * 0: not present (default value) 611 * FFFFFFFF: not supported (old QEMU without PIDX reg) 612 * other: device's acpi-index 613 */ 614 ifctx3 = aml_if(aml_lnot( 615 aml_or(aml_equal(acpi_index, zero), 616 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 617 )); 618 { 619 byte_list[0] = 620 1 /* have supported functions */ | 621 1 << 7 /* support for function 7 */ 622 ; 623 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); 624 } 625 aml_append(ifctx2, ifctx3); 626 } 627 aml_append(ifctx1, ifctx2); 628 629 byte_list[0] = 0; /* nothing supported */ 630 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); 631 } 632 aml_append(ifctx, ifctx1); 633 elsectx = aml_else(); 634 /* 635 * PCI Firmware Specification 3.1 636 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 637 * Operating Systems 638 */ 639 ifctx1 = aml_if(aml_equal(func, aml_int(7))); 640 { 641 Aml *pkg = aml_package(2); 642 Aml *ret = aml_local(1); 643 644 aml_append(pkg, zero); 645 /* 646 * optional, if not impl. should return null string 647 */ 648 aml_append(pkg, aml_string("%s", "")); 649 aml_append(ifctx1, aml_store(pkg, ret)); 650 /* 651 * update acpi-index to actual value 652 */ 653 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 654 aml_append(ifctx1, aml_return(ret)); 655 } 656 aml_append(elsectx, ifctx1); 657 aml_append(ifctx, elsectx); 658 } 659 aml_append(method, ifctx); 660 return method; 661 } 662 663 /** 664 * build_prt_entry: 665 * @link_name: link name for PCI route entry 666 * 667 * build AML package containing a PCI route entry for @link_name 668 */ 669 static Aml *build_prt_entry(const char *link_name) 670 { 671 Aml *a_zero = aml_int(0); 672 Aml *pkg = aml_package(4); 673 aml_append(pkg, a_zero); 674 aml_append(pkg, a_zero); 675 aml_append(pkg, aml_name("%s", link_name)); 676 aml_append(pkg, a_zero); 677 return pkg; 678 } 679 680 /* 681 * initialize_route - Initialize the interrupt routing rule 682 * through a specific LINK: 683 * if (lnk_idx == idx) 684 * route using link 'link_name' 685 */ 686 static Aml *initialize_route(Aml *route, const char *link_name, 687 Aml *lnk_idx, int idx) 688 { 689 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 690 Aml *pkg = build_prt_entry(link_name); 691 692 aml_append(if_ctx, aml_store(pkg, route)); 693 694 return if_ctx; 695 } 696 697 /* 698 * build_prt - Define interrupt rounting rules 699 * 700 * Returns an array of 128 routes, one for each device, 701 * based on device location. 702 * The main goal is to equaly distribute the interrupts 703 * over the 4 existing ACPI links (works only for i440fx). 704 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 705 * 706 */ 707 static Aml *build_prt(bool is_pci0_prt) 708 { 709 Aml *method, *while_ctx, *pin, *res; 710 711 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 712 res = aml_local(0); 713 pin = aml_local(1); 714 aml_append(method, aml_store(aml_package(128), res)); 715 aml_append(method, aml_store(aml_int(0), pin)); 716 717 /* while (pin < 128) */ 718 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 719 { 720 Aml *slot = aml_local(2); 721 Aml *lnk_idx = aml_local(3); 722 Aml *route = aml_local(4); 723 724 /* slot = pin >> 2 */ 725 aml_append(while_ctx, 726 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 727 /* lnk_idx = (slot + pin) & 3 */ 728 aml_append(while_ctx, 729 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 730 lnk_idx)); 731 732 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 733 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 734 if (is_pci0_prt) { 735 Aml *if_device_1, *if_pin_4, *else_pin_4; 736 737 /* device 1 is the power-management device, needs SCI */ 738 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 739 { 740 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 741 { 742 aml_append(if_pin_4, 743 aml_store(build_prt_entry("LNKS"), route)); 744 } 745 aml_append(if_device_1, if_pin_4); 746 else_pin_4 = aml_else(); 747 { 748 aml_append(else_pin_4, 749 aml_store(build_prt_entry("LNKA"), route)); 750 } 751 aml_append(if_device_1, else_pin_4); 752 } 753 aml_append(while_ctx, if_device_1); 754 } else { 755 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 756 } 757 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 758 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 759 760 /* route[0] = 0x[slot]FFFF */ 761 aml_append(while_ctx, 762 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 763 NULL), 764 aml_index(route, aml_int(0)))); 765 /* route[1] = pin & 3 */ 766 aml_append(while_ctx, 767 aml_store(aml_and(pin, aml_int(3), NULL), 768 aml_index(route, aml_int(1)))); 769 /* res[pin] = route */ 770 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 771 /* pin++ */ 772 aml_append(while_ctx, aml_increment(pin)); 773 } 774 aml_append(method, while_ctx); 775 /* return res*/ 776 aml_append(method, aml_return(res)); 777 778 return method; 779 } 780 781 static void build_hpet_aml(Aml *table) 782 { 783 Aml *crs; 784 Aml *field; 785 Aml *method; 786 Aml *if_ctx; 787 Aml *scope = aml_scope("_SB"); 788 Aml *dev = aml_device("HPET"); 789 Aml *zero = aml_int(0); 790 Aml *id = aml_local(0); 791 Aml *period = aml_local(1); 792 793 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 794 aml_append(dev, aml_name_decl("_UID", zero)); 795 796 aml_append(dev, 797 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 798 HPET_LEN)); 799 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 800 aml_append(field, aml_named_field("VEND", 32)); 801 aml_append(field, aml_named_field("PRD", 32)); 802 aml_append(dev, field); 803 804 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 805 aml_append(method, aml_store(aml_name("VEND"), id)); 806 aml_append(method, aml_store(aml_name("PRD"), period)); 807 aml_append(method, aml_shiftright(id, aml_int(16), id)); 808 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 809 aml_equal(id, aml_int(0xffff)))); 810 { 811 aml_append(if_ctx, aml_return(zero)); 812 } 813 aml_append(method, if_ctx); 814 815 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 816 aml_lgreater(period, aml_int(100000000)))); 817 { 818 aml_append(if_ctx, aml_return(zero)); 819 } 820 aml_append(method, if_ctx); 821 822 aml_append(method, aml_return(aml_int(0x0F))); 823 aml_append(dev, method); 824 825 crs = aml_resource_template(); 826 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 827 aml_append(dev, aml_name_decl("_CRS", crs)); 828 829 aml_append(scope, dev); 830 aml_append(table, scope); 831 } 832 833 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 834 { 835 Aml *dev; 836 Aml *method; 837 Aml *crs; 838 839 dev = aml_device("VMBS"); 840 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 841 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 842 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 843 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 844 845 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 846 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 847 aml_name("STA"))); 848 aml_append(dev, method); 849 850 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 851 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 852 aml_name("STA"))); 853 aml_append(dev, method); 854 855 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 856 aml_append(method, aml_return(aml_name("STA"))); 857 aml_append(dev, method); 858 859 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 860 861 crs = aml_resource_template(); 862 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 863 aml_append(dev, aml_name_decl("_CRS", crs)); 864 865 return dev; 866 } 867 868 static void build_isa_devices_aml(Aml *table) 869 { 870 bool ambiguous; 871 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 872 Aml *scope; 873 874 assert(obj && !ambiguous); 875 876 scope = aml_scope("_SB.PCI0.ISA"); 877 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 878 isa_build_aml(ISA_BUS(obj), scope); 879 880 aml_append(table, scope); 881 } 882 883 static void build_dbg_aml(Aml *table) 884 { 885 Aml *field; 886 Aml *method; 887 Aml *while_ctx; 888 Aml *scope = aml_scope("\\"); 889 Aml *buf = aml_local(0); 890 Aml *len = aml_local(1); 891 Aml *idx = aml_local(2); 892 893 aml_append(scope, 894 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 895 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 896 aml_append(field, aml_named_field("DBGB", 8)); 897 aml_append(scope, field); 898 899 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 900 901 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 902 aml_append(method, aml_to_buffer(buf, buf)); 903 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 904 aml_append(method, aml_store(aml_int(0), idx)); 905 906 while_ctx = aml_while(aml_lless(idx, len)); 907 aml_append(while_ctx, 908 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 909 aml_append(while_ctx, aml_increment(idx)); 910 aml_append(method, while_ctx); 911 912 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 913 aml_append(scope, method); 914 915 aml_append(table, scope); 916 } 917 918 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 919 { 920 Aml *dev; 921 Aml *crs; 922 Aml *method; 923 uint32_t irqs[] = {5, 10, 11}; 924 925 dev = aml_device("%s", name); 926 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 927 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 928 929 crs = aml_resource_template(); 930 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 931 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 932 aml_append(dev, aml_name_decl("_PRS", crs)); 933 934 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 935 aml_append(method, aml_return(aml_call1("IQST", reg))); 936 aml_append(dev, method); 937 938 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 939 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 940 aml_append(dev, method); 941 942 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 943 aml_append(method, aml_return(aml_call1("IQCR", reg))); 944 aml_append(dev, method); 945 946 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 947 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 948 aml_append(method, aml_store(aml_name("PRRI"), reg)); 949 aml_append(dev, method); 950 951 return dev; 952 } 953 954 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 955 { 956 Aml *dev; 957 Aml *crs; 958 Aml *method; 959 uint32_t irqs; 960 961 dev = aml_device("%s", name); 962 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 963 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 964 965 crs = aml_resource_template(); 966 irqs = gsi; 967 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 968 AML_SHARED, &irqs, 1)); 969 aml_append(dev, aml_name_decl("_PRS", crs)); 970 971 aml_append(dev, aml_name_decl("_CRS", crs)); 972 973 /* 974 * _DIS can be no-op because the interrupt cannot be disabled. 975 */ 976 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 977 aml_append(dev, method); 978 979 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 980 aml_append(dev, method); 981 982 return dev; 983 } 984 985 /* _CRS method - get current settings */ 986 static Aml *build_iqcr_method(bool is_piix4) 987 { 988 Aml *if_ctx; 989 uint32_t irqs; 990 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 991 Aml *crs = aml_resource_template(); 992 993 irqs = 0; 994 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 995 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 996 aml_append(method, aml_name_decl("PRR0", crs)); 997 998 aml_append(method, 999 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1000 1001 if (is_piix4) { 1002 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1003 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1004 aml_append(method, if_ctx); 1005 } else { 1006 aml_append(method, 1007 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1008 aml_name("PRRI"))); 1009 } 1010 1011 aml_append(method, aml_return(aml_name("PRR0"))); 1012 return method; 1013 } 1014 1015 /* _STA method - get status */ 1016 static Aml *build_irq_status_method(void) 1017 { 1018 Aml *if_ctx; 1019 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1020 1021 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1022 aml_append(if_ctx, aml_return(aml_int(0x09))); 1023 aml_append(method, if_ctx); 1024 aml_append(method, aml_return(aml_int(0x0B))); 1025 return method; 1026 } 1027 1028 static void build_piix4_pci0_int(Aml *table) 1029 { 1030 Aml *dev; 1031 Aml *crs; 1032 Aml *field; 1033 Aml *method; 1034 uint32_t irqs; 1035 Aml *sb_scope = aml_scope("_SB"); 1036 Aml *pci0_scope = aml_scope("PCI0"); 1037 1038 aml_append(pci0_scope, build_prt(true)); 1039 aml_append(sb_scope, pci0_scope); 1040 1041 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1042 aml_append(field, aml_named_field("PRQ0", 8)); 1043 aml_append(field, aml_named_field("PRQ1", 8)); 1044 aml_append(field, aml_named_field("PRQ2", 8)); 1045 aml_append(field, aml_named_field("PRQ3", 8)); 1046 aml_append(sb_scope, field); 1047 1048 aml_append(sb_scope, build_irq_status_method()); 1049 aml_append(sb_scope, build_iqcr_method(true)); 1050 1051 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1052 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1053 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1054 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1055 1056 dev = aml_device("LNKS"); 1057 { 1058 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1059 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1060 1061 crs = aml_resource_template(); 1062 irqs = 9; 1063 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1064 AML_ACTIVE_HIGH, AML_SHARED, 1065 &irqs, 1)); 1066 aml_append(dev, aml_name_decl("_PRS", crs)); 1067 1068 /* The SCI cannot be disabled and is always attached to GSI 9, 1069 * so these are no-ops. We only need this link to override the 1070 * polarity to active high and match the content of the MADT. 1071 */ 1072 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1073 aml_append(method, aml_return(aml_int(0x0b))); 1074 aml_append(dev, method); 1075 1076 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1077 aml_append(dev, method); 1078 1079 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1080 aml_append(method, aml_return(aml_name("_PRS"))); 1081 aml_append(dev, method); 1082 1083 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1084 aml_append(dev, method); 1085 } 1086 aml_append(sb_scope, dev); 1087 1088 aml_append(table, sb_scope); 1089 } 1090 1091 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1092 { 1093 int i; 1094 int head; 1095 Aml *pkg; 1096 char base = name[3] < 'E' ? 'A' : 'E'; 1097 char *s = g_strdup(name); 1098 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1099 1100 assert(strlen(s) == 4); 1101 1102 head = name[3] - base; 1103 for (i = 0; i < 4; i++) { 1104 if (head + i > 3) { 1105 head = i * -1; 1106 } 1107 s[3] = base + head + i; 1108 pkg = aml_package(4); 1109 aml_append(pkg, a_nr); 1110 aml_append(pkg, aml_int(i)); 1111 aml_append(pkg, aml_name("%s", s)); 1112 aml_append(pkg, aml_int(0)); 1113 aml_append(ctx, pkg); 1114 } 1115 g_free(s); 1116 } 1117 1118 static Aml *build_q35_routing_table(const char *str) 1119 { 1120 int i; 1121 Aml *pkg; 1122 char *name = g_strdup_printf("%s ", str); 1123 1124 pkg = aml_package(128); 1125 for (i = 0; i < 0x18; i++) { 1126 name[3] = 'E' + (i & 0x3); 1127 append_q35_prt_entry(pkg, i, name); 1128 } 1129 1130 name[3] = 'E'; 1131 append_q35_prt_entry(pkg, 0x18, name); 1132 1133 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1134 for (i = 0x0019; i < 0x1e; i++) { 1135 name[3] = 'A'; 1136 append_q35_prt_entry(pkg, i, name); 1137 } 1138 1139 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1140 name[3] = 'E'; 1141 append_q35_prt_entry(pkg, 0x1e, name); 1142 name[3] = 'A'; 1143 append_q35_prt_entry(pkg, 0x1f, name); 1144 1145 g_free(name); 1146 return pkg; 1147 } 1148 1149 static void build_q35_pci0_int(Aml *table) 1150 { 1151 Aml *field; 1152 Aml *method; 1153 Aml *sb_scope = aml_scope("_SB"); 1154 Aml *pci0_scope = aml_scope("PCI0"); 1155 1156 /* Zero => PIC mode, One => APIC Mode */ 1157 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1158 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1159 { 1160 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1161 } 1162 aml_append(table, method); 1163 1164 aml_append(pci0_scope, 1165 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1166 aml_append(pci0_scope, 1167 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1168 1169 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1170 { 1171 Aml *if_ctx; 1172 Aml *else_ctx; 1173 1174 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1175 section 6.2.8.1 */ 1176 /* Note: we provide the same info as the PCI routing 1177 table of the Bochs BIOS */ 1178 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1179 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1180 aml_append(method, if_ctx); 1181 else_ctx = aml_else(); 1182 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1183 aml_append(method, else_ctx); 1184 } 1185 aml_append(pci0_scope, method); 1186 aml_append(sb_scope, pci0_scope); 1187 1188 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1189 aml_append(field, aml_named_field("PRQA", 8)); 1190 aml_append(field, aml_named_field("PRQB", 8)); 1191 aml_append(field, aml_named_field("PRQC", 8)); 1192 aml_append(field, aml_named_field("PRQD", 8)); 1193 aml_append(field, aml_reserved_field(0x20)); 1194 aml_append(field, aml_named_field("PRQE", 8)); 1195 aml_append(field, aml_named_field("PRQF", 8)); 1196 aml_append(field, aml_named_field("PRQG", 8)); 1197 aml_append(field, aml_named_field("PRQH", 8)); 1198 aml_append(sb_scope, field); 1199 1200 aml_append(sb_scope, build_irq_status_method()); 1201 aml_append(sb_scope, build_iqcr_method(false)); 1202 1203 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1204 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1205 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1206 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1207 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1208 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1209 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1210 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1211 1212 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1213 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1214 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1215 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1216 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1217 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1218 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1219 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1220 1221 aml_append(table, sb_scope); 1222 } 1223 1224 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1225 { 1226 Aml *dev; 1227 Aml *resource_template; 1228 1229 /* DRAM controller */ 1230 dev = aml_device("DRAC"); 1231 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1232 1233 resource_template = aml_resource_template(); 1234 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1235 aml_append(resource_template, 1236 aml_qword_memory(AML_POS_DECODE, 1237 AML_MIN_FIXED, 1238 AML_MAX_FIXED, 1239 AML_NON_CACHEABLE, 1240 AML_READ_WRITE, 1241 0x0000000000000000, 1242 mcfg->base, 1243 mcfg->base + mcfg->size - 1, 1244 0x0000000000000000, 1245 mcfg->size)); 1246 } else { 1247 aml_append(resource_template, 1248 aml_dword_memory(AML_POS_DECODE, 1249 AML_MIN_FIXED, 1250 AML_MAX_FIXED, 1251 AML_NON_CACHEABLE, 1252 AML_READ_WRITE, 1253 0x0000000000000000, 1254 mcfg->base, 1255 mcfg->base + mcfg->size - 1, 1256 0x0000000000000000, 1257 mcfg->size)); 1258 } 1259 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1260 1261 return dev; 1262 } 1263 1264 static void build_q35_isa_bridge(Aml *table) 1265 { 1266 Aml *dev; 1267 Aml *scope; 1268 1269 scope = aml_scope("_SB.PCI0"); 1270 dev = aml_device("ISA"); 1271 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1272 1273 /* ICH9 PCI to ISA irq remapping */ 1274 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1275 aml_int(0x60), 0x0C)); 1276 1277 aml_append(scope, dev); 1278 aml_append(table, scope); 1279 } 1280 1281 static void build_piix4_isa_bridge(Aml *table) 1282 { 1283 Aml *dev; 1284 Aml *scope; 1285 1286 scope = aml_scope("_SB.PCI0"); 1287 dev = aml_device("ISA"); 1288 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1289 1290 /* PIIX PCI to ISA irq remapping */ 1291 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1292 aml_int(0x60), 0x04)); 1293 1294 aml_append(scope, dev); 1295 aml_append(table, scope); 1296 } 1297 1298 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1299 { 1300 Aml *scope; 1301 Aml *field; 1302 Aml *method; 1303 1304 scope = aml_scope("_SB.PCI0"); 1305 1306 aml_append(scope, 1307 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1308 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1309 aml_append(field, aml_named_field("PCIU", 32)); 1310 aml_append(field, aml_named_field("PCID", 32)); 1311 aml_append(scope, field); 1312 1313 aml_append(scope, 1314 aml_operation_region("SEJ", AML_SYSTEM_IO, 1315 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1316 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1317 aml_append(field, aml_named_field("B0EJ", 32)); 1318 aml_append(scope, field); 1319 1320 aml_append(scope, 1321 aml_operation_region("BNMR", AML_SYSTEM_IO, 1322 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1323 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1324 aml_append(field, aml_named_field("BNUM", 32)); 1325 aml_append(field, aml_named_field("PIDX", 32)); 1326 aml_append(scope, field); 1327 1328 aml_append(scope, aml_mutex("BLCK", 0)); 1329 1330 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1331 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1332 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1333 aml_append(method, 1334 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1335 aml_append(method, aml_release(aml_name("BLCK"))); 1336 aml_append(method, aml_return(aml_int(0))); 1337 aml_append(scope, method); 1338 1339 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1340 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1341 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1342 aml_append(method, 1343 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1344 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1345 aml_append(method, aml_release(aml_name("BLCK"))); 1346 aml_append(method, aml_return(aml_local(0))); 1347 aml_append(scope, method); 1348 1349 aml_append(scope, aml_pci_device_dsm()); 1350 1351 aml_append(table, scope); 1352 } 1353 1354 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1355 { 1356 Aml *if_ctx; 1357 Aml *if_ctx2; 1358 Aml *else_ctx; 1359 Aml *method; 1360 Aml *a_cwd1 = aml_name("CDW1"); 1361 Aml *a_ctrl = aml_local(0); 1362 1363 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1364 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1365 1366 if_ctx = aml_if(aml_equal( 1367 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1368 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1369 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1370 1371 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1372 1373 /* 1374 * Always allow native PME, AER (no dependencies) 1375 * Allow SHPC (PCI bridges can have SHPC controller) 1376 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1377 */ 1378 aml_append(if_ctx, aml_and(a_ctrl, 1379 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1380 1381 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1382 /* Unknown revision */ 1383 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1384 aml_append(if_ctx, if_ctx2); 1385 1386 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1387 /* Capabilities bits were masked */ 1388 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1389 aml_append(if_ctx, if_ctx2); 1390 1391 /* Update DWORD3 in the buffer */ 1392 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1393 aml_append(method, if_ctx); 1394 1395 else_ctx = aml_else(); 1396 /* Unrecognized UUID */ 1397 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1398 aml_append(method, else_ctx); 1399 1400 aml_append(method, aml_return(aml_arg(3))); 1401 return method; 1402 } 1403 1404 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1405 { 1406 Aml *scope = aml_scope("_SB.PCI0"); 1407 Aml *dev = aml_device("SMB0"); 1408 1409 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1410 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1411 aml_append(scope, dev); 1412 aml_append(table, scope); 1413 } 1414 1415 static void build_acpi0017(Aml *table) 1416 { 1417 Aml *dev, *scope, *method; 1418 1419 scope = aml_scope("_SB"); 1420 dev = aml_device("CXLM"); 1421 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1422 1423 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1424 aml_append(method, aml_return(aml_int(0x01))); 1425 aml_append(dev, method); 1426 1427 aml_append(scope, dev); 1428 aml_append(table, scope); 1429 } 1430 1431 static void 1432 build_dsdt(GArray *table_data, BIOSLinker *linker, 1433 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1434 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1435 { 1436 CrsRangeEntry *entry; 1437 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1438 CrsRangeSet crs_range_set; 1439 PCMachineState *pcms = PC_MACHINE(machine); 1440 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1441 X86MachineState *x86ms = X86_MACHINE(machine); 1442 AcpiMcfgInfo mcfg; 1443 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1444 uint32_t nr_mem = machine->ram_slots; 1445 int root_bus_limit = 0xFF; 1446 PCIBus *bus = NULL; 1447 #ifdef CONFIG_TPM 1448 TPMIf *tpm = tpm_find(); 1449 #endif 1450 bool cxl_present = false; 1451 int i; 1452 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1453 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1454 .oem_table_id = x86ms->oem_table_id }; 1455 1456 acpi_table_begin(&table, table_data); 1457 dsdt = init_aml_allocator(); 1458 1459 build_dbg_aml(dsdt); 1460 if (misc->is_piix4) { 1461 sb_scope = aml_scope("_SB"); 1462 dev = aml_device("PCI0"); 1463 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1464 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1465 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1466 aml_append(sb_scope, dev); 1467 aml_append(dsdt, sb_scope); 1468 1469 if (misc->has_hpet) { 1470 build_hpet_aml(dsdt); 1471 } 1472 build_piix4_isa_bridge(dsdt); 1473 build_isa_devices_aml(dsdt); 1474 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1475 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1476 } 1477 build_piix4_pci0_int(dsdt); 1478 } else { 1479 sb_scope = aml_scope("_SB"); 1480 dev = aml_device("PCI0"); 1481 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1482 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1483 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1484 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1485 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1486 aml_append(sb_scope, dev); 1487 if (mcfg_valid) { 1488 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1489 } 1490 1491 if (pm->smi_on_cpuhp) { 1492 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1493 dev = aml_device("PCI0.SMI0"); 1494 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1495 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1496 crs = aml_resource_template(); 1497 aml_append(crs, 1498 aml_io( 1499 AML_DECODE16, 1500 ACPI_PORT_SMI_CMD, 1501 ACPI_PORT_SMI_CMD, 1502 1, 1503 2) 1504 ); 1505 aml_append(dev, aml_name_decl("_CRS", crs)); 1506 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1507 aml_int(ACPI_PORT_SMI_CMD), 2)); 1508 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1509 AML_WRITE_AS_ZEROS); 1510 aml_append(field, aml_named_field("SMIC", 8)); 1511 aml_append(field, aml_reserved_field(8)); 1512 aml_append(dev, field); 1513 aml_append(sb_scope, dev); 1514 } 1515 1516 aml_append(dsdt, sb_scope); 1517 1518 if (misc->has_hpet) { 1519 build_hpet_aml(dsdt); 1520 } 1521 build_q35_isa_bridge(dsdt); 1522 build_isa_devices_aml(dsdt); 1523 if (pm->pcihp_bridge_en) { 1524 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1525 } 1526 build_q35_pci0_int(dsdt); 1527 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1528 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1529 } 1530 } 1531 1532 if (vmbus_bridge) { 1533 sb_scope = aml_scope("_SB"); 1534 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1535 aml_append(dsdt, sb_scope); 1536 } 1537 1538 if (pcmc->legacy_cpu_hotplug) { 1539 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1540 } else { 1541 CPUHotplugFeatures opts = { 1542 .acpi_1_compatible = true, .has_legacy_cphp = true, 1543 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1544 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1545 }; 1546 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1547 "\\_SB.PCI0", "\\_GPE._E02"); 1548 } 1549 1550 if (pcms->memhp_io_base && nr_mem) { 1551 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1552 "\\_GPE._E03", AML_SYSTEM_IO, 1553 pcms->memhp_io_base); 1554 } 1555 1556 scope = aml_scope("_GPE"); 1557 { 1558 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1559 1560 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1561 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1562 aml_append(method, 1563 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1564 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1565 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1566 aml_append(scope, method); 1567 } 1568 1569 if (machine->nvdimms_state->is_enabled) { 1570 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1571 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1572 aml_int(0x80))); 1573 aml_append(scope, method); 1574 } 1575 } 1576 aml_append(dsdt, scope); 1577 1578 crs_range_set_init(&crs_range_set); 1579 bus = PC_MACHINE(machine)->bus; 1580 if (bus) { 1581 QLIST_FOREACH(bus, &bus->child, sibling) { 1582 uint8_t bus_num = pci_bus_num(bus); 1583 uint8_t numa_node = pci_bus_numa_node(bus); 1584 1585 /* look only for expander root buses */ 1586 if (!pci_bus_is_root(bus)) { 1587 continue; 1588 } 1589 1590 if (bus_num < root_bus_limit) { 1591 root_bus_limit = bus_num - 1; 1592 } 1593 1594 scope = aml_scope("\\_SB"); 1595 1596 if (pci_bus_is_cxl(bus)) { 1597 dev = aml_device("CL%.02X", bus_num); 1598 } else { 1599 dev = aml_device("PC%.02X", bus_num); 1600 } 1601 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1602 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1603 if (pci_bus_is_cxl(bus)) { 1604 struct Aml *pkg = aml_package(2); 1605 1606 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1607 aml_append(pkg, aml_eisaid("PNP0A08")); 1608 aml_append(pkg, aml_eisaid("PNP0A03")); 1609 aml_append(dev, aml_name_decl("_CID", pkg)); 1610 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1611 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1612 build_cxl_osc_method(dev); 1613 } else if (pci_bus_is_express(bus)) { 1614 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1615 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1616 1617 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1618 aml_append(dev, build_q35_osc_method(true)); 1619 } else { 1620 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1621 } 1622 1623 if (numa_node != NUMA_NODE_UNASSIGNED) { 1624 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1625 } 1626 1627 aml_append(dev, build_prt(false)); 1628 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1629 0, 0, 0, 0); 1630 aml_append(dev, aml_name_decl("_CRS", crs)); 1631 aml_append(scope, dev); 1632 aml_append(dsdt, scope); 1633 1634 /* Handle the ranges for the PXB expanders */ 1635 if (pci_bus_is_cxl(bus)) { 1636 MemoryRegion *mr = &machine->cxl_devices_state->host_mr; 1637 uint64_t base = mr->addr; 1638 1639 cxl_present = true; 1640 crs_range_insert(crs_range_set.mem_ranges, base, 1641 base + memory_region_size(mr) - 1); 1642 } 1643 } 1644 } 1645 1646 if (cxl_present) { 1647 build_acpi0017(dsdt); 1648 } 1649 1650 /* 1651 * At this point crs_range_set has all the ranges used by pci 1652 * busses *other* than PCI0. These ranges will be excluded from 1653 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1654 * too. 1655 */ 1656 if (mcfg_valid) { 1657 crs_range_insert(crs_range_set.mem_ranges, 1658 mcfg.base, mcfg.base + mcfg.size - 1); 1659 } 1660 1661 scope = aml_scope("\\_SB.PCI0"); 1662 /* build PCI0._CRS */ 1663 crs = aml_resource_template(); 1664 aml_append(crs, 1665 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1666 0x0000, 0x0, root_bus_limit, 1667 0x0000, root_bus_limit + 1)); 1668 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1669 1670 aml_append(crs, 1671 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1672 AML_POS_DECODE, AML_ENTIRE_RANGE, 1673 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1674 1675 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1676 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1677 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1678 aml_append(crs, 1679 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1680 AML_POS_DECODE, AML_ENTIRE_RANGE, 1681 0x0000, entry->base, entry->limit, 1682 0x0000, entry->limit - entry->base + 1)); 1683 } 1684 1685 aml_append(crs, 1686 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1687 AML_CACHEABLE, AML_READ_WRITE, 1688 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1689 1690 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1691 range_lob(pci_hole), 1692 range_upb(pci_hole)); 1693 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1694 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1695 aml_append(crs, 1696 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1697 AML_NON_CACHEABLE, AML_READ_WRITE, 1698 0, entry->base, entry->limit, 1699 0, entry->limit - entry->base + 1)); 1700 } 1701 1702 if (!range_is_empty(pci_hole64)) { 1703 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1704 range_lob(pci_hole64), 1705 range_upb(pci_hole64)); 1706 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1707 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1708 aml_append(crs, 1709 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1710 AML_MAX_FIXED, 1711 AML_CACHEABLE, AML_READ_WRITE, 1712 0, entry->base, entry->limit, 1713 0, entry->limit - entry->base + 1)); 1714 } 1715 } 1716 1717 #ifdef CONFIG_TPM 1718 if (TPM_IS_TIS_ISA(tpm_find())) { 1719 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1720 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1721 } 1722 #endif 1723 aml_append(scope, aml_name_decl("_CRS", crs)); 1724 1725 /* reserve GPE0 block resources */ 1726 dev = aml_device("GPE0"); 1727 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1728 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1729 /* device present, functioning, decoding, not shown in UI */ 1730 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1731 crs = aml_resource_template(); 1732 aml_append(crs, 1733 aml_io( 1734 AML_DECODE16, 1735 pm->fadt.gpe0_blk.address, 1736 pm->fadt.gpe0_blk.address, 1737 1, 1738 pm->fadt.gpe0_blk.bit_width / 8) 1739 ); 1740 aml_append(dev, aml_name_decl("_CRS", crs)); 1741 aml_append(scope, dev); 1742 1743 crs_range_set_free(&crs_range_set); 1744 1745 /* reserve PCIHP resources */ 1746 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1747 dev = aml_device("PHPR"); 1748 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1749 aml_append(dev, 1750 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1751 /* device present, functioning, decoding, not shown in UI */ 1752 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1753 crs = aml_resource_template(); 1754 aml_append(crs, 1755 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1756 pm->pcihp_io_len) 1757 ); 1758 aml_append(dev, aml_name_decl("_CRS", crs)); 1759 aml_append(scope, dev); 1760 } 1761 aml_append(dsdt, scope); 1762 1763 /* create S3_ / S4_ / S5_ packages if necessary */ 1764 scope = aml_scope("\\"); 1765 if (!pm->s3_disabled) { 1766 pkg = aml_package(4); 1767 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1768 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1769 aml_append(pkg, aml_int(0)); /* reserved */ 1770 aml_append(pkg, aml_int(0)); /* reserved */ 1771 aml_append(scope, aml_name_decl("_S3", pkg)); 1772 } 1773 1774 if (!pm->s4_disabled) { 1775 pkg = aml_package(4); 1776 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1777 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1778 aml_append(pkg, aml_int(pm->s4_val)); 1779 aml_append(pkg, aml_int(0)); /* reserved */ 1780 aml_append(pkg, aml_int(0)); /* reserved */ 1781 aml_append(scope, aml_name_decl("_S4", pkg)); 1782 } 1783 1784 pkg = aml_package(4); 1785 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1786 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1787 aml_append(pkg, aml_int(0)); /* reserved */ 1788 aml_append(pkg, aml_int(0)); /* reserved */ 1789 aml_append(scope, aml_name_decl("_S5", pkg)); 1790 aml_append(dsdt, scope); 1791 1792 /* create fw_cfg node, unconditionally */ 1793 { 1794 scope = aml_scope("\\_SB.PCI0"); 1795 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1796 aml_append(dsdt, scope); 1797 } 1798 1799 if (misc->applesmc_io_base) { 1800 scope = aml_scope("\\_SB.PCI0.ISA"); 1801 dev = aml_device("SMC"); 1802 1803 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1804 /* device present, functioning, decoding, not shown in UI */ 1805 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1806 1807 crs = aml_resource_template(); 1808 aml_append(crs, 1809 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1810 0x01, APPLESMC_MAX_DATA_LENGTH) 1811 ); 1812 aml_append(crs, aml_irq_no_flags(6)); 1813 aml_append(dev, aml_name_decl("_CRS", crs)); 1814 1815 aml_append(scope, dev); 1816 aml_append(dsdt, scope); 1817 } 1818 1819 if (misc->pvpanic_port) { 1820 scope = aml_scope("\\_SB.PCI0.ISA"); 1821 1822 dev = aml_device("PEVT"); 1823 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1824 1825 crs = aml_resource_template(); 1826 aml_append(crs, 1827 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1828 ); 1829 aml_append(dev, aml_name_decl("_CRS", crs)); 1830 1831 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1832 aml_int(misc->pvpanic_port), 1)); 1833 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1834 aml_append(field, aml_named_field("PEPT", 8)); 1835 aml_append(dev, field); 1836 1837 /* device present, functioning, decoding, shown in UI */ 1838 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1839 1840 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1841 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1842 aml_append(method, aml_return(aml_local(0))); 1843 aml_append(dev, method); 1844 1845 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1846 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1847 aml_append(dev, method); 1848 1849 aml_append(scope, dev); 1850 aml_append(dsdt, scope); 1851 } 1852 1853 sb_scope = aml_scope("\\_SB"); 1854 { 1855 Object *pci_host; 1856 PCIBus *bus = NULL; 1857 1858 pci_host = acpi_get_i386_pci_host(); 1859 1860 if (pci_host) { 1861 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1862 } 1863 1864 if (bus) { 1865 Aml *scope = aml_scope("PCI0"); 1866 /* Scan all PCI buses. Generate tables to support hotplug. */ 1867 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1868 1869 #ifdef CONFIG_TPM 1870 if (TPM_IS_TIS_ISA(tpm)) { 1871 if (misc->tpm_version == TPM_VERSION_2_0) { 1872 dev = aml_device("TPM"); 1873 aml_append(dev, aml_name_decl("_HID", 1874 aml_string("MSFT0101"))); 1875 aml_append(dev, 1876 aml_name_decl("_STR", 1877 aml_string("TPM 2.0 Device"))); 1878 } else { 1879 dev = aml_device("ISA.TPM"); 1880 aml_append(dev, aml_name_decl("_HID", 1881 aml_eisaid("PNP0C31"))); 1882 } 1883 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1884 1885 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1886 crs = aml_resource_template(); 1887 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1888 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1889 /* 1890 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1891 Rewrite to take IRQ from TPM device model and 1892 fix default IRQ value there to use some unused IRQ 1893 */ 1894 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1895 aml_append(dev, aml_name_decl("_CRS", crs)); 1896 1897 tpm_build_ppi_acpi(tpm, dev); 1898 1899 aml_append(scope, dev); 1900 } 1901 #endif 1902 1903 aml_append(sb_scope, scope); 1904 } 1905 } 1906 1907 #ifdef CONFIG_TPM 1908 if (TPM_IS_CRB(tpm)) { 1909 dev = aml_device("TPM"); 1910 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1911 aml_append(dev, aml_name_decl("_STR", 1912 aml_string("TPM 2.0 Device"))); 1913 crs = aml_resource_template(); 1914 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1915 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1916 aml_append(dev, aml_name_decl("_CRS", crs)); 1917 1918 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1919 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1920 1921 tpm_build_ppi_acpi(tpm, dev); 1922 1923 aml_append(sb_scope, dev); 1924 } 1925 #endif 1926 1927 if (pcms->sgx_epc.size != 0) { 1928 uint64_t epc_base = pcms->sgx_epc.base; 1929 uint64_t epc_size = pcms->sgx_epc.size; 1930 1931 dev = aml_device("EPC"); 1932 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1933 aml_append(dev, aml_name_decl("_STR", 1934 aml_unicode("Enclave Page Cache 1.0"))); 1935 crs = aml_resource_template(); 1936 aml_append(crs, 1937 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1938 AML_MAX_FIXED, AML_NON_CACHEABLE, 1939 AML_READ_WRITE, 0, epc_base, 1940 epc_base + epc_size - 1, 0, epc_size)); 1941 aml_append(dev, aml_name_decl("_CRS", crs)); 1942 1943 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1944 aml_append(method, aml_return(aml_int(0x0f))); 1945 aml_append(dev, method); 1946 1947 aml_append(sb_scope, dev); 1948 } 1949 aml_append(dsdt, sb_scope); 1950 1951 /* copy AML table into ACPI tables blob and patch header there */ 1952 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1953 acpi_table_end(linker, &table); 1954 free_aml_allocator(); 1955 } 1956 1957 /* 1958 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1959 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1960 */ 1961 static void 1962 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1963 const char *oem_table_id) 1964 { 1965 AcpiTable table = { .sig = "HPET", .rev = 1, 1966 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1967 1968 acpi_table_begin(&table, table_data); 1969 /* Note timer_block_id value must be kept in sync with value advertised by 1970 * emulated hpet 1971 */ 1972 /* Event Timer Block ID */ 1973 build_append_int_noprefix(table_data, 0x8086a201, 4); 1974 /* BASE_ADDRESS */ 1975 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1976 /* HPET Number */ 1977 build_append_int_noprefix(table_data, 0, 1); 1978 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1979 build_append_int_noprefix(table_data, 0, 2); 1980 /* Page Protection And OEM Attribute */ 1981 build_append_int_noprefix(table_data, 0, 1); 1982 acpi_table_end(linker, &table); 1983 } 1984 1985 #ifdef CONFIG_TPM 1986 /* 1987 * TCPA Description Table 1988 * 1989 * Following Level 00, Rev 00.37 of specs: 1990 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1991 * 7.1.2 ACPI Table Layout 1992 */ 1993 static void 1994 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1995 const char *oem_id, const char *oem_table_id) 1996 { 1997 unsigned log_addr_offset; 1998 AcpiTable table = { .sig = "TCPA", .rev = 2, 1999 .oem_id = oem_id, .oem_table_id = oem_table_id }; 2000 2001 acpi_table_begin(&table, table_data); 2002 /* Platform Class */ 2003 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 2004 /* Log Area Minimum Length (LAML) */ 2005 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 2006 /* Log Area Start Address (LASA) */ 2007 log_addr_offset = table_data->len; 2008 build_append_int_noprefix(table_data, 0, 8); 2009 2010 /* allocate/reserve space for TPM log area */ 2011 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 2012 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2013 false /* high memory */); 2014 /* log area start address to be filled by Guest linker */ 2015 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2016 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 2017 2018 acpi_table_end(linker, &table); 2019 } 2020 #endif 2021 2022 #define HOLE_640K_START (640 * KiB) 2023 #define HOLE_640K_END (1 * MiB) 2024 2025 /* 2026 * ACPI spec, Revision 3.0 2027 * 5.2.15 System Resource Affinity Table (SRAT) 2028 */ 2029 static void 2030 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2031 { 2032 int i; 2033 int numa_mem_start, slots; 2034 uint64_t mem_len, mem_base, next_base; 2035 MachineClass *mc = MACHINE_GET_CLASS(machine); 2036 X86MachineState *x86ms = X86_MACHINE(machine); 2037 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2038 PCMachineState *pcms = PC_MACHINE(machine); 2039 int nb_numa_nodes = machine->numa_state->num_nodes; 2040 NodeInfo *numa_info = machine->numa_state->nodes; 2041 ram_addr_t hotpluggable_address_space_size = 2042 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 2043 NULL); 2044 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 2045 .oem_table_id = x86ms->oem_table_id }; 2046 2047 acpi_table_begin(&table, table_data); 2048 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 2049 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 2050 2051 for (i = 0; i < apic_ids->len; i++) { 2052 int node_id = apic_ids->cpus[i].props.node_id; 2053 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2054 2055 if (apic_id < 255) { 2056 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 2057 build_append_int_noprefix(table_data, 0, 1); /* Type */ 2058 build_append_int_noprefix(table_data, 16, 1); /* Length */ 2059 /* Proximity Domain [7:0] */ 2060 build_append_int_noprefix(table_data, node_id, 1); 2061 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 2062 /* Flags, Table 5-36 */ 2063 build_append_int_noprefix(table_data, 1, 4); 2064 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 2065 /* Proximity Domain [31:8] */ 2066 build_append_int_noprefix(table_data, 0, 3); 2067 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2068 } else { 2069 /* 2070 * ACPI spec, Revision 4.0 2071 * 5.2.16.3 Processor Local x2APIC Affinity Structure 2072 */ 2073 build_append_int_noprefix(table_data, 2, 1); /* Type */ 2074 build_append_int_noprefix(table_data, 24, 1); /* Length */ 2075 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2076 /* Proximity Domain */ 2077 build_append_int_noprefix(table_data, node_id, 4); 2078 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 2079 /* Flags, Table 5-39 */ 2080 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 2081 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 2082 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2083 } 2084 } 2085 2086 /* the memory map is a bit tricky, it contains at least one hole 2087 * from 640k-1M and possibly another one from 3.5G-4G. 2088 */ 2089 next_base = 0; 2090 numa_mem_start = table_data->len; 2091 2092 for (i = 1; i < nb_numa_nodes + 1; ++i) { 2093 mem_base = next_base; 2094 mem_len = numa_info[i - 1].node_mem; 2095 next_base = mem_base + mem_len; 2096 2097 /* Cut out the 640K hole */ 2098 if (mem_base <= HOLE_640K_START && 2099 next_base > HOLE_640K_START) { 2100 mem_len -= next_base - HOLE_640K_START; 2101 if (mem_len > 0) { 2102 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2103 MEM_AFFINITY_ENABLED); 2104 } 2105 2106 /* Check for the rare case: 640K < RAM < 1M */ 2107 if (next_base <= HOLE_640K_END) { 2108 next_base = HOLE_640K_END; 2109 continue; 2110 } 2111 mem_base = HOLE_640K_END; 2112 mem_len = next_base - HOLE_640K_END; 2113 } 2114 2115 /* Cut out the ACPI_PCI hole */ 2116 if (mem_base <= x86ms->below_4g_mem_size && 2117 next_base > x86ms->below_4g_mem_size) { 2118 mem_len -= next_base - x86ms->below_4g_mem_size; 2119 if (mem_len > 0) { 2120 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2121 MEM_AFFINITY_ENABLED); 2122 } 2123 mem_base = 1ULL << 32; 2124 mem_len = next_base - x86ms->below_4g_mem_size; 2125 next_base = mem_base + mem_len; 2126 } 2127 2128 if (mem_len > 0) { 2129 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2130 MEM_AFFINITY_ENABLED); 2131 } 2132 } 2133 2134 if (machine->nvdimms_state->is_enabled) { 2135 nvdimm_build_srat(table_data); 2136 } 2137 2138 sgx_epc_build_srat(table_data); 2139 2140 /* 2141 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2142 * without these entries. But I recall there were issues the last time I 2143 * tried to remove it with some ancient guest OS, however I can't remember 2144 * what that was so keep this around for now 2145 */ 2146 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2147 for (; slots < nb_numa_nodes + 2; slots++) { 2148 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2149 } 2150 2151 /* 2152 * Entry is required for Windows to enable memory hotplug in OS 2153 * and for Linux to enable SWIOTLB when booted with less than 2154 * 4G of RAM. Windows works better if the entry sets proximity 2155 * to the highest NUMA node in the machine. 2156 * Memory devices may override proximity set by this entry, 2157 * providing _PXM method if necessary. 2158 */ 2159 if (hotpluggable_address_space_size) { 2160 build_srat_memory(table_data, machine->device_memory->base, 2161 hotpluggable_address_space_size, nb_numa_nodes - 1, 2162 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2163 } 2164 2165 acpi_table_end(linker, &table); 2166 } 2167 2168 /* 2169 * Insert DMAR scope for PCI bridges and endpoint devcie 2170 */ 2171 static void 2172 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2173 { 2174 const size_t device_scope_size = 6 /* device scope structure */ + 2175 2 /* 1 path entry */; 2176 GArray *scope_blob = opaque; 2177 2178 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2179 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2180 build_append_int_noprefix(scope_blob, 0x02, 1); 2181 } else { 2182 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2183 build_append_int_noprefix(scope_blob, 0x01, 1); 2184 } 2185 2186 /* length */ 2187 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2188 /* reserved */ 2189 build_append_int_noprefix(scope_blob, 0, 2); 2190 /* enumeration_id */ 2191 build_append_int_noprefix(scope_blob, 0, 1); 2192 /* bus */ 2193 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2194 /* device */ 2195 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2196 /* function */ 2197 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2198 } 2199 2200 /* For a given PCI host bridge, walk and insert DMAR scope */ 2201 static int 2202 dmar_host_bridges(Object *obj, void *opaque) 2203 { 2204 GArray *scope_blob = opaque; 2205 2206 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2207 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2208 2209 if (bus && !pci_bus_bypass_iommu(bus)) { 2210 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2211 } 2212 } 2213 2214 return 0; 2215 } 2216 2217 /* 2218 * Intel ® Virtualization Technology for Directed I/O 2219 * Architecture Specification. Revision 3.3 2220 * 8.1 DMA Remapping Reporting Structure 2221 */ 2222 static void 2223 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2224 const char *oem_table_id) 2225 { 2226 uint8_t dmar_flags = 0; 2227 uint8_t rsvd10[10] = {}; 2228 /* Root complex IOAPIC uses one path only */ 2229 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2230 2 /* 1 path entry */; 2231 X86IOMMUState *iommu = x86_iommu_get_default(); 2232 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2233 GArray *scope_blob = g_array_new(false, true, 1); 2234 2235 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2236 .oem_table_id = oem_table_id }; 2237 2238 /* 2239 * A PCI bus walk, for each PCI host bridge. 2240 * Insert scope for each PCI bridge and endpoint device which 2241 * is attached to a bus with iommu enabled. 2242 */ 2243 object_child_foreach_recursive(object_get_root(), 2244 dmar_host_bridges, scope_blob); 2245 2246 assert(iommu); 2247 if (x86_iommu_ir_supported(iommu)) { 2248 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2249 } 2250 2251 acpi_table_begin(&table, table_data); 2252 /* Host Address Width */ 2253 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2254 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2255 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2256 2257 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2258 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2259 /* Length */ 2260 build_append_int_noprefix(table_data, 2261 16 + ioapic_scope_size + scope_blob->len, 2); 2262 /* Flags */ 2263 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2264 1); 2265 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2266 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2267 /* Register Base Address */ 2268 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2269 2270 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2271 * 8.3.1 (version Oct. 2014 or later). */ 2272 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2273 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2274 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2275 /* Enumeration ID */ 2276 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2277 /* Start Bus Number */ 2278 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2279 /* Path, {Device, Function} pair */ 2280 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2281 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2282 2283 /* Add scope found above */ 2284 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2285 g_array_free(scope_blob, true); 2286 2287 if (iommu->dt_supported) { 2288 /* 8.5 Root Port ATS Capability Reporting Structure */ 2289 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2290 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2291 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2292 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2293 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2294 } 2295 2296 acpi_table_end(linker, &table); 2297 } 2298 2299 /* 2300 * Windows ACPI Emulated Devices Table 2301 * (Version 1.0 - April 6, 2009) 2302 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2303 * 2304 * Helpful to speedup Windows guests and ignored by others. 2305 */ 2306 static void 2307 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2308 const char *oem_table_id) 2309 { 2310 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2311 .oem_table_id = oem_table_id }; 2312 2313 acpi_table_begin(&table, table_data); 2314 /* 2315 * Set "ACPI PM timer good" flag. 2316 * 2317 * Tells Windows guests that our ACPI PM timer is reliable in the 2318 * sense that guest can read it only once to obtain a reliable value. 2319 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2320 */ 2321 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2322 acpi_table_end(linker, &table); 2323 } 2324 2325 /* 2326 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2327 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2328 */ 2329 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2330 2331 /* 2332 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2333 * necessary for the PCI topology. 2334 */ 2335 static void 2336 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2337 { 2338 GArray *table_data = opaque; 2339 uint32_t entry; 2340 2341 /* "Select" IVHD entry, type 0x2 */ 2342 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2343 build_append_int_noprefix(table_data, entry, 4); 2344 2345 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2346 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2347 uint8_t sec = pci_bus_num(sec_bus); 2348 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2349 2350 if (pci_bus_is_express(sec_bus)) { 2351 /* 2352 * Walk the bus if there are subordinates, otherwise use a range 2353 * to cover an entire leaf bus. We could potentially also use a 2354 * range for traversed buses, but we'd need to take care not to 2355 * create both Select and Range entries covering the same device. 2356 * This is easier and potentially more compact. 2357 * 2358 * An example bare metal system seems to use Select entries for 2359 * root ports without a slot (ie. built-ins) and Range entries 2360 * when there is a slot. The same system also only hard-codes 2361 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2362 * making no effort to support nested bridges. We attempt to 2363 * be more thorough here. 2364 */ 2365 if (sec == sub) { /* leaf bus */ 2366 /* "Start of Range" IVHD entry, type 0x3 */ 2367 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2368 build_append_int_noprefix(table_data, entry, 4); 2369 /* "End of Range" IVHD entry, type 0x4 */ 2370 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2371 build_append_int_noprefix(table_data, entry, 4); 2372 } else { 2373 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2374 } 2375 } else { 2376 /* 2377 * If the secondary bus is conventional, then we need to create an 2378 * Alias range for everything downstream. The range covers the 2379 * first devfn on the secondary bus to the last devfn on the 2380 * subordinate bus. The alias target depends on legacy versus 2381 * express bridges, just as in pci_device_iommu_address_space(). 2382 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2383 */ 2384 uint16_t dev_id_a, dev_id_b; 2385 2386 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2387 2388 if (pci_is_express(dev) && 2389 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2390 dev_id_b = dev_id_a; 2391 } else { 2392 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2393 } 2394 2395 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2396 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2397 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2398 2399 /* "End of Range" IVHD entry, type 0x4 */ 2400 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2401 build_append_int_noprefix(table_data, entry, 4); 2402 } 2403 } 2404 } 2405 2406 /* For all PCI host bridges, walk and insert IVHD entries */ 2407 static int 2408 ivrs_host_bridges(Object *obj, void *opaque) 2409 { 2410 GArray *ivhd_blob = opaque; 2411 2412 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2413 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2414 2415 if (bus && !pci_bus_bypass_iommu(bus)) { 2416 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2417 } 2418 } 2419 2420 return 0; 2421 } 2422 2423 static void 2424 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2425 const char *oem_table_id) 2426 { 2427 int ivhd_table_len = 24; 2428 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2429 GArray *ivhd_blob = g_array_new(false, true, 1); 2430 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2431 .oem_table_id = oem_table_id }; 2432 2433 acpi_table_begin(&table, table_data); 2434 /* IVinfo - IO virtualization information common to all 2435 * IOMMU units in a system 2436 */ 2437 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2438 /* reserved */ 2439 build_append_int_noprefix(table_data, 0, 8); 2440 2441 /* IVHD definition - type 10h */ 2442 build_append_int_noprefix(table_data, 0x10, 1); 2443 /* virtualization flags */ 2444 build_append_int_noprefix(table_data, 2445 (1UL << 0) | /* HtTunEn */ 2446 (1UL << 4) | /* iotblSup */ 2447 (1UL << 6) | /* PrefSup */ 2448 (1UL << 7), /* PPRSup */ 2449 1); 2450 2451 /* 2452 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2453 * complete set of IVHD entries. Do this into a separate blob so that we 2454 * can calculate the total IVRS table length here and then append the new 2455 * blob further below. Fall back to an entry covering all devices, which 2456 * is sufficient when no aliases are present. 2457 */ 2458 object_child_foreach_recursive(object_get_root(), 2459 ivrs_host_bridges, ivhd_blob); 2460 2461 if (!ivhd_blob->len) { 2462 /* 2463 * Type 1 device entry reporting all devices 2464 * These are 4-byte device entries currently reporting the range of 2465 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2466 */ 2467 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2468 } 2469 2470 ivhd_table_len += ivhd_blob->len; 2471 2472 /* 2473 * When interrupt remapping is supported, we add a special IVHD device 2474 * for type IO-APIC. 2475 */ 2476 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2477 ivhd_table_len += 8; 2478 } 2479 2480 /* IVHD length */ 2481 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2482 /* DeviceID */ 2483 build_append_int_noprefix(table_data, s->devid, 2); 2484 /* Capability offset */ 2485 build_append_int_noprefix(table_data, s->capab_offset, 2); 2486 /* IOMMU base address */ 2487 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2488 /* PCI Segment Group */ 2489 build_append_int_noprefix(table_data, 0, 2); 2490 /* IOMMU info */ 2491 build_append_int_noprefix(table_data, 0, 2); 2492 /* IOMMU Feature Reporting */ 2493 build_append_int_noprefix(table_data, 2494 (48UL << 30) | /* HATS */ 2495 (48UL << 28) | /* GATS */ 2496 (1UL << 2) | /* GTSup */ 2497 (1UL << 6), /* GASup */ 2498 4); 2499 2500 /* IVHD entries as found above */ 2501 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2502 g_array_free(ivhd_blob, TRUE); 2503 2504 /* 2505 * Add a special IVHD device type. 2506 * Refer to spec - Table 95: IVHD device entry type codes 2507 * 2508 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2509 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2510 */ 2511 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2512 build_append_int_noprefix(table_data, 2513 (0x1ull << 56) | /* type IOAPIC */ 2514 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2515 0x48, /* special device */ 2516 8); 2517 } 2518 acpi_table_end(linker, &table); 2519 } 2520 2521 typedef 2522 struct AcpiBuildState { 2523 /* Copy of table in RAM (for patching). */ 2524 MemoryRegion *table_mr; 2525 /* Is table patched? */ 2526 uint8_t patched; 2527 void *rsdp; 2528 MemoryRegion *rsdp_mr; 2529 MemoryRegion *linker_mr; 2530 } AcpiBuildState; 2531 2532 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2533 { 2534 Object *pci_host; 2535 QObject *o; 2536 2537 pci_host = acpi_get_i386_pci_host(); 2538 if (!pci_host) { 2539 return false; 2540 } 2541 2542 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2543 if (!o) { 2544 return false; 2545 } 2546 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2547 qobject_unref(o); 2548 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2549 return false; 2550 } 2551 2552 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2553 assert(o); 2554 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2555 qobject_unref(o); 2556 return true; 2557 } 2558 2559 static 2560 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2561 { 2562 PCMachineState *pcms = PC_MACHINE(machine); 2563 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2564 X86MachineState *x86ms = X86_MACHINE(machine); 2565 DeviceState *iommu = pcms->iommu; 2566 GArray *table_offsets; 2567 unsigned facs, dsdt, rsdt, fadt; 2568 AcpiPmInfo pm; 2569 AcpiMiscInfo misc; 2570 AcpiMcfgInfo mcfg; 2571 Range pci_hole = {}, pci_hole64 = {}; 2572 uint8_t *u; 2573 size_t aml_len = 0; 2574 GArray *tables_blob = tables->table_data; 2575 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2576 Object *vmgenid_dev; 2577 char *oem_id; 2578 char *oem_table_id; 2579 2580 acpi_get_pm_info(machine, &pm); 2581 acpi_get_misc_info(&misc); 2582 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2583 acpi_get_slic_oem(&slic_oem); 2584 2585 if (slic_oem.id) { 2586 oem_id = slic_oem.id; 2587 } else { 2588 oem_id = x86ms->oem_id; 2589 } 2590 2591 if (slic_oem.table_id) { 2592 oem_table_id = slic_oem.table_id; 2593 } else { 2594 oem_table_id = x86ms->oem_table_id; 2595 } 2596 2597 table_offsets = g_array_new(false, true /* clear */, 2598 sizeof(uint32_t)); 2599 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2600 2601 bios_linker_loader_alloc(tables->linker, 2602 ACPI_BUILD_TABLE_FILE, tables_blob, 2603 64 /* Ensure FACS is aligned */, 2604 false /* high memory */); 2605 2606 /* 2607 * FACS is pointed to by FADT. 2608 * We place it first since it's the only table that has alignment 2609 * requirements. 2610 */ 2611 facs = tables_blob->len; 2612 build_facs(tables_blob); 2613 2614 /* DSDT is pointed to by FADT */ 2615 dsdt = tables_blob->len; 2616 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2617 &pci_hole, &pci_hole64, machine); 2618 2619 /* Count the size of the DSDT and SSDT, we will need it for legacy 2620 * sizing of ACPI tables. 2621 */ 2622 aml_len += tables_blob->len - dsdt; 2623 2624 /* ACPI tables pointed to by RSDT */ 2625 fadt = tables_blob->len; 2626 acpi_add_table(table_offsets, tables_blob); 2627 pm.fadt.facs_tbl_offset = &facs; 2628 pm.fadt.dsdt_tbl_offset = &dsdt; 2629 pm.fadt.xdsdt_tbl_offset = &dsdt; 2630 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2631 aml_len += tables_blob->len - fadt; 2632 2633 acpi_add_table(table_offsets, tables_blob); 2634 acpi_build_madt(tables_blob, tables->linker, x86ms, 2635 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2636 x86ms->oem_table_id); 2637 2638 #ifdef CONFIG_ACPI_ERST 2639 { 2640 Object *erst_dev; 2641 erst_dev = find_erst_dev(); 2642 if (erst_dev) { 2643 acpi_add_table(table_offsets, tables_blob); 2644 build_erst(tables_blob, tables->linker, erst_dev, 2645 x86ms->oem_id, x86ms->oem_table_id); 2646 } 2647 } 2648 #endif 2649 2650 vmgenid_dev = find_vmgenid_dev(); 2651 if (vmgenid_dev) { 2652 acpi_add_table(table_offsets, tables_blob); 2653 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2654 tables->vmgenid, tables->linker, x86ms->oem_id); 2655 } 2656 2657 if (misc.has_hpet) { 2658 acpi_add_table(table_offsets, tables_blob); 2659 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2660 x86ms->oem_table_id); 2661 } 2662 #ifdef CONFIG_TPM 2663 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2664 if (misc.tpm_version == TPM_VERSION_1_2) { 2665 acpi_add_table(table_offsets, tables_blob); 2666 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2667 x86ms->oem_id, x86ms->oem_table_id); 2668 } else { /* TPM_VERSION_2_0 */ 2669 acpi_add_table(table_offsets, tables_blob); 2670 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2671 x86ms->oem_id, x86ms->oem_table_id); 2672 } 2673 } 2674 #endif 2675 if (machine->numa_state->num_nodes) { 2676 acpi_add_table(table_offsets, tables_blob); 2677 build_srat(tables_blob, tables->linker, machine); 2678 if (machine->numa_state->have_numa_distance) { 2679 acpi_add_table(table_offsets, tables_blob); 2680 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2681 x86ms->oem_table_id); 2682 } 2683 if (machine->numa_state->hmat_enabled) { 2684 acpi_add_table(table_offsets, tables_blob); 2685 build_hmat(tables_blob, tables->linker, machine->numa_state, 2686 x86ms->oem_id, x86ms->oem_table_id); 2687 } 2688 } 2689 if (acpi_get_mcfg(&mcfg)) { 2690 acpi_add_table(table_offsets, tables_blob); 2691 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2692 x86ms->oem_table_id); 2693 } 2694 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2695 acpi_add_table(table_offsets, tables_blob); 2696 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2697 x86ms->oem_table_id); 2698 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2699 acpi_add_table(table_offsets, tables_blob); 2700 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2701 x86ms->oem_table_id); 2702 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2703 PCIDevice *pdev = PCI_DEVICE(iommu); 2704 2705 acpi_add_table(table_offsets, tables_blob); 2706 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2707 x86ms->oem_id, x86ms->oem_table_id); 2708 } 2709 if (machine->nvdimms_state->is_enabled) { 2710 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2711 machine->nvdimms_state, machine->ram_slots, 2712 x86ms->oem_id, x86ms->oem_table_id); 2713 } 2714 if (machine->cxl_devices_state->is_enabled) { 2715 cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker, 2716 x86ms->oem_id, x86ms->oem_table_id); 2717 } 2718 2719 acpi_add_table(table_offsets, tables_blob); 2720 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2721 2722 /* Add tables supplied by user (if any) */ 2723 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2724 unsigned len = acpi_table_len(u); 2725 2726 acpi_add_table(table_offsets, tables_blob); 2727 g_array_append_vals(tables_blob, u, len); 2728 } 2729 2730 /* RSDT is pointed to by RSDP */ 2731 rsdt = tables_blob->len; 2732 build_rsdt(tables_blob, tables->linker, table_offsets, 2733 oem_id, oem_table_id); 2734 2735 /* RSDP is in FSEG memory, so allocate it separately */ 2736 { 2737 AcpiRsdpData rsdp_data = { 2738 .revision = 0, 2739 .oem_id = x86ms->oem_id, 2740 .xsdt_tbl_offset = NULL, 2741 .rsdt_tbl_offset = &rsdt, 2742 }; 2743 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2744 if (!pcmc->rsdp_in_ram) { 2745 /* We used to allocate some extra space for RSDP revision 2 but 2746 * only used the RSDP revision 0 space. The extra bytes were 2747 * zeroed out and not used. 2748 * Here we continue wasting those extra 16 bytes to make sure we 2749 * don't break migration for machine types 2.2 and older due to 2750 * RSDP blob size mismatch. 2751 */ 2752 build_append_int_noprefix(tables->rsdp, 0, 16); 2753 } 2754 } 2755 2756 /* We'll expose it all to Guest so we want to reduce 2757 * chance of size changes. 2758 * 2759 * We used to align the tables to 4k, but of course this would 2760 * too simple to be enough. 4k turned out to be too small an 2761 * alignment very soon, and in fact it is almost impossible to 2762 * keep the table size stable for all (max_cpus, max_memory_slots) 2763 * combinations. So the table size is always 64k for pc-i440fx-2.1 2764 * and we give an error if the table grows beyond that limit. 2765 * 2766 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2767 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2768 * than 2.0 and we can always pad the smaller tables with zeros. We can 2769 * then use the exact size of the 2.0 tables. 2770 * 2771 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2772 */ 2773 if (pcmc->legacy_acpi_table_size) { 2774 /* Subtracting aml_len gives the size of fixed tables. Then add the 2775 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2776 */ 2777 int legacy_aml_len = 2778 pcmc->legacy_acpi_table_size + 2779 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2780 int legacy_table_size = 2781 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2782 ACPI_BUILD_ALIGN_SIZE); 2783 if (tables_blob->len > legacy_table_size) { 2784 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2785 warn_report("ACPI table size %u exceeds %d bytes," 2786 " migration may not work", 2787 tables_blob->len, legacy_table_size); 2788 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2789 " or PCI bridges."); 2790 } 2791 g_array_set_size(tables_blob, legacy_table_size); 2792 } else { 2793 /* Make sure we have a buffer in case we need to resize the tables. */ 2794 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2795 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2796 warn_report("ACPI table size %u exceeds %d bytes," 2797 " migration may not work", 2798 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2799 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2800 " or PCI bridges."); 2801 } 2802 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2803 } 2804 2805 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2806 2807 /* Cleanup memory that's no longer used. */ 2808 g_array_free(table_offsets, true); 2809 g_free(slic_oem.id); 2810 g_free(slic_oem.table_id); 2811 } 2812 2813 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2814 { 2815 uint32_t size = acpi_data_len(data); 2816 2817 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2818 memory_region_ram_resize(mr, size, &error_abort); 2819 2820 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2821 memory_region_set_dirty(mr, 0, size); 2822 } 2823 2824 static void acpi_build_update(void *build_opaque) 2825 { 2826 AcpiBuildState *build_state = build_opaque; 2827 AcpiBuildTables tables; 2828 2829 /* No state to update or already patched? Nothing to do. */ 2830 if (!build_state || build_state->patched) { 2831 return; 2832 } 2833 build_state->patched = 1; 2834 2835 acpi_build_tables_init(&tables); 2836 2837 acpi_build(&tables, MACHINE(qdev_get_machine())); 2838 2839 acpi_ram_update(build_state->table_mr, tables.table_data); 2840 2841 if (build_state->rsdp) { 2842 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2843 } else { 2844 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2845 } 2846 2847 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2848 acpi_build_tables_cleanup(&tables, true); 2849 } 2850 2851 static void acpi_build_reset(void *build_opaque) 2852 { 2853 AcpiBuildState *build_state = build_opaque; 2854 build_state->patched = 0; 2855 } 2856 2857 static const VMStateDescription vmstate_acpi_build = { 2858 .name = "acpi_build", 2859 .version_id = 1, 2860 .minimum_version_id = 1, 2861 .fields = (VMStateField[]) { 2862 VMSTATE_UINT8(patched, AcpiBuildState), 2863 VMSTATE_END_OF_LIST() 2864 }, 2865 }; 2866 2867 void acpi_setup(void) 2868 { 2869 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2870 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2871 X86MachineState *x86ms = X86_MACHINE(pcms); 2872 AcpiBuildTables tables; 2873 AcpiBuildState *build_state; 2874 Object *vmgenid_dev; 2875 #ifdef CONFIG_TPM 2876 TPMIf *tpm; 2877 static FwCfgTPMConfig tpm_config; 2878 #endif 2879 2880 if (!x86ms->fw_cfg) { 2881 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2882 return; 2883 } 2884 2885 if (!pcms->acpi_build_enabled) { 2886 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2887 return; 2888 } 2889 2890 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2891 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2892 return; 2893 } 2894 2895 build_state = g_malloc0(sizeof *build_state); 2896 2897 acpi_build_tables_init(&tables); 2898 acpi_build(&tables, MACHINE(pcms)); 2899 2900 /* Now expose it all to Guest */ 2901 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2902 build_state, tables.table_data, 2903 ACPI_BUILD_TABLE_FILE); 2904 assert(build_state->table_mr != NULL); 2905 2906 build_state->linker_mr = 2907 acpi_add_rom_blob(acpi_build_update, build_state, 2908 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2909 2910 #ifdef CONFIG_TPM 2911 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2912 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2913 2914 tpm = tpm_find(); 2915 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2916 tpm_config = (FwCfgTPMConfig) { 2917 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2918 .tpm_version = tpm_get_version(tpm), 2919 .tpmppi_version = TPM_PPI_VERSION_1_30 2920 }; 2921 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2922 &tpm_config, sizeof tpm_config); 2923 } 2924 #endif 2925 2926 vmgenid_dev = find_vmgenid_dev(); 2927 if (vmgenid_dev) { 2928 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2929 tables.vmgenid); 2930 } 2931 2932 if (!pcmc->rsdp_in_ram) { 2933 /* 2934 * Keep for compatibility with old machine types. 2935 * Though RSDP is small, its contents isn't immutable, so 2936 * we'll update it along with the rest of tables on guest access. 2937 */ 2938 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2939 2940 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2941 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2942 acpi_build_update, NULL, build_state, 2943 build_state->rsdp, rsdp_size, true); 2944 build_state->rsdp_mr = NULL; 2945 } else { 2946 build_state->rsdp = NULL; 2947 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2948 build_state, tables.rsdp, 2949 ACPI_BUILD_RSDP_FILE); 2950 } 2951 2952 qemu_register_reset(acpi_build_reset, build_state); 2953 acpi_build_reset(build_state); 2954 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2955 2956 /* Cleanup tables but don't free the memory: we track it 2957 * in build_state. 2958 */ 2959 acpi_build_tables_cleanup(&tables, false); 2960 } 2961