1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/ich9.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/pc.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 80 #include CONFIG_DEVICES 81 82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 84 * a little bit, there should be plenty of free space since the DSDT 85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 86 */ 87 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 88 #define ACPI_BUILD_ALIGN_SIZE 0x1000 89 90 #define ACPI_BUILD_TABLE_SIZE 0x20000 91 92 /* #define DEBUG_ACPI_BUILD */ 93 #ifdef DEBUG_ACPI_BUILD 94 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 96 #else 97 #define ACPI_BUILD_DPRINTF(fmt, ...) 98 #endif 99 100 typedef struct AcpiPmInfo { 101 bool s3_disabled; 102 bool s4_disabled; 103 bool pcihp_bridge_en; 104 bool smi_on_cpuhp; 105 bool smi_on_cpu_unplug; 106 bool pcihp_root_en; 107 uint8_t s4_val; 108 AcpiFadtData fadt; 109 uint16_t cpu_hp_io_base; 110 uint16_t pcihp_io_base; 111 uint16_t pcihp_io_len; 112 } AcpiPmInfo; 113 114 typedef struct AcpiMiscInfo { 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 } AcpiMiscInfo; 120 121 typedef struct FwCfgTPMConfig { 122 uint32_t tpmppi_address; 123 uint8_t tpm_version; 124 uint8_t tpmppi_version; 125 } QEMU_PACKED FwCfgTPMConfig; 126 127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 128 129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 130 .space_id = AML_AS_SYSTEM_IO, 131 .address = NVDIMM_ACPI_IO_BASE, 132 .bit_width = NVDIMM_ACPI_IO_LEN << 3 133 }; 134 135 static void init_common_fadt_data(MachineState *ms, Object *o, 136 AcpiFadtData *data) 137 { 138 X86MachineState *x86ms = X86_MACHINE(ms); 139 /* 140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 141 * behavior for compatibility irrelevant to smm_enabled, which doesn't 142 * comforms to ACPI spec. 143 */ 144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 145 true : x86_machine_is_smm_enabled(x86ms); 146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 147 AmlAddressSpace as = AML_AS_SYSTEM_IO; 148 AcpiFadtData fadt = { 149 .rev = 3, 150 .flags = 151 (1 << ACPI_FADT_F_WBINVD) | 152 (1 << ACPI_FADT_F_PROC_C1) | 153 (1 << ACPI_FADT_F_SLP_BUTTON) | 154 (1 << ACPI_FADT_F_RTC_S4) | 155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 156 /* APIC destination mode ("Flat Logical") has an upper limit of 8 157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 158 * used 159 */ 160 ((ms->smp.max_cpus > 8) ? 161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 162 .int_model = 1 /* Multiple APIC */, 163 .rtc_century = RTC_CENTURY, 164 .plvl2_lat = 0xfff /* C2 state not supported */, 165 .plvl3_lat = 0xfff /* C3 state not supported */, 166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 168 .acpi_enable_cmd = 169 smm_enabled ? 170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 171 0, 172 .acpi_disable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 175 0, 176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 178 .address = io + 0x04 }, 179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 180 .gpe0_blk = { .space_id = as, .bit_width = 181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 183 }, 184 }; 185 186 /* 187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 188 * Flags, bit offset 1 - 8042. 189 */ 190 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 191 192 *data = fadt; 193 } 194 195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 196 { 197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL); 198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL); 199 Object *obj = piix ? piix : lpc; 200 QObject *o; 201 pm->cpu_hp_io_base = 0; 202 pm->pcihp_io_base = 0; 203 pm->pcihp_io_len = 0; 204 pm->smi_on_cpuhp = false; 205 pm->smi_on_cpu_unplug = false; 206 207 assert(obj); 208 init_common_fadt_data(machine, obj, &pm->fadt); 209 if (piix) { 210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 211 pm->fadt.rev = 1; 212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 213 } 214 if (lpc) { 215 uint64_t smi_features = object_property_get_uint(lpc, 216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 219 pm->fadt.reset_reg = r; 220 pm->fadt.reset_val = 0xf; 221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 223 pm->smi_on_cpuhp = 224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 225 pm->smi_on_cpu_unplug = 226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 227 } 228 pm->pcihp_io_base = 229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 230 pm->pcihp_io_len = 231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 232 233 /* Fill in optional s3/s4 related properties */ 234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 235 if (o) { 236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 237 } else { 238 pm->s3_disabled = false; 239 } 240 qobject_unref(o); 241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 242 if (o) { 243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 244 } else { 245 pm->s4_disabled = false; 246 } 247 qobject_unref(o); 248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 249 if (o) { 250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 251 } else { 252 pm->s4_val = false; 253 } 254 qobject_unref(o); 255 256 pm->pcihp_bridge_en = 257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 258 NULL); 259 pm->pcihp_root_en = 260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 261 NULL); 262 } 263 264 static void acpi_get_misc_info(AcpiMiscInfo *info) 265 { 266 info->has_hpet = hpet_find(); 267 #ifdef CONFIG_TPM 268 info->tpm_version = tpm_get_version(tpm_find()); 269 #endif 270 } 271 272 /* 273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 274 * On i386 arch we only have two pci hosts, so we can look only for them. 275 */ 276 Object *acpi_get_i386_pci_host(void) 277 { 278 PCIHostState *host; 279 280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 281 if (!host) { 282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 283 } 284 285 return OBJECT(host); 286 } 287 288 static void acpi_get_pci_holes(Range *hole, Range *hole64) 289 { 290 Object *pci_host; 291 292 pci_host = acpi_get_i386_pci_host(); 293 294 if (!pci_host) { 295 return; 296 } 297 298 range_set_bounds1(hole, 299 object_property_get_uint(pci_host, 300 PCI_HOST_PROP_PCI_HOLE_START, 301 NULL), 302 object_property_get_uint(pci_host, 303 PCI_HOST_PROP_PCI_HOLE_END, 304 NULL)); 305 range_set_bounds1(hole64, 306 object_property_get_uint(pci_host, 307 PCI_HOST_PROP_PCI_HOLE64_START, 308 NULL), 309 object_property_get_uint(pci_host, 310 PCI_HOST_PROP_PCI_HOLE64_END, 311 NULL)); 312 } 313 314 static void acpi_align_size(GArray *blob, unsigned align) 315 { 316 /* Align size to multiple of given size. This reduces the chance 317 * we need to change size in the future (breaking cross version migration). 318 */ 319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 320 } 321 322 /* 323 * ACPI spec 1.0b, 324 * 5.2.6 Firmware ACPI Control Structure 325 */ 326 static void 327 build_facs(GArray *table_data) 328 { 329 const char *sig = "FACS"; 330 const uint8_t reserved[40] = {}; 331 332 g_array_append_vals(table_data, sig, 4); /* Signature */ 333 build_append_int_noprefix(table_data, 64, 4); /* Length */ 334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 337 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 338 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 339 } 340 341 Aml *aml_pci_device_dsm(void) 342 { 343 Aml *method; 344 345 method = aml_method("_DSM", 4, AML_SERIALIZED); 346 { 347 Aml *params = aml_local(0); 348 Aml *pkg = aml_package(2); 349 aml_append(pkg, aml_int(0)); 350 aml_append(pkg, aml_int(0)); 351 aml_append(method, aml_store(pkg, params)); 352 aml_append(method, 353 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); 354 aml_append(method, 355 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); 356 aml_append(method, 357 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 358 aml_arg(2), aml_arg(3), params)) 359 ); 360 } 361 return method; 362 } 363 364 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) 365 { 366 Aml *UUID, *ifctx1; 367 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 368 369 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); 370 /* 371 * PCI Firmware Specification 3.1 372 * 4.6. _DSM Definitions for PCI 373 */ 374 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 375 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 376 { 377 /* call is for unsupported UUID, bail out */ 378 aml_append(ifctx1, aml_return(retvar)); 379 } 380 aml_append(ctx, ifctx1); 381 382 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2))); 383 { 384 /* call is for unsupported REV, bail out */ 385 aml_append(ifctx1, aml_return(retvar)); 386 } 387 aml_append(ctx, ifctx1); 388 } 389 390 static Aml *aml_pci_edsm(void) 391 { 392 Aml *method, *ifctx; 393 Aml *zero = aml_int(0); 394 Aml *func = aml_arg(2); 395 Aml *ret = aml_local(0); 396 Aml *aidx = aml_local(1); 397 Aml *params = aml_arg(4); 398 399 method = aml_method("EDSM", 5, AML_SERIALIZED); 400 401 /* get supported functions */ 402 ifctx = aml_if(aml_equal(func, zero)); 403 { 404 /* 1: have supported functions */ 405 /* 7: support for function 7 */ 406 const uint8_t caps = 1 | BIT(7); 407 build_append_pci_dsm_func0_common(ifctx, ret); 408 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 409 aml_append(ifctx, aml_return(ret)); 410 } 411 aml_append(method, ifctx); 412 413 /* handle specific functions requests */ 414 /* 415 * PCI Firmware Specification 3.1 416 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 417 * Operating Systems 418 */ 419 ifctx = aml_if(aml_equal(func, aml_int(7))); 420 { 421 Aml *pkg = aml_package(2); 422 aml_append(pkg, zero); 423 /* optional, if not impl. should return null string */ 424 aml_append(pkg, aml_string("%s", "")); 425 aml_append(ifctx, aml_store(pkg, ret)); 426 427 /* 428 * IASL is fine when initializing Package with computational data, 429 * however it makes guest unhappy /it fails to process such AML/. 430 * So use runtime assignment to set acpi-index after initializer 431 * to make OSPM happy. 432 */ 433 aml_append(ifctx, 434 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 435 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 436 aml_append(ifctx, aml_return(ret)); 437 } 438 aml_append(method, ifctx); 439 440 return method; 441 } 442 443 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 444 { 445 Aml *method; 446 447 g_assert(pdev->acpi_index != 0); 448 method = aml_method("_DSM", 4, AML_SERIALIZED); 449 { 450 Aml *params = aml_local(0); 451 Aml *pkg = aml_package(1); 452 aml_append(pkg, aml_int(pdev->acpi_index)); 453 aml_append(method, aml_store(pkg, params)); 454 aml_append(method, 455 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 456 aml_arg(2), aml_arg(3), params)) 457 ); 458 } 459 return method; 460 } 461 462 static void build_append_pcihp_notify_entry(Aml *method, int slot) 463 { 464 Aml *if_ctx; 465 int32_t devfn = PCI_DEVFN(slot, 0); 466 467 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 468 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 469 aml_append(method, if_ctx); 470 } 471 472 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 473 { 474 const PCIDevice *pdev = bus->devices[devfn]; 475 476 if (PCI_FUNC(devfn)) { 477 if (IS_PCI_BRIDGE(pdev)) { 478 /* 479 * Ignore only hotplugged PCI bridges on !0 functions, but 480 * allow describing cold plugged bridges on all functions 481 */ 482 if (DEVICE(pdev)->hotplugged) { 483 return true; 484 } 485 } 486 } 487 return false; 488 } 489 490 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 491 { 492 PCIDevice *pdev = bus->devices[devfn]; 493 if (pdev) { 494 return is_devfn_ignored_generic(devfn, bus) || 495 !DEVICE_GET_CLASS(pdev)->hotpluggable || 496 /* Cold plugged bridges aren't themselves hot-pluggable */ 497 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 498 } else { /* non populated slots */ 499 /* 500 * hotplug is supported only for non-multifunction device 501 * so generate device description only for function 0 502 */ 503 if (PCI_FUNC(devfn) || 504 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 505 return true; 506 } 507 } 508 return false; 509 } 510 511 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) 512 { 513 int devfn; 514 Aml *dev, *notify_method = NULL, *method; 515 QObject *bsel = object_property_get_qobject(OBJECT(bus), 516 ACPI_PCIHP_PROP_BSEL, NULL); 517 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 518 qobject_unref(bsel); 519 520 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 521 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 522 523 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 524 int slot = PCI_SLOT(devfn); 525 int adr = slot << 16 | PCI_FUNC(devfn); 526 527 if (is_devfn_ignored_hotplug(devfn, bus)) { 528 continue; 529 } 530 531 if (bus->devices[devfn]) { 532 dev = aml_scope("S%.02X", devfn); 533 } else { 534 dev = aml_device("S%.02X", devfn); 535 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 536 } 537 538 /* 539 * Can't declare _SUN here for every device as it changes 'slot' 540 * enumeration order in linux kernel, so use another variable for it 541 */ 542 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 543 aml_append(dev, aml_pci_device_dsm()); 544 545 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 546 /* add _EJ0 to make slot hotpluggable */ 547 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 548 aml_append(method, 549 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 550 ); 551 aml_append(dev, method); 552 553 build_append_pcihp_notify_entry(notify_method, slot); 554 555 /* device descriptor has been composed, add it into parent context */ 556 aml_append(parent_scope, dev); 557 } 558 aml_append(parent_scope, notify_method); 559 } 560 561 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 562 { 563 int devfn; 564 Aml *dev; 565 566 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 567 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 568 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 569 PCIDevice *pdev = bus->devices[devfn]; 570 571 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 572 continue; 573 } 574 575 /* start to compose PCI device descriptor */ 576 dev = aml_device("S%.02X", devfn); 577 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 578 579 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 580 /* add _DSM if device has acpi-index set */ 581 if (pdev->acpi_index && 582 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 583 &error_abort)) { 584 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 585 } 586 587 /* device descriptor has been composed, add it into parent context */ 588 aml_append(parent_scope, dev); 589 } 590 } 591 592 static bool build_append_notfication_callback(Aml *parent_scope, 593 const PCIBus *bus) 594 { 595 Aml *method; 596 PCIBus *sec; 597 QObject *bsel; 598 int nr_notifiers = 0; 599 GQueue *pcnt_bus_list = g_queue_new(); 600 601 QLIST_FOREACH(sec, &bus->child, sibling) { 602 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 603 if (pci_bus_is_root(sec)) { 604 continue; 605 } 606 nr_notifiers = nr_notifiers + 607 build_append_notfication_callback(br_scope, sec); 608 /* 609 * add new child scope to parent 610 * and keep track of bus that have PCNT, 611 * bus list is used later to call children PCNTs from this level PCNT 612 */ 613 if (nr_notifiers) { 614 g_queue_push_tail(pcnt_bus_list, sec); 615 aml_append(parent_scope, br_scope); 616 } 617 } 618 619 /* 620 * Append PCNT method to notify about events on local and child buses. 621 * ps: hostbridge might not have hotplug (bsel) enabled but might have 622 * child bridges that do have bsel. 623 */ 624 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 625 626 /* If bus supports hotplug select it and notify about local events */ 627 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 628 if (bsel) { 629 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 630 631 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 632 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 633 aml_int(1))); /* Device Check */ 634 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 635 aml_int(3))); /* Eject Request */ 636 nr_notifiers++; 637 } 638 639 /* Notify about child bus events in any case */ 640 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 641 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 642 } 643 644 aml_append(parent_scope, method); 645 qobject_unref(bsel); 646 g_queue_free(pcnt_bus_list); 647 return !!nr_notifiers; 648 } 649 650 static Aml *aml_pci_pdsm(void) 651 { 652 Aml *method, *ifctx, *ifctx1; 653 Aml *ret = aml_local(0); 654 Aml *caps = aml_local(1); 655 Aml *acpi_index = aml_local(2); 656 Aml *zero = aml_int(0); 657 Aml *one = aml_int(1); 658 Aml *func = aml_arg(2); 659 Aml *params = aml_arg(4); 660 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 661 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 662 663 method = aml_method("PDSM", 5, AML_SERIALIZED); 664 665 /* get supported functions */ 666 ifctx = aml_if(aml_equal(func, zero)); 667 { 668 build_append_pci_dsm_func0_common(ifctx, ret); 669 670 aml_append(ifctx, aml_store(zero, caps)); 671 aml_append(ifctx, 672 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 673 /* 674 * advertise function 7 if device has acpi-index 675 * acpi_index values: 676 * 0: not present (default value) 677 * FFFFFFFF: not supported (old QEMU without PIDX reg) 678 * other: device's acpi-index 679 */ 680 ifctx1 = aml_if(aml_lnot( 681 aml_or(aml_equal(acpi_index, zero), 682 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 683 )); 684 { 685 /* have supported functions */ 686 aml_append(ifctx1, aml_or(caps, one, caps)); 687 /* support for function 7 */ 688 aml_append(ifctx1, 689 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 690 } 691 aml_append(ifctx, ifctx1); 692 693 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 694 aml_append(ifctx, aml_return(ret)); 695 } 696 aml_append(method, ifctx); 697 698 /* handle specific functions requests */ 699 /* 700 * PCI Firmware Specification 3.1 701 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 702 * Operating Systems 703 */ 704 ifctx = aml_if(aml_equal(func, aml_int(7))); 705 { 706 Aml *pkg = aml_package(2); 707 708 aml_append(pkg, zero); 709 /* 710 * optional, if not impl. should return null string 711 */ 712 aml_append(pkg, aml_string("%s", "")); 713 aml_append(ifctx, aml_store(pkg, ret)); 714 715 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 716 /* 717 * update acpi-index to actual value 718 */ 719 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 720 aml_append(ifctx, aml_return(ret)); 721 } 722 723 aml_append(method, ifctx); 724 return method; 725 } 726 727 /** 728 * build_prt_entry: 729 * @link_name: link name for PCI route entry 730 * 731 * build AML package containing a PCI route entry for @link_name 732 */ 733 static Aml *build_prt_entry(const char *link_name) 734 { 735 Aml *a_zero = aml_int(0); 736 Aml *pkg = aml_package(4); 737 aml_append(pkg, a_zero); 738 aml_append(pkg, a_zero); 739 aml_append(pkg, aml_name("%s", link_name)); 740 aml_append(pkg, a_zero); 741 return pkg; 742 } 743 744 /* 745 * initialize_route - Initialize the interrupt routing rule 746 * through a specific LINK: 747 * if (lnk_idx == idx) 748 * route using link 'link_name' 749 */ 750 static Aml *initialize_route(Aml *route, const char *link_name, 751 Aml *lnk_idx, int idx) 752 { 753 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 754 Aml *pkg = build_prt_entry(link_name); 755 756 aml_append(if_ctx, aml_store(pkg, route)); 757 758 return if_ctx; 759 } 760 761 /* 762 * build_prt - Define interrupt rounting rules 763 * 764 * Returns an array of 128 routes, one for each device, 765 * based on device location. 766 * The main goal is to equally distribute the interrupts 767 * over the 4 existing ACPI links (works only for i440fx). 768 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 769 * 770 */ 771 static Aml *build_prt(bool is_pci0_prt) 772 { 773 Aml *method, *while_ctx, *pin, *res; 774 775 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 776 res = aml_local(0); 777 pin = aml_local(1); 778 aml_append(method, aml_store(aml_package(128), res)); 779 aml_append(method, aml_store(aml_int(0), pin)); 780 781 /* while (pin < 128) */ 782 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 783 { 784 Aml *slot = aml_local(2); 785 Aml *lnk_idx = aml_local(3); 786 Aml *route = aml_local(4); 787 788 /* slot = pin >> 2 */ 789 aml_append(while_ctx, 790 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 791 /* lnk_idx = (slot + pin) & 3 */ 792 aml_append(while_ctx, 793 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 794 lnk_idx)); 795 796 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 797 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 798 if (is_pci0_prt) { 799 Aml *if_device_1, *if_pin_4, *else_pin_4; 800 801 /* device 1 is the power-management device, needs SCI */ 802 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 803 { 804 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 805 { 806 aml_append(if_pin_4, 807 aml_store(build_prt_entry("LNKS"), route)); 808 } 809 aml_append(if_device_1, if_pin_4); 810 else_pin_4 = aml_else(); 811 { 812 aml_append(else_pin_4, 813 aml_store(build_prt_entry("LNKA"), route)); 814 } 815 aml_append(if_device_1, else_pin_4); 816 } 817 aml_append(while_ctx, if_device_1); 818 } else { 819 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 820 } 821 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 822 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 823 824 /* route[0] = 0x[slot]FFFF */ 825 aml_append(while_ctx, 826 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 827 NULL), 828 aml_index(route, aml_int(0)))); 829 /* route[1] = pin & 3 */ 830 aml_append(while_ctx, 831 aml_store(aml_and(pin, aml_int(3), NULL), 832 aml_index(route, aml_int(1)))); 833 /* res[pin] = route */ 834 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 835 /* pin++ */ 836 aml_append(while_ctx, aml_increment(pin)); 837 } 838 aml_append(method, while_ctx); 839 /* return res*/ 840 aml_append(method, aml_return(res)); 841 842 return method; 843 } 844 845 static void build_hpet_aml(Aml *table) 846 { 847 Aml *crs; 848 Aml *field; 849 Aml *method; 850 Aml *if_ctx; 851 Aml *scope = aml_scope("_SB"); 852 Aml *dev = aml_device("HPET"); 853 Aml *zero = aml_int(0); 854 Aml *id = aml_local(0); 855 Aml *period = aml_local(1); 856 857 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 858 aml_append(dev, aml_name_decl("_UID", zero)); 859 860 aml_append(dev, 861 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 862 HPET_LEN)); 863 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 864 aml_append(field, aml_named_field("VEND", 32)); 865 aml_append(field, aml_named_field("PRD", 32)); 866 aml_append(dev, field); 867 868 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 869 aml_append(method, aml_store(aml_name("VEND"), id)); 870 aml_append(method, aml_store(aml_name("PRD"), period)); 871 aml_append(method, aml_shiftright(id, aml_int(16), id)); 872 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 873 aml_equal(id, aml_int(0xffff)))); 874 { 875 aml_append(if_ctx, aml_return(zero)); 876 } 877 aml_append(method, if_ctx); 878 879 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 880 aml_lgreater(period, aml_int(100000000)))); 881 { 882 aml_append(if_ctx, aml_return(zero)); 883 } 884 aml_append(method, if_ctx); 885 886 aml_append(method, aml_return(aml_int(0x0F))); 887 aml_append(dev, method); 888 889 crs = aml_resource_template(); 890 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 891 aml_append(dev, aml_name_decl("_CRS", crs)); 892 893 aml_append(scope, dev); 894 aml_append(table, scope); 895 } 896 897 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 898 { 899 Aml *dev; 900 Aml *method; 901 Aml *crs; 902 903 dev = aml_device("VMBS"); 904 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 905 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 906 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 907 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 908 909 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 910 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 911 aml_name("STA"))); 912 aml_append(dev, method); 913 914 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 915 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 916 aml_name("STA"))); 917 aml_append(dev, method); 918 919 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 920 aml_append(method, aml_return(aml_name("STA"))); 921 aml_append(dev, method); 922 923 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 924 925 crs = aml_resource_template(); 926 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 927 aml_append(dev, aml_name_decl("_CRS", crs)); 928 929 return dev; 930 } 931 932 static void build_dbg_aml(Aml *table) 933 { 934 Aml *field; 935 Aml *method; 936 Aml *while_ctx; 937 Aml *scope = aml_scope("\\"); 938 Aml *buf = aml_local(0); 939 Aml *len = aml_local(1); 940 Aml *idx = aml_local(2); 941 942 aml_append(scope, 943 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 944 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 945 aml_append(field, aml_named_field("DBGB", 8)); 946 aml_append(scope, field); 947 948 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 949 950 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 951 aml_append(method, aml_to_buffer(buf, buf)); 952 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 953 aml_append(method, aml_store(aml_int(0), idx)); 954 955 while_ctx = aml_while(aml_lless(idx, len)); 956 aml_append(while_ctx, 957 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 958 aml_append(while_ctx, aml_increment(idx)); 959 aml_append(method, while_ctx); 960 961 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 962 aml_append(scope, method); 963 964 aml_append(table, scope); 965 } 966 967 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 968 { 969 Aml *dev; 970 Aml *crs; 971 Aml *method; 972 uint32_t irqs[] = {5, 10, 11}; 973 974 dev = aml_device("%s", name); 975 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 976 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 977 978 crs = aml_resource_template(); 979 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 980 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 981 aml_append(dev, aml_name_decl("_PRS", crs)); 982 983 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 984 aml_append(method, aml_return(aml_call1("IQST", reg))); 985 aml_append(dev, method); 986 987 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 988 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 989 aml_append(dev, method); 990 991 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 992 aml_append(method, aml_return(aml_call1("IQCR", reg))); 993 aml_append(dev, method); 994 995 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 996 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 997 aml_append(method, aml_store(aml_name("PRRI"), reg)); 998 aml_append(dev, method); 999 1000 return dev; 1001 } 1002 1003 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1004 { 1005 Aml *dev; 1006 Aml *crs; 1007 Aml *method; 1008 uint32_t irqs; 1009 1010 dev = aml_device("%s", name); 1011 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1012 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1013 1014 crs = aml_resource_template(); 1015 irqs = gsi; 1016 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1017 AML_SHARED, &irqs, 1)); 1018 aml_append(dev, aml_name_decl("_PRS", crs)); 1019 1020 aml_append(dev, aml_name_decl("_CRS", crs)); 1021 1022 /* 1023 * _DIS can be no-op because the interrupt cannot be disabled. 1024 */ 1025 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1026 aml_append(dev, method); 1027 1028 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1029 aml_append(dev, method); 1030 1031 return dev; 1032 } 1033 1034 /* _CRS method - get current settings */ 1035 static Aml *build_iqcr_method(bool is_piix4) 1036 { 1037 Aml *if_ctx; 1038 uint32_t irqs; 1039 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1040 Aml *crs = aml_resource_template(); 1041 1042 irqs = 0; 1043 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1044 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1045 aml_append(method, aml_name_decl("PRR0", crs)); 1046 1047 aml_append(method, 1048 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1049 1050 if (is_piix4) { 1051 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1052 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1053 aml_append(method, if_ctx); 1054 } else { 1055 aml_append(method, 1056 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1057 aml_name("PRRI"))); 1058 } 1059 1060 aml_append(method, aml_return(aml_name("PRR0"))); 1061 return method; 1062 } 1063 1064 /* _STA method - get status */ 1065 static Aml *build_irq_status_method(void) 1066 { 1067 Aml *if_ctx; 1068 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1069 1070 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1071 aml_append(if_ctx, aml_return(aml_int(0x09))); 1072 aml_append(method, if_ctx); 1073 aml_append(method, aml_return(aml_int(0x0B))); 1074 return method; 1075 } 1076 1077 static void build_piix4_pci0_int(Aml *table) 1078 { 1079 Aml *dev; 1080 Aml *crs; 1081 Aml *method; 1082 uint32_t irqs; 1083 Aml *sb_scope = aml_scope("_SB"); 1084 Aml *pci0_scope = aml_scope("PCI0"); 1085 1086 aml_append(pci0_scope, build_prt(true)); 1087 aml_append(sb_scope, pci0_scope); 1088 1089 aml_append(sb_scope, build_irq_status_method()); 1090 aml_append(sb_scope, build_iqcr_method(true)); 1091 1092 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1093 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1094 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1095 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1096 1097 dev = aml_device("LNKS"); 1098 { 1099 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1100 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1101 1102 crs = aml_resource_template(); 1103 irqs = 9; 1104 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1105 AML_ACTIVE_HIGH, AML_SHARED, 1106 &irqs, 1)); 1107 aml_append(dev, aml_name_decl("_PRS", crs)); 1108 1109 /* The SCI cannot be disabled and is always attached to GSI 9, 1110 * so these are no-ops. We only need this link to override the 1111 * polarity to active high and match the content of the MADT. 1112 */ 1113 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1114 aml_append(method, aml_return(aml_int(0x0b))); 1115 aml_append(dev, method); 1116 1117 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1118 aml_append(dev, method); 1119 1120 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1121 aml_append(method, aml_return(aml_name("_PRS"))); 1122 aml_append(dev, method); 1123 1124 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1125 aml_append(dev, method); 1126 } 1127 aml_append(sb_scope, dev); 1128 1129 aml_append(table, sb_scope); 1130 } 1131 1132 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1133 { 1134 int i; 1135 int head; 1136 Aml *pkg; 1137 char base = name[3] < 'E' ? 'A' : 'E'; 1138 char *s = g_strdup(name); 1139 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1140 1141 assert(strlen(s) == 4); 1142 1143 head = name[3] - base; 1144 for (i = 0; i < 4; i++) { 1145 if (head + i > 3) { 1146 head = i * -1; 1147 } 1148 s[3] = base + head + i; 1149 pkg = aml_package(4); 1150 aml_append(pkg, a_nr); 1151 aml_append(pkg, aml_int(i)); 1152 aml_append(pkg, aml_name("%s", s)); 1153 aml_append(pkg, aml_int(0)); 1154 aml_append(ctx, pkg); 1155 } 1156 g_free(s); 1157 } 1158 1159 static Aml *build_q35_routing_table(const char *str) 1160 { 1161 int i; 1162 Aml *pkg; 1163 char *name = g_strdup_printf("%s ", str); 1164 1165 pkg = aml_package(128); 1166 for (i = 0; i < 0x18; i++) { 1167 name[3] = 'E' + (i & 0x3); 1168 append_q35_prt_entry(pkg, i, name); 1169 } 1170 1171 name[3] = 'E'; 1172 append_q35_prt_entry(pkg, 0x18, name); 1173 1174 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1175 for (i = 0x0019; i < 0x1e; i++) { 1176 name[3] = 'A'; 1177 append_q35_prt_entry(pkg, i, name); 1178 } 1179 1180 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1181 name[3] = 'E'; 1182 append_q35_prt_entry(pkg, 0x1e, name); 1183 name[3] = 'A'; 1184 append_q35_prt_entry(pkg, 0x1f, name); 1185 1186 g_free(name); 1187 return pkg; 1188 } 1189 1190 static void build_q35_pci0_int(Aml *table) 1191 { 1192 Aml *method; 1193 Aml *sb_scope = aml_scope("_SB"); 1194 Aml *pci0_scope = aml_scope("PCI0"); 1195 1196 /* Zero => PIC mode, One => APIC Mode */ 1197 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1198 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1199 { 1200 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1201 } 1202 aml_append(table, method); 1203 1204 aml_append(pci0_scope, 1205 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1206 aml_append(pci0_scope, 1207 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1208 1209 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1210 { 1211 Aml *if_ctx; 1212 Aml *else_ctx; 1213 1214 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1215 section 6.2.8.1 */ 1216 /* Note: we provide the same info as the PCI routing 1217 table of the Bochs BIOS */ 1218 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1219 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1220 aml_append(method, if_ctx); 1221 else_ctx = aml_else(); 1222 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1223 aml_append(method, else_ctx); 1224 } 1225 aml_append(pci0_scope, method); 1226 aml_append(sb_scope, pci0_scope); 1227 1228 aml_append(sb_scope, build_irq_status_method()); 1229 aml_append(sb_scope, build_iqcr_method(false)); 1230 1231 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1232 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1233 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1234 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1235 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1236 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1237 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1238 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1239 1240 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1241 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1242 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1243 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1244 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1245 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1246 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1247 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1248 1249 aml_append(table, sb_scope); 1250 } 1251 1252 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1253 { 1254 Aml *dev; 1255 Aml *resource_template; 1256 1257 /* DRAM controller */ 1258 dev = aml_device("DRAC"); 1259 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1260 1261 resource_template = aml_resource_template(); 1262 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1263 aml_append(resource_template, 1264 aml_qword_memory(AML_POS_DECODE, 1265 AML_MIN_FIXED, 1266 AML_MAX_FIXED, 1267 AML_NON_CACHEABLE, 1268 AML_READ_WRITE, 1269 0x0000000000000000, 1270 mcfg->base, 1271 mcfg->base + mcfg->size - 1, 1272 0x0000000000000000, 1273 mcfg->size)); 1274 } else { 1275 aml_append(resource_template, 1276 aml_dword_memory(AML_POS_DECODE, 1277 AML_MIN_FIXED, 1278 AML_MAX_FIXED, 1279 AML_NON_CACHEABLE, 1280 AML_READ_WRITE, 1281 0x0000000000000000, 1282 mcfg->base, 1283 mcfg->base + mcfg->size - 1, 1284 0x0000000000000000, 1285 mcfg->size)); 1286 } 1287 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1288 1289 return dev; 1290 } 1291 1292 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1293 { 1294 Aml *scope; 1295 Aml *field; 1296 Aml *method; 1297 1298 scope = aml_scope("_SB.PCI0"); 1299 1300 aml_append(scope, 1301 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1302 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1303 aml_append(field, aml_named_field("PCIU", 32)); 1304 aml_append(field, aml_named_field("PCID", 32)); 1305 aml_append(scope, field); 1306 1307 aml_append(scope, 1308 aml_operation_region("SEJ", AML_SYSTEM_IO, 1309 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1310 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1311 aml_append(field, aml_named_field("B0EJ", 32)); 1312 aml_append(scope, field); 1313 1314 aml_append(scope, 1315 aml_operation_region("BNMR", AML_SYSTEM_IO, 1316 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1317 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1318 aml_append(field, aml_named_field("BNUM", 32)); 1319 aml_append(field, aml_named_field("PIDX", 32)); 1320 aml_append(scope, field); 1321 1322 aml_append(scope, aml_mutex("BLCK", 0)); 1323 1324 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1325 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1326 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1327 aml_append(method, 1328 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1329 aml_append(method, aml_release(aml_name("BLCK"))); 1330 aml_append(method, aml_return(aml_int(0))); 1331 aml_append(scope, method); 1332 1333 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1334 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1335 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1336 aml_append(method, 1337 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1338 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1339 aml_append(method, aml_release(aml_name("BLCK"))); 1340 aml_append(method, aml_return(aml_local(0))); 1341 aml_append(scope, method); 1342 1343 aml_append(scope, aml_pci_pdsm()); 1344 1345 aml_append(table, scope); 1346 } 1347 1348 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1349 { 1350 Aml *if_ctx; 1351 Aml *if_ctx2; 1352 Aml *else_ctx; 1353 Aml *method; 1354 Aml *a_cwd1 = aml_name("CDW1"); 1355 Aml *a_ctrl = aml_local(0); 1356 1357 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1358 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1359 1360 if_ctx = aml_if(aml_equal( 1361 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1362 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1363 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1364 1365 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1366 1367 /* 1368 * Always allow native PME, AER (no dependencies) 1369 * Allow SHPC (PCI bridges can have SHPC controller) 1370 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1371 */ 1372 aml_append(if_ctx, aml_and(a_ctrl, 1373 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1374 1375 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1376 /* Unknown revision */ 1377 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1378 aml_append(if_ctx, if_ctx2); 1379 1380 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1381 /* Capabilities bits were masked */ 1382 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1383 aml_append(if_ctx, if_ctx2); 1384 1385 /* Update DWORD3 in the buffer */ 1386 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1387 aml_append(method, if_ctx); 1388 1389 else_ctx = aml_else(); 1390 /* Unrecognized UUID */ 1391 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1392 aml_append(method, else_ctx); 1393 1394 aml_append(method, aml_return(aml_arg(3))); 1395 return method; 1396 } 1397 1398 static void build_acpi0017(Aml *table) 1399 { 1400 Aml *dev, *scope, *method; 1401 1402 scope = aml_scope("_SB"); 1403 dev = aml_device("CXLM"); 1404 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1405 1406 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1407 aml_append(method, aml_return(aml_int(0x0B))); 1408 aml_append(dev, method); 1409 build_cxl_dsm_method(dev); 1410 1411 aml_append(scope, dev); 1412 aml_append(table, scope); 1413 } 1414 1415 static void 1416 build_dsdt(GArray *table_data, BIOSLinker *linker, 1417 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1418 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1419 { 1420 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE, 1421 NULL); 1422 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL); 1423 CrsRangeEntry *entry; 1424 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1425 CrsRangeSet crs_range_set; 1426 PCMachineState *pcms = PC_MACHINE(machine); 1427 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1428 X86MachineState *x86ms = X86_MACHINE(machine); 1429 AcpiMcfgInfo mcfg; 1430 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1431 uint32_t nr_mem = machine->ram_slots; 1432 int root_bus_limit = 0xFF; 1433 PCIBus *bus = NULL; 1434 #ifdef CONFIG_TPM 1435 TPMIf *tpm = tpm_find(); 1436 #endif 1437 bool cxl_present = false; 1438 int i; 1439 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1440 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1441 .oem_table_id = x86ms->oem_table_id }; 1442 1443 assert(!!i440fx != !!q35); 1444 1445 acpi_table_begin(&table, table_data); 1446 dsdt = init_aml_allocator(); 1447 1448 build_dbg_aml(dsdt); 1449 if (i440fx) { 1450 sb_scope = aml_scope("_SB"); 1451 dev = aml_device("PCI0"); 1452 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1453 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1454 aml_append(dev, aml_pci_edsm()); 1455 aml_append(sb_scope, dev); 1456 aml_append(dsdt, sb_scope); 1457 1458 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1459 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1460 } 1461 build_piix4_pci0_int(dsdt); 1462 } else if (q35) { 1463 sb_scope = aml_scope("_SB"); 1464 dev = aml_device("PCI0"); 1465 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1466 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1467 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1468 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1469 aml_append(dev, aml_pci_edsm()); 1470 aml_append(sb_scope, dev); 1471 if (mcfg_valid) { 1472 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1473 } 1474 1475 if (pm->smi_on_cpuhp) { 1476 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1477 dev = aml_device("PCI0.SMI0"); 1478 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1479 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1480 crs = aml_resource_template(); 1481 aml_append(crs, 1482 aml_io( 1483 AML_DECODE16, 1484 pm->fadt.smi_cmd, 1485 pm->fadt.smi_cmd, 1486 1, 1487 2) 1488 ); 1489 aml_append(dev, aml_name_decl("_CRS", crs)); 1490 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1491 aml_int(pm->fadt.smi_cmd), 2)); 1492 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1493 AML_WRITE_AS_ZEROS); 1494 aml_append(field, aml_named_field("SMIC", 8)); 1495 aml_append(field, aml_reserved_field(8)); 1496 aml_append(dev, field); 1497 aml_append(sb_scope, dev); 1498 } 1499 1500 aml_append(dsdt, sb_scope); 1501 1502 if (pm->pcihp_bridge_en) { 1503 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1504 } 1505 build_q35_pci0_int(dsdt); 1506 } 1507 1508 if (misc->has_hpet) { 1509 build_hpet_aml(dsdt); 1510 } 1511 1512 if (vmbus_bridge) { 1513 sb_scope = aml_scope("_SB"); 1514 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1515 aml_append(dsdt, sb_scope); 1516 } 1517 1518 scope = aml_scope("_GPE"); 1519 { 1520 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1521 if (machine->nvdimms_state->is_enabled) { 1522 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1523 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1524 aml_int(0x80))); 1525 aml_append(scope, method); 1526 } 1527 } 1528 aml_append(dsdt, scope); 1529 1530 if (pcmc->legacy_cpu_hotplug) { 1531 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1532 } else { 1533 CPUHotplugFeatures opts = { 1534 .acpi_1_compatible = true, .has_legacy_cphp = true, 1535 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1536 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1537 }; 1538 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, 1539 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); 1540 } 1541 1542 if (pcms->memhp_io_base && nr_mem) { 1543 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1544 "\\_GPE._E03", AML_SYSTEM_IO, 1545 pcms->memhp_io_base); 1546 } 1547 1548 crs_range_set_init(&crs_range_set); 1549 bus = PC_MACHINE(machine)->pcibus; 1550 if (bus) { 1551 QLIST_FOREACH(bus, &bus->child, sibling) { 1552 uint8_t bus_num = pci_bus_num(bus); 1553 uint8_t numa_node = pci_bus_numa_node(bus); 1554 1555 /* look only for expander root buses */ 1556 if (!pci_bus_is_root(bus)) { 1557 continue; 1558 } 1559 1560 if (bus_num < root_bus_limit) { 1561 root_bus_limit = bus_num - 1; 1562 } 1563 1564 scope = aml_scope("\\_SB"); 1565 1566 if (pci_bus_is_cxl(bus)) { 1567 dev = aml_device("CL%.02X", bus_num); 1568 } else { 1569 dev = aml_device("PC%.02X", bus_num); 1570 } 1571 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1572 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1573 if (pci_bus_is_cxl(bus)) { 1574 struct Aml *aml_pkg = aml_package(2); 1575 1576 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1577 aml_append(aml_pkg, aml_eisaid("PNP0A08")); 1578 aml_append(aml_pkg, aml_eisaid("PNP0A03")); 1579 aml_append(dev, aml_name_decl("_CID", aml_pkg)); 1580 build_cxl_osc_method(dev); 1581 } else if (pci_bus_is_express(bus)) { 1582 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1583 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1584 1585 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1586 aml_append(dev, build_q35_osc_method(true)); 1587 } else { 1588 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1589 } 1590 1591 if (numa_node != NUMA_NODE_UNASSIGNED) { 1592 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1593 } 1594 1595 aml_append(dev, build_prt(false)); 1596 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1597 0, 0, 0, 0); 1598 aml_append(dev, aml_name_decl("_CRS", crs)); 1599 aml_append(scope, dev); 1600 aml_append(dsdt, scope); 1601 1602 /* Handle the ranges for the PXB expanders */ 1603 if (pci_bus_is_cxl(bus)) { 1604 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1605 uint64_t base = mr->addr; 1606 1607 cxl_present = true; 1608 crs_range_insert(crs_range_set.mem_ranges, base, 1609 base + memory_region_size(mr) - 1); 1610 } 1611 } 1612 } 1613 1614 if (cxl_present) { 1615 build_acpi0017(dsdt); 1616 } 1617 1618 /* 1619 * At this point crs_range_set has all the ranges used by pci 1620 * busses *other* than PCI0. These ranges will be excluded from 1621 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1622 * too. 1623 */ 1624 if (mcfg_valid) { 1625 crs_range_insert(crs_range_set.mem_ranges, 1626 mcfg.base, mcfg.base + mcfg.size - 1); 1627 } 1628 1629 scope = aml_scope("\\_SB.PCI0"); 1630 /* build PCI0._CRS */ 1631 crs = aml_resource_template(); 1632 aml_append(crs, 1633 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1634 0x0000, 0x0, root_bus_limit, 1635 0x0000, root_bus_limit + 1)); 1636 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1637 1638 aml_append(crs, 1639 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1640 AML_POS_DECODE, AML_ENTIRE_RANGE, 1641 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1642 1643 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1644 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1645 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1646 aml_append(crs, 1647 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1648 AML_POS_DECODE, AML_ENTIRE_RANGE, 1649 0x0000, entry->base, entry->limit, 1650 0x0000, entry->limit - entry->base + 1)); 1651 } 1652 1653 aml_append(crs, 1654 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1655 AML_CACHEABLE, AML_READ_WRITE, 1656 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1657 1658 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1659 range_lob(pci_hole), 1660 range_upb(pci_hole)); 1661 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1662 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1663 aml_append(crs, 1664 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1665 AML_NON_CACHEABLE, AML_READ_WRITE, 1666 0, entry->base, entry->limit, 1667 0, entry->limit - entry->base + 1)); 1668 } 1669 1670 if (!range_is_empty(pci_hole64)) { 1671 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1672 range_lob(pci_hole64), 1673 range_upb(pci_hole64)); 1674 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1675 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1676 aml_append(crs, 1677 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1678 AML_MAX_FIXED, 1679 AML_CACHEABLE, AML_READ_WRITE, 1680 0, entry->base, entry->limit, 1681 0, entry->limit - entry->base + 1)); 1682 } 1683 } 1684 1685 #ifdef CONFIG_TPM 1686 if (TPM_IS_TIS_ISA(tpm_find())) { 1687 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1688 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1689 } 1690 #endif 1691 aml_append(scope, aml_name_decl("_CRS", crs)); 1692 1693 /* reserve GPE0 block resources */ 1694 dev = aml_device("GPE0"); 1695 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1696 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1697 /* device present, functioning, decoding, not shown in UI */ 1698 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1699 crs = aml_resource_template(); 1700 aml_append(crs, 1701 aml_io( 1702 AML_DECODE16, 1703 pm->fadt.gpe0_blk.address, 1704 pm->fadt.gpe0_blk.address, 1705 1, 1706 pm->fadt.gpe0_blk.bit_width / 8) 1707 ); 1708 aml_append(dev, aml_name_decl("_CRS", crs)); 1709 aml_append(scope, dev); 1710 1711 crs_range_set_free(&crs_range_set); 1712 1713 /* reserve PCIHP resources */ 1714 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1715 dev = aml_device("PHPR"); 1716 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1717 aml_append(dev, 1718 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1719 /* device present, functioning, decoding, not shown in UI */ 1720 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1721 crs = aml_resource_template(); 1722 aml_append(crs, 1723 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1724 pm->pcihp_io_len) 1725 ); 1726 aml_append(dev, aml_name_decl("_CRS", crs)); 1727 aml_append(scope, dev); 1728 } 1729 aml_append(dsdt, scope); 1730 1731 /* create S3_ / S4_ / S5_ packages if necessary */ 1732 scope = aml_scope("\\"); 1733 if (!pm->s3_disabled) { 1734 pkg = aml_package(4); 1735 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1736 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1737 aml_append(pkg, aml_int(0)); /* reserved */ 1738 aml_append(pkg, aml_int(0)); /* reserved */ 1739 aml_append(scope, aml_name_decl("_S3", pkg)); 1740 } 1741 1742 if (!pm->s4_disabled) { 1743 pkg = aml_package(4); 1744 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1745 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1746 aml_append(pkg, aml_int(pm->s4_val)); 1747 aml_append(pkg, aml_int(0)); /* reserved */ 1748 aml_append(pkg, aml_int(0)); /* reserved */ 1749 aml_append(scope, aml_name_decl("_S4", pkg)); 1750 } 1751 1752 pkg = aml_package(4); 1753 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1754 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1755 aml_append(pkg, aml_int(0)); /* reserved */ 1756 aml_append(pkg, aml_int(0)); /* reserved */ 1757 aml_append(scope, aml_name_decl("_S5", pkg)); 1758 aml_append(dsdt, scope); 1759 1760 /* create fw_cfg node, unconditionally */ 1761 { 1762 scope = aml_scope("\\_SB.PCI0"); 1763 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1764 aml_append(dsdt, scope); 1765 } 1766 1767 sb_scope = aml_scope("\\_SB"); 1768 { 1769 Object *pci_host = acpi_get_i386_pci_host(); 1770 1771 if (pci_host) { 1772 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; 1773 Aml *ascope = aml_scope("PCI0"); 1774 /* Scan all PCI buses. Generate tables to support hotplug. */ 1775 build_append_pci_bus_devices(ascope, pbus); 1776 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) { 1777 build_append_pcihp_slots(ascope, pbus); 1778 } 1779 aml_append(sb_scope, ascope); 1780 } 1781 } 1782 1783 #ifdef CONFIG_TPM 1784 if (TPM_IS_CRB(tpm)) { 1785 dev = aml_device("TPM"); 1786 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1787 aml_append(dev, aml_name_decl("_STR", 1788 aml_string("TPM 2.0 Device"))); 1789 crs = aml_resource_template(); 1790 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1791 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1792 aml_append(dev, aml_name_decl("_CRS", crs)); 1793 1794 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1795 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1796 1797 tpm_build_ppi_acpi(tpm, dev); 1798 1799 aml_append(sb_scope, dev); 1800 } 1801 #endif 1802 1803 if (pcms->sgx_epc.size != 0) { 1804 uint64_t epc_base = pcms->sgx_epc.base; 1805 uint64_t epc_size = pcms->sgx_epc.size; 1806 1807 dev = aml_device("EPC"); 1808 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1809 aml_append(dev, aml_name_decl("_STR", 1810 aml_unicode("Enclave Page Cache 1.0"))); 1811 crs = aml_resource_template(); 1812 aml_append(crs, 1813 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1814 AML_MAX_FIXED, AML_NON_CACHEABLE, 1815 AML_READ_WRITE, 0, epc_base, 1816 epc_base + epc_size - 1, 0, epc_size)); 1817 aml_append(dev, aml_name_decl("_CRS", crs)); 1818 1819 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1820 aml_append(method, aml_return(aml_int(0x0f))); 1821 aml_append(dev, method); 1822 1823 aml_append(sb_scope, dev); 1824 } 1825 aml_append(dsdt, sb_scope); 1826 1827 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1828 bool has_pcnt; 1829 1830 Object *pci_host = acpi_get_i386_pci_host(); 1831 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; 1832 1833 scope = aml_scope("\\_SB.PCI0"); 1834 has_pcnt = build_append_notfication_callback(scope, b); 1835 if (has_pcnt) { 1836 aml_append(dsdt, scope); 1837 } 1838 1839 scope = aml_scope("_GPE"); 1840 { 1841 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1842 if (has_pcnt) { 1843 aml_append(method, 1844 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1845 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1846 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1847 } 1848 aml_append(scope, method); 1849 } 1850 aml_append(dsdt, scope); 1851 } 1852 1853 /* copy AML table into ACPI tables blob and patch header there */ 1854 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1855 acpi_table_end(linker, &table); 1856 free_aml_allocator(); 1857 } 1858 1859 /* 1860 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1861 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1862 */ 1863 static void 1864 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1865 const char *oem_table_id) 1866 { 1867 AcpiTable table = { .sig = "HPET", .rev = 1, 1868 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1869 1870 acpi_table_begin(&table, table_data); 1871 /* Note timer_block_id value must be kept in sync with value advertised by 1872 * emulated hpet 1873 */ 1874 /* Event Timer Block ID */ 1875 build_append_int_noprefix(table_data, 0x8086a201, 4); 1876 /* BASE_ADDRESS */ 1877 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1878 /* HPET Number */ 1879 build_append_int_noprefix(table_data, 0, 1); 1880 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1881 build_append_int_noprefix(table_data, 0, 2); 1882 /* Page Protection And OEM Attribute */ 1883 build_append_int_noprefix(table_data, 0, 1); 1884 acpi_table_end(linker, &table); 1885 } 1886 1887 #ifdef CONFIG_TPM 1888 /* 1889 * TCPA Description Table 1890 * 1891 * Following Level 00, Rev 00.37 of specs: 1892 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1893 * 7.1.2 ACPI Table Layout 1894 */ 1895 static void 1896 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1897 const char *oem_id, const char *oem_table_id) 1898 { 1899 unsigned log_addr_offset; 1900 AcpiTable table = { .sig = "TCPA", .rev = 2, 1901 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1902 1903 acpi_table_begin(&table, table_data); 1904 /* Platform Class */ 1905 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1906 /* Log Area Minimum Length (LAML) */ 1907 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1908 /* Log Area Start Address (LASA) */ 1909 log_addr_offset = table_data->len; 1910 build_append_int_noprefix(table_data, 0, 8); 1911 1912 /* allocate/reserve space for TPM log area */ 1913 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1914 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1915 false /* high memory */); 1916 /* log area start address to be filled by Guest linker */ 1917 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1918 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1919 1920 acpi_table_end(linker, &table); 1921 } 1922 #endif 1923 1924 #define HOLE_640K_START (640 * KiB) 1925 #define HOLE_640K_END (1 * MiB) 1926 1927 /* 1928 * ACPI spec, Revision 3.0 1929 * 5.2.15 System Resource Affinity Table (SRAT) 1930 */ 1931 static void 1932 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1933 { 1934 int i; 1935 int numa_mem_start, slots; 1936 uint64_t mem_len, mem_base, next_base; 1937 MachineClass *mc = MACHINE_GET_CLASS(machine); 1938 X86MachineState *x86ms = X86_MACHINE(machine); 1939 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1940 int nb_numa_nodes = machine->numa_state->num_nodes; 1941 NodeInfo *numa_info = machine->numa_state->nodes; 1942 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1943 .oem_table_id = x86ms->oem_table_id }; 1944 1945 acpi_table_begin(&table, table_data); 1946 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1947 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1948 1949 for (i = 0; i < apic_ids->len; i++) { 1950 int node_id = apic_ids->cpus[i].props.node_id; 1951 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1952 1953 if (apic_id < 255) { 1954 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1955 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1956 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1957 /* Proximity Domain [7:0] */ 1958 build_append_int_noprefix(table_data, node_id, 1); 1959 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1960 /* Flags, Table 5-36 */ 1961 build_append_int_noprefix(table_data, 1, 4); 1962 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1963 /* Proximity Domain [31:8] */ 1964 build_append_int_noprefix(table_data, 0, 3); 1965 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1966 } else { 1967 /* 1968 * ACPI spec, Revision 4.0 1969 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1970 */ 1971 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1972 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1973 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1974 /* Proximity Domain */ 1975 build_append_int_noprefix(table_data, node_id, 4); 1976 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1977 /* Flags, Table 5-39 */ 1978 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1979 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1980 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1981 } 1982 } 1983 1984 /* the memory map is a bit tricky, it contains at least one hole 1985 * from 640k-1M and possibly another one from 3.5G-4G. 1986 */ 1987 next_base = 0; 1988 numa_mem_start = table_data->len; 1989 1990 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1991 mem_base = next_base; 1992 mem_len = numa_info[i - 1].node_mem; 1993 next_base = mem_base + mem_len; 1994 1995 /* Cut out the 640K hole */ 1996 if (mem_base <= HOLE_640K_START && 1997 next_base > HOLE_640K_START) { 1998 mem_len -= next_base - HOLE_640K_START; 1999 if (mem_len > 0) { 2000 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2001 MEM_AFFINITY_ENABLED); 2002 } 2003 2004 /* Check for the rare case: 640K < RAM < 1M */ 2005 if (next_base <= HOLE_640K_END) { 2006 next_base = HOLE_640K_END; 2007 continue; 2008 } 2009 mem_base = HOLE_640K_END; 2010 mem_len = next_base - HOLE_640K_END; 2011 } 2012 2013 /* Cut out the ACPI_PCI hole */ 2014 if (mem_base <= x86ms->below_4g_mem_size && 2015 next_base > x86ms->below_4g_mem_size) { 2016 mem_len -= next_base - x86ms->below_4g_mem_size; 2017 if (mem_len > 0) { 2018 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2019 MEM_AFFINITY_ENABLED); 2020 } 2021 mem_base = x86ms->above_4g_mem_start; 2022 mem_len = next_base - x86ms->below_4g_mem_size; 2023 next_base = mem_base + mem_len; 2024 } 2025 2026 if (mem_len > 0) { 2027 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2028 MEM_AFFINITY_ENABLED); 2029 } 2030 } 2031 2032 if (machine->nvdimms_state->is_enabled) { 2033 nvdimm_build_srat(table_data); 2034 } 2035 2036 sgx_epc_build_srat(table_data); 2037 2038 /* 2039 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2040 * without these entries. But I recall there were issues the last time I 2041 * tried to remove it with some ancient guest OS, however I can't remember 2042 * what that was so keep this around for now 2043 */ 2044 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2045 for (; slots < nb_numa_nodes + 2; slots++) { 2046 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2047 } 2048 2049 /* 2050 * Entry is required for Windows to enable memory hotplug in OS 2051 * and for Linux to enable SWIOTLB when booted with less than 2052 * 4G of RAM. Windows works better if the entry sets proximity 2053 * to the highest NUMA node in the machine. 2054 * Memory devices may override proximity set by this entry, 2055 * providing _PXM method if necessary. 2056 */ 2057 if (machine->device_memory) { 2058 build_srat_memory(table_data, machine->device_memory->base, 2059 memory_region_size(&machine->device_memory->mr), 2060 nb_numa_nodes - 1, 2061 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2062 } 2063 2064 acpi_table_end(linker, &table); 2065 } 2066 2067 /* 2068 * Insert DMAR scope for PCI bridges and endpoint devices 2069 */ 2070 static void 2071 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2072 { 2073 const size_t device_scope_size = 6 /* device scope structure */ + 2074 2 /* 1 path entry */; 2075 GArray *scope_blob = opaque; 2076 2077 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2078 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2079 build_append_int_noprefix(scope_blob, 0x02, 1); 2080 } else { 2081 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2082 build_append_int_noprefix(scope_blob, 0x01, 1); 2083 } 2084 2085 /* length */ 2086 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2087 /* reserved */ 2088 build_append_int_noprefix(scope_blob, 0, 2); 2089 /* enumeration_id */ 2090 build_append_int_noprefix(scope_blob, 0, 1); 2091 /* bus */ 2092 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2093 /* device */ 2094 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2095 /* function */ 2096 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2097 } 2098 2099 /* For a given PCI host bridge, walk and insert DMAR scope */ 2100 static int 2101 dmar_host_bridges(Object *obj, void *opaque) 2102 { 2103 GArray *scope_blob = opaque; 2104 2105 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2106 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2107 2108 if (bus && !pci_bus_bypass_iommu(bus)) { 2109 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2110 } 2111 } 2112 2113 return 0; 2114 } 2115 2116 /* 2117 * Intel ® Virtualization Technology for Directed I/O 2118 * Architecture Specification. Revision 3.3 2119 * 8.1 DMA Remapping Reporting Structure 2120 */ 2121 static void 2122 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2123 const char *oem_table_id) 2124 { 2125 uint8_t dmar_flags = 0; 2126 uint8_t rsvd10[10] = {}; 2127 /* Root complex IOAPIC uses one path only */ 2128 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2129 2 /* 1 path entry */; 2130 X86IOMMUState *iommu = x86_iommu_get_default(); 2131 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2132 GArray *scope_blob = g_array_new(false, true, 1); 2133 2134 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2135 .oem_table_id = oem_table_id }; 2136 2137 /* 2138 * A PCI bus walk, for each PCI host bridge. 2139 * Insert scope for each PCI bridge and endpoint device which 2140 * is attached to a bus with iommu enabled. 2141 */ 2142 object_child_foreach_recursive(object_get_root(), 2143 dmar_host_bridges, scope_blob); 2144 2145 assert(iommu); 2146 if (x86_iommu_ir_supported(iommu)) { 2147 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2148 } 2149 2150 acpi_table_begin(&table, table_data); 2151 /* Host Address Width */ 2152 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2153 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2154 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2155 2156 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2157 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2158 /* Length */ 2159 build_append_int_noprefix(table_data, 2160 16 + ioapic_scope_size + scope_blob->len, 2); 2161 /* Flags */ 2162 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2163 1); 2164 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2165 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2166 /* Register Base Address */ 2167 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2168 2169 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2170 * 8.3.1 (version Oct. 2014 or later). */ 2171 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2172 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2173 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2174 /* Enumeration ID */ 2175 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2176 /* Start Bus Number */ 2177 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2178 /* Path, {Device, Function} pair */ 2179 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2180 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2181 2182 /* Add scope found above */ 2183 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2184 g_array_free(scope_blob, true); 2185 2186 if (iommu->dt_supported) { 2187 /* 8.5 Root Port ATS Capability Reporting Structure */ 2188 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2189 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2190 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2191 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2192 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2193 } 2194 2195 acpi_table_end(linker, &table); 2196 } 2197 2198 /* 2199 * Windows ACPI Emulated Devices Table 2200 * (Version 1.0 - April 6, 2009) 2201 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2202 * 2203 * Helpful to speedup Windows guests and ignored by others. 2204 */ 2205 static void 2206 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2207 const char *oem_table_id) 2208 { 2209 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2210 .oem_table_id = oem_table_id }; 2211 2212 acpi_table_begin(&table, table_data); 2213 /* 2214 * Set "ACPI PM timer good" flag. 2215 * 2216 * Tells Windows guests that our ACPI PM timer is reliable in the 2217 * sense that guest can read it only once to obtain a reliable value. 2218 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2219 */ 2220 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2221 acpi_table_end(linker, &table); 2222 } 2223 2224 /* 2225 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2226 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2227 */ 2228 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2229 2230 /* 2231 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2232 * necessary for the PCI topology. 2233 */ 2234 static void 2235 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2236 { 2237 GArray *table_data = opaque; 2238 uint32_t entry; 2239 2240 /* "Select" IVHD entry, type 0x2 */ 2241 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2242 build_append_int_noprefix(table_data, entry, 4); 2243 2244 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2245 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2246 uint8_t sec = pci_bus_num(sec_bus); 2247 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2248 2249 if (pci_bus_is_express(sec_bus)) { 2250 /* 2251 * Walk the bus if there are subordinates, otherwise use a range 2252 * to cover an entire leaf bus. We could potentially also use a 2253 * range for traversed buses, but we'd need to take care not to 2254 * create both Select and Range entries covering the same device. 2255 * This is easier and potentially more compact. 2256 * 2257 * An example bare metal system seems to use Select entries for 2258 * root ports without a slot (ie. built-ins) and Range entries 2259 * when there is a slot. The same system also only hard-codes 2260 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2261 * making no effort to support nested bridges. We attempt to 2262 * be more thorough here. 2263 */ 2264 if (sec == sub) { /* leaf bus */ 2265 /* "Start of Range" IVHD entry, type 0x3 */ 2266 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2267 build_append_int_noprefix(table_data, entry, 4); 2268 /* "End of Range" IVHD entry, type 0x4 */ 2269 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2270 build_append_int_noprefix(table_data, entry, 4); 2271 } else { 2272 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2273 } 2274 } else { 2275 /* 2276 * If the secondary bus is conventional, then we need to create an 2277 * Alias range for everything downstream. The range covers the 2278 * first devfn on the secondary bus to the last devfn on the 2279 * subordinate bus. The alias target depends on legacy versus 2280 * express bridges, just as in pci_device_iommu_address_space(). 2281 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2282 */ 2283 uint16_t dev_id_a, dev_id_b; 2284 2285 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2286 2287 if (pci_is_express(dev) && 2288 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2289 dev_id_b = dev_id_a; 2290 } else { 2291 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2292 } 2293 2294 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2295 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2296 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2297 2298 /* "End of Range" IVHD entry, type 0x4 */ 2299 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2300 build_append_int_noprefix(table_data, entry, 4); 2301 } 2302 } 2303 } 2304 2305 /* For all PCI host bridges, walk and insert IVHD entries */ 2306 static int 2307 ivrs_host_bridges(Object *obj, void *opaque) 2308 { 2309 GArray *ivhd_blob = opaque; 2310 2311 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2312 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2313 2314 if (bus && !pci_bus_bypass_iommu(bus)) { 2315 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2316 } 2317 } 2318 2319 return 0; 2320 } 2321 2322 static void 2323 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2324 const char *oem_table_id) 2325 { 2326 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2327 GArray *ivhd_blob = g_array_new(false, true, 1); 2328 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2329 .oem_table_id = oem_table_id }; 2330 uint64_t feature_report; 2331 2332 acpi_table_begin(&table, table_data); 2333 /* IVinfo - IO virtualization information common to all 2334 * IOMMU units in a system 2335 */ 2336 build_append_int_noprefix(table_data, 2337 (1UL << 0) | /* EFRSup */ 2338 (40UL << 8), /* PASize */ 2339 4); 2340 /* reserved */ 2341 build_append_int_noprefix(table_data, 0, 8); 2342 2343 /* 2344 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2345 * complete set of IVHD entries. Do this into a separate blob so that we 2346 * can calculate the total IVRS table length here and then append the new 2347 * blob further below. Fall back to an entry covering all devices, which 2348 * is sufficient when no aliases are present. 2349 */ 2350 object_child_foreach_recursive(object_get_root(), 2351 ivrs_host_bridges, ivhd_blob); 2352 2353 if (!ivhd_blob->len) { 2354 /* 2355 * Type 1 device entry reporting all devices 2356 * These are 4-byte device entries currently reporting the range of 2357 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2358 */ 2359 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2360 } 2361 2362 /* 2363 * When interrupt remapping is supported, we add a special IVHD device 2364 * for type IO-APIC 2365 * Refer to spec - Table 95: IVHD device entry type codes 2366 * 2367 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2368 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2369 */ 2370 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2371 build_append_int_noprefix(ivhd_blob, 2372 (0x1ull << 56) | /* type IOAPIC */ 2373 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2374 0x48, /* special device */ 2375 8); 2376 } 2377 2378 /* IVHD definition - type 10h */ 2379 build_append_int_noprefix(table_data, 0x10, 1); 2380 /* virtualization flags */ 2381 build_append_int_noprefix(table_data, 2382 (1UL << 0) | /* HtTunEn */ 2383 (1UL << 4) | /* iotblSup */ 2384 (1UL << 6) | /* PrefSup */ 2385 (1UL << 7), /* PPRSup */ 2386 1); 2387 2388 /* IVHD length */ 2389 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); 2390 /* DeviceID */ 2391 build_append_int_noprefix(table_data, 2392 object_property_get_int(OBJECT(&s->pci), "addr", 2393 &error_abort), 2); 2394 /* Capability offset */ 2395 build_append_int_noprefix(table_data, s->pci.capab_offset, 2); 2396 /* IOMMU base address */ 2397 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2398 /* PCI Segment Group */ 2399 build_append_int_noprefix(table_data, 0, 2); 2400 /* IOMMU info */ 2401 build_append_int_noprefix(table_data, 0, 2); 2402 /* IOMMU Feature Reporting */ 2403 feature_report = (48UL << 30) | /* HATS */ 2404 (48UL << 28) | /* GATS */ 2405 (1UL << 2) | /* GTSup */ 2406 (1UL << 6); /* GASup */ 2407 if (s->xtsup) { 2408 feature_report |= (1UL << 0); /* XTSup */ 2409 } 2410 build_append_int_noprefix(table_data, feature_report, 4); 2411 2412 /* IVHD entries as found above */ 2413 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2414 2415 /* IVHD definition - type 11h */ 2416 build_append_int_noprefix(table_data, 0x11, 1); 2417 /* virtualization flags */ 2418 build_append_int_noprefix(table_data, 2419 (1UL << 0) | /* HtTunEn */ 2420 (1UL << 4), /* iotblSup */ 2421 1); 2422 2423 /* IVHD length */ 2424 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); 2425 /* DeviceID */ 2426 build_append_int_noprefix(table_data, 2427 object_property_get_int(OBJECT(&s->pci), "addr", 2428 &error_abort), 2); 2429 /* Capability offset */ 2430 build_append_int_noprefix(table_data, s->pci.capab_offset, 2); 2431 /* IOMMU base address */ 2432 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2433 /* PCI Segment Group */ 2434 build_append_int_noprefix(table_data, 0, 2); 2435 /* IOMMU info */ 2436 build_append_int_noprefix(table_data, 0, 2); 2437 /* IOMMU Attributes */ 2438 build_append_int_noprefix(table_data, 0, 4); 2439 /* EFR Register Image */ 2440 build_append_int_noprefix(table_data, 2441 amdvi_extended_feature_register(s), 2442 8); 2443 /* EFR Register Image 2 */ 2444 build_append_int_noprefix(table_data, 0, 8); 2445 2446 /* IVHD entries as found above */ 2447 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2448 2449 g_array_free(ivhd_blob, TRUE); 2450 acpi_table_end(linker, &table); 2451 } 2452 2453 typedef 2454 struct AcpiBuildState { 2455 /* Copy of table in RAM (for patching). */ 2456 MemoryRegion *table_mr; 2457 /* Is table patched? */ 2458 uint8_t patched; 2459 void *rsdp; 2460 MemoryRegion *rsdp_mr; 2461 MemoryRegion *linker_mr; 2462 } AcpiBuildState; 2463 2464 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2465 { 2466 Object *pci_host; 2467 QObject *o; 2468 2469 pci_host = acpi_get_i386_pci_host(); 2470 if (!pci_host) { 2471 return false; 2472 } 2473 2474 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2475 if (!o) { 2476 return false; 2477 } 2478 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2479 qobject_unref(o); 2480 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2481 return false; 2482 } 2483 2484 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2485 assert(o); 2486 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2487 qobject_unref(o); 2488 return true; 2489 } 2490 2491 static 2492 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2493 { 2494 PCMachineState *pcms = PC_MACHINE(machine); 2495 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2496 X86MachineState *x86ms = X86_MACHINE(machine); 2497 DeviceState *iommu = pcms->iommu; 2498 GArray *table_offsets; 2499 unsigned facs, dsdt, rsdt, fadt; 2500 AcpiPmInfo pm; 2501 AcpiMiscInfo misc; 2502 AcpiMcfgInfo mcfg; 2503 Range pci_hole = {}, pci_hole64 = {}; 2504 uint8_t *u; 2505 size_t aml_len = 0; 2506 GArray *tables_blob = tables->table_data; 2507 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2508 Object *vmgenid_dev; 2509 char *oem_id; 2510 char *oem_table_id; 2511 2512 acpi_get_pm_info(machine, &pm); 2513 acpi_get_misc_info(&misc); 2514 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2515 acpi_get_slic_oem(&slic_oem); 2516 2517 if (slic_oem.id) { 2518 oem_id = slic_oem.id; 2519 } else { 2520 oem_id = x86ms->oem_id; 2521 } 2522 2523 if (slic_oem.table_id) { 2524 oem_table_id = slic_oem.table_id; 2525 } else { 2526 oem_table_id = x86ms->oem_table_id; 2527 } 2528 2529 table_offsets = g_array_new(false, true /* clear */, 2530 sizeof(uint32_t)); 2531 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2532 2533 bios_linker_loader_alloc(tables->linker, 2534 ACPI_BUILD_TABLE_FILE, tables_blob, 2535 64 /* Ensure FACS is aligned */, 2536 false /* high memory */); 2537 2538 /* 2539 * FACS is pointed to by FADT. 2540 * We place it first since it's the only table that has alignment 2541 * requirements. 2542 */ 2543 facs = tables_blob->len; 2544 build_facs(tables_blob); 2545 2546 /* DSDT is pointed to by FADT */ 2547 dsdt = tables_blob->len; 2548 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2549 &pci_hole, &pci_hole64, machine); 2550 2551 /* Count the size of the DSDT and SSDT, we will need it for legacy 2552 * sizing of ACPI tables. 2553 */ 2554 aml_len += tables_blob->len - dsdt; 2555 2556 /* ACPI tables pointed to by RSDT */ 2557 fadt = tables_blob->len; 2558 acpi_add_table(table_offsets, tables_blob); 2559 pm.fadt.facs_tbl_offset = &facs; 2560 pm.fadt.dsdt_tbl_offset = &dsdt; 2561 pm.fadt.xdsdt_tbl_offset = &dsdt; 2562 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2563 aml_len += tables_blob->len - fadt; 2564 2565 acpi_add_table(table_offsets, tables_blob); 2566 acpi_build_madt(tables_blob, tables->linker, x86ms, 2567 x86ms->oem_id, x86ms->oem_table_id); 2568 2569 #ifdef CONFIG_ACPI_ERST 2570 { 2571 Object *erst_dev; 2572 erst_dev = find_erst_dev(); 2573 if (erst_dev) { 2574 acpi_add_table(table_offsets, tables_blob); 2575 build_erst(tables_blob, tables->linker, erst_dev, 2576 x86ms->oem_id, x86ms->oem_table_id); 2577 } 2578 } 2579 #endif 2580 2581 vmgenid_dev = find_vmgenid_dev(); 2582 if (vmgenid_dev) { 2583 acpi_add_table(table_offsets, tables_blob); 2584 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2585 tables->vmgenid, tables->linker, x86ms->oem_id); 2586 } 2587 2588 if (misc.has_hpet) { 2589 acpi_add_table(table_offsets, tables_blob); 2590 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2591 x86ms->oem_table_id); 2592 } 2593 #ifdef CONFIG_TPM 2594 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2595 if (misc.tpm_version == TPM_VERSION_1_2) { 2596 acpi_add_table(table_offsets, tables_blob); 2597 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2598 x86ms->oem_id, x86ms->oem_table_id); 2599 } else { /* TPM_VERSION_2_0 */ 2600 acpi_add_table(table_offsets, tables_blob); 2601 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2602 x86ms->oem_id, x86ms->oem_table_id); 2603 } 2604 } 2605 #endif 2606 if (machine->numa_state->num_nodes) { 2607 acpi_add_table(table_offsets, tables_blob); 2608 build_srat(tables_blob, tables->linker, machine); 2609 if (machine->numa_state->have_numa_distance) { 2610 acpi_add_table(table_offsets, tables_blob); 2611 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2612 x86ms->oem_table_id); 2613 } 2614 if (machine->numa_state->hmat_enabled) { 2615 acpi_add_table(table_offsets, tables_blob); 2616 build_hmat(tables_blob, tables->linker, machine->numa_state, 2617 x86ms->oem_id, x86ms->oem_table_id); 2618 } 2619 } 2620 if (acpi_get_mcfg(&mcfg)) { 2621 acpi_add_table(table_offsets, tables_blob); 2622 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2623 x86ms->oem_table_id); 2624 } 2625 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2626 acpi_add_table(table_offsets, tables_blob); 2627 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2628 x86ms->oem_table_id); 2629 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2630 acpi_add_table(table_offsets, tables_blob); 2631 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2632 x86ms->oem_table_id); 2633 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2634 PCIDevice *pdev = PCI_DEVICE(iommu); 2635 2636 acpi_add_table(table_offsets, tables_blob); 2637 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2638 x86ms->oem_id, x86ms->oem_table_id); 2639 } 2640 if (machine->nvdimms_state->is_enabled) { 2641 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2642 machine->nvdimms_state, machine->ram_slots, 2643 x86ms->oem_id, x86ms->oem_table_id); 2644 } 2645 if (pcms->cxl_devices_state.is_enabled) { 2646 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2647 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2648 } 2649 2650 acpi_add_table(table_offsets, tables_blob); 2651 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2652 2653 /* Add tables supplied by user (if any) */ 2654 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2655 unsigned len = acpi_table_len(u); 2656 2657 acpi_add_table(table_offsets, tables_blob); 2658 g_array_append_vals(tables_blob, u, len); 2659 } 2660 2661 /* RSDT is pointed to by RSDP */ 2662 rsdt = tables_blob->len; 2663 build_rsdt(tables_blob, tables->linker, table_offsets, 2664 oem_id, oem_table_id); 2665 2666 /* RSDP is in FSEG memory, so allocate it separately */ 2667 { 2668 AcpiRsdpData rsdp_data = { 2669 .revision = 0, 2670 .oem_id = x86ms->oem_id, 2671 .xsdt_tbl_offset = NULL, 2672 .rsdt_tbl_offset = &rsdt, 2673 }; 2674 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2675 if (!pcmc->rsdp_in_ram) { 2676 /* We used to allocate some extra space for RSDP revision 2 but 2677 * only used the RSDP revision 0 space. The extra bytes were 2678 * zeroed out and not used. 2679 * Here we continue wasting those extra 16 bytes to make sure we 2680 * don't break migration for machine types 2.2 and older due to 2681 * RSDP blob size mismatch. 2682 */ 2683 build_append_int_noprefix(tables->rsdp, 0, 16); 2684 } 2685 } 2686 2687 /* We'll expose it all to Guest so we want to reduce 2688 * chance of size changes. 2689 * 2690 * We used to align the tables to 4k, but of course this would 2691 * too simple to be enough. 4k turned out to be too small an 2692 * alignment very soon, and in fact it is almost impossible to 2693 * keep the table size stable for all (max_cpus, max_memory_slots) 2694 * combinations. So the table size is always 64k for pc-i440fx-2.1 2695 * and we give an error if the table grows beyond that limit. 2696 * 2697 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2698 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2699 * than 2.0 and we can always pad the smaller tables with zeros. We can 2700 * then use the exact size of the 2.0 tables. 2701 * 2702 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2703 */ 2704 if (pcmc->legacy_acpi_table_size) { 2705 /* Subtracting aml_len gives the size of fixed tables. Then add the 2706 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2707 */ 2708 int legacy_aml_len = 2709 pcmc->legacy_acpi_table_size + 2710 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2711 int legacy_table_size = 2712 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2713 ACPI_BUILD_ALIGN_SIZE); 2714 if ((tables_blob->len > legacy_table_size) && 2715 !pcmc->resizable_acpi_blob) { 2716 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2717 warn_report("ACPI table size %u exceeds %d bytes," 2718 " migration may not work", 2719 tables_blob->len, legacy_table_size); 2720 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2721 " or PCI bridges.\n"); 2722 } 2723 g_array_set_size(tables_blob, legacy_table_size); 2724 } else { 2725 /* Make sure we have a buffer in case we need to resize the tables. */ 2726 if ((tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) && 2727 !pcmc->resizable_acpi_blob) { 2728 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2729 warn_report("ACPI table size %u exceeds %d bytes," 2730 " migration may not work", 2731 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2732 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2733 " or PCI bridges.\n"); 2734 } 2735 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2736 } 2737 2738 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2739 2740 /* Cleanup memory that's no longer used. */ 2741 g_array_free(table_offsets, true); 2742 g_free(slic_oem.id); 2743 g_free(slic_oem.table_id); 2744 } 2745 2746 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2747 { 2748 uint32_t size = acpi_data_len(data); 2749 2750 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2751 memory_region_ram_resize(mr, size, &error_abort); 2752 2753 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2754 memory_region_set_dirty(mr, 0, size); 2755 } 2756 2757 static void acpi_build_update(void *build_opaque) 2758 { 2759 AcpiBuildState *build_state = build_opaque; 2760 AcpiBuildTables tables; 2761 2762 /* No state to update or already patched? Nothing to do. */ 2763 if (!build_state || build_state->patched) { 2764 return; 2765 } 2766 build_state->patched = 1; 2767 2768 acpi_build_tables_init(&tables); 2769 2770 acpi_build(&tables, MACHINE(qdev_get_machine())); 2771 2772 acpi_ram_update(build_state->table_mr, tables.table_data); 2773 2774 if (build_state->rsdp) { 2775 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2776 } else { 2777 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2778 } 2779 2780 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2781 acpi_build_tables_cleanup(&tables, true); 2782 } 2783 2784 static void acpi_build_reset(void *build_opaque) 2785 { 2786 AcpiBuildState *build_state = build_opaque; 2787 build_state->patched = 0; 2788 } 2789 2790 static const VMStateDescription vmstate_acpi_build = { 2791 .name = "acpi_build", 2792 .version_id = 1, 2793 .minimum_version_id = 1, 2794 .fields = (const VMStateField[]) { 2795 VMSTATE_UINT8(patched, AcpiBuildState), 2796 VMSTATE_END_OF_LIST() 2797 }, 2798 }; 2799 2800 void acpi_setup(void) 2801 { 2802 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2803 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2804 X86MachineState *x86ms = X86_MACHINE(pcms); 2805 AcpiBuildTables tables; 2806 AcpiBuildState *build_state; 2807 Object *vmgenid_dev; 2808 #ifdef CONFIG_TPM 2809 TPMIf *tpm; 2810 static FwCfgTPMConfig tpm_config; 2811 #endif 2812 2813 if (!x86ms->fw_cfg) { 2814 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2815 return; 2816 } 2817 2818 if (!pcms->acpi_build_enabled) { 2819 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2820 return; 2821 } 2822 2823 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2824 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2825 return; 2826 } 2827 2828 build_state = g_malloc0(sizeof *build_state); 2829 2830 acpi_build_tables_init(&tables); 2831 acpi_build(&tables, MACHINE(pcms)); 2832 2833 /* Now expose it all to Guest */ 2834 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2835 build_state, tables.table_data, 2836 ACPI_BUILD_TABLE_FILE); 2837 assert(build_state->table_mr != NULL); 2838 2839 build_state->linker_mr = 2840 acpi_add_rom_blob(acpi_build_update, build_state, 2841 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2842 2843 #ifdef CONFIG_TPM 2844 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2845 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2846 2847 tpm = tpm_find(); 2848 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2849 tpm_config = (FwCfgTPMConfig) { 2850 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2851 .tpm_version = tpm_get_version(tpm), 2852 .tpmppi_version = TPM_PPI_VERSION_1_30 2853 }; 2854 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2855 &tpm_config, sizeof tpm_config); 2856 } 2857 #endif 2858 2859 vmgenid_dev = find_vmgenid_dev(); 2860 if (vmgenid_dev) { 2861 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2862 tables.vmgenid); 2863 } 2864 2865 if (!pcmc->rsdp_in_ram) { 2866 /* 2867 * Keep for compatibility with old machine types. 2868 * Though RSDP is small, its contents isn't immutable, so 2869 * we'll update it along with the rest of tables on guest access. 2870 */ 2871 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2872 2873 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2874 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2875 acpi_build_update, NULL, build_state, 2876 build_state->rsdp, rsdp_size, true); 2877 build_state->rsdp_mr = NULL; 2878 } else { 2879 build_state->rsdp = NULL; 2880 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2881 build_state, tables.rsdp, 2882 ACPI_BUILD_RSDP_FILE); 2883 } 2884 2885 qemu_register_reset(acpi_build_reset, build_state); 2886 acpi_build_reset(build_state); 2887 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2888 2889 /* Cleanup tables but don't free the memory: we track it 2890 * in build_state. 2891 */ 2892 acpi_build_tables_cleanup(&tables, false); 2893 } 2894