1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qobject/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "system/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/vmclock.h" 47 #include "hw/acpi/erst.h" 48 #include "hw/acpi/piix4.h" 49 #include "system/tpm_backend.h" 50 #include "hw/rtc/mc146818rtc_regs.h" 51 #include "migration/vmstate.h" 52 #include "hw/mem/memory-device.h" 53 #include "hw/mem/nvdimm.h" 54 #include "system/numa.h" 55 #include "system/reset.h" 56 #include "hw/hyperv/vmbus-bridge.h" 57 58 /* Supported chipsets: */ 59 #include "hw/southbridge/ich9.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/pc.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/i440fx.h" 65 #include "hw/pci-host/q35.h" 66 #include "hw/i386/x86-iommu.h" 67 68 #include "hw/acpi/aml-build.h" 69 #include "hw/acpi/utils.h" 70 #include "hw/acpi/pci.h" 71 #include "hw/acpi/cxl.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_ALIGN_SIZE 0x1000 89 90 #define ACPI_BUILD_TABLE_SIZE 0x20000 91 92 /* #define DEBUG_ACPI_BUILD */ 93 #ifdef DEBUG_ACPI_BUILD 94 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 96 #else 97 #define ACPI_BUILD_DPRINTF(fmt, ...) 98 #endif 99 100 typedef struct AcpiPmInfo { 101 bool s3_disabled; 102 bool s4_disabled; 103 bool pcihp_bridge_en; 104 bool smi_on_cpuhp; 105 bool smi_on_cpu_unplug; 106 bool pcihp_root_en; 107 uint8_t s4_val; 108 AcpiFadtData fadt; 109 uint16_t cpu_hp_io_base; 110 uint16_t pcihp_io_base; 111 uint16_t pcihp_io_len; 112 } AcpiPmInfo; 113 114 typedef struct AcpiMiscInfo { 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 } AcpiMiscInfo; 120 121 typedef struct FwCfgTPMConfig { 122 uint32_t tpmppi_address; 123 uint8_t tpm_version; 124 uint8_t tpmppi_version; 125 } QEMU_PACKED FwCfgTPMConfig; 126 127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 128 129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 130 .space_id = AML_AS_SYSTEM_IO, 131 .address = NVDIMM_ACPI_IO_BASE, 132 .bit_width = NVDIMM_ACPI_IO_LEN << 3 133 }; 134 135 static void init_common_fadt_data(MachineState *ms, Object *o, 136 AcpiFadtData *data) 137 { 138 X86MachineState *x86ms = X86_MACHINE(ms); 139 /* 140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 141 * behavior for compatibility irrelevant to smm_enabled, which doesn't 142 * conform to the ACPI spec. 143 */ 144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 145 true : x86_machine_is_smm_enabled(x86ms); 146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 147 AmlAddressSpace as = AML_AS_SYSTEM_IO; 148 AcpiFadtData fadt = { 149 .rev = 3, 150 .flags = 151 (1 << ACPI_FADT_F_WBINVD) | 152 (1 << ACPI_FADT_F_PROC_C1) | 153 (1 << ACPI_FADT_F_SLP_BUTTON) | 154 (1 << ACPI_FADT_F_RTC_S4) | 155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 156 /* APIC destination mode ("Flat Logical") has an upper limit of 8 157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 158 * used 159 */ 160 ((ms->smp.max_cpus > 8) ? 161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 162 .int_model = 1 /* Multiple APIC */, 163 .rtc_century = RTC_CENTURY, 164 .plvl2_lat = 0xfff /* C2 state not supported */, 165 .plvl3_lat = 0xfff /* C3 state not supported */, 166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 168 .acpi_enable_cmd = 169 smm_enabled ? 170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 171 0, 172 .acpi_disable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 175 0, 176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 178 .address = io + 0x04 }, 179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 180 .gpe0_blk = { .space_id = as, .bit_width = 181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 183 }, 184 }; 185 186 /* 187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 188 * Flags, bit offset 1 - 8042. 189 */ 190 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 191 192 *data = fadt; 193 } 194 195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 196 { 197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL); 198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL); 199 Object *obj = piix ? piix : lpc; 200 QObject *o; 201 pm->cpu_hp_io_base = 0; 202 pm->pcihp_io_base = 0; 203 pm->pcihp_io_len = 0; 204 pm->smi_on_cpuhp = false; 205 pm->smi_on_cpu_unplug = false; 206 207 assert(obj); 208 init_common_fadt_data(machine, obj, &pm->fadt); 209 if (piix) { 210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 211 pm->fadt.rev = 1; 212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 213 } 214 if (lpc) { 215 uint64_t smi_features = object_property_get_uint(lpc, 216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 219 pm->fadt.reset_reg = r; 220 pm->fadt.reset_val = 0xf; 221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 223 pm->smi_on_cpuhp = 224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 225 pm->smi_on_cpu_unplug = 226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 227 } 228 pm->pcihp_io_base = 229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 230 pm->pcihp_io_len = 231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 232 233 /* Fill in optional s3/s4 related properties */ 234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 235 if (o) { 236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 237 } else { 238 pm->s3_disabled = false; 239 } 240 qobject_unref(o); 241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 242 if (o) { 243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 244 } else { 245 pm->s4_disabled = false; 246 } 247 qobject_unref(o); 248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 249 if (o) { 250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 251 } else { 252 pm->s4_val = false; 253 } 254 qobject_unref(o); 255 256 pm->pcihp_bridge_en = 257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 258 NULL); 259 pm->pcihp_root_en = 260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 261 NULL); 262 } 263 264 static void acpi_get_misc_info(AcpiMiscInfo *info) 265 { 266 info->has_hpet = hpet_find(); 267 #ifdef CONFIG_TPM 268 info->tpm_version = tpm_get_version(tpm_find()); 269 #endif 270 } 271 272 /* 273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 274 * On i386 arch we only have two pci hosts, so we can look only for them. 275 */ 276 Object *acpi_get_i386_pci_host(void) 277 { 278 PCIHostState *host; 279 280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 281 if (!host) { 282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 283 } 284 285 return OBJECT(host); 286 } 287 288 static void acpi_get_pci_holes(Range *hole, Range *hole64) 289 { 290 Object *pci_host; 291 292 pci_host = acpi_get_i386_pci_host(); 293 294 if (!pci_host) { 295 return; 296 } 297 298 range_set_bounds1(hole, 299 object_property_get_uint(pci_host, 300 PCI_HOST_PROP_PCI_HOLE_START, 301 NULL), 302 object_property_get_uint(pci_host, 303 PCI_HOST_PROP_PCI_HOLE_END, 304 NULL)); 305 range_set_bounds1(hole64, 306 object_property_get_uint(pci_host, 307 PCI_HOST_PROP_PCI_HOLE64_START, 308 NULL), 309 object_property_get_uint(pci_host, 310 PCI_HOST_PROP_PCI_HOLE64_END, 311 NULL)); 312 } 313 314 static void acpi_align_size(GArray *blob, unsigned align) 315 { 316 /* Align size to multiple of given size. This reduces the chance 317 * we need to change size in the future (breaking cross version migration). 318 */ 319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 320 } 321 322 /* 323 * ACPI spec 1.0b, 324 * 5.2.6 Firmware ACPI Control Structure 325 */ 326 static void 327 build_facs(GArray *table_data) 328 { 329 const char *sig = "FACS"; 330 const uint8_t reserved[40] = {}; 331 332 g_array_append_vals(table_data, sig, 4); /* Signature */ 333 build_append_int_noprefix(table_data, 64, 4); /* Length */ 334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 337 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 338 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 339 } 340 341 static Aml *aml_pci_device_dsm(void) 342 { 343 Aml *method; 344 345 method = aml_method("_DSM", 4, AML_SERIALIZED); 346 { 347 Aml *params = aml_local(0); 348 Aml *pkg = aml_package(2); 349 aml_append(pkg, aml_int(0)); 350 aml_append(pkg, aml_int(0)); 351 aml_append(method, aml_store(pkg, params)); 352 aml_append(method, 353 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); 354 aml_append(method, 355 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); 356 aml_append(method, 357 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 358 aml_arg(2), aml_arg(3), params)) 359 ); 360 } 361 return method; 362 } 363 364 static Aml *aml_pci_edsm(void) 365 { 366 Aml *method, *ifctx; 367 Aml *zero = aml_int(0); 368 Aml *func = aml_arg(2); 369 Aml *ret = aml_local(0); 370 Aml *aidx = aml_local(1); 371 Aml *params = aml_arg(4); 372 373 method = aml_method("EDSM", 5, AML_SERIALIZED); 374 375 /* get supported functions */ 376 ifctx = aml_if(aml_equal(func, zero)); 377 { 378 /* 1: have supported functions */ 379 /* 7: support for function 7 */ 380 const uint8_t caps = 1 | BIT(7); 381 build_append_pci_dsm_func0_common(ifctx, ret); 382 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 383 aml_append(ifctx, aml_return(ret)); 384 } 385 aml_append(method, ifctx); 386 387 /* handle specific functions requests */ 388 /* 389 * PCI Firmware Specification 3.1 390 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 391 * Operating Systems 392 */ 393 ifctx = aml_if(aml_equal(func, aml_int(7))); 394 { 395 Aml *pkg = aml_package(2); 396 aml_append(pkg, zero); 397 /* optional, if not impl. should return null string */ 398 aml_append(pkg, aml_string("%s", "")); 399 aml_append(ifctx, aml_store(pkg, ret)); 400 401 /* 402 * IASL is fine when initializing Package with computational data, 403 * however it makes guest unhappy /it fails to process such AML/. 404 * So use runtime assignment to set acpi-index after initializer 405 * to make OSPM happy. 406 */ 407 aml_append(ifctx, 408 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 409 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 410 aml_append(ifctx, aml_return(ret)); 411 } 412 aml_append(method, ifctx); 413 414 return method; 415 } 416 417 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 418 { 419 Aml *method; 420 421 g_assert(pdev->acpi_index != 0); 422 method = aml_method("_DSM", 4, AML_SERIALIZED); 423 { 424 Aml *params = aml_local(0); 425 Aml *pkg = aml_package(1); 426 aml_append(pkg, aml_int(pdev->acpi_index)); 427 aml_append(method, aml_store(pkg, params)); 428 aml_append(method, 429 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 430 aml_arg(2), aml_arg(3), params)) 431 ); 432 } 433 return method; 434 } 435 436 static void build_append_pcihp_notify_entry(Aml *method, int slot) 437 { 438 Aml *if_ctx; 439 int32_t devfn = PCI_DEVFN(slot, 0); 440 441 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 442 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 443 aml_append(method, if_ctx); 444 } 445 446 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 447 { 448 const PCIDevice *pdev = bus->devices[devfn]; 449 450 if (PCI_FUNC(devfn)) { 451 if (IS_PCI_BRIDGE(pdev)) { 452 /* 453 * Ignore only hotplugged PCI bridges on !0 functions, but 454 * allow describing cold plugged bridges on all functions 455 */ 456 if (DEVICE(pdev)->hotplugged) { 457 return true; 458 } 459 } 460 } 461 return false; 462 } 463 464 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 465 { 466 PCIDevice *pdev = bus->devices[devfn]; 467 if (pdev) { 468 return is_devfn_ignored_generic(devfn, bus) || 469 !DEVICE_GET_CLASS(pdev)->hotpluggable || 470 /* Cold plugged bridges aren't themselves hot-pluggable */ 471 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 472 } else { /* non populated slots */ 473 /* 474 * hotplug is supported only for non-multifunction device 475 * so generate device description only for function 0 476 */ 477 if (PCI_FUNC(devfn) || 478 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 479 return true; 480 } 481 } 482 return false; 483 } 484 485 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) 486 { 487 int devfn; 488 Aml *dev, *notify_method = NULL, *method; 489 QObject *bsel = object_property_get_qobject(OBJECT(bus), 490 ACPI_PCIHP_PROP_BSEL, NULL); 491 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 492 qobject_unref(bsel); 493 494 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 495 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 496 497 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 498 int slot = PCI_SLOT(devfn); 499 int adr = slot << 16 | PCI_FUNC(devfn); 500 501 if (is_devfn_ignored_hotplug(devfn, bus)) { 502 continue; 503 } 504 505 if (bus->devices[devfn]) { 506 dev = aml_scope("S%.02X", devfn); 507 } else { 508 dev = aml_device("S%.02X", devfn); 509 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 510 } 511 512 /* 513 * Can't declare _SUN here for every device as it changes 'slot' 514 * enumeration order in linux kernel, so use another variable for it 515 */ 516 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 517 aml_append(dev, aml_pci_device_dsm()); 518 519 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 520 /* add _EJ0 to make slot hotpluggable */ 521 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 522 aml_append(method, 523 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 524 ); 525 aml_append(dev, method); 526 527 build_append_pcihp_notify_entry(notify_method, slot); 528 529 /* device descriptor has been composed, add it into parent context */ 530 aml_append(parent_scope, dev); 531 } 532 aml_append(parent_scope, notify_method); 533 } 534 535 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 536 { 537 int devfn; 538 Aml *dev; 539 540 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 541 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 542 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 543 PCIDevice *pdev = bus->devices[devfn]; 544 545 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 546 continue; 547 } 548 549 /* start to compose PCI device descriptor */ 550 dev = aml_device("S%.02X", devfn); 551 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 552 553 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 554 /* add _DSM if device has acpi-index set */ 555 if (pdev->acpi_index && 556 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 557 &error_abort)) { 558 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 559 } 560 561 /* device descriptor has been composed, add it into parent context */ 562 aml_append(parent_scope, dev); 563 } 564 } 565 566 static bool build_append_notification_callback(Aml *parent_scope, 567 const PCIBus *bus) 568 { 569 Aml *method; 570 PCIBus *sec; 571 QObject *bsel; 572 int nr_notifiers = 0; 573 GQueue *pcnt_bus_list = g_queue_new(); 574 575 QLIST_FOREACH(sec, &bus->child, sibling) { 576 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 577 if (pci_bus_is_root(sec)) { 578 continue; 579 } 580 nr_notifiers = nr_notifiers + 581 build_append_notification_callback(br_scope, sec); 582 /* 583 * add new child scope to parent 584 * and keep track of bus that have PCNT, 585 * bus list is used later to call children PCNTs from this level PCNT 586 */ 587 if (nr_notifiers) { 588 g_queue_push_tail(pcnt_bus_list, sec); 589 aml_append(parent_scope, br_scope); 590 } 591 } 592 593 /* 594 * Append PCNT method to notify about events on local and child buses. 595 * ps: hostbridge might not have hotplug (bsel) enabled but might have 596 * child bridges that do have bsel. 597 */ 598 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 599 600 /* If bus supports hotplug select it and notify about local events */ 601 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 602 if (bsel) { 603 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 604 605 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 606 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 607 aml_int(1))); /* Device Check */ 608 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 609 aml_int(3))); /* Eject Request */ 610 nr_notifiers++; 611 } 612 613 /* Notify about child bus events in any case */ 614 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 615 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 616 } 617 618 aml_append(parent_scope, method); 619 qobject_unref(bsel); 620 g_queue_free(pcnt_bus_list); 621 return !!nr_notifiers; 622 } 623 624 /* 625 * build_prt - Define interrupt routing rules 626 * 627 * Returns an array of 128 routes, one for each device, 628 * based on device location. 629 * The main goal is to equally distribute the interrupts 630 * over the 4 existing ACPI links (works only for i440fx). 631 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]". 632 * 633 */ 634 static Aml *build_prt(bool is_pci0_prt) 635 { 636 const int nroutes = 128; 637 Aml *rt_pkg, *method; 638 int pin; 639 640 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 641 assert(nroutes < 256); 642 rt_pkg = aml_package(nroutes); 643 644 for (pin = 0; pin < nroutes; pin++) { 645 Aml *pkg = aml_package(4); 646 int slot = pin >> 2; 647 648 aml_append(pkg, aml_int((slot << 16) | 0xFFFF)); 649 aml_append(pkg, aml_int(pin & 3)); 650 /* device 1 is the power-management device, needs SCI */ 651 if (is_pci0_prt && pin == 4) { 652 aml_append(pkg, aml_name("%s", "LNKS")); 653 } else { 654 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"}; 655 int hash = (slot + pin) & 3; 656 aml_append(pkg, aml_name("%s", link_name[hash])); 657 } 658 aml_append(pkg, aml_int(0)); 659 aml_append(rt_pkg, pkg); 660 } 661 662 aml_append(method, aml_return(rt_pkg)); 663 664 return method; 665 } 666 667 static void build_hpet_aml(Aml *table) 668 { 669 Aml *crs; 670 Aml *field; 671 Aml *method; 672 Aml *if_ctx; 673 Aml *scope = aml_scope("_SB"); 674 Aml *dev = aml_device("HPET"); 675 Aml *zero = aml_int(0); 676 Aml *id = aml_local(0); 677 Aml *period = aml_local(1); 678 679 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 680 aml_append(dev, aml_name_decl("_UID", zero)); 681 682 aml_append(dev, 683 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 684 HPET_LEN)); 685 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 686 aml_append(field, aml_named_field("VEND", 32)); 687 aml_append(field, aml_named_field("PRD", 32)); 688 aml_append(dev, field); 689 690 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 691 aml_append(method, aml_store(aml_name("VEND"), id)); 692 aml_append(method, aml_store(aml_name("PRD"), period)); 693 aml_append(method, aml_shiftright(id, aml_int(16), id)); 694 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 695 aml_equal(id, aml_int(0xffff)))); 696 { 697 aml_append(if_ctx, aml_return(zero)); 698 } 699 aml_append(method, if_ctx); 700 701 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 702 aml_lgreater(period, aml_int(100000000)))); 703 { 704 aml_append(if_ctx, aml_return(zero)); 705 } 706 aml_append(method, if_ctx); 707 708 aml_append(method, aml_return(aml_int(0x0F))); 709 aml_append(dev, method); 710 711 crs = aml_resource_template(); 712 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 713 aml_append(dev, aml_name_decl("_CRS", crs)); 714 715 aml_append(scope, dev); 716 aml_append(table, scope); 717 } 718 719 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 720 { 721 Aml *dev; 722 Aml *method; 723 Aml *crs; 724 725 dev = aml_device("VMBS"); 726 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 727 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 728 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 729 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 730 731 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 732 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 733 aml_name("STA"))); 734 aml_append(dev, method); 735 736 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 737 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 738 aml_name("STA"))); 739 aml_append(dev, method); 740 741 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 742 aml_append(method, aml_return(aml_name("STA"))); 743 aml_append(dev, method); 744 745 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 746 747 crs = aml_resource_template(); 748 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 749 aml_append(dev, aml_name_decl("_CRS", crs)); 750 751 return dev; 752 } 753 754 static void build_dbg_aml(Aml *table) 755 { 756 Aml *field; 757 Aml *method; 758 Aml *while_ctx; 759 Aml *scope = aml_scope("\\"); 760 Aml *buf = aml_local(0); 761 Aml *len = aml_local(1); 762 Aml *idx = aml_local(2); 763 764 aml_append(scope, 765 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 766 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 767 aml_append(field, aml_named_field("DBGB", 8)); 768 aml_append(scope, field); 769 770 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 771 772 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 773 aml_append(method, aml_to_buffer(buf, buf)); 774 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 775 aml_append(method, aml_store(aml_int(0), idx)); 776 777 while_ctx = aml_while(aml_lless(idx, len)); 778 aml_append(while_ctx, 779 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 780 aml_append(while_ctx, aml_increment(idx)); 781 aml_append(method, while_ctx); 782 783 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 784 aml_append(scope, method); 785 786 aml_append(table, scope); 787 } 788 789 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 790 { 791 Aml *dev; 792 Aml *crs; 793 Aml *method; 794 uint32_t irqs[] = {5, 10, 11}; 795 796 dev = aml_device("%s", name); 797 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 798 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 799 800 crs = aml_resource_template(); 801 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 802 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 803 aml_append(dev, aml_name_decl("_PRS", crs)); 804 805 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 806 aml_append(method, aml_return(aml_call1("IQST", reg))); 807 aml_append(dev, method); 808 809 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 810 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 811 aml_append(dev, method); 812 813 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 814 aml_append(method, aml_return(aml_call1("IQCR", reg))); 815 aml_append(dev, method); 816 817 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 818 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 819 aml_append(method, aml_store(aml_name("PRRI"), reg)); 820 aml_append(dev, method); 821 822 return dev; 823 } 824 825 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 826 { 827 Aml *dev; 828 Aml *crs; 829 Aml *method; 830 uint32_t irqs; 831 832 dev = aml_device("%s", name); 833 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 834 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 835 836 crs = aml_resource_template(); 837 irqs = gsi; 838 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 839 AML_SHARED, &irqs, 1)); 840 aml_append(dev, aml_name_decl("_PRS", crs)); 841 842 aml_append(dev, aml_name_decl("_CRS", crs)); 843 844 /* 845 * _DIS can be no-op because the interrupt cannot be disabled. 846 */ 847 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 848 aml_append(dev, method); 849 850 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 851 aml_append(dev, method); 852 853 return dev; 854 } 855 856 /* _CRS method - get current settings */ 857 static Aml *build_iqcr_method(bool is_piix4) 858 { 859 Aml *if_ctx; 860 uint32_t irqs; 861 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 862 Aml *crs = aml_resource_template(); 863 864 irqs = 0; 865 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 866 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 867 aml_append(method, aml_name_decl("PRR0", crs)); 868 869 aml_append(method, 870 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 871 872 if (is_piix4) { 873 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 874 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 875 aml_append(method, if_ctx); 876 } else { 877 aml_append(method, 878 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 879 aml_name("PRRI"))); 880 } 881 882 aml_append(method, aml_return(aml_name("PRR0"))); 883 return method; 884 } 885 886 /* _STA method - get status */ 887 static Aml *build_irq_status_method(void) 888 { 889 Aml *if_ctx; 890 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 891 892 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 893 aml_append(if_ctx, aml_return(aml_int(0x09))); 894 aml_append(method, if_ctx); 895 aml_append(method, aml_return(aml_int(0x0B))); 896 return method; 897 } 898 899 static void build_piix4_pci0_int(Aml *table) 900 { 901 Aml *dev; 902 Aml *crs; 903 Aml *method; 904 uint32_t irqs; 905 Aml *sb_scope = aml_scope("_SB"); 906 Aml *pci0_scope = aml_scope("PCI0"); 907 908 aml_append(pci0_scope, build_prt(true)); 909 aml_append(sb_scope, pci0_scope); 910 911 aml_append(sb_scope, build_irq_status_method()); 912 aml_append(sb_scope, build_iqcr_method(true)); 913 914 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 915 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 916 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 917 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 918 919 dev = aml_device("LNKS"); 920 { 921 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 922 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 923 924 crs = aml_resource_template(); 925 irqs = 9; 926 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 927 AML_ACTIVE_HIGH, AML_SHARED, 928 &irqs, 1)); 929 aml_append(dev, aml_name_decl("_PRS", crs)); 930 931 /* The SCI cannot be disabled and is always attached to GSI 9, 932 * so these are no-ops. We only need this link to override the 933 * polarity to active high and match the content of the MADT. 934 */ 935 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 936 aml_append(method, aml_return(aml_int(0x0b))); 937 aml_append(dev, method); 938 939 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 940 aml_append(dev, method); 941 942 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 943 aml_append(method, aml_return(aml_name("_PRS"))); 944 aml_append(dev, method); 945 946 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 947 aml_append(dev, method); 948 } 949 aml_append(sb_scope, dev); 950 951 aml_append(table, sb_scope); 952 } 953 954 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 955 { 956 int i; 957 int head; 958 Aml *pkg; 959 char base = name[3] < 'E' ? 'A' : 'E'; 960 char *s = g_strdup(name); 961 Aml *a_nr = aml_int((nr << 16) | 0xffff); 962 963 assert(strlen(s) == 4); 964 965 head = name[3] - base; 966 for (i = 0; i < 4; i++) { 967 if (head + i > 3) { 968 head = i * -1; 969 } 970 s[3] = base + head + i; 971 pkg = aml_package(4); 972 aml_append(pkg, a_nr); 973 aml_append(pkg, aml_int(i)); 974 aml_append(pkg, aml_name("%s", s)); 975 aml_append(pkg, aml_int(0)); 976 aml_append(ctx, pkg); 977 } 978 g_free(s); 979 } 980 981 static Aml *build_q35_routing_table(const char *str) 982 { 983 int i; 984 Aml *pkg; 985 char *name = g_strdup_printf("%s ", str); 986 987 pkg = aml_package(128); 988 for (i = 0; i < 0x18; i++) { 989 name[3] = 'E' + (i & 0x3); 990 append_q35_prt_entry(pkg, i, name); 991 } 992 993 name[3] = 'E'; 994 append_q35_prt_entry(pkg, 0x18, name); 995 996 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 997 for (i = 0x0019; i < 0x1e; i++) { 998 name[3] = 'A'; 999 append_q35_prt_entry(pkg, i, name); 1000 } 1001 1002 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1003 name[3] = 'E'; 1004 append_q35_prt_entry(pkg, 0x1e, name); 1005 name[3] = 'A'; 1006 append_q35_prt_entry(pkg, 0x1f, name); 1007 1008 g_free(name); 1009 return pkg; 1010 } 1011 1012 static void build_q35_pci0_int(Aml *table) 1013 { 1014 Aml *method; 1015 Aml *sb_scope = aml_scope("_SB"); 1016 Aml *pci0_scope = aml_scope("PCI0"); 1017 1018 /* Zero => PIC mode, One => APIC Mode */ 1019 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1020 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1021 { 1022 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1023 } 1024 aml_append(table, method); 1025 1026 aml_append(pci0_scope, 1027 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1028 aml_append(pci0_scope, 1029 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1030 1031 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1032 { 1033 Aml *if_ctx; 1034 Aml *else_ctx; 1035 1036 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1037 section 6.2.8.1 */ 1038 /* Note: we provide the same info as the PCI routing 1039 table of the Bochs BIOS */ 1040 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1041 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1042 aml_append(method, if_ctx); 1043 else_ctx = aml_else(); 1044 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1045 aml_append(method, else_ctx); 1046 } 1047 aml_append(pci0_scope, method); 1048 aml_append(sb_scope, pci0_scope); 1049 1050 aml_append(sb_scope, build_irq_status_method()); 1051 aml_append(sb_scope, build_iqcr_method(false)); 1052 1053 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1054 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1055 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1056 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1057 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1058 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1059 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1060 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1061 1062 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1063 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1064 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1065 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1066 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1067 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1068 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1069 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1070 1071 aml_append(table, sb_scope); 1072 } 1073 1074 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1075 { 1076 Aml *dev; 1077 Aml *resource_template; 1078 1079 /* DRAM controller */ 1080 dev = aml_device("DRAC"); 1081 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1082 1083 resource_template = aml_resource_template(); 1084 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1085 aml_append(resource_template, 1086 aml_qword_memory(AML_POS_DECODE, 1087 AML_MIN_FIXED, 1088 AML_MAX_FIXED, 1089 AML_NON_CACHEABLE, 1090 AML_READ_WRITE, 1091 0x0000000000000000, 1092 mcfg->base, 1093 mcfg->base + mcfg->size - 1, 1094 0x0000000000000000, 1095 mcfg->size)); 1096 } else { 1097 aml_append(resource_template, 1098 aml_dword_memory(AML_POS_DECODE, 1099 AML_MIN_FIXED, 1100 AML_MAX_FIXED, 1101 AML_NON_CACHEABLE, 1102 AML_READ_WRITE, 1103 0x0000000000000000, 1104 mcfg->base, 1105 mcfg->base + mcfg->size - 1, 1106 0x0000000000000000, 1107 mcfg->size)); 1108 } 1109 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1110 1111 return dev; 1112 } 1113 1114 static void build_acpi0017(Aml *table) 1115 { 1116 Aml *dev, *scope, *method; 1117 1118 scope = aml_scope("_SB"); 1119 dev = aml_device("CXLM"); 1120 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1121 1122 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1123 aml_append(method, aml_return(aml_int(0x0B))); 1124 aml_append(dev, method); 1125 build_cxl_dsm_method(dev); 1126 1127 aml_append(scope, dev); 1128 aml_append(table, scope); 1129 } 1130 1131 static void 1132 build_dsdt(GArray *table_data, BIOSLinker *linker, 1133 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1134 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1135 { 1136 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE, 1137 NULL); 1138 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL); 1139 CrsRangeEntry *entry; 1140 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1141 CrsRangeSet crs_range_set; 1142 PCMachineState *pcms = PC_MACHINE(machine); 1143 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1144 X86MachineState *x86ms = X86_MACHINE(machine); 1145 AcpiMcfgInfo mcfg; 1146 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1147 uint32_t nr_mem = machine->ram_slots; 1148 int root_bus_limit = 0xFF; 1149 PCIBus *bus = NULL; 1150 #ifdef CONFIG_TPM 1151 TPMIf *tpm = tpm_find(); 1152 #endif 1153 bool cxl_present = false; 1154 int i; 1155 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1156 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1157 .oem_table_id = x86ms->oem_table_id }; 1158 1159 assert(!!i440fx != !!q35); 1160 1161 acpi_table_begin(&table, table_data); 1162 dsdt = init_aml_allocator(); 1163 1164 build_dbg_aml(dsdt); 1165 if (i440fx) { 1166 sb_scope = aml_scope("_SB"); 1167 dev = aml_device("PCI0"); 1168 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1169 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1170 aml_append(dev, aml_pci_edsm()); 1171 aml_append(sb_scope, dev); 1172 aml_append(dsdt, sb_scope); 1173 1174 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1175 build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1176 } 1177 build_piix4_pci0_int(dsdt); 1178 } else if (q35) { 1179 sb_scope = aml_scope("_SB"); 1180 dev = aml_device("PCI0"); 1181 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1182 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1183 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1184 aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en)); 1185 aml_append(dev, aml_pci_edsm()); 1186 aml_append(sb_scope, dev); 1187 if (mcfg_valid) { 1188 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1189 } 1190 1191 if (pm->smi_on_cpuhp) { 1192 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1193 dev = aml_device("PCI0.SMI0"); 1194 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1195 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1196 crs = aml_resource_template(); 1197 aml_append(crs, 1198 aml_io( 1199 AML_DECODE16, 1200 pm->fadt.smi_cmd, 1201 pm->fadt.smi_cmd, 1202 1, 1203 2) 1204 ); 1205 aml_append(dev, aml_name_decl("_CRS", crs)); 1206 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1207 aml_int(pm->fadt.smi_cmd), 2)); 1208 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1209 AML_WRITE_AS_ZEROS); 1210 aml_append(field, aml_named_field("SMIC", 8)); 1211 aml_append(field, aml_reserved_field(8)); 1212 aml_append(dev, field); 1213 aml_append(sb_scope, dev); 1214 } 1215 1216 aml_append(dsdt, sb_scope); 1217 1218 if (pm->pcihp_bridge_en) { 1219 build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1220 } 1221 build_q35_pci0_int(dsdt); 1222 } 1223 1224 if (misc->has_hpet) { 1225 build_hpet_aml(dsdt); 1226 } 1227 1228 if (vmbus_bridge) { 1229 sb_scope = aml_scope("_SB"); 1230 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1231 aml_append(dsdt, sb_scope); 1232 } 1233 1234 scope = aml_scope("_GPE"); 1235 { 1236 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1237 if (machine->nvdimms_state->is_enabled) { 1238 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1239 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1240 aml_int(0x80))); 1241 aml_append(scope, method); 1242 } 1243 } 1244 aml_append(dsdt, scope); 1245 1246 if (pcmc->legacy_cpu_hotplug) { 1247 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1248 } else { 1249 CPUHotplugFeatures opts = { 1250 .acpi_1_compatible = true, .has_legacy_cphp = true, 1251 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1252 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1253 }; 1254 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, 1255 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", 1256 AML_SYSTEM_IO); 1257 } 1258 1259 if (pcms->memhp_io_base && nr_mem) { 1260 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1261 "\\_GPE._E03", AML_SYSTEM_IO, 1262 pcms->memhp_io_base); 1263 } 1264 1265 crs_range_set_init(&crs_range_set); 1266 bus = PC_MACHINE(machine)->pcibus; 1267 if (bus) { 1268 QLIST_FOREACH(bus, &bus->child, sibling) { 1269 uint8_t bus_num = pci_bus_num(bus); 1270 uint8_t numa_node = pci_bus_numa_node(bus); 1271 uint32_t uid; 1272 1273 /* look only for expander root buses */ 1274 if (!pci_bus_is_root(bus)) { 1275 continue; 1276 } 1277 1278 if (bus_num < root_bus_limit) { 1279 root_bus_limit = bus_num - 1; 1280 } 1281 1282 uid = object_property_get_uint(OBJECT(bus), "acpi_uid", 1283 &error_fatal); 1284 scope = aml_scope("\\_SB"); 1285 1286 if (pci_bus_is_cxl(bus)) { 1287 dev = aml_device("CL%.02X", bus_num); 1288 } else { 1289 dev = aml_device("PC%.02X", bus_num); 1290 } 1291 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1292 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1293 if (pci_bus_is_cxl(bus)) { 1294 struct Aml *aml_pkg = aml_package(2); 1295 1296 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1297 aml_append(aml_pkg, aml_eisaid("PNP0A08")); 1298 aml_append(aml_pkg, aml_eisaid("PNP0A03")); 1299 aml_append(dev, aml_name_decl("_CID", aml_pkg)); 1300 build_cxl_osc_method(dev); 1301 } else if (pci_bus_is_express(bus)) { 1302 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1303 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1304 1305 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1306 aml_append(dev, build_pci_host_bridge_osc_method(true)); 1307 } else { 1308 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1309 } 1310 1311 if (numa_node != NUMA_NODE_UNASSIGNED) { 1312 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1313 } 1314 1315 aml_append(dev, build_prt(false)); 1316 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1317 0, 0, 0, 0); 1318 aml_append(dev, aml_name_decl("_CRS", crs)); 1319 aml_append(scope, dev); 1320 aml_append(dsdt, scope); 1321 1322 /* Handle the ranges for the PXB expanders */ 1323 if (pci_bus_is_cxl(bus)) { 1324 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1325 uint64_t base = mr->addr; 1326 1327 cxl_present = true; 1328 crs_range_insert(crs_range_set.mem_ranges, base, 1329 base + memory_region_size(mr) - 1); 1330 } 1331 } 1332 } 1333 1334 if (cxl_present) { 1335 build_acpi0017(dsdt); 1336 } 1337 1338 /* 1339 * At this point crs_range_set has all the ranges used by pci 1340 * busses *other* than PCI0. These ranges will be excluded from 1341 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1342 * too. 1343 */ 1344 if (mcfg_valid) { 1345 crs_range_insert(crs_range_set.mem_ranges, 1346 mcfg.base, mcfg.base + mcfg.size - 1); 1347 } 1348 1349 scope = aml_scope("\\_SB.PCI0"); 1350 /* build PCI0._CRS */ 1351 crs = aml_resource_template(); 1352 aml_append(crs, 1353 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1354 0x0000, 0x0, root_bus_limit, 1355 0x0000, root_bus_limit + 1)); 1356 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1357 1358 aml_append(crs, 1359 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1360 AML_POS_DECODE, AML_ENTIRE_RANGE, 1361 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1362 1363 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1364 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1365 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1366 aml_append(crs, 1367 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1368 AML_POS_DECODE, AML_ENTIRE_RANGE, 1369 0x0000, entry->base, entry->limit, 1370 0x0000, entry->limit - entry->base + 1)); 1371 } 1372 1373 aml_append(crs, 1374 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1375 AML_CACHEABLE, AML_READ_WRITE, 1376 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1377 1378 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1379 range_lob(pci_hole), 1380 range_upb(pci_hole)); 1381 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1382 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1383 aml_append(crs, 1384 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1385 AML_NON_CACHEABLE, AML_READ_WRITE, 1386 0, entry->base, entry->limit, 1387 0, entry->limit - entry->base + 1)); 1388 } 1389 1390 if (!range_is_empty(pci_hole64)) { 1391 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1392 range_lob(pci_hole64), 1393 range_upb(pci_hole64)); 1394 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1395 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1396 aml_append(crs, 1397 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1398 AML_MAX_FIXED, 1399 AML_CACHEABLE, AML_READ_WRITE, 1400 0, entry->base, entry->limit, 1401 0, entry->limit - entry->base + 1)); 1402 } 1403 } 1404 1405 #ifdef CONFIG_TPM 1406 if (TPM_IS_TIS_ISA(tpm_find())) { 1407 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1408 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1409 } 1410 #endif 1411 aml_append(scope, aml_name_decl("_CRS", crs)); 1412 1413 /* reserve GPE0 block resources */ 1414 dev = aml_device("GPE0"); 1415 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1416 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1417 /* device present, functioning, decoding, not shown in UI */ 1418 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1419 crs = aml_resource_template(); 1420 aml_append(crs, 1421 aml_io( 1422 AML_DECODE16, 1423 pm->fadt.gpe0_blk.address, 1424 pm->fadt.gpe0_blk.address, 1425 1, 1426 pm->fadt.gpe0_blk.bit_width / 8) 1427 ); 1428 aml_append(dev, aml_name_decl("_CRS", crs)); 1429 aml_append(scope, dev); 1430 1431 crs_range_set_free(&crs_range_set); 1432 1433 /* reserve PCIHP resources */ 1434 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1435 build_append_pcihp_resources(scope, 1436 pm->pcihp_io_base, pm->pcihp_io_len); 1437 } 1438 aml_append(dsdt, scope); 1439 1440 /* create S3_ / S4_ / S5_ packages if necessary */ 1441 scope = aml_scope("\\"); 1442 if (!pm->s3_disabled) { 1443 pkg = aml_package(4); 1444 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1445 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1446 aml_append(pkg, aml_int(0)); /* reserved */ 1447 aml_append(pkg, aml_int(0)); /* reserved */ 1448 aml_append(scope, aml_name_decl("_S3", pkg)); 1449 } 1450 1451 if (!pm->s4_disabled) { 1452 pkg = aml_package(4); 1453 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1454 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1455 aml_append(pkg, aml_int(pm->s4_val)); 1456 aml_append(pkg, aml_int(0)); /* reserved */ 1457 aml_append(pkg, aml_int(0)); /* reserved */ 1458 aml_append(scope, aml_name_decl("_S4", pkg)); 1459 } 1460 1461 pkg = aml_package(4); 1462 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1463 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1464 aml_append(pkg, aml_int(0)); /* reserved */ 1465 aml_append(pkg, aml_int(0)); /* reserved */ 1466 aml_append(scope, aml_name_decl("_S5", pkg)); 1467 aml_append(dsdt, scope); 1468 1469 /* create fw_cfg node, unconditionally */ 1470 { 1471 scope = aml_scope("\\_SB.PCI0"); 1472 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1473 aml_append(dsdt, scope); 1474 } 1475 1476 sb_scope = aml_scope("\\_SB"); 1477 { 1478 Object *pci_host = acpi_get_i386_pci_host(); 1479 1480 if (pci_host) { 1481 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; 1482 Aml *ascope = aml_scope("PCI0"); 1483 /* Scan all PCI buses. Generate tables to support hotplug. */ 1484 build_append_pci_bus_devices(ascope, pbus); 1485 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) { 1486 build_append_pcihp_slots(ascope, pbus); 1487 } 1488 aml_append(sb_scope, ascope); 1489 } 1490 } 1491 1492 #ifdef CONFIG_TPM 1493 if (TPM_IS_CRB(tpm)) { 1494 dev = aml_device("TPM"); 1495 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1496 aml_append(dev, aml_name_decl("_STR", 1497 aml_string("TPM 2.0 Device"))); 1498 crs = aml_resource_template(); 1499 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1500 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1501 aml_append(dev, aml_name_decl("_CRS", crs)); 1502 1503 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1504 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1505 1506 tpm_build_ppi_acpi(tpm, dev); 1507 1508 aml_append(sb_scope, dev); 1509 } 1510 #endif 1511 1512 if (pcms->sgx_epc.size != 0) { 1513 uint64_t epc_base = pcms->sgx_epc.base; 1514 uint64_t epc_size = pcms->sgx_epc.size; 1515 1516 dev = aml_device("EPC"); 1517 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1518 aml_append(dev, aml_name_decl("_STR", 1519 aml_unicode("Enclave Page Cache 1.0"))); 1520 crs = aml_resource_template(); 1521 aml_append(crs, 1522 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1523 AML_MAX_FIXED, AML_NON_CACHEABLE, 1524 AML_READ_WRITE, 0, epc_base, 1525 epc_base + epc_size - 1, 0, epc_size)); 1526 aml_append(dev, aml_name_decl("_CRS", crs)); 1527 1528 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1529 aml_append(method, aml_return(aml_int(0x0f))); 1530 aml_append(dev, method); 1531 1532 aml_append(sb_scope, dev); 1533 } 1534 aml_append(dsdt, sb_scope); 1535 1536 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1537 bool has_pcnt; 1538 1539 Object *pci_host = acpi_get_i386_pci_host(); 1540 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; 1541 1542 scope = aml_scope("\\_SB.PCI0"); 1543 has_pcnt = build_append_notification_callback(scope, b); 1544 if (has_pcnt) { 1545 aml_append(dsdt, scope); 1546 } 1547 1548 scope = aml_scope("_GPE"); 1549 { 1550 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1551 if (has_pcnt) { 1552 aml_append(method, 1553 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1554 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1555 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1556 } 1557 aml_append(scope, method); 1558 } 1559 aml_append(dsdt, scope); 1560 } 1561 1562 /* copy AML table into ACPI tables blob and patch header there */ 1563 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1564 acpi_table_end(linker, &table); 1565 free_aml_allocator(); 1566 } 1567 1568 /* 1569 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1570 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1571 */ 1572 static void 1573 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1574 const char *oem_table_id) 1575 { 1576 AcpiTable table = { .sig = "HPET", .rev = 1, 1577 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1578 1579 acpi_table_begin(&table, table_data); 1580 /* Note timer_block_id value must be kept in sync with value advertised by 1581 * emulated hpet 1582 */ 1583 /* Event Timer Block ID */ 1584 build_append_int_noprefix(table_data, 0x8086a201, 4); 1585 /* BASE_ADDRESS */ 1586 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1587 /* HPET Number */ 1588 build_append_int_noprefix(table_data, 0, 1); 1589 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1590 build_append_int_noprefix(table_data, 0, 2); 1591 /* Page Protection And OEM Attribute */ 1592 build_append_int_noprefix(table_data, 0, 1); 1593 acpi_table_end(linker, &table); 1594 } 1595 1596 #ifdef CONFIG_TPM 1597 /* 1598 * TCPA Description Table 1599 * 1600 * Following Level 00, Rev 00.37 of specs: 1601 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1602 * 7.1.2 ACPI Table Layout 1603 */ 1604 static void 1605 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1606 const char *oem_id, const char *oem_table_id) 1607 { 1608 unsigned log_addr_offset; 1609 AcpiTable table = { .sig = "TCPA", .rev = 2, 1610 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1611 1612 acpi_table_begin(&table, table_data); 1613 /* Platform Class */ 1614 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1615 /* Log Area Minimum Length (LAML) */ 1616 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1617 /* Log Area Start Address (LASA) */ 1618 log_addr_offset = table_data->len; 1619 build_append_int_noprefix(table_data, 0, 8); 1620 1621 /* allocate/reserve space for TPM log area */ 1622 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1623 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1624 false /* high memory */); 1625 /* log area start address to be filled by Guest linker */ 1626 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1627 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1628 1629 acpi_table_end(linker, &table); 1630 } 1631 #endif 1632 1633 #define HOLE_640K_START (640 * KiB) 1634 #define HOLE_640K_END (1 * MiB) 1635 1636 /* 1637 * ACPI spec, Revision 3.0 1638 * 5.2.15 System Resource Affinity Table (SRAT) 1639 */ 1640 static void 1641 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1642 { 1643 int i; 1644 int numa_mem_start, slots; 1645 uint64_t mem_len, mem_base, next_base; 1646 MachineClass *mc = MACHINE_GET_CLASS(machine); 1647 X86MachineState *x86ms = X86_MACHINE(machine); 1648 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1649 int nb_numa_nodes = machine->numa_state->num_nodes; 1650 NodeInfo *numa_info = machine->numa_state->nodes; 1651 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1652 .oem_table_id = x86ms->oem_table_id }; 1653 1654 acpi_table_begin(&table, table_data); 1655 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1656 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1657 1658 for (i = 0; i < apic_ids->len; i++) { 1659 int node_id = apic_ids->cpus[i].props.node_id; 1660 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1661 1662 if (apic_id < 255) { 1663 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1664 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1665 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1666 /* Proximity Domain [7:0] */ 1667 build_append_int_noprefix(table_data, node_id, 1); 1668 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1669 /* Flags, Table 5-36 */ 1670 build_append_int_noprefix(table_data, 1, 4); 1671 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1672 /* Proximity Domain [31:8] */ 1673 build_append_int_noprefix(table_data, 0, 3); 1674 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1675 } else { 1676 /* 1677 * ACPI spec, Revision 4.0 1678 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1679 */ 1680 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1681 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1682 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1683 /* Proximity Domain */ 1684 build_append_int_noprefix(table_data, node_id, 4); 1685 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1686 /* Flags, Table 5-39 */ 1687 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1688 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1689 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1690 } 1691 } 1692 1693 /* the memory map is a bit tricky, it contains at least one hole 1694 * from 640k-1M and possibly another one from 3.5G-4G. 1695 */ 1696 next_base = 0; 1697 numa_mem_start = table_data->len; 1698 1699 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1700 mem_base = next_base; 1701 mem_len = numa_info[i - 1].node_mem; 1702 next_base = mem_base + mem_len; 1703 1704 /* Cut out the 640K hole */ 1705 if (mem_base <= HOLE_640K_START && 1706 next_base > HOLE_640K_START) { 1707 mem_len -= next_base - HOLE_640K_START; 1708 if (mem_len > 0) { 1709 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1710 MEM_AFFINITY_ENABLED); 1711 } 1712 1713 /* Check for the rare case: 640K < RAM < 1M */ 1714 if (next_base <= HOLE_640K_END) { 1715 next_base = HOLE_640K_END; 1716 continue; 1717 } 1718 mem_base = HOLE_640K_END; 1719 mem_len = next_base - HOLE_640K_END; 1720 } 1721 1722 /* Cut out the ACPI_PCI hole */ 1723 if (mem_base <= x86ms->below_4g_mem_size && 1724 next_base > x86ms->below_4g_mem_size) { 1725 mem_len -= next_base - x86ms->below_4g_mem_size; 1726 if (mem_len > 0) { 1727 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1728 MEM_AFFINITY_ENABLED); 1729 } 1730 mem_base = x86ms->above_4g_mem_start; 1731 mem_len = next_base - x86ms->below_4g_mem_size; 1732 next_base = mem_base + mem_len; 1733 } 1734 1735 if (mem_len > 0) { 1736 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1737 MEM_AFFINITY_ENABLED); 1738 } 1739 } 1740 1741 if (machine->nvdimms_state->is_enabled) { 1742 nvdimm_build_srat(table_data); 1743 } 1744 1745 sgx_epc_build_srat(table_data); 1746 1747 /* 1748 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1749 * without these entries. But I recall there were issues the last time I 1750 * tried to remove it with some ancient guest OS, however I can't remember 1751 * what that was so keep this around for now 1752 */ 1753 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1754 for (; slots < nb_numa_nodes + 2; slots++) { 1755 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1756 } 1757 1758 build_srat_generic_affinity_structures(table_data); 1759 1760 /* 1761 * Entry is required for Windows to enable memory hotplug in OS 1762 * and for Linux to enable SWIOTLB when booted with less than 1763 * 4G of RAM. Windows works better if the entry sets proximity 1764 * to the highest NUMA node in the machine. 1765 * Memory devices may override proximity set by this entry, 1766 * providing _PXM method if necessary. 1767 */ 1768 if (machine->device_memory) { 1769 build_srat_memory(table_data, machine->device_memory->base, 1770 memory_region_size(&machine->device_memory->mr), 1771 nb_numa_nodes - 1, 1772 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1773 } 1774 1775 acpi_table_end(linker, &table); 1776 } 1777 1778 /* 1779 * Insert DMAR scope for PCI bridges and endpoint devices 1780 */ 1781 static void 1782 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1783 { 1784 const size_t device_scope_size = 6 /* device scope structure */ + 1785 2 /* 1 path entry */; 1786 GArray *scope_blob = opaque; 1787 1788 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1789 /* Dmar Scope Type: 0x02 for PCI Bridge */ 1790 build_append_int_noprefix(scope_blob, 0x02, 1); 1791 } else { 1792 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 1793 build_append_int_noprefix(scope_blob, 0x01, 1); 1794 } 1795 1796 /* length */ 1797 build_append_int_noprefix(scope_blob, device_scope_size, 1); 1798 /* reserved */ 1799 build_append_int_noprefix(scope_blob, 0, 2); 1800 /* enumeration_id */ 1801 build_append_int_noprefix(scope_blob, 0, 1); 1802 /* bus */ 1803 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 1804 /* device */ 1805 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 1806 /* function */ 1807 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 1808 } 1809 1810 /* For a given PCI host bridge, walk and insert DMAR scope */ 1811 static int 1812 dmar_host_bridges(Object *obj, void *opaque) 1813 { 1814 GArray *scope_blob = opaque; 1815 1816 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1817 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 1818 1819 if (bus && !pci_bus_bypass_iommu(bus)) { 1820 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 1821 } 1822 } 1823 1824 return 0; 1825 } 1826 1827 /* 1828 * Intel ® Virtualization Technology for Directed I/O 1829 * Architecture Specification. Revision 3.3 1830 * 8.1 DMA Remapping Reporting Structure 1831 */ 1832 static void 1833 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1834 const char *oem_table_id) 1835 { 1836 uint8_t dmar_flags = 0; 1837 uint8_t rsvd10[10] = {}; 1838 /* Root complex IOAPIC uses one path only */ 1839 const size_t ioapic_scope_size = 6 /* device scope structure */ + 1840 2 /* 1 path entry */; 1841 X86IOMMUState *iommu = x86_iommu_get_default(); 1842 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1843 GArray *scope_blob = g_array_new(false, true, 1); 1844 1845 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 1846 .oem_table_id = oem_table_id }; 1847 1848 /* 1849 * A PCI bus walk, for each PCI host bridge. 1850 * Insert scope for each PCI bridge and endpoint device which 1851 * is attached to a bus with iommu enabled. 1852 */ 1853 object_child_foreach_recursive(object_get_root(), 1854 dmar_host_bridges, scope_blob); 1855 1856 assert(iommu); 1857 if (x86_iommu_ir_supported(iommu)) { 1858 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 1859 } 1860 1861 acpi_table_begin(&table, table_data); 1862 /* Host Address Width */ 1863 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 1864 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 1865 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 1866 1867 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 1868 build_append_int_noprefix(table_data, 0, 2); /* Type */ 1869 /* Length */ 1870 build_append_int_noprefix(table_data, 1871 16 + ioapic_scope_size + scope_blob->len, 2); 1872 /* Flags */ 1873 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 1874 1); 1875 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 1876 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 1877 /* Register Base Address */ 1878 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 1879 1880 /* Scope definition for the root-complex IOAPIC. See VT-d spec 1881 * 8.3.1 (version Oct. 2014 or later). */ 1882 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 1883 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 1884 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1885 /* Enumeration ID */ 1886 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 1887 /* Start Bus Number */ 1888 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 1889 /* Path, {Device, Function} pair */ 1890 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 1891 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 1892 1893 /* Add scope found above */ 1894 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 1895 g_array_free(scope_blob, true); 1896 1897 if (iommu->dt_supported) { 1898 /* 8.5 Root Port ATS Capability Reporting Structure */ 1899 build_append_int_noprefix(table_data, 2, 2); /* Type */ 1900 build_append_int_noprefix(table_data, 8, 2); /* Length */ 1901 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 1902 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 1903 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 1904 } 1905 1906 acpi_table_end(linker, &table); 1907 } 1908 1909 /* 1910 * Windows ACPI Emulated Devices Table 1911 * (Version 1.0 - April 6, 2009) 1912 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 1913 * 1914 * Helpful to speedup Windows guests and ignored by others. 1915 */ 1916 static void 1917 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1918 const char *oem_table_id) 1919 { 1920 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 1921 .oem_table_id = oem_table_id }; 1922 1923 acpi_table_begin(&table, table_data); 1924 /* 1925 * Set "ACPI PM timer good" flag. 1926 * 1927 * Tells Windows guests that our ACPI PM timer is reliable in the 1928 * sense that guest can read it only once to obtain a reliable value. 1929 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 1930 */ 1931 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 1932 acpi_table_end(linker, &table); 1933 } 1934 1935 /* 1936 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 1937 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 1938 */ 1939 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 1940 1941 /* 1942 * Insert IVHD entry for device and recurse, insert alias, or insert range as 1943 * necessary for the PCI topology. 1944 */ 1945 static void 1946 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 1947 { 1948 GArray *table_data = opaque; 1949 uint32_t entry; 1950 1951 /* "Select" IVHD entry, type 0x2 */ 1952 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 1953 build_append_int_noprefix(table_data, entry, 4); 1954 1955 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1956 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1957 uint8_t sec = pci_bus_num(sec_bus); 1958 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 1959 1960 if (pci_bus_is_express(sec_bus)) { 1961 /* 1962 * Walk the bus if there are subordinates, otherwise use a range 1963 * to cover an entire leaf bus. We could potentially also use a 1964 * range for traversed buses, but we'd need to take care not to 1965 * create both Select and Range entries covering the same device. 1966 * This is easier and potentially more compact. 1967 * 1968 * An example bare metal system seems to use Select entries for 1969 * root ports without a slot (ie. built-ins) and Range entries 1970 * when there is a slot. The same system also only hard-codes 1971 * the alias range for an onboard PCIe-to-PCI bridge, apparently 1972 * making no effort to support nested bridges. We attempt to 1973 * be more thorough here. 1974 */ 1975 if (sec == sub) { /* leaf bus */ 1976 /* "Start of Range" IVHD entry, type 0x3 */ 1977 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 1978 build_append_int_noprefix(table_data, entry, 4); 1979 /* "End of Range" IVHD entry, type 0x4 */ 1980 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 1981 build_append_int_noprefix(table_data, entry, 4); 1982 } else { 1983 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 1984 } 1985 } else { 1986 /* 1987 * If the secondary bus is conventional, then we need to create an 1988 * Alias range for everything downstream. The range covers the 1989 * first devfn on the secondary bus to the last devfn on the 1990 * subordinate bus. The alias target depends on legacy versus 1991 * express bridges, just as in pci_device_iommu_address_space(). 1992 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 1993 */ 1994 uint16_t dev_id_a, dev_id_b; 1995 1996 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 1997 1998 if (pci_is_express(dev) && 1999 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2000 dev_id_b = dev_id_a; 2001 } else { 2002 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2003 } 2004 2005 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2006 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2007 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2008 2009 /* "End of Range" IVHD entry, type 0x4 */ 2010 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2011 build_append_int_noprefix(table_data, entry, 4); 2012 } 2013 } 2014 } 2015 2016 /* For all PCI host bridges, walk and insert IVHD entries */ 2017 static int 2018 ivrs_host_bridges(Object *obj, void *opaque) 2019 { 2020 GArray *ivhd_blob = opaque; 2021 2022 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2023 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2024 2025 if (bus && !pci_bus_bypass_iommu(bus)) { 2026 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2027 } 2028 } 2029 2030 return 0; 2031 } 2032 2033 static void 2034 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2035 const char *oem_table_id) 2036 { 2037 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2038 GArray *ivhd_blob = g_array_new(false, true, 1); 2039 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2040 .oem_table_id = oem_table_id }; 2041 uint64_t feature_report; 2042 2043 acpi_table_begin(&table, table_data); 2044 /* IVinfo - IO virtualization information common to all 2045 * IOMMU units in a system 2046 */ 2047 build_append_int_noprefix(table_data, 2048 (1UL << 0) | /* EFRSup */ 2049 (40UL << 8), /* PASize */ 2050 4); 2051 /* reserved */ 2052 build_append_int_noprefix(table_data, 0, 8); 2053 2054 /* 2055 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2056 * complete set of IVHD entries. Do this into a separate blob so that we 2057 * can calculate the total IVRS table length here and then append the new 2058 * blob further below. Fall back to an entry covering all devices, which 2059 * is sufficient when no aliases are present. 2060 */ 2061 object_child_foreach_recursive(object_get_root(), 2062 ivrs_host_bridges, ivhd_blob); 2063 2064 if (!ivhd_blob->len) { 2065 /* 2066 * Type 1 device entry reporting all devices 2067 * These are 4-byte device entries currently reporting the range of 2068 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2069 */ 2070 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2071 } 2072 2073 /* 2074 * When interrupt remapping is supported, we add a special IVHD device 2075 * for type IO-APIC 2076 * Refer to spec - Table 95: IVHD device entry type codes 2077 * 2078 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2079 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2080 */ 2081 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2082 build_append_int_noprefix(ivhd_blob, 2083 (0x1ull << 56) | /* type IOAPIC */ 2084 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2085 0x48, /* special device */ 2086 8); 2087 } 2088 2089 /* IVHD definition - type 10h */ 2090 build_append_int_noprefix(table_data, 0x10, 1); 2091 /* virtualization flags */ 2092 build_append_int_noprefix(table_data, 2093 (1UL << 0) | /* HtTunEn */ 2094 (1UL << 4) | /* iotblSup */ 2095 (1UL << 6) | /* PrefSup */ 2096 (1UL << 7), /* PPRSup */ 2097 1); 2098 2099 /* IVHD length */ 2100 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); 2101 /* DeviceID */ 2102 build_append_int_noprefix(table_data, 2103 object_property_get_int(OBJECT(s->pci), "addr", 2104 &error_abort), 2); 2105 /* Capability offset */ 2106 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); 2107 /* IOMMU base address */ 2108 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 2109 /* PCI Segment Group */ 2110 build_append_int_noprefix(table_data, 0, 2); 2111 /* IOMMU info */ 2112 build_append_int_noprefix(table_data, 0, 2); 2113 /* IOMMU Feature Reporting */ 2114 feature_report = (48UL << 30) | /* HATS */ 2115 (48UL << 28) | /* GATS */ 2116 (1UL << 2) | /* GTSup */ 2117 (1UL << 6); /* GASup */ 2118 if (s->xtsup) { 2119 feature_report |= (1UL << 0); /* XTSup */ 2120 } 2121 build_append_int_noprefix(table_data, feature_report, 4); 2122 2123 /* IVHD entries as found above */ 2124 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2125 2126 /* IVHD definition - type 11h */ 2127 build_append_int_noprefix(table_data, 0x11, 1); 2128 /* virtualization flags */ 2129 build_append_int_noprefix(table_data, 2130 (1UL << 0) | /* HtTunEn */ 2131 (1UL << 4), /* iotblSup */ 2132 1); 2133 2134 /* IVHD length */ 2135 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); 2136 /* DeviceID */ 2137 build_append_int_noprefix(table_data, 2138 object_property_get_int(OBJECT(s->pci), "addr", 2139 &error_abort), 2); 2140 /* Capability offset */ 2141 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); 2142 /* IOMMU base address */ 2143 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 2144 /* PCI Segment Group */ 2145 build_append_int_noprefix(table_data, 0, 2); 2146 /* IOMMU info */ 2147 build_append_int_noprefix(table_data, 0, 2); 2148 /* IOMMU Attributes */ 2149 build_append_int_noprefix(table_data, 0, 4); 2150 /* EFR Register Image */ 2151 build_append_int_noprefix(table_data, 2152 amdvi_extended_feature_register(s), 2153 8); 2154 /* EFR Register Image 2 */ 2155 build_append_int_noprefix(table_data, 0, 8); 2156 2157 /* IVHD entries as found above */ 2158 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2159 2160 g_array_free(ivhd_blob, TRUE); 2161 acpi_table_end(linker, &table); 2162 } 2163 2164 typedef 2165 struct AcpiBuildState { 2166 /* Copy of table in RAM (for patching). */ 2167 MemoryRegion *table_mr; 2168 /* Is table patched? */ 2169 uint8_t patched; 2170 MemoryRegion *rsdp_mr; 2171 MemoryRegion *linker_mr; 2172 } AcpiBuildState; 2173 2174 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2175 { 2176 Object *pci_host; 2177 QObject *o; 2178 2179 pci_host = acpi_get_i386_pci_host(); 2180 if (!pci_host) { 2181 return false; 2182 } 2183 2184 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2185 if (!o) { 2186 return false; 2187 } 2188 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2189 qobject_unref(o); 2190 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2191 return false; 2192 } 2193 2194 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2195 assert(o); 2196 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2197 qobject_unref(o); 2198 return true; 2199 } 2200 2201 static 2202 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2203 { 2204 PCMachineState *pcms = PC_MACHINE(machine); 2205 X86MachineState *x86ms = X86_MACHINE(machine); 2206 DeviceState *iommu = pcms->iommu; 2207 GArray *table_offsets; 2208 unsigned facs, dsdt, rsdt; 2209 AcpiPmInfo pm; 2210 AcpiMiscInfo misc; 2211 AcpiMcfgInfo mcfg; 2212 Range pci_hole = {}, pci_hole64 = {}; 2213 uint8_t *u; 2214 GArray *tables_blob = tables->table_data; 2215 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2216 Object *vmgenid_dev, *vmclock_dev; 2217 char *oem_id; 2218 char *oem_table_id; 2219 2220 acpi_get_pm_info(machine, &pm); 2221 acpi_get_misc_info(&misc); 2222 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2223 acpi_get_slic_oem(&slic_oem); 2224 2225 if (slic_oem.id) { 2226 oem_id = slic_oem.id; 2227 } else { 2228 oem_id = x86ms->oem_id; 2229 } 2230 2231 if (slic_oem.table_id) { 2232 oem_table_id = slic_oem.table_id; 2233 } else { 2234 oem_table_id = x86ms->oem_table_id; 2235 } 2236 2237 table_offsets = g_array_new(false, true /* clear */, 2238 sizeof(uint32_t)); 2239 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2240 2241 bios_linker_loader_alloc(tables->linker, 2242 ACPI_BUILD_TABLE_FILE, tables_blob, 2243 64 /* Ensure FACS is aligned */, 2244 false /* high memory */); 2245 2246 /* 2247 * FACS is pointed to by FADT. 2248 * We place it first since it's the only table that has alignment 2249 * requirements. 2250 */ 2251 facs = tables_blob->len; 2252 build_facs(tables_blob); 2253 2254 /* DSDT is pointed to by FADT */ 2255 dsdt = tables_blob->len; 2256 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2257 &pci_hole, &pci_hole64, machine); 2258 2259 /* ACPI tables pointed to by RSDT */ 2260 acpi_add_table(table_offsets, tables_blob); 2261 pm.fadt.facs_tbl_offset = &facs; 2262 pm.fadt.dsdt_tbl_offset = &dsdt; 2263 pm.fadt.xdsdt_tbl_offset = &dsdt; 2264 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2265 2266 acpi_add_table(table_offsets, tables_blob); 2267 acpi_build_madt(tables_blob, tables->linker, x86ms, 2268 x86ms->oem_id, x86ms->oem_table_id); 2269 2270 #ifdef CONFIG_ACPI_ERST 2271 { 2272 Object *erst_dev; 2273 erst_dev = find_erst_dev(); 2274 if (erst_dev) { 2275 acpi_add_table(table_offsets, tables_blob); 2276 build_erst(tables_blob, tables->linker, erst_dev, 2277 x86ms->oem_id, x86ms->oem_table_id); 2278 } 2279 } 2280 #endif 2281 2282 vmgenid_dev = find_vmgenid_dev(); 2283 if (vmgenid_dev) { 2284 acpi_add_table(table_offsets, tables_blob); 2285 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2286 tables->vmgenid, tables->linker, x86ms->oem_id); 2287 } 2288 2289 vmclock_dev = find_vmclock_dev(); 2290 if (vmclock_dev) { 2291 acpi_add_table(table_offsets, tables_blob); 2292 vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker, 2293 x86ms->oem_id); 2294 } 2295 2296 if (misc.has_hpet) { 2297 acpi_add_table(table_offsets, tables_blob); 2298 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2299 x86ms->oem_table_id); 2300 } 2301 #ifdef CONFIG_TPM 2302 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2303 if (misc.tpm_version == TPM_VERSION_1_2) { 2304 acpi_add_table(table_offsets, tables_blob); 2305 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2306 x86ms->oem_id, x86ms->oem_table_id); 2307 } else { /* TPM_VERSION_2_0 */ 2308 acpi_add_table(table_offsets, tables_blob); 2309 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2310 x86ms->oem_id, x86ms->oem_table_id); 2311 } 2312 } 2313 #endif 2314 if (machine->numa_state->num_nodes) { 2315 acpi_add_table(table_offsets, tables_blob); 2316 build_srat(tables_blob, tables->linker, machine); 2317 if (machine->numa_state->have_numa_distance) { 2318 acpi_add_table(table_offsets, tables_blob); 2319 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2320 x86ms->oem_table_id); 2321 } 2322 if (machine->numa_state->hmat_enabled) { 2323 acpi_add_table(table_offsets, tables_blob); 2324 build_hmat(tables_blob, tables->linker, machine->numa_state, 2325 x86ms->oem_id, x86ms->oem_table_id); 2326 } 2327 } 2328 if (acpi_get_mcfg(&mcfg)) { 2329 acpi_add_table(table_offsets, tables_blob); 2330 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2331 x86ms->oem_table_id); 2332 } 2333 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2334 acpi_add_table(table_offsets, tables_blob); 2335 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2336 x86ms->oem_table_id); 2337 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2338 acpi_add_table(table_offsets, tables_blob); 2339 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2340 x86ms->oem_table_id); 2341 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2342 PCIDevice *pdev = PCI_DEVICE(iommu); 2343 2344 acpi_add_table(table_offsets, tables_blob); 2345 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2346 x86ms->oem_id, x86ms->oem_table_id); 2347 } 2348 if (machine->nvdimms_state->is_enabled) { 2349 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2350 machine->nvdimms_state, machine->ram_slots, 2351 x86ms->oem_id, x86ms->oem_table_id); 2352 } 2353 if (pcms->cxl_devices_state.is_enabled) { 2354 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2355 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2356 } 2357 2358 acpi_add_table(table_offsets, tables_blob); 2359 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2360 2361 /* Add tables supplied by user (if any) */ 2362 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2363 unsigned len = acpi_table_len(u); 2364 2365 acpi_add_table(table_offsets, tables_blob); 2366 g_array_append_vals(tables_blob, u, len); 2367 } 2368 2369 /* RSDT is pointed to by RSDP */ 2370 rsdt = tables_blob->len; 2371 build_rsdt(tables_blob, tables->linker, table_offsets, 2372 oem_id, oem_table_id); 2373 2374 /* RSDP is in FSEG memory, so allocate it separately */ 2375 { 2376 AcpiRsdpData rsdp_data = { 2377 .revision = 0, 2378 .oem_id = x86ms->oem_id, 2379 .xsdt_tbl_offset = NULL, 2380 .rsdt_tbl_offset = &rsdt, 2381 }; 2382 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2383 } 2384 2385 /* We'll expose it all to Guest so we want to reduce 2386 * chance of size changes. 2387 * 2388 * We used to align the tables to 4k, but of course this would 2389 * too simple to be enough. 4k turned out to be too small an 2390 * alignment very soon, and in fact it is almost impossible to 2391 * keep the table size stable for all (max_cpus, max_memory_slots) 2392 * combinations. 2393 */ 2394 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2395 2396 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2397 2398 /* Cleanup memory that's no longer used. */ 2399 g_array_free(table_offsets, true); 2400 g_free(slic_oem.id); 2401 g_free(slic_oem.table_id); 2402 } 2403 2404 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2405 { 2406 uint32_t size = acpi_data_len(data); 2407 2408 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2409 memory_region_ram_resize(mr, size, &error_abort); 2410 2411 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2412 memory_region_set_dirty(mr, 0, size); 2413 } 2414 2415 static void acpi_build_update(void *build_opaque) 2416 { 2417 AcpiBuildState *build_state = build_opaque; 2418 AcpiBuildTables tables; 2419 2420 /* No state to update or already patched? Nothing to do. */ 2421 if (!build_state || build_state->patched) { 2422 return; 2423 } 2424 build_state->patched = 1; 2425 2426 acpi_build_tables_init(&tables); 2427 2428 acpi_build(&tables, MACHINE(qdev_get_machine())); 2429 2430 acpi_ram_update(build_state->table_mr, tables.table_data); 2431 2432 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2433 2434 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2435 acpi_build_tables_cleanup(&tables, true); 2436 } 2437 2438 static void acpi_build_reset(void *build_opaque) 2439 { 2440 AcpiBuildState *build_state = build_opaque; 2441 build_state->patched = 0; 2442 } 2443 2444 static const VMStateDescription vmstate_acpi_build = { 2445 .name = "acpi_build", 2446 .version_id = 1, 2447 .minimum_version_id = 1, 2448 .fields = (const VMStateField[]) { 2449 VMSTATE_UINT8(patched, AcpiBuildState), 2450 VMSTATE_END_OF_LIST() 2451 }, 2452 }; 2453 2454 void acpi_setup(void) 2455 { 2456 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2457 X86MachineState *x86ms = X86_MACHINE(pcms); 2458 AcpiBuildTables tables; 2459 AcpiBuildState *build_state; 2460 Object *vmgenid_dev; 2461 #ifdef CONFIG_TPM 2462 TPMIf *tpm; 2463 static FwCfgTPMConfig tpm_config; 2464 #endif 2465 2466 if (!x86ms->fw_cfg) { 2467 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2468 return; 2469 } 2470 2471 if (!pcms->acpi_build_enabled) { 2472 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2473 return; 2474 } 2475 2476 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2477 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2478 return; 2479 } 2480 2481 build_state = g_malloc0(sizeof *build_state); 2482 2483 acpi_build_tables_init(&tables); 2484 acpi_build(&tables, MACHINE(pcms)); 2485 2486 /* Now expose it all to Guest */ 2487 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2488 build_state, tables.table_data, 2489 ACPI_BUILD_TABLE_FILE); 2490 assert(build_state->table_mr != NULL); 2491 2492 build_state->linker_mr = 2493 acpi_add_rom_blob(acpi_build_update, build_state, 2494 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2495 2496 #ifdef CONFIG_TPM 2497 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2498 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2499 2500 tpm = tpm_find(); 2501 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2502 tpm_config = (FwCfgTPMConfig) { 2503 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2504 .tpm_version = tpm_get_version(tpm), 2505 .tpmppi_version = TPM_PPI_VERSION_1_30 2506 }; 2507 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2508 &tpm_config, sizeof tpm_config); 2509 } 2510 #endif 2511 2512 vmgenid_dev = find_vmgenid_dev(); 2513 if (vmgenid_dev) { 2514 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2515 tables.vmgenid); 2516 } 2517 2518 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2519 build_state, tables.rsdp, 2520 ACPI_BUILD_RSDP_FILE); 2521 2522 qemu_register_reset(acpi_build_reset, build_state); 2523 acpi_build_reset(build_state); 2524 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2525 2526 /* Cleanup tables but don't free the memory: we track it 2527 * in build_state. 2528 */ 2529 acpi_build_tables_cleanup(&tables, false); 2530 } 2531