1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "qom/cpu.h" 32 #include "hw/i386/pc.h" 33 #include "target-i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "sysemu/tpm.h" 43 #include "hw/acpi/tpm.h" 44 #include "sysemu/tpm_backend.h" 45 46 /* Supported chipsets: */ 47 #include "hw/acpi/piix4.h" 48 #include "hw/acpi/pcihp.h" 49 #include "hw/i386/ich9.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/q35.h" 52 #include "hw/i386/intel_iommu.h" 53 54 #include "hw/i386/q35-acpi-dsdt.hex" 55 #include "hw/i386/acpi-dsdt.hex" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 64 * a little bit, there should be plenty of free space since the DSDT 65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 66 */ 67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 68 #define ACPI_BUILD_ALIGN_SIZE 0x1000 69 70 #define ACPI_BUILD_TABLE_SIZE 0x20000 71 72 /* #define DEBUG_ACPI_BUILD */ 73 #ifdef DEBUG_ACPI_BUILD 74 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 76 #else 77 #define ACPI_BUILD_DPRINTF(fmt, ...) 78 #endif 79 80 typedef struct AcpiCpuInfo { 81 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 82 } AcpiCpuInfo; 83 84 typedef struct AcpiMcfgInfo { 85 uint64_t mcfg_base; 86 uint32_t mcfg_size; 87 } AcpiMcfgInfo; 88 89 typedef struct AcpiPmInfo { 90 bool s3_disabled; 91 bool s4_disabled; 92 bool pcihp_bridge_en; 93 uint8_t s4_val; 94 uint16_t sci_int; 95 uint8_t acpi_enable_cmd; 96 uint8_t acpi_disable_cmd; 97 uint32_t gpe0_blk; 98 uint32_t gpe0_blk_len; 99 uint32_t io_base; 100 uint16_t cpu_hp_io_base; 101 uint16_t cpu_hp_io_len; 102 uint16_t mem_hp_io_base; 103 uint16_t mem_hp_io_len; 104 uint16_t pcihp_io_base; 105 uint16_t pcihp_io_len; 106 } AcpiPmInfo; 107 108 typedef struct AcpiMiscInfo { 109 bool has_hpet; 110 TPMVersion tpm_version; 111 const unsigned char *dsdt_code; 112 unsigned dsdt_size; 113 uint16_t pvpanic_port; 114 uint16_t applesmc_io_base; 115 } AcpiMiscInfo; 116 117 typedef struct AcpiBuildPciBusHotplugState { 118 GArray *device_table; 119 GArray *notify_table; 120 struct AcpiBuildPciBusHotplugState *parent; 121 bool pcihp_bridge_en; 122 } AcpiBuildPciBusHotplugState; 123 124 static void acpi_get_dsdt(AcpiMiscInfo *info) 125 { 126 Object *piix = piix4_pm_find(); 127 Object *lpc = ich9_lpc_find(); 128 assert(!!piix != !!lpc); 129 130 if (piix) { 131 info->dsdt_code = AcpiDsdtAmlCode; 132 info->dsdt_size = sizeof AcpiDsdtAmlCode; 133 } 134 if (lpc) { 135 info->dsdt_code = Q35AcpiDsdtAmlCode; 136 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 137 } 138 } 139 140 static 141 int acpi_add_cpu_info(Object *o, void *opaque) 142 { 143 AcpiCpuInfo *cpu = opaque; 144 uint64_t apic_id; 145 146 if (object_dynamic_cast(o, TYPE_CPU)) { 147 apic_id = object_property_get_int(o, "apic-id", NULL); 148 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 149 150 set_bit(apic_id, cpu->found_cpus); 151 } 152 153 object_child_foreach(o, acpi_add_cpu_info, opaque); 154 return 0; 155 } 156 157 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 158 { 159 Object *root = object_get_root(); 160 161 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 162 object_child_foreach(root, acpi_add_cpu_info, cpu); 163 } 164 165 static void acpi_get_pm_info(AcpiPmInfo *pm) 166 { 167 Object *piix = piix4_pm_find(); 168 Object *lpc = ich9_lpc_find(); 169 Object *obj = NULL; 170 QObject *o; 171 172 pm->pcihp_io_base = 0; 173 pm->pcihp_io_len = 0; 174 if (piix) { 175 obj = piix; 176 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 177 pm->pcihp_io_base = 178 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 179 pm->pcihp_io_len = 180 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 181 } 182 if (lpc) { 183 obj = lpc; 184 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 185 } 186 assert(obj); 187 188 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 189 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 190 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 191 192 /* Fill in optional s3/s4 related properties */ 193 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 194 if (o) { 195 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 196 } else { 197 pm->s3_disabled = false; 198 } 199 qobject_decref(o); 200 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 201 if (o) { 202 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 203 } else { 204 pm->s4_disabled = false; 205 } 206 qobject_decref(o); 207 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 208 if (o) { 209 pm->s4_val = qint_get_int(qobject_to_qint(o)); 210 } else { 211 pm->s4_val = false; 212 } 213 qobject_decref(o); 214 215 /* Fill in mandatory properties */ 216 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 217 218 pm->acpi_enable_cmd = object_property_get_int(obj, 219 ACPI_PM_PROP_ACPI_ENABLE_CMD, 220 NULL); 221 pm->acpi_disable_cmd = object_property_get_int(obj, 222 ACPI_PM_PROP_ACPI_DISABLE_CMD, 223 NULL); 224 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 225 NULL); 226 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 227 NULL); 228 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 229 NULL); 230 pm->pcihp_bridge_en = 231 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 232 NULL); 233 } 234 235 static void acpi_get_misc_info(AcpiMiscInfo *info) 236 { 237 info->has_hpet = hpet_find(); 238 info->tpm_version = tpm_get_version(); 239 info->pvpanic_port = pvpanic_port(); 240 info->applesmc_io_base = applesmc_port(); 241 } 242 243 static void acpi_get_pci_info(PcPciInfo *info) 244 { 245 Object *pci_host; 246 bool ambiguous; 247 248 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 249 g_assert(!ambiguous); 250 g_assert(pci_host); 251 252 info->w32.begin = object_property_get_int(pci_host, 253 PCI_HOST_PROP_PCI_HOLE_START, 254 NULL); 255 info->w32.end = object_property_get_int(pci_host, 256 PCI_HOST_PROP_PCI_HOLE_END, 257 NULL); 258 info->w64.begin = object_property_get_int(pci_host, 259 PCI_HOST_PROP_PCI_HOLE64_START, 260 NULL); 261 info->w64.end = object_property_get_int(pci_host, 262 PCI_HOST_PROP_PCI_HOLE64_END, 263 NULL); 264 } 265 266 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 267 268 static void acpi_align_size(GArray *blob, unsigned align) 269 { 270 /* Align size to multiple of given size. This reduces the chance 271 * we need to change size in the future (breaking cross version migration). 272 */ 273 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 274 } 275 276 /* FACS */ 277 static void 278 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 279 { 280 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 281 memcpy(&facs->signature, "FACS", 4); 282 facs->length = cpu_to_le32(sizeof(*facs)); 283 } 284 285 /* Load chipset information in FADT */ 286 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 287 { 288 fadt->model = 1; 289 fadt->reserved1 = 0; 290 fadt->sci_int = cpu_to_le16(pm->sci_int); 291 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 292 fadt->acpi_enable = pm->acpi_enable_cmd; 293 fadt->acpi_disable = pm->acpi_disable_cmd; 294 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 295 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 296 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 297 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 298 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 299 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 300 fadt->pm1_evt_len = 4; 301 fadt->pm1_cnt_len = 2; 302 fadt->pm_tmr_len = 4; 303 fadt->gpe0_blk_len = pm->gpe0_blk_len; 304 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 305 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 306 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 307 (1 << ACPI_FADT_F_PROC_C1) | 308 (1 << ACPI_FADT_F_SLP_BUTTON) | 309 (1 << ACPI_FADT_F_RTC_S4)); 310 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 311 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 312 * For more than 8 CPUs, "Clustered Logical" mode has to be used 313 */ 314 if (max_cpus > 8) { 315 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 316 } 317 } 318 319 320 /* FADT */ 321 static void 322 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 323 unsigned facs, unsigned dsdt) 324 { 325 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 326 327 fadt->firmware_ctrl = cpu_to_le32(facs); 328 /* FACS address to be filled by Guest linker */ 329 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 330 ACPI_BUILD_TABLE_FILE, 331 table_data, &fadt->firmware_ctrl, 332 sizeof fadt->firmware_ctrl); 333 334 fadt->dsdt = cpu_to_le32(dsdt); 335 /* DSDT address to be filled by Guest linker */ 336 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 337 ACPI_BUILD_TABLE_FILE, 338 table_data, &fadt->dsdt, 339 sizeof fadt->dsdt); 340 341 fadt_setup(fadt, pm); 342 343 build_header(linker, table_data, 344 (void *)fadt, "FACP", sizeof(*fadt), 1); 345 } 346 347 static void 348 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 349 PcGuestInfo *guest_info) 350 { 351 int madt_start = table_data->len; 352 353 AcpiMultipleApicTable *madt; 354 AcpiMadtIoApic *io_apic; 355 AcpiMadtIntsrcovr *intsrcovr; 356 AcpiMadtLocalNmi *local_nmi; 357 int i; 358 359 madt = acpi_data_push(table_data, sizeof *madt); 360 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 361 madt->flags = cpu_to_le32(1); 362 363 for (i = 0; i < guest_info->apic_id_limit; i++) { 364 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 365 apic->type = ACPI_APIC_PROCESSOR; 366 apic->length = sizeof(*apic); 367 apic->processor_id = i; 368 apic->local_apic_id = i; 369 if (test_bit(i, cpu->found_cpus)) { 370 apic->flags = cpu_to_le32(1); 371 } else { 372 apic->flags = cpu_to_le32(0); 373 } 374 } 375 io_apic = acpi_data_push(table_data, sizeof *io_apic); 376 io_apic->type = ACPI_APIC_IO; 377 io_apic->length = sizeof(*io_apic); 378 #define ACPI_BUILD_IOAPIC_ID 0x0 379 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 380 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 381 io_apic->interrupt = cpu_to_le32(0); 382 383 if (guest_info->apic_xrupt_override) { 384 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 385 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 386 intsrcovr->length = sizeof(*intsrcovr); 387 intsrcovr->source = 0; 388 intsrcovr->gsi = cpu_to_le32(2); 389 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 390 } 391 for (i = 1; i < 16; i++) { 392 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 393 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 394 /* No need for a INT source override structure. */ 395 continue; 396 } 397 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 398 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 399 intsrcovr->length = sizeof(*intsrcovr); 400 intsrcovr->source = i; 401 intsrcovr->gsi = cpu_to_le32(i); 402 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 403 } 404 405 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 406 local_nmi->type = ACPI_APIC_LOCAL_NMI; 407 local_nmi->length = sizeof(*local_nmi); 408 local_nmi->processor_id = 0xff; /* all processors */ 409 local_nmi->flags = cpu_to_le16(0); 410 local_nmi->lint = 1; /* ACPI_LINT1 */ 411 412 build_header(linker, table_data, 413 (void *)(table_data->data + madt_start), "APIC", 414 table_data->len - madt_start, 1); 415 } 416 417 #include "hw/i386/ssdt-tpm.hex" 418 #include "hw/i386/ssdt-tpm2.hex" 419 420 /* Assign BSEL property to all buses. In the future, this can be changed 421 * to only assign to buses that support hotplug. 422 */ 423 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 424 { 425 unsigned *bsel_alloc = opaque; 426 unsigned *bus_bsel; 427 428 if (qbus_is_hotpluggable(BUS(bus))) { 429 bus_bsel = g_malloc(sizeof *bus_bsel); 430 431 *bus_bsel = (*bsel_alloc)++; 432 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 433 bus_bsel, NULL); 434 } 435 436 return bsel_alloc; 437 } 438 439 static void acpi_set_pci_info(void) 440 { 441 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 442 unsigned bsel_alloc = 0; 443 444 if (bus) { 445 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 446 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 447 } 448 } 449 450 static void build_append_pcihp_notify_entry(Aml *method, int slot) 451 { 452 Aml *if_ctx; 453 int32_t devfn = PCI_DEVFN(slot, 0); 454 455 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); 456 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 457 aml_append(method, if_ctx); 458 } 459 460 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 461 bool pcihp_bridge_en) 462 { 463 Aml *dev, *notify_method, *method; 464 QObject *bsel; 465 PCIBus *sec; 466 int i; 467 468 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 469 if (bsel) { 470 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 471 472 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 473 notify_method = aml_method("DVNT", 2); 474 } 475 476 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 477 DeviceClass *dc; 478 PCIDeviceClass *pc; 479 PCIDevice *pdev = bus->devices[i]; 480 int slot = PCI_SLOT(i); 481 bool hotplug_enabled_dev; 482 bool bridge_in_acpi; 483 484 if (!pdev) { 485 if (bsel) { /* add hotplug slots for non present devices */ 486 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 487 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 488 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 489 method = aml_method("_EJ0", 1); 490 aml_append(method, 491 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 492 ); 493 aml_append(dev, method); 494 aml_append(parent_scope, dev); 495 496 build_append_pcihp_notify_entry(notify_method, slot); 497 } 498 continue; 499 } 500 501 pc = PCI_DEVICE_GET_CLASS(pdev); 502 dc = DEVICE_GET_CLASS(pdev); 503 504 /* When hotplug for bridges is enabled, bridges are 505 * described in ACPI separately (see build_pci_bus_end). 506 * In this case they aren't themselves hot-pluggable. 507 * Hotplugged bridges *are* hot-pluggable. 508 */ 509 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 510 !DEVICE(pdev)->hotplugged; 511 512 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 513 514 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 515 continue; 516 } 517 518 /* start to compose PCI slot descriptor */ 519 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 520 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 521 522 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 523 /* add VGA specific AML methods */ 524 int s3d; 525 526 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 527 s3d = 3; 528 } else { 529 s3d = 0; 530 } 531 532 method = aml_method("_S1D", 0); 533 aml_append(method, aml_return(aml_int(0))); 534 aml_append(dev, method); 535 536 method = aml_method("_S2D", 0); 537 aml_append(method, aml_return(aml_int(0))); 538 aml_append(dev, method); 539 540 method = aml_method("_S3D", 0); 541 aml_append(method, aml_return(aml_int(s3d))); 542 aml_append(dev, method); 543 } else if (hotplug_enabled_dev) { 544 /* add _SUN/_EJ0 to make slot hotpluggable */ 545 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 546 547 method = aml_method("_EJ0", 1); 548 aml_append(method, 549 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 550 ); 551 aml_append(dev, method); 552 553 if (bsel) { 554 build_append_pcihp_notify_entry(notify_method, slot); 555 } 556 } else if (bridge_in_acpi) { 557 /* 558 * device is coldplugged bridge, 559 * add child device descriptions into its scope 560 */ 561 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 562 563 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 564 } 565 /* slot descriptor has been composed, add it into parent context */ 566 aml_append(parent_scope, dev); 567 } 568 569 if (bsel) { 570 aml_append(parent_scope, notify_method); 571 } 572 573 /* Append PCNT method to notify about events on local and child buses. 574 * Add unconditionally for root since DSDT expects it. 575 */ 576 method = aml_method("PCNT", 0); 577 578 /* If bus supports hotplug select it and notify about local events */ 579 if (bsel) { 580 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 581 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 582 aml_append(method, 583 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 584 ); 585 aml_append(method, 586 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 587 ); 588 } 589 590 /* Notify about child bus events in any case */ 591 if (pcihp_bridge_en) { 592 QLIST_FOREACH(sec, &bus->child, sibling) { 593 int32_t devfn = sec->parent_dev->devfn; 594 595 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 596 } 597 } 598 aml_append(parent_scope, method); 599 } 600 601 static void 602 build_ssdt(GArray *table_data, GArray *linker, 603 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 604 PcPciInfo *pci, PcGuestInfo *guest_info) 605 { 606 MachineState *machine = MACHINE(qdev_get_machine()); 607 uint32_t nr_mem = machine->ram_slots; 608 unsigned acpi_cpus = guest_info->apic_id_limit; 609 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 610 int i; 611 612 ssdt = init_aml_allocator(); 613 /* The current AML generator can cover the APIC ID range [0..255], 614 * inclusive, for VCPU hotplug. */ 615 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 616 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 617 618 /* Reserve space for header */ 619 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 620 621 scope = aml_scope("\\_SB.PCI0"); 622 /* build PCI0._CRS */ 623 crs = aml_resource_template(); 624 aml_append(crs, 625 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 626 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); 627 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 628 629 aml_append(crs, 630 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 631 AML_POS_DECODE, AML_ENTIRE_RANGE, 632 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 633 aml_append(crs, 634 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 635 AML_POS_DECODE, AML_ENTIRE_RANGE, 636 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 637 aml_append(crs, 638 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 639 AML_CACHEABLE, AML_READ_WRITE, 640 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 641 aml_append(crs, 642 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 643 AML_NON_CACHEABLE, AML_READ_WRITE, 644 0, pci->w32.begin, pci->w32.end - 1, 0, 645 pci->w32.end - pci->w32.begin)); 646 if (pci->w64.begin) { 647 aml_append(crs, 648 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 649 AML_CACHEABLE, AML_READ_WRITE, 650 0, pci->w64.begin, pci->w64.end - 1, 0, 651 pci->w64.end - pci->w64.begin)); 652 } 653 aml_append(scope, aml_name_decl("_CRS", crs)); 654 655 /* reserve GPE0 block resources */ 656 dev = aml_device("GPE0"); 657 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 658 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 659 /* device present, functioning, decoding, not shown in UI */ 660 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 661 crs = aml_resource_template(); 662 aml_append(crs, 663 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 664 ); 665 aml_append(dev, aml_name_decl("_CRS", crs)); 666 aml_append(scope, dev); 667 668 /* reserve PCIHP resources */ 669 if (pm->pcihp_io_len) { 670 dev = aml_device("PHPR"); 671 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 672 aml_append(dev, 673 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 674 /* device present, functioning, decoding, not shown in UI */ 675 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 676 crs = aml_resource_template(); 677 aml_append(crs, 678 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 679 pm->pcihp_io_len) 680 ); 681 aml_append(dev, aml_name_decl("_CRS", crs)); 682 aml_append(scope, dev); 683 } 684 aml_append(ssdt, scope); 685 686 /* create S3_ / S4_ / S5_ packages if necessary */ 687 scope = aml_scope("\\"); 688 if (!pm->s3_disabled) { 689 pkg = aml_package(4); 690 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 691 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 692 aml_append(pkg, aml_int(0)); /* reserved */ 693 aml_append(pkg, aml_int(0)); /* reserved */ 694 aml_append(scope, aml_name_decl("_S3", pkg)); 695 } 696 697 if (!pm->s4_disabled) { 698 pkg = aml_package(4); 699 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 700 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 701 aml_append(pkg, aml_int(pm->s4_val)); 702 aml_append(pkg, aml_int(0)); /* reserved */ 703 aml_append(pkg, aml_int(0)); /* reserved */ 704 aml_append(scope, aml_name_decl("_S4", pkg)); 705 } 706 707 pkg = aml_package(4); 708 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 709 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 710 aml_append(pkg, aml_int(0)); /* reserved */ 711 aml_append(pkg, aml_int(0)); /* reserved */ 712 aml_append(scope, aml_name_decl("_S5", pkg)); 713 aml_append(ssdt, scope); 714 715 if (misc->applesmc_io_base) { 716 scope = aml_scope("\\_SB.PCI0.ISA"); 717 dev = aml_device("SMC"); 718 719 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 720 /* device present, functioning, decoding, not shown in UI */ 721 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 722 723 crs = aml_resource_template(); 724 aml_append(crs, 725 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 726 0x01, APPLESMC_MAX_DATA_LENGTH) 727 ); 728 aml_append(crs, aml_irq_no_flags(6)); 729 aml_append(dev, aml_name_decl("_CRS", crs)); 730 731 aml_append(scope, dev); 732 aml_append(ssdt, scope); 733 } 734 735 if (misc->pvpanic_port) { 736 scope = aml_scope("\\_SB.PCI0.ISA"); 737 738 dev = aml_device("PEVT"); 739 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 740 741 crs = aml_resource_template(); 742 aml_append(crs, 743 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 744 ); 745 aml_append(dev, aml_name_decl("_CRS", crs)); 746 747 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 748 misc->pvpanic_port, 1)); 749 field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); 750 aml_append(field, aml_named_field("PEPT", 8)); 751 aml_append(dev, field); 752 753 /* device present, functioning, decoding, not shown in UI */ 754 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 755 756 method = aml_method("RDPT", 0); 757 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 758 aml_append(method, aml_return(aml_local(0))); 759 aml_append(dev, method); 760 761 method = aml_method("WRPT", 1); 762 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 763 aml_append(dev, method); 764 765 aml_append(scope, dev); 766 aml_append(ssdt, scope); 767 } 768 769 sb_scope = aml_scope("\\_SB"); 770 { 771 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 772 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 773 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 774 aml_append(dev, 775 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 776 ); 777 /* device present, functioning, decoding, not shown in UI */ 778 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 779 crs = aml_resource_template(); 780 aml_append(crs, 781 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 782 pm->cpu_hp_io_len) 783 ); 784 aml_append(dev, aml_name_decl("_CRS", crs)); 785 aml_append(sb_scope, dev); 786 /* declare CPU hotplug MMIO region and PRS field to access it */ 787 aml_append(sb_scope, aml_operation_region( 788 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 789 field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); 790 aml_append(field, aml_named_field("PRS", 256)); 791 aml_append(sb_scope, field); 792 793 /* build Processor object for each processor */ 794 for (i = 0; i < acpi_cpus; i++) { 795 dev = aml_processor(i, 0, 0, "CP%.02X", i); 796 797 method = aml_method("_MAT", 0); 798 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 799 aml_append(dev, method); 800 801 method = aml_method("_STA", 0); 802 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 803 aml_append(dev, method); 804 805 method = aml_method("_EJ0", 1); 806 aml_append(method, 807 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 808 ); 809 aml_append(dev, method); 810 811 aml_append(sb_scope, dev); 812 } 813 814 /* build this code: 815 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 816 */ 817 /* Arg0 = Processor ID = APIC ID */ 818 method = aml_method("NTFY", 2); 819 for (i = 0; i < acpi_cpus; i++) { 820 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 821 aml_append(ifctx, 822 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 823 ); 824 aml_append(method, ifctx); 825 } 826 aml_append(sb_scope, method); 827 828 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 829 * 830 * Note: The ability to create variable-sized packages was first 831 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 832 * ith up to 255 elements. Windows guests up to win2k8 fail when 833 * VarPackageOp is used. 834 */ 835 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 836 aml_varpackage(acpi_cpus); 837 838 for (i = 0; i < acpi_cpus; i++) { 839 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 840 aml_append(pkg, aml_int(b)); 841 } 842 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 843 844 /* build memory devices */ 845 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 846 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 847 aml_append(scope, 848 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 849 ); 850 851 crs = aml_resource_template(); 852 aml_append(crs, 853 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 854 pm->mem_hp_io_len) 855 ); 856 aml_append(scope, aml_name_decl("_CRS", crs)); 857 858 aml_append(scope, aml_operation_region( 859 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, 860 pm->mem_hp_io_base, pm->mem_hp_io_len) 861 ); 862 863 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 864 AML_PRESERVE); 865 aml_append(field, /* read only */ 866 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 867 aml_append(field, /* read only */ 868 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 869 aml_append(field, /* read only */ 870 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 871 aml_append(field, /* read only */ 872 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 873 aml_append(field, /* read only */ 874 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 875 aml_append(scope, field); 876 877 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, 878 AML_WRITE_AS_ZEROS); 879 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 880 aml_append(field, /* 1 if enabled, read only */ 881 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 882 aml_append(field, 883 /*(read) 1 if has a insert event. (write) 1 to clear event */ 884 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 885 aml_append(field, 886 /* (read) 1 if has a remove event. (write) 1 to clear event */ 887 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); 888 aml_append(field, 889 /* initiates device eject, write only */ 890 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); 891 aml_append(scope, field); 892 893 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 894 AML_PRESERVE); 895 aml_append(field, /* DIMM selector, write only */ 896 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 897 aml_append(field, /* _OST event code, write only */ 898 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 899 aml_append(field, /* _OST status code, write only */ 900 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 901 aml_append(scope, field); 902 903 aml_append(sb_scope, scope); 904 905 for (i = 0; i < nr_mem; i++) { 906 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 907 const char *s; 908 909 dev = aml_device("MP%02X", i); 910 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 911 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 912 913 method = aml_method("_CRS", 0); 914 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 915 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 916 aml_append(dev, method); 917 918 method = aml_method("_STA", 0); 919 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 920 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 921 aml_append(dev, method); 922 923 method = aml_method("_PXM", 0); 924 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 925 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 926 aml_append(dev, method); 927 928 method = aml_method("_OST", 3); 929 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 930 aml_append(method, aml_return(aml_call4( 931 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 932 ))); 933 aml_append(dev, method); 934 935 method = aml_method("_EJ0", 1); 936 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); 937 aml_append(method, aml_return(aml_call2( 938 s, aml_name("_UID"), aml_arg(0)))); 939 aml_append(dev, method); 940 941 aml_append(sb_scope, dev); 942 } 943 944 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 945 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 946 */ 947 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); 948 for (i = 0; i < nr_mem; i++) { 949 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 950 aml_append(ifctx, 951 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 952 ); 953 aml_append(method, ifctx); 954 } 955 aml_append(sb_scope, method); 956 957 { 958 Object *pci_host; 959 PCIBus *bus = NULL; 960 bool ambiguous; 961 962 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 963 if (!ambiguous && pci_host) { 964 bus = PCI_HOST_BRIDGE(pci_host)->bus; 965 } 966 967 if (bus) { 968 Aml *scope = aml_scope("PCI0"); 969 /* Scan all PCI buses. Generate tables to support hotplug. */ 970 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 971 aml_append(sb_scope, scope); 972 } 973 } 974 aml_append(ssdt, sb_scope); 975 } 976 977 /* copy AML table into ACPI tables blob and patch header there */ 978 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 979 build_header(linker, table_data, 980 (void *)(table_data->data + table_data->len - ssdt->buf->len), 981 "SSDT", ssdt->buf->len, 1); 982 free_aml_allocator(); 983 } 984 985 static void 986 build_hpet(GArray *table_data, GArray *linker) 987 { 988 Acpi20Hpet *hpet; 989 990 hpet = acpi_data_push(table_data, sizeof(*hpet)); 991 /* Note timer_block_id value must be kept in sync with value advertised by 992 * emulated hpet 993 */ 994 hpet->timer_block_id = cpu_to_le32(0x8086a201); 995 hpet->addr.address = cpu_to_le64(HPET_BASE); 996 build_header(linker, table_data, 997 (void *)hpet, "HPET", sizeof(*hpet), 1); 998 } 999 1000 static void 1001 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 1002 { 1003 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1004 uint64_t log_area_start_address = acpi_data_len(tcpalog); 1005 1006 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1007 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1008 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 1009 1010 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 1011 false /* high memory */); 1012 1013 /* log area start address to be filled by Guest linker */ 1014 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1015 ACPI_BUILD_TPMLOG_FILE, 1016 table_data, &tcpa->log_area_start_address, 1017 sizeof(tcpa->log_area_start_address)); 1018 1019 build_header(linker, table_data, 1020 (void *)tcpa, "TCPA", sizeof(*tcpa), 2); 1021 1022 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1023 } 1024 1025 static void 1026 build_tpm_ssdt(GArray *table_data, GArray *linker) 1027 { 1028 void *tpm_ptr; 1029 1030 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); 1031 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); 1032 } 1033 1034 static void 1035 build_tpm2(GArray *table_data, GArray *linker) 1036 { 1037 Acpi20TPM2 *tpm2_ptr; 1038 void *tpm_ptr; 1039 1040 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm2_aml)); 1041 memcpy(tpm_ptr, ssdt_tpm2_aml, sizeof(ssdt_tpm2_aml)); 1042 1043 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 1044 1045 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 1046 tpm2_ptr->control_area_address = cpu_to_le64(0); 1047 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 1048 1049 build_header(linker, table_data, 1050 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4); 1051 } 1052 1053 typedef enum { 1054 MEM_AFFINITY_NOFLAGS = 0, 1055 MEM_AFFINITY_ENABLED = (1 << 0), 1056 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1057 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1058 } MemoryAffinityFlags; 1059 1060 static void 1061 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1062 uint64_t len, int node, MemoryAffinityFlags flags) 1063 { 1064 numamem->type = ACPI_SRAT_MEMORY; 1065 numamem->length = sizeof(*numamem); 1066 memset(numamem->proximity, 0, 4); 1067 numamem->proximity[0] = node; 1068 numamem->flags = cpu_to_le32(flags); 1069 numamem->base_addr = cpu_to_le64(base); 1070 numamem->range_length = cpu_to_le64(len); 1071 } 1072 1073 static void 1074 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1075 { 1076 AcpiSystemResourceAffinityTable *srat; 1077 AcpiSratProcessorAffinity *core; 1078 AcpiSratMemoryAffinity *numamem; 1079 1080 int i; 1081 uint64_t curnode; 1082 int srat_start, numa_start, slots; 1083 uint64_t mem_len, mem_base, next_base; 1084 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1085 ram_addr_t hotplugabble_address_space_size = 1086 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1087 NULL); 1088 1089 srat_start = table_data->len; 1090 1091 srat = acpi_data_push(table_data, sizeof *srat); 1092 srat->reserved1 = cpu_to_le32(1); 1093 core = (void *)(srat + 1); 1094 1095 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1096 core = acpi_data_push(table_data, sizeof *core); 1097 core->type = ACPI_SRAT_PROCESSOR; 1098 core->length = sizeof(*core); 1099 core->local_apic_id = i; 1100 curnode = guest_info->node_cpu[i]; 1101 core->proximity_lo = curnode; 1102 memset(core->proximity_hi, 0, 3); 1103 core->local_sapic_eid = 0; 1104 core->flags = cpu_to_le32(1); 1105 } 1106 1107 1108 /* the memory map is a bit tricky, it contains at least one hole 1109 * from 640k-1M and possibly another one from 3.5G-4G. 1110 */ 1111 next_base = 0; 1112 numa_start = table_data->len; 1113 1114 numamem = acpi_data_push(table_data, sizeof *numamem); 1115 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1116 next_base = 1024 * 1024; 1117 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1118 mem_base = next_base; 1119 mem_len = guest_info->node_mem[i - 1]; 1120 if (i == 1) { 1121 mem_len -= 1024 * 1024; 1122 } 1123 next_base = mem_base + mem_len; 1124 1125 /* Cut out the ACPI_PCI hole */ 1126 if (mem_base <= guest_info->ram_size_below_4g && 1127 next_base > guest_info->ram_size_below_4g) { 1128 mem_len -= next_base - guest_info->ram_size_below_4g; 1129 if (mem_len > 0) { 1130 numamem = acpi_data_push(table_data, sizeof *numamem); 1131 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1132 MEM_AFFINITY_ENABLED); 1133 } 1134 mem_base = 1ULL << 32; 1135 mem_len = next_base - guest_info->ram_size_below_4g; 1136 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1137 } 1138 numamem = acpi_data_push(table_data, sizeof *numamem); 1139 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1140 MEM_AFFINITY_ENABLED); 1141 } 1142 slots = (table_data->len - numa_start) / sizeof *numamem; 1143 for (; slots < guest_info->numa_nodes + 2; slots++) { 1144 numamem = acpi_data_push(table_data, sizeof *numamem); 1145 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1146 } 1147 1148 /* 1149 * Entry is required for Windows to enable memory hotplug in OS. 1150 * Memory devices may override proximity set by this entry, 1151 * providing _PXM method if necessary. 1152 */ 1153 if (hotplugabble_address_space_size) { 1154 numamem = acpi_data_push(table_data, sizeof *numamem); 1155 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, 1156 hotplugabble_address_space_size, 0, 1157 MEM_AFFINITY_HOTPLUGGABLE | 1158 MEM_AFFINITY_ENABLED); 1159 } 1160 1161 build_header(linker, table_data, 1162 (void *)(table_data->data + srat_start), 1163 "SRAT", 1164 table_data->len - srat_start, 1); 1165 } 1166 1167 static void 1168 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1169 { 1170 AcpiTableMcfg *mcfg; 1171 const char *sig; 1172 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1173 1174 mcfg = acpi_data_push(table_data, len); 1175 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1176 /* Only a single allocation so no need to play with segments */ 1177 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1178 mcfg->allocation[0].start_bus_number = 0; 1179 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1180 1181 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1182 * To avoid table size changes (which create migration issues), 1183 * always create the table even if there are no allocations, 1184 * but set the signature to a reserved value in this case. 1185 * ACPI spec requires OSPMs to ignore such tables. 1186 */ 1187 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1188 /* Reserved signature: ignored by OSPM */ 1189 sig = "QEMU"; 1190 } else { 1191 sig = "MCFG"; 1192 } 1193 build_header(linker, table_data, (void *)mcfg, sig, len, 1); 1194 } 1195 1196 static void 1197 build_dmar_q35(GArray *table_data, GArray *linker) 1198 { 1199 int dmar_start = table_data->len; 1200 1201 AcpiTableDmar *dmar; 1202 AcpiDmarHardwareUnit *drhd; 1203 1204 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1205 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1206 dmar->flags = 0; /* No intr_remap for now */ 1207 1208 /* DMAR Remapping Hardware Unit Definition structure */ 1209 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1210 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1211 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1212 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1213 drhd->pci_segment = cpu_to_le16(0); 1214 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1215 1216 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1217 "DMAR", table_data->len - dmar_start, 1); 1218 } 1219 1220 static void 1221 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1222 { 1223 AcpiTableHeader *dsdt; 1224 1225 assert(misc->dsdt_code && misc->dsdt_size); 1226 1227 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1228 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1229 1230 memset(dsdt, 0, sizeof *dsdt); 1231 build_header(linker, table_data, dsdt, "DSDT", 1232 misc->dsdt_size, 1); 1233 } 1234 1235 static GArray * 1236 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1237 { 1238 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1239 1240 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1241 true /* fseg memory */); 1242 1243 memcpy(&rsdp->signature, "RSD PTR ", 8); 1244 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1245 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1246 /* Address to be filled by Guest linker */ 1247 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1248 ACPI_BUILD_TABLE_FILE, 1249 rsdp_table, &rsdp->rsdt_physical_address, 1250 sizeof rsdp->rsdt_physical_address); 1251 rsdp->checksum = 0; 1252 /* Checksum to be filled by Guest linker */ 1253 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1254 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1255 1256 return rsdp_table; 1257 } 1258 1259 typedef 1260 struct AcpiBuildState { 1261 /* Copy of table in RAM (for patching). */ 1262 MemoryRegion *table_mr; 1263 /* Is table patched? */ 1264 uint8_t patched; 1265 PcGuestInfo *guest_info; 1266 void *rsdp; 1267 MemoryRegion *rsdp_mr; 1268 MemoryRegion *linker_mr; 1269 } AcpiBuildState; 1270 1271 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1272 { 1273 Object *pci_host; 1274 QObject *o; 1275 bool ambiguous; 1276 1277 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1278 g_assert(!ambiguous); 1279 g_assert(pci_host); 1280 1281 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1282 if (!o) { 1283 return false; 1284 } 1285 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1286 qobject_decref(o); 1287 1288 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1289 assert(o); 1290 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1291 qobject_decref(o); 1292 return true; 1293 } 1294 1295 static bool acpi_has_iommu(void) 1296 { 1297 bool ambiguous; 1298 Object *intel_iommu; 1299 1300 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1301 &ambiguous); 1302 return intel_iommu && !ambiguous; 1303 } 1304 1305 static 1306 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1307 { 1308 GArray *table_offsets; 1309 unsigned facs, ssdt, dsdt, rsdt; 1310 AcpiCpuInfo cpu; 1311 AcpiPmInfo pm; 1312 AcpiMiscInfo misc; 1313 AcpiMcfgInfo mcfg; 1314 PcPciInfo pci; 1315 uint8_t *u; 1316 size_t aml_len = 0; 1317 GArray *tables_blob = tables->table_data; 1318 1319 acpi_get_cpu_info(&cpu); 1320 acpi_get_pm_info(&pm); 1321 acpi_get_dsdt(&misc); 1322 acpi_get_misc_info(&misc); 1323 acpi_get_pci_info(&pci); 1324 1325 table_offsets = g_array_new(false, true /* clear */, 1326 sizeof(uint32_t)); 1327 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1328 1329 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1330 64 /* Ensure FACS is aligned */, 1331 false /* high memory */); 1332 1333 /* 1334 * FACS is pointed to by FADT. 1335 * We place it first since it's the only table that has alignment 1336 * requirements. 1337 */ 1338 facs = tables_blob->len; 1339 build_facs(tables_blob, tables->linker, guest_info); 1340 1341 /* DSDT is pointed to by FADT */ 1342 dsdt = tables_blob->len; 1343 build_dsdt(tables_blob, tables->linker, &misc); 1344 1345 /* Count the size of the DSDT and SSDT, we will need it for legacy 1346 * sizing of ACPI tables. 1347 */ 1348 aml_len += tables_blob->len - dsdt; 1349 1350 /* ACPI tables pointed to by RSDT */ 1351 acpi_add_table(table_offsets, tables_blob); 1352 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1353 1354 ssdt = tables_blob->len; 1355 acpi_add_table(table_offsets, tables_blob); 1356 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1357 guest_info); 1358 aml_len += tables_blob->len - ssdt; 1359 1360 acpi_add_table(table_offsets, tables_blob); 1361 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1362 1363 if (misc.has_hpet) { 1364 acpi_add_table(table_offsets, tables_blob); 1365 build_hpet(tables_blob, tables->linker); 1366 } 1367 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 1368 acpi_add_table(table_offsets, tables_blob); 1369 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1370 1371 acpi_add_table(table_offsets, tables_blob); 1372 switch (misc.tpm_version) { 1373 case TPM_VERSION_1_2: 1374 build_tpm_ssdt(tables_blob, tables->linker); 1375 break; 1376 case TPM_VERSION_2_0: 1377 build_tpm2(tables_blob, tables->linker); 1378 break; 1379 default: 1380 assert(false); 1381 } 1382 } 1383 if (guest_info->numa_nodes) { 1384 acpi_add_table(table_offsets, tables_blob); 1385 build_srat(tables_blob, tables->linker, guest_info); 1386 } 1387 if (acpi_get_mcfg(&mcfg)) { 1388 acpi_add_table(table_offsets, tables_blob); 1389 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1390 } 1391 if (acpi_has_iommu()) { 1392 acpi_add_table(table_offsets, tables_blob); 1393 build_dmar_q35(tables_blob, tables->linker); 1394 } 1395 1396 /* Add tables supplied by user (if any) */ 1397 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1398 unsigned len = acpi_table_len(u); 1399 1400 acpi_add_table(table_offsets, tables_blob); 1401 g_array_append_vals(tables_blob, u, len); 1402 } 1403 1404 /* RSDT is pointed to by RSDP */ 1405 rsdt = tables_blob->len; 1406 build_rsdt(tables_blob, tables->linker, table_offsets); 1407 1408 /* RSDP is in FSEG memory, so allocate it separately */ 1409 build_rsdp(tables->rsdp, tables->linker, rsdt); 1410 1411 /* We'll expose it all to Guest so we want to reduce 1412 * chance of size changes. 1413 * 1414 * We used to align the tables to 4k, but of course this would 1415 * too simple to be enough. 4k turned out to be too small an 1416 * alignment very soon, and in fact it is almost impossible to 1417 * keep the table size stable for all (max_cpus, max_memory_slots) 1418 * combinations. So the table size is always 64k for pc-i440fx-2.1 1419 * and we give an error if the table grows beyond that limit. 1420 * 1421 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1422 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1423 * than 2.0 and we can always pad the smaller tables with zeros. We can 1424 * then use the exact size of the 2.0 tables. 1425 * 1426 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1427 */ 1428 if (guest_info->legacy_acpi_table_size) { 1429 /* Subtracting aml_len gives the size of fixed tables. Then add the 1430 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1431 */ 1432 int legacy_aml_len = 1433 guest_info->legacy_acpi_table_size + 1434 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1435 int legacy_table_size = 1436 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1437 ACPI_BUILD_ALIGN_SIZE); 1438 if (tables_blob->len > legacy_table_size) { 1439 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1440 error_report("Warning: migration may not work."); 1441 } 1442 g_array_set_size(tables_blob, legacy_table_size); 1443 } else { 1444 /* Make sure we have a buffer in case we need to resize the tables. */ 1445 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1446 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1447 error_report("Warning: ACPI tables are larger than 64k."); 1448 error_report("Warning: migration may not work."); 1449 error_report("Warning: please remove CPUs, NUMA nodes, " 1450 "memory slots or PCI bridges."); 1451 } 1452 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1453 } 1454 1455 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1456 1457 /* Cleanup memory that's no longer used. */ 1458 g_array_free(table_offsets, true); 1459 } 1460 1461 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1462 { 1463 uint32_t size = acpi_data_len(data); 1464 1465 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1466 memory_region_ram_resize(mr, size, &error_abort); 1467 1468 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1469 memory_region_set_dirty(mr, 0, size); 1470 } 1471 1472 static void acpi_build_update(void *build_opaque, uint32_t offset) 1473 { 1474 AcpiBuildState *build_state = build_opaque; 1475 AcpiBuildTables tables; 1476 1477 /* No state to update or already patched? Nothing to do. */ 1478 if (!build_state || build_state->patched) { 1479 return; 1480 } 1481 build_state->patched = 1; 1482 1483 acpi_build_tables_init(&tables); 1484 1485 acpi_build(build_state->guest_info, &tables); 1486 1487 acpi_ram_update(build_state->table_mr, tables.table_data); 1488 1489 if (build_state->rsdp) { 1490 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1491 } else { 1492 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1493 } 1494 1495 acpi_ram_update(build_state->linker_mr, tables.linker); 1496 acpi_build_tables_cleanup(&tables, true); 1497 } 1498 1499 static void acpi_build_reset(void *build_opaque) 1500 { 1501 AcpiBuildState *build_state = build_opaque; 1502 build_state->patched = 0; 1503 } 1504 1505 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 1506 GArray *blob, const char *name, 1507 uint64_t max_size) 1508 { 1509 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1510 name, acpi_build_update, build_state); 1511 } 1512 1513 static const VMStateDescription vmstate_acpi_build = { 1514 .name = "acpi_build", 1515 .version_id = 1, 1516 .minimum_version_id = 1, 1517 .fields = (VMStateField[]) { 1518 VMSTATE_UINT8(patched, AcpiBuildState), 1519 VMSTATE_END_OF_LIST() 1520 }, 1521 }; 1522 1523 void acpi_setup(PcGuestInfo *guest_info) 1524 { 1525 AcpiBuildTables tables; 1526 AcpiBuildState *build_state; 1527 1528 if (!guest_info->fw_cfg) { 1529 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1530 return; 1531 } 1532 1533 if (!guest_info->has_acpi_build) { 1534 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1535 return; 1536 } 1537 1538 if (!acpi_enabled) { 1539 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1540 return; 1541 } 1542 1543 build_state = g_malloc0(sizeof *build_state); 1544 1545 build_state->guest_info = guest_info; 1546 1547 acpi_set_pci_info(); 1548 1549 acpi_build_tables_init(&tables); 1550 acpi_build(build_state->guest_info, &tables); 1551 1552 /* Now expose it all to Guest */ 1553 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 1554 ACPI_BUILD_TABLE_FILE, 1555 ACPI_BUILD_TABLE_MAX_SIZE); 1556 assert(build_state->table_mr != NULL); 1557 1558 build_state->linker_mr = 1559 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1560 1561 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1562 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1563 1564 if (!guest_info->rsdp_in_ram) { 1565 /* 1566 * Keep for compatibility with old machine types. 1567 * Though RSDP is small, its contents isn't immutable, so 1568 * we'll update it along with the rest of tables on guest access. 1569 */ 1570 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1571 1572 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1573 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1574 acpi_build_update, build_state, 1575 build_state->rsdp, rsdp_size); 1576 build_state->rsdp_mr = NULL; 1577 } else { 1578 build_state->rsdp = NULL; 1579 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 1580 ACPI_BUILD_RSDP_FILE, 0); 1581 } 1582 1583 qemu_register_reset(acpi_build_reset, build_state); 1584 acpi_build_reset(build_state); 1585 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1586 1587 /* Cleanup tables but don't free the memory: we track it 1588 * in build_state. 1589 */ 1590 acpi_build_tables_cleanup(&tables, false); 1591 } 1592