1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/piix.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/ich9.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 #include "hw/acpi/cxl.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool has_hpet; 117 #ifdef CONFIG_TPM 118 TPMVersion tpm_version; 119 #endif 120 } AcpiMiscInfo; 121 122 typedef struct FwCfgTPMConfig { 123 uint32_t tpmppi_address; 124 uint8_t tpm_version; 125 uint8_t tpmppi_version; 126 } QEMU_PACKED FwCfgTPMConfig; 127 128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 129 130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 131 .space_id = AML_AS_SYSTEM_IO, 132 .address = NVDIMM_ACPI_IO_BASE, 133 .bit_width = NVDIMM_ACPI_IO_LEN << 3 134 }; 135 136 static void init_common_fadt_data(MachineState *ms, Object *o, 137 AcpiFadtData *data) 138 { 139 X86MachineState *x86ms = X86_MACHINE(ms); 140 /* 141 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 142 * behavior for compatibility irrelevant to smm_enabled, which doesn't 143 * comforms to ACPI spec. 144 */ 145 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 146 true : x86_machine_is_smm_enabled(x86ms); 147 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 148 AmlAddressSpace as = AML_AS_SYSTEM_IO; 149 AcpiFadtData fadt = { 150 .rev = 3, 151 .flags = 152 (1 << ACPI_FADT_F_WBINVD) | 153 (1 << ACPI_FADT_F_PROC_C1) | 154 (1 << ACPI_FADT_F_SLP_BUTTON) | 155 (1 << ACPI_FADT_F_RTC_S4) | 156 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 157 /* APIC destination mode ("Flat Logical") has an upper limit of 8 158 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 159 * used 160 */ 161 ((ms->smp.max_cpus > 8) ? 162 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 163 .int_model = 1 /* Multiple APIC */, 164 .rtc_century = RTC_CENTURY, 165 .plvl2_lat = 0xfff /* C2 state not supported */, 166 .plvl3_lat = 0xfff /* C3 state not supported */, 167 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 168 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 169 .acpi_enable_cmd = 170 smm_enabled ? 171 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 172 0, 173 .acpi_disable_cmd = 174 smm_enabled ? 175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 176 0, 177 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 178 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 179 .address = io + 0x04 }, 180 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 181 .gpe0_blk = { .space_id = as, .bit_width = 182 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 183 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 184 }, 185 }; 186 187 /* 188 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 189 * Flags, bit offset 1 - 8042. 190 */ 191 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 192 193 *data = fadt; 194 } 195 196 static Object *object_resolve_type_unambiguous(const char *typename) 197 { 198 bool ambig; 199 Object *o = object_resolve_path_type("", typename, &ambig); 200 201 if (ambig || !o) { 202 return NULL; 203 } 204 return o; 205 } 206 207 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 208 { 209 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 210 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 211 Object *obj = piix ? piix : lpc; 212 QObject *o; 213 pm->cpu_hp_io_base = 0; 214 pm->pcihp_io_base = 0; 215 pm->pcihp_io_len = 0; 216 pm->smi_on_cpuhp = false; 217 pm->smi_on_cpu_unplug = false; 218 219 assert(obj); 220 init_common_fadt_data(machine, obj, &pm->fadt); 221 if (piix) { 222 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 223 pm->fadt.rev = 1; 224 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 225 } 226 if (lpc) { 227 uint64_t smi_features = object_property_get_uint(lpc, 228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 231 pm->fadt.reset_reg = r; 232 pm->fadt.reset_val = 0xf; 233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 235 pm->smi_on_cpuhp = 236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 237 pm->smi_on_cpu_unplug = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 239 } 240 pm->pcihp_io_base = 241 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 242 pm->pcihp_io_len = 243 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 244 245 /* The above need not be conditional on machine type because the reset port 246 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 247 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 248 249 /* Fill in optional s3/s4 related properties */ 250 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 251 if (o) { 252 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 253 } else { 254 pm->s3_disabled = false; 255 } 256 qobject_unref(o); 257 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 258 if (o) { 259 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 260 } else { 261 pm->s4_disabled = false; 262 } 263 qobject_unref(o); 264 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 265 if (o) { 266 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 267 } else { 268 pm->s4_val = false; 269 } 270 qobject_unref(o); 271 272 pm->pcihp_bridge_en = 273 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 274 NULL); 275 pm->pcihp_root_en = 276 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 277 NULL); 278 } 279 280 static void acpi_get_misc_info(AcpiMiscInfo *info) 281 { 282 info->has_hpet = hpet_find(); 283 #ifdef CONFIG_TPM 284 info->tpm_version = tpm_get_version(tpm_find()); 285 #endif 286 } 287 288 /* 289 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 290 * On i386 arch we only have two pci hosts, so we can look only for them. 291 */ 292 Object *acpi_get_i386_pci_host(void) 293 { 294 PCIHostState *host; 295 296 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 297 if (!host) { 298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 299 } 300 301 return OBJECT(host); 302 } 303 304 static void acpi_get_pci_holes(Range *hole, Range *hole64) 305 { 306 Object *pci_host; 307 308 pci_host = acpi_get_i386_pci_host(); 309 310 if (!pci_host) { 311 return; 312 } 313 314 range_set_bounds1(hole, 315 object_property_get_uint(pci_host, 316 PCI_HOST_PROP_PCI_HOLE_START, 317 NULL), 318 object_property_get_uint(pci_host, 319 PCI_HOST_PROP_PCI_HOLE_END, 320 NULL)); 321 range_set_bounds1(hole64, 322 object_property_get_uint(pci_host, 323 PCI_HOST_PROP_PCI_HOLE64_START, 324 NULL), 325 object_property_get_uint(pci_host, 326 PCI_HOST_PROP_PCI_HOLE64_END, 327 NULL)); 328 } 329 330 static void acpi_align_size(GArray *blob, unsigned align) 331 { 332 /* Align size to multiple of given size. This reduces the chance 333 * we need to change size in the future (breaking cross version migration). 334 */ 335 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 336 } 337 338 /* 339 * ACPI spec 1.0b, 340 * 5.2.6 Firmware ACPI Control Structure 341 */ 342 static void 343 build_facs(GArray *table_data) 344 { 345 const char *sig = "FACS"; 346 const uint8_t reserved[40] = {}; 347 348 g_array_append_vals(table_data, sig, 4); /* Signature */ 349 build_append_int_noprefix(table_data, 64, 4); /* Length */ 350 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 351 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 352 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 353 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 354 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 355 } 356 357 Aml *aml_pci_device_dsm(void) 358 { 359 Aml *method; 360 361 method = aml_method("_DSM", 4, AML_SERIALIZED); 362 { 363 Aml *params = aml_local(0); 364 Aml *pkg = aml_package(2); 365 aml_append(pkg, aml_name("BSEL")); 366 aml_append(pkg, aml_name("ASUN")); 367 aml_append(method, aml_store(pkg, params)); 368 aml_append(method, 369 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 370 aml_arg(2), aml_arg(3), params)) 371 ); 372 } 373 return method; 374 } 375 376 static void build_append_pcihp_notify_entry(Aml *method, int slot) 377 { 378 Aml *if_ctx; 379 int32_t devfn = PCI_DEVFN(slot, 0); 380 381 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 382 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 383 aml_append(method, if_ctx); 384 } 385 386 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 387 bool pcihp_bridge_en) 388 { 389 Aml *dev, *notify_method = NULL, *method; 390 QObject *bsel; 391 PCIBus *sec; 392 int devfn; 393 394 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 395 if (bsel) { 396 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 397 398 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 399 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 400 } 401 402 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 403 DeviceClass *dc; 404 PCIDevice *pdev = bus->devices[devfn]; 405 int slot = PCI_SLOT(devfn); 406 int func = PCI_FUNC(devfn); 407 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 408 int adr = slot << 16 | func; 409 bool hotpluggbale_slot = false; 410 bool bridge_in_acpi = false; 411 bool cold_plugged_bridge = false; 412 413 if (pdev) { 414 dc = DEVICE_GET_CLASS(pdev); 415 416 /* 417 * Cold plugged bridges aren't themselves hot-pluggable. 418 * Hotplugged bridges *are* hot-pluggable. 419 */ 420 cold_plugged_bridge = IS_PCI_BRIDGE(pdev) && 421 !DEVICE(pdev)->hotplugged; 422 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 423 424 hotpluggbale_slot = bsel && dc->hotpluggable && 425 !cold_plugged_bridge; 426 427 /* 428 * allow describing coldplugged bridges in ACPI even if they are not 429 * on function 0, as they are not unpluggable, for all other devices 430 * generate description only for function 0 per slot, and for other 431 * functions if device on function provides its own AML 432 */ 433 if (func && !bridge_in_acpi && !get_dev_aml_func(DEVICE(pdev))) { 434 continue; 435 } 436 } else { 437 /* 438 * hotplug is supported only for non-multifunction device 439 * so generate device description only for function 0 440 */ 441 if (bsel && !func) { 442 if (pci_bus_is_express(bus) && slot > 0) { 443 break; 444 } 445 /* mark it as empty hotpluggable slot */ 446 hotpluggbale_slot = true; 447 } else { 448 continue; 449 } 450 } 451 452 /* start to compose PCI device descriptor */ 453 dev = aml_device("S%.02X", devfn); 454 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 455 456 if (bsel) { 457 /* 458 * Can't declare _SUN here for every device as it changes 'slot' 459 * enumeration order in linux kernel, so use another variable for it 460 */ 461 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 462 aml_append(dev, aml_pci_device_dsm()); 463 } 464 465 call_dev_aml_func(DEVICE(pdev), dev); 466 467 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 468 if (bridge_in_acpi) { 469 /* 470 * device is coldplugged bridge, 471 * add child device descriptions into its scope 472 */ 473 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 474 475 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 476 } 477 478 if (hotpluggbale_slot) { 479 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 480 /* add _EJ0 to make slot hotpluggable */ 481 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 482 aml_append(method, 483 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 484 ); 485 aml_append(dev, method); 486 487 build_append_pcihp_notify_entry(notify_method, slot); 488 } 489 490 /* device descriptor has been composed, add it into parent context */ 491 aml_append(parent_scope, dev); 492 } 493 494 if (bsel) { 495 aml_append(parent_scope, notify_method); 496 } 497 498 /* Append PCNT method to notify about events on local and child buses. 499 * Add this method for root bus only when hotplug is enabled since DSDT 500 * expects it. 501 */ 502 if (bsel || pcihp_bridge_en) { 503 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 504 505 /* If bus supports hotplug select it and notify about local events */ 506 if (bsel) { 507 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 508 509 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 510 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 511 aml_int(1))); /* Device Check */ 512 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 513 aml_int(3))); /* Eject Request */ 514 } 515 516 /* Notify about child bus events in any case */ 517 if (pcihp_bridge_en) { 518 QLIST_FOREACH(sec, &bus->child, sibling) { 519 if (pci_bus_is_root(sec)) { 520 continue; 521 } 522 523 aml_append(method, aml_name("^S%.02X.PCNT", 524 sec->parent_dev->devfn)); 525 } 526 } 527 528 aml_append(parent_scope, method); 529 } 530 qobject_unref(bsel); 531 } 532 533 static Aml *aml_pci_pdsm(void) 534 { 535 Aml *method, *UUID, *ifctx, *ifctx1; 536 Aml *ret = aml_local(0); 537 Aml *caps = aml_local(1); 538 Aml *acpi_index = aml_local(2); 539 Aml *zero = aml_int(0); 540 Aml *one = aml_int(1); 541 Aml *func = aml_arg(2); 542 Aml *rev = aml_arg(1); 543 Aml *params = aml_arg(4); 544 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 545 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 546 547 method = aml_method("PDSM", 5, AML_SERIALIZED); 548 549 /* get supported functions */ 550 ifctx = aml_if(aml_equal(func, zero)); 551 { 552 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 553 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); 554 aml_append(ifctx, aml_store(zero, caps)); 555 556 /* 557 * PCI Firmware Specification 3.1 558 * 4.6. _DSM Definitions for PCI 559 */ 560 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 561 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 562 { 563 /* call is for unsupported UUID, bail out */ 564 aml_append(ifctx1, aml_return(ret)); 565 } 566 aml_append(ifctx, ifctx1); 567 568 ifctx1 = aml_if(aml_lless(rev, aml_int(2))); 569 { 570 /* call is for unsupported REV, bail out */ 571 aml_append(ifctx1, aml_return(ret)); 572 } 573 aml_append(ifctx, ifctx1); 574 575 aml_append(ifctx, 576 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 577 /* 578 * advertise function 7 if device has acpi-index 579 * acpi_index values: 580 * 0: not present (default value) 581 * FFFFFFFF: not supported (old QEMU without PIDX reg) 582 * other: device's acpi-index 583 */ 584 ifctx1 = aml_if(aml_lnot( 585 aml_or(aml_equal(acpi_index, zero), 586 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 587 )); 588 { 589 /* have supported functions */ 590 aml_append(ifctx1, aml_or(caps, one, caps)); 591 /* support for function 7 */ 592 aml_append(ifctx1, 593 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 594 } 595 aml_append(ifctx, ifctx1); 596 597 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 598 aml_append(ifctx, aml_return(ret)); 599 } 600 aml_append(method, ifctx); 601 602 /* handle specific functions requests */ 603 /* 604 * PCI Firmware Specification 3.1 605 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 606 * Operating Systems 607 */ 608 ifctx = aml_if(aml_equal(func, aml_int(7))); 609 { 610 Aml *pkg = aml_package(2); 611 612 aml_append(pkg, zero); 613 /* 614 * optional, if not impl. should return null string 615 */ 616 aml_append(pkg, aml_string("%s", "")); 617 aml_append(ifctx, aml_store(pkg, ret)); 618 619 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 620 /* 621 * update acpi-index to actual value 622 */ 623 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 624 aml_append(ifctx, aml_return(ret)); 625 } 626 627 aml_append(method, ifctx); 628 return method; 629 } 630 631 /** 632 * build_prt_entry: 633 * @link_name: link name for PCI route entry 634 * 635 * build AML package containing a PCI route entry for @link_name 636 */ 637 static Aml *build_prt_entry(const char *link_name) 638 { 639 Aml *a_zero = aml_int(0); 640 Aml *pkg = aml_package(4); 641 aml_append(pkg, a_zero); 642 aml_append(pkg, a_zero); 643 aml_append(pkg, aml_name("%s", link_name)); 644 aml_append(pkg, a_zero); 645 return pkg; 646 } 647 648 /* 649 * initialize_route - Initialize the interrupt routing rule 650 * through a specific LINK: 651 * if (lnk_idx == idx) 652 * route using link 'link_name' 653 */ 654 static Aml *initialize_route(Aml *route, const char *link_name, 655 Aml *lnk_idx, int idx) 656 { 657 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 658 Aml *pkg = build_prt_entry(link_name); 659 660 aml_append(if_ctx, aml_store(pkg, route)); 661 662 return if_ctx; 663 } 664 665 /* 666 * build_prt - Define interrupt rounting rules 667 * 668 * Returns an array of 128 routes, one for each device, 669 * based on device location. 670 * The main goal is to equaly distribute the interrupts 671 * over the 4 existing ACPI links (works only for i440fx). 672 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 673 * 674 */ 675 static Aml *build_prt(bool is_pci0_prt) 676 { 677 Aml *method, *while_ctx, *pin, *res; 678 679 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 680 res = aml_local(0); 681 pin = aml_local(1); 682 aml_append(method, aml_store(aml_package(128), res)); 683 aml_append(method, aml_store(aml_int(0), pin)); 684 685 /* while (pin < 128) */ 686 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 687 { 688 Aml *slot = aml_local(2); 689 Aml *lnk_idx = aml_local(3); 690 Aml *route = aml_local(4); 691 692 /* slot = pin >> 2 */ 693 aml_append(while_ctx, 694 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 695 /* lnk_idx = (slot + pin) & 3 */ 696 aml_append(while_ctx, 697 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 698 lnk_idx)); 699 700 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 701 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 702 if (is_pci0_prt) { 703 Aml *if_device_1, *if_pin_4, *else_pin_4; 704 705 /* device 1 is the power-management device, needs SCI */ 706 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 707 { 708 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 709 { 710 aml_append(if_pin_4, 711 aml_store(build_prt_entry("LNKS"), route)); 712 } 713 aml_append(if_device_1, if_pin_4); 714 else_pin_4 = aml_else(); 715 { 716 aml_append(else_pin_4, 717 aml_store(build_prt_entry("LNKA"), route)); 718 } 719 aml_append(if_device_1, else_pin_4); 720 } 721 aml_append(while_ctx, if_device_1); 722 } else { 723 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 724 } 725 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 726 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 727 728 /* route[0] = 0x[slot]FFFF */ 729 aml_append(while_ctx, 730 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 731 NULL), 732 aml_index(route, aml_int(0)))); 733 /* route[1] = pin & 3 */ 734 aml_append(while_ctx, 735 aml_store(aml_and(pin, aml_int(3), NULL), 736 aml_index(route, aml_int(1)))); 737 /* res[pin] = route */ 738 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 739 /* pin++ */ 740 aml_append(while_ctx, aml_increment(pin)); 741 } 742 aml_append(method, while_ctx); 743 /* return res*/ 744 aml_append(method, aml_return(res)); 745 746 return method; 747 } 748 749 static void build_hpet_aml(Aml *table) 750 { 751 Aml *crs; 752 Aml *field; 753 Aml *method; 754 Aml *if_ctx; 755 Aml *scope = aml_scope("_SB"); 756 Aml *dev = aml_device("HPET"); 757 Aml *zero = aml_int(0); 758 Aml *id = aml_local(0); 759 Aml *period = aml_local(1); 760 761 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 762 aml_append(dev, aml_name_decl("_UID", zero)); 763 764 aml_append(dev, 765 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 766 HPET_LEN)); 767 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 768 aml_append(field, aml_named_field("VEND", 32)); 769 aml_append(field, aml_named_field("PRD", 32)); 770 aml_append(dev, field); 771 772 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 773 aml_append(method, aml_store(aml_name("VEND"), id)); 774 aml_append(method, aml_store(aml_name("PRD"), period)); 775 aml_append(method, aml_shiftright(id, aml_int(16), id)); 776 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 777 aml_equal(id, aml_int(0xffff)))); 778 { 779 aml_append(if_ctx, aml_return(zero)); 780 } 781 aml_append(method, if_ctx); 782 783 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 784 aml_lgreater(period, aml_int(100000000)))); 785 { 786 aml_append(if_ctx, aml_return(zero)); 787 } 788 aml_append(method, if_ctx); 789 790 aml_append(method, aml_return(aml_int(0x0F))); 791 aml_append(dev, method); 792 793 crs = aml_resource_template(); 794 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 795 aml_append(dev, aml_name_decl("_CRS", crs)); 796 797 aml_append(scope, dev); 798 aml_append(table, scope); 799 } 800 801 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 802 { 803 Aml *dev; 804 Aml *method; 805 Aml *crs; 806 807 dev = aml_device("VMBS"); 808 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 809 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 810 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 811 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 812 813 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 814 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 815 aml_name("STA"))); 816 aml_append(dev, method); 817 818 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 819 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 820 aml_name("STA"))); 821 aml_append(dev, method); 822 823 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 824 aml_append(method, aml_return(aml_name("STA"))); 825 aml_append(dev, method); 826 827 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 828 829 crs = aml_resource_template(); 830 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 831 aml_append(dev, aml_name_decl("_CRS", crs)); 832 833 return dev; 834 } 835 836 static void build_dbg_aml(Aml *table) 837 { 838 Aml *field; 839 Aml *method; 840 Aml *while_ctx; 841 Aml *scope = aml_scope("\\"); 842 Aml *buf = aml_local(0); 843 Aml *len = aml_local(1); 844 Aml *idx = aml_local(2); 845 846 aml_append(scope, 847 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 848 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 849 aml_append(field, aml_named_field("DBGB", 8)); 850 aml_append(scope, field); 851 852 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 853 854 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 855 aml_append(method, aml_to_buffer(buf, buf)); 856 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 857 aml_append(method, aml_store(aml_int(0), idx)); 858 859 while_ctx = aml_while(aml_lless(idx, len)); 860 aml_append(while_ctx, 861 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 862 aml_append(while_ctx, aml_increment(idx)); 863 aml_append(method, while_ctx); 864 865 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 866 aml_append(scope, method); 867 868 aml_append(table, scope); 869 } 870 871 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 872 { 873 Aml *dev; 874 Aml *crs; 875 Aml *method; 876 uint32_t irqs[] = {5, 10, 11}; 877 878 dev = aml_device("%s", name); 879 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 880 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 881 882 crs = aml_resource_template(); 883 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 884 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 885 aml_append(dev, aml_name_decl("_PRS", crs)); 886 887 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 888 aml_append(method, aml_return(aml_call1("IQST", reg))); 889 aml_append(dev, method); 890 891 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 892 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 893 aml_append(dev, method); 894 895 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 896 aml_append(method, aml_return(aml_call1("IQCR", reg))); 897 aml_append(dev, method); 898 899 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 900 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 901 aml_append(method, aml_store(aml_name("PRRI"), reg)); 902 aml_append(dev, method); 903 904 return dev; 905 } 906 907 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 908 { 909 Aml *dev; 910 Aml *crs; 911 Aml *method; 912 uint32_t irqs; 913 914 dev = aml_device("%s", name); 915 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 916 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 917 918 crs = aml_resource_template(); 919 irqs = gsi; 920 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 921 AML_SHARED, &irqs, 1)); 922 aml_append(dev, aml_name_decl("_PRS", crs)); 923 924 aml_append(dev, aml_name_decl("_CRS", crs)); 925 926 /* 927 * _DIS can be no-op because the interrupt cannot be disabled. 928 */ 929 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 930 aml_append(dev, method); 931 932 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 933 aml_append(dev, method); 934 935 return dev; 936 } 937 938 /* _CRS method - get current settings */ 939 static Aml *build_iqcr_method(bool is_piix4) 940 { 941 Aml *if_ctx; 942 uint32_t irqs; 943 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 944 Aml *crs = aml_resource_template(); 945 946 irqs = 0; 947 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 948 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 949 aml_append(method, aml_name_decl("PRR0", crs)); 950 951 aml_append(method, 952 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 953 954 if (is_piix4) { 955 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 956 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 957 aml_append(method, if_ctx); 958 } else { 959 aml_append(method, 960 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 961 aml_name("PRRI"))); 962 } 963 964 aml_append(method, aml_return(aml_name("PRR0"))); 965 return method; 966 } 967 968 /* _STA method - get status */ 969 static Aml *build_irq_status_method(void) 970 { 971 Aml *if_ctx; 972 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 973 974 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 975 aml_append(if_ctx, aml_return(aml_int(0x09))); 976 aml_append(method, if_ctx); 977 aml_append(method, aml_return(aml_int(0x0B))); 978 return method; 979 } 980 981 static void build_piix4_pci0_int(Aml *table) 982 { 983 Aml *dev; 984 Aml *crs; 985 Aml *method; 986 uint32_t irqs; 987 Aml *sb_scope = aml_scope("_SB"); 988 Aml *pci0_scope = aml_scope("PCI0"); 989 990 aml_append(pci0_scope, build_prt(true)); 991 aml_append(sb_scope, pci0_scope); 992 993 aml_append(sb_scope, build_irq_status_method()); 994 aml_append(sb_scope, build_iqcr_method(true)); 995 996 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 997 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 998 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 999 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1000 1001 dev = aml_device("LNKS"); 1002 { 1003 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1004 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1005 1006 crs = aml_resource_template(); 1007 irqs = 9; 1008 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1009 AML_ACTIVE_HIGH, AML_SHARED, 1010 &irqs, 1)); 1011 aml_append(dev, aml_name_decl("_PRS", crs)); 1012 1013 /* The SCI cannot be disabled and is always attached to GSI 9, 1014 * so these are no-ops. We only need this link to override the 1015 * polarity to active high and match the content of the MADT. 1016 */ 1017 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1018 aml_append(method, aml_return(aml_int(0x0b))); 1019 aml_append(dev, method); 1020 1021 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1022 aml_append(dev, method); 1023 1024 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1025 aml_append(method, aml_return(aml_name("_PRS"))); 1026 aml_append(dev, method); 1027 1028 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1029 aml_append(dev, method); 1030 } 1031 aml_append(sb_scope, dev); 1032 1033 aml_append(table, sb_scope); 1034 } 1035 1036 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1037 { 1038 int i; 1039 int head; 1040 Aml *pkg; 1041 char base = name[3] < 'E' ? 'A' : 'E'; 1042 char *s = g_strdup(name); 1043 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1044 1045 assert(strlen(s) == 4); 1046 1047 head = name[3] - base; 1048 for (i = 0; i < 4; i++) { 1049 if (head + i > 3) { 1050 head = i * -1; 1051 } 1052 s[3] = base + head + i; 1053 pkg = aml_package(4); 1054 aml_append(pkg, a_nr); 1055 aml_append(pkg, aml_int(i)); 1056 aml_append(pkg, aml_name("%s", s)); 1057 aml_append(pkg, aml_int(0)); 1058 aml_append(ctx, pkg); 1059 } 1060 g_free(s); 1061 } 1062 1063 static Aml *build_q35_routing_table(const char *str) 1064 { 1065 int i; 1066 Aml *pkg; 1067 char *name = g_strdup_printf("%s ", str); 1068 1069 pkg = aml_package(128); 1070 for (i = 0; i < 0x18; i++) { 1071 name[3] = 'E' + (i & 0x3); 1072 append_q35_prt_entry(pkg, i, name); 1073 } 1074 1075 name[3] = 'E'; 1076 append_q35_prt_entry(pkg, 0x18, name); 1077 1078 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1079 for (i = 0x0019; i < 0x1e; i++) { 1080 name[3] = 'A'; 1081 append_q35_prt_entry(pkg, i, name); 1082 } 1083 1084 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1085 name[3] = 'E'; 1086 append_q35_prt_entry(pkg, 0x1e, name); 1087 name[3] = 'A'; 1088 append_q35_prt_entry(pkg, 0x1f, name); 1089 1090 g_free(name); 1091 return pkg; 1092 } 1093 1094 static void build_q35_pci0_int(Aml *table) 1095 { 1096 Aml *method; 1097 Aml *sb_scope = aml_scope("_SB"); 1098 Aml *pci0_scope = aml_scope("PCI0"); 1099 1100 /* Zero => PIC mode, One => APIC Mode */ 1101 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1102 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1103 { 1104 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1105 } 1106 aml_append(table, method); 1107 1108 aml_append(pci0_scope, 1109 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1110 aml_append(pci0_scope, 1111 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1112 1113 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1114 { 1115 Aml *if_ctx; 1116 Aml *else_ctx; 1117 1118 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1119 section 6.2.8.1 */ 1120 /* Note: we provide the same info as the PCI routing 1121 table of the Bochs BIOS */ 1122 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1123 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1124 aml_append(method, if_ctx); 1125 else_ctx = aml_else(); 1126 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1127 aml_append(method, else_ctx); 1128 } 1129 aml_append(pci0_scope, method); 1130 aml_append(sb_scope, pci0_scope); 1131 1132 aml_append(sb_scope, build_irq_status_method()); 1133 aml_append(sb_scope, build_iqcr_method(false)); 1134 1135 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1136 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1137 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1138 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1139 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1140 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1141 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1142 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1143 1144 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1145 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1146 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1147 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1148 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1149 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1150 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1151 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1152 1153 aml_append(table, sb_scope); 1154 } 1155 1156 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1157 { 1158 Aml *dev; 1159 Aml *resource_template; 1160 1161 /* DRAM controller */ 1162 dev = aml_device("DRAC"); 1163 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1164 1165 resource_template = aml_resource_template(); 1166 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1167 aml_append(resource_template, 1168 aml_qword_memory(AML_POS_DECODE, 1169 AML_MIN_FIXED, 1170 AML_MAX_FIXED, 1171 AML_NON_CACHEABLE, 1172 AML_READ_WRITE, 1173 0x0000000000000000, 1174 mcfg->base, 1175 mcfg->base + mcfg->size - 1, 1176 0x0000000000000000, 1177 mcfg->size)); 1178 } else { 1179 aml_append(resource_template, 1180 aml_dword_memory(AML_POS_DECODE, 1181 AML_MIN_FIXED, 1182 AML_MAX_FIXED, 1183 AML_NON_CACHEABLE, 1184 AML_READ_WRITE, 1185 0x0000000000000000, 1186 mcfg->base, 1187 mcfg->base + mcfg->size - 1, 1188 0x0000000000000000, 1189 mcfg->size)); 1190 } 1191 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1192 1193 return dev; 1194 } 1195 1196 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1197 { 1198 Aml *scope; 1199 Aml *field; 1200 Aml *method; 1201 1202 scope = aml_scope("_SB.PCI0"); 1203 1204 aml_append(scope, 1205 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1206 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1207 aml_append(field, aml_named_field("PCIU", 32)); 1208 aml_append(field, aml_named_field("PCID", 32)); 1209 aml_append(scope, field); 1210 1211 aml_append(scope, 1212 aml_operation_region("SEJ", AML_SYSTEM_IO, 1213 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1214 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1215 aml_append(field, aml_named_field("B0EJ", 32)); 1216 aml_append(scope, field); 1217 1218 aml_append(scope, 1219 aml_operation_region("BNMR", AML_SYSTEM_IO, 1220 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1221 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1222 aml_append(field, aml_named_field("BNUM", 32)); 1223 aml_append(field, aml_named_field("PIDX", 32)); 1224 aml_append(scope, field); 1225 1226 aml_append(scope, aml_mutex("BLCK", 0)); 1227 1228 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1229 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1230 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1231 aml_append(method, 1232 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1233 aml_append(method, aml_release(aml_name("BLCK"))); 1234 aml_append(method, aml_return(aml_int(0))); 1235 aml_append(scope, method); 1236 1237 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1238 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1239 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1240 aml_append(method, 1241 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1242 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1243 aml_append(method, aml_release(aml_name("BLCK"))); 1244 aml_append(method, aml_return(aml_local(0))); 1245 aml_append(scope, method); 1246 1247 aml_append(scope, aml_pci_pdsm()); 1248 1249 aml_append(table, scope); 1250 } 1251 1252 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1253 { 1254 Aml *if_ctx; 1255 Aml *if_ctx2; 1256 Aml *else_ctx; 1257 Aml *method; 1258 Aml *a_cwd1 = aml_name("CDW1"); 1259 Aml *a_ctrl = aml_local(0); 1260 1261 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1262 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1263 1264 if_ctx = aml_if(aml_equal( 1265 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1266 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1267 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1268 1269 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1270 1271 /* 1272 * Always allow native PME, AER (no dependencies) 1273 * Allow SHPC (PCI bridges can have SHPC controller) 1274 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1275 */ 1276 aml_append(if_ctx, aml_and(a_ctrl, 1277 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1278 1279 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1280 /* Unknown revision */ 1281 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1282 aml_append(if_ctx, if_ctx2); 1283 1284 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1285 /* Capabilities bits were masked */ 1286 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1287 aml_append(if_ctx, if_ctx2); 1288 1289 /* Update DWORD3 in the buffer */ 1290 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1291 aml_append(method, if_ctx); 1292 1293 else_ctx = aml_else(); 1294 /* Unrecognized UUID */ 1295 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1296 aml_append(method, else_ctx); 1297 1298 aml_append(method, aml_return(aml_arg(3))); 1299 return method; 1300 } 1301 1302 static void build_acpi0017(Aml *table) 1303 { 1304 Aml *dev, *scope, *method; 1305 1306 scope = aml_scope("_SB"); 1307 dev = aml_device("CXLM"); 1308 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1309 1310 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1311 aml_append(method, aml_return(aml_int(0x01))); 1312 aml_append(dev, method); 1313 1314 aml_append(scope, dev); 1315 aml_append(table, scope); 1316 } 1317 1318 static void 1319 build_dsdt(GArray *table_data, BIOSLinker *linker, 1320 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1321 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1322 { 1323 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1324 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1325 CrsRangeEntry *entry; 1326 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1327 CrsRangeSet crs_range_set; 1328 PCMachineState *pcms = PC_MACHINE(machine); 1329 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1330 X86MachineState *x86ms = X86_MACHINE(machine); 1331 AcpiMcfgInfo mcfg; 1332 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1333 uint32_t nr_mem = machine->ram_slots; 1334 int root_bus_limit = 0xFF; 1335 PCIBus *bus = NULL; 1336 #ifdef CONFIG_TPM 1337 TPMIf *tpm = tpm_find(); 1338 #endif 1339 bool cxl_present = false; 1340 int i; 1341 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1342 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1343 .oem_table_id = x86ms->oem_table_id }; 1344 1345 assert(!!i440fx != !!q35); 1346 1347 acpi_table_begin(&table, table_data); 1348 dsdt = init_aml_allocator(); 1349 1350 build_dbg_aml(dsdt); 1351 if (i440fx) { 1352 sb_scope = aml_scope("_SB"); 1353 dev = aml_device("PCI0"); 1354 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1355 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1356 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1357 aml_append(sb_scope, dev); 1358 aml_append(dsdt, sb_scope); 1359 1360 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1361 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1362 } 1363 build_piix4_pci0_int(dsdt); 1364 } else if (q35) { 1365 sb_scope = aml_scope("_SB"); 1366 dev = aml_device("PCI0"); 1367 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1368 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1369 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1370 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1371 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1372 aml_append(sb_scope, dev); 1373 if (mcfg_valid) { 1374 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1375 } 1376 1377 if (pm->smi_on_cpuhp) { 1378 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1379 dev = aml_device("PCI0.SMI0"); 1380 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1381 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1382 crs = aml_resource_template(); 1383 aml_append(crs, 1384 aml_io( 1385 AML_DECODE16, 1386 ACPI_PORT_SMI_CMD, 1387 ACPI_PORT_SMI_CMD, 1388 1, 1389 2) 1390 ); 1391 aml_append(dev, aml_name_decl("_CRS", crs)); 1392 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1393 aml_int(ACPI_PORT_SMI_CMD), 2)); 1394 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1395 AML_WRITE_AS_ZEROS); 1396 aml_append(field, aml_named_field("SMIC", 8)); 1397 aml_append(field, aml_reserved_field(8)); 1398 aml_append(dev, field); 1399 aml_append(sb_scope, dev); 1400 } 1401 1402 aml_append(dsdt, sb_scope); 1403 1404 if (pm->pcihp_bridge_en) { 1405 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1406 } 1407 build_q35_pci0_int(dsdt); 1408 } 1409 1410 if (misc->has_hpet) { 1411 build_hpet_aml(dsdt); 1412 } 1413 1414 if (vmbus_bridge) { 1415 sb_scope = aml_scope("_SB"); 1416 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1417 aml_append(dsdt, sb_scope); 1418 } 1419 1420 scope = aml_scope("_GPE"); 1421 { 1422 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1423 if (machine->nvdimms_state->is_enabled) { 1424 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1425 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1426 aml_int(0x80))); 1427 aml_append(scope, method); 1428 } 1429 } 1430 aml_append(dsdt, scope); 1431 1432 if (pcmc->legacy_cpu_hotplug) { 1433 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1434 } else { 1435 CPUHotplugFeatures opts = { 1436 .acpi_1_compatible = true, .has_legacy_cphp = true, 1437 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1438 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1439 }; 1440 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1441 "\\_SB.PCI0", "\\_GPE._E02"); 1442 } 1443 1444 if (pcms->memhp_io_base && nr_mem) { 1445 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1446 "\\_GPE._E03", AML_SYSTEM_IO, 1447 pcms->memhp_io_base); 1448 } 1449 1450 crs_range_set_init(&crs_range_set); 1451 bus = PC_MACHINE(machine)->bus; 1452 if (bus) { 1453 QLIST_FOREACH(bus, &bus->child, sibling) { 1454 uint8_t bus_num = pci_bus_num(bus); 1455 uint8_t numa_node = pci_bus_numa_node(bus); 1456 1457 /* look only for expander root buses */ 1458 if (!pci_bus_is_root(bus)) { 1459 continue; 1460 } 1461 1462 if (bus_num < root_bus_limit) { 1463 root_bus_limit = bus_num - 1; 1464 } 1465 1466 scope = aml_scope("\\_SB"); 1467 1468 if (pci_bus_is_cxl(bus)) { 1469 dev = aml_device("CL%.02X", bus_num); 1470 } else { 1471 dev = aml_device("PC%.02X", bus_num); 1472 } 1473 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1474 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1475 if (pci_bus_is_cxl(bus)) { 1476 struct Aml *pkg = aml_package(2); 1477 1478 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1479 aml_append(pkg, aml_eisaid("PNP0A08")); 1480 aml_append(pkg, aml_eisaid("PNP0A03")); 1481 aml_append(dev, aml_name_decl("_CID", pkg)); 1482 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1483 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1484 build_cxl_osc_method(dev); 1485 } else if (pci_bus_is_express(bus)) { 1486 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1487 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1488 1489 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1490 aml_append(dev, build_q35_osc_method(true)); 1491 } else { 1492 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1493 } 1494 1495 if (numa_node != NUMA_NODE_UNASSIGNED) { 1496 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1497 } 1498 1499 aml_append(dev, build_prt(false)); 1500 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1501 0, 0, 0, 0); 1502 aml_append(dev, aml_name_decl("_CRS", crs)); 1503 aml_append(scope, dev); 1504 aml_append(dsdt, scope); 1505 1506 /* Handle the ranges for the PXB expanders */ 1507 if (pci_bus_is_cxl(bus)) { 1508 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1509 uint64_t base = mr->addr; 1510 1511 cxl_present = true; 1512 crs_range_insert(crs_range_set.mem_ranges, base, 1513 base + memory_region_size(mr) - 1); 1514 } 1515 } 1516 } 1517 1518 if (cxl_present) { 1519 build_acpi0017(dsdt); 1520 } 1521 1522 /* 1523 * At this point crs_range_set has all the ranges used by pci 1524 * busses *other* than PCI0. These ranges will be excluded from 1525 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1526 * too. 1527 */ 1528 if (mcfg_valid) { 1529 crs_range_insert(crs_range_set.mem_ranges, 1530 mcfg.base, mcfg.base + mcfg.size - 1); 1531 } 1532 1533 scope = aml_scope("\\_SB.PCI0"); 1534 /* build PCI0._CRS */ 1535 crs = aml_resource_template(); 1536 aml_append(crs, 1537 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1538 0x0000, 0x0, root_bus_limit, 1539 0x0000, root_bus_limit + 1)); 1540 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1541 1542 aml_append(crs, 1543 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1544 AML_POS_DECODE, AML_ENTIRE_RANGE, 1545 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1546 1547 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1548 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1549 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1550 aml_append(crs, 1551 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1552 AML_POS_DECODE, AML_ENTIRE_RANGE, 1553 0x0000, entry->base, entry->limit, 1554 0x0000, entry->limit - entry->base + 1)); 1555 } 1556 1557 aml_append(crs, 1558 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1559 AML_CACHEABLE, AML_READ_WRITE, 1560 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1561 1562 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1563 range_lob(pci_hole), 1564 range_upb(pci_hole)); 1565 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1566 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1567 aml_append(crs, 1568 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1569 AML_NON_CACHEABLE, AML_READ_WRITE, 1570 0, entry->base, entry->limit, 1571 0, entry->limit - entry->base + 1)); 1572 } 1573 1574 if (!range_is_empty(pci_hole64)) { 1575 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1576 range_lob(pci_hole64), 1577 range_upb(pci_hole64)); 1578 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1579 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1580 aml_append(crs, 1581 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1582 AML_MAX_FIXED, 1583 AML_CACHEABLE, AML_READ_WRITE, 1584 0, entry->base, entry->limit, 1585 0, entry->limit - entry->base + 1)); 1586 } 1587 } 1588 1589 #ifdef CONFIG_TPM 1590 if (TPM_IS_TIS_ISA(tpm_find())) { 1591 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1592 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1593 } 1594 #endif 1595 aml_append(scope, aml_name_decl("_CRS", crs)); 1596 1597 /* reserve GPE0 block resources */ 1598 dev = aml_device("GPE0"); 1599 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1600 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1601 /* device present, functioning, decoding, not shown in UI */ 1602 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1603 crs = aml_resource_template(); 1604 aml_append(crs, 1605 aml_io( 1606 AML_DECODE16, 1607 pm->fadt.gpe0_blk.address, 1608 pm->fadt.gpe0_blk.address, 1609 1, 1610 pm->fadt.gpe0_blk.bit_width / 8) 1611 ); 1612 aml_append(dev, aml_name_decl("_CRS", crs)); 1613 aml_append(scope, dev); 1614 1615 crs_range_set_free(&crs_range_set); 1616 1617 /* reserve PCIHP resources */ 1618 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1619 dev = aml_device("PHPR"); 1620 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1621 aml_append(dev, 1622 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1623 /* device present, functioning, decoding, not shown in UI */ 1624 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1625 crs = aml_resource_template(); 1626 aml_append(crs, 1627 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1628 pm->pcihp_io_len) 1629 ); 1630 aml_append(dev, aml_name_decl("_CRS", crs)); 1631 aml_append(scope, dev); 1632 } 1633 aml_append(dsdt, scope); 1634 1635 /* create S3_ / S4_ / S5_ packages if necessary */ 1636 scope = aml_scope("\\"); 1637 if (!pm->s3_disabled) { 1638 pkg = aml_package(4); 1639 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1640 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1641 aml_append(pkg, aml_int(0)); /* reserved */ 1642 aml_append(pkg, aml_int(0)); /* reserved */ 1643 aml_append(scope, aml_name_decl("_S3", pkg)); 1644 } 1645 1646 if (!pm->s4_disabled) { 1647 pkg = aml_package(4); 1648 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1649 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1650 aml_append(pkg, aml_int(pm->s4_val)); 1651 aml_append(pkg, aml_int(0)); /* reserved */ 1652 aml_append(pkg, aml_int(0)); /* reserved */ 1653 aml_append(scope, aml_name_decl("_S4", pkg)); 1654 } 1655 1656 pkg = aml_package(4); 1657 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1658 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1659 aml_append(pkg, aml_int(0)); /* reserved */ 1660 aml_append(pkg, aml_int(0)); /* reserved */ 1661 aml_append(scope, aml_name_decl("_S5", pkg)); 1662 aml_append(dsdt, scope); 1663 1664 /* create fw_cfg node, unconditionally */ 1665 { 1666 scope = aml_scope("\\_SB.PCI0"); 1667 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1668 aml_append(dsdt, scope); 1669 } 1670 1671 sb_scope = aml_scope("\\_SB"); 1672 { 1673 Object *pci_host = acpi_get_i386_pci_host(); 1674 1675 if (pci_host) { 1676 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1677 Aml *scope = aml_scope("PCI0"); 1678 /* Scan all PCI buses. Generate tables to support hotplug. */ 1679 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1680 aml_append(sb_scope, scope); 1681 } 1682 } 1683 1684 #ifdef CONFIG_TPM 1685 if (TPM_IS_CRB(tpm)) { 1686 dev = aml_device("TPM"); 1687 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1688 aml_append(dev, aml_name_decl("_STR", 1689 aml_string("TPM 2.0 Device"))); 1690 crs = aml_resource_template(); 1691 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1692 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1693 aml_append(dev, aml_name_decl("_CRS", crs)); 1694 1695 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1696 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1697 1698 tpm_build_ppi_acpi(tpm, dev); 1699 1700 aml_append(sb_scope, dev); 1701 } 1702 #endif 1703 1704 if (pcms->sgx_epc.size != 0) { 1705 uint64_t epc_base = pcms->sgx_epc.base; 1706 uint64_t epc_size = pcms->sgx_epc.size; 1707 1708 dev = aml_device("EPC"); 1709 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1710 aml_append(dev, aml_name_decl("_STR", 1711 aml_unicode("Enclave Page Cache 1.0"))); 1712 crs = aml_resource_template(); 1713 aml_append(crs, 1714 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1715 AML_MAX_FIXED, AML_NON_CACHEABLE, 1716 AML_READ_WRITE, 0, epc_base, 1717 epc_base + epc_size - 1, 0, epc_size)); 1718 aml_append(dev, aml_name_decl("_CRS", crs)); 1719 1720 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1721 aml_append(method, aml_return(aml_int(0x0f))); 1722 aml_append(dev, method); 1723 1724 aml_append(sb_scope, dev); 1725 } 1726 aml_append(dsdt, sb_scope); 1727 1728 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1729 scope = aml_scope("_GPE"); 1730 { 1731 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1732 aml_append(method, 1733 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1734 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1735 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1736 aml_append(scope, method); 1737 } 1738 aml_append(dsdt, scope); 1739 } 1740 1741 /* copy AML table into ACPI tables blob and patch header there */ 1742 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1743 acpi_table_end(linker, &table); 1744 free_aml_allocator(); 1745 } 1746 1747 /* 1748 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1749 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1750 */ 1751 static void 1752 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1753 const char *oem_table_id) 1754 { 1755 AcpiTable table = { .sig = "HPET", .rev = 1, 1756 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1757 1758 acpi_table_begin(&table, table_data); 1759 /* Note timer_block_id value must be kept in sync with value advertised by 1760 * emulated hpet 1761 */ 1762 /* Event Timer Block ID */ 1763 build_append_int_noprefix(table_data, 0x8086a201, 4); 1764 /* BASE_ADDRESS */ 1765 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1766 /* HPET Number */ 1767 build_append_int_noprefix(table_data, 0, 1); 1768 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1769 build_append_int_noprefix(table_data, 0, 2); 1770 /* Page Protection And OEM Attribute */ 1771 build_append_int_noprefix(table_data, 0, 1); 1772 acpi_table_end(linker, &table); 1773 } 1774 1775 #ifdef CONFIG_TPM 1776 /* 1777 * TCPA Description Table 1778 * 1779 * Following Level 00, Rev 00.37 of specs: 1780 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1781 * 7.1.2 ACPI Table Layout 1782 */ 1783 static void 1784 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1785 const char *oem_id, const char *oem_table_id) 1786 { 1787 unsigned log_addr_offset; 1788 AcpiTable table = { .sig = "TCPA", .rev = 2, 1789 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1790 1791 acpi_table_begin(&table, table_data); 1792 /* Platform Class */ 1793 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1794 /* Log Area Minimum Length (LAML) */ 1795 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1796 /* Log Area Start Address (LASA) */ 1797 log_addr_offset = table_data->len; 1798 build_append_int_noprefix(table_data, 0, 8); 1799 1800 /* allocate/reserve space for TPM log area */ 1801 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1802 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1803 false /* high memory */); 1804 /* log area start address to be filled by Guest linker */ 1805 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1806 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1807 1808 acpi_table_end(linker, &table); 1809 } 1810 #endif 1811 1812 #define HOLE_640K_START (640 * KiB) 1813 #define HOLE_640K_END (1 * MiB) 1814 1815 /* 1816 * ACPI spec, Revision 3.0 1817 * 5.2.15 System Resource Affinity Table (SRAT) 1818 */ 1819 static void 1820 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1821 { 1822 int i; 1823 int numa_mem_start, slots; 1824 uint64_t mem_len, mem_base, next_base; 1825 MachineClass *mc = MACHINE_GET_CLASS(machine); 1826 X86MachineState *x86ms = X86_MACHINE(machine); 1827 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1828 PCMachineState *pcms = PC_MACHINE(machine); 1829 int nb_numa_nodes = machine->numa_state->num_nodes; 1830 NodeInfo *numa_info = machine->numa_state->nodes; 1831 ram_addr_t hotpluggable_address_space_size = 1832 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1833 NULL); 1834 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1835 .oem_table_id = x86ms->oem_table_id }; 1836 1837 acpi_table_begin(&table, table_data); 1838 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1839 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1840 1841 for (i = 0; i < apic_ids->len; i++) { 1842 int node_id = apic_ids->cpus[i].props.node_id; 1843 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1844 1845 if (apic_id < 255) { 1846 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1847 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1848 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1849 /* Proximity Domain [7:0] */ 1850 build_append_int_noprefix(table_data, node_id, 1); 1851 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1852 /* Flags, Table 5-36 */ 1853 build_append_int_noprefix(table_data, 1, 4); 1854 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1855 /* Proximity Domain [31:8] */ 1856 build_append_int_noprefix(table_data, 0, 3); 1857 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1858 } else { 1859 /* 1860 * ACPI spec, Revision 4.0 1861 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1862 */ 1863 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1864 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1865 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1866 /* Proximity Domain */ 1867 build_append_int_noprefix(table_data, node_id, 4); 1868 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1869 /* Flags, Table 5-39 */ 1870 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1871 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1872 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1873 } 1874 } 1875 1876 /* the memory map is a bit tricky, it contains at least one hole 1877 * from 640k-1M and possibly another one from 3.5G-4G. 1878 */ 1879 next_base = 0; 1880 numa_mem_start = table_data->len; 1881 1882 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1883 mem_base = next_base; 1884 mem_len = numa_info[i - 1].node_mem; 1885 next_base = mem_base + mem_len; 1886 1887 /* Cut out the 640K hole */ 1888 if (mem_base <= HOLE_640K_START && 1889 next_base > HOLE_640K_START) { 1890 mem_len -= next_base - HOLE_640K_START; 1891 if (mem_len > 0) { 1892 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1893 MEM_AFFINITY_ENABLED); 1894 } 1895 1896 /* Check for the rare case: 640K < RAM < 1M */ 1897 if (next_base <= HOLE_640K_END) { 1898 next_base = HOLE_640K_END; 1899 continue; 1900 } 1901 mem_base = HOLE_640K_END; 1902 mem_len = next_base - HOLE_640K_END; 1903 } 1904 1905 /* Cut out the ACPI_PCI hole */ 1906 if (mem_base <= x86ms->below_4g_mem_size && 1907 next_base > x86ms->below_4g_mem_size) { 1908 mem_len -= next_base - x86ms->below_4g_mem_size; 1909 if (mem_len > 0) { 1910 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1911 MEM_AFFINITY_ENABLED); 1912 } 1913 mem_base = x86ms->above_4g_mem_start; 1914 mem_len = next_base - x86ms->below_4g_mem_size; 1915 next_base = mem_base + mem_len; 1916 } 1917 1918 if (mem_len > 0) { 1919 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1920 MEM_AFFINITY_ENABLED); 1921 } 1922 } 1923 1924 if (machine->nvdimms_state->is_enabled) { 1925 nvdimm_build_srat(table_data); 1926 } 1927 1928 sgx_epc_build_srat(table_data); 1929 1930 /* 1931 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1932 * without these entries. But I recall there were issues the last time I 1933 * tried to remove it with some ancient guest OS, however I can't remember 1934 * what that was so keep this around for now 1935 */ 1936 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1937 for (; slots < nb_numa_nodes + 2; slots++) { 1938 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1939 } 1940 1941 /* 1942 * Entry is required for Windows to enable memory hotplug in OS 1943 * and for Linux to enable SWIOTLB when booted with less than 1944 * 4G of RAM. Windows works better if the entry sets proximity 1945 * to the highest NUMA node in the machine. 1946 * Memory devices may override proximity set by this entry, 1947 * providing _PXM method if necessary. 1948 */ 1949 if (hotpluggable_address_space_size) { 1950 build_srat_memory(table_data, machine->device_memory->base, 1951 hotpluggable_address_space_size, nb_numa_nodes - 1, 1952 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1953 } 1954 1955 acpi_table_end(linker, &table); 1956 } 1957 1958 /* 1959 * Insert DMAR scope for PCI bridges and endpoint devcie 1960 */ 1961 static void 1962 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1963 { 1964 const size_t device_scope_size = 6 /* device scope structure */ + 1965 2 /* 1 path entry */; 1966 GArray *scope_blob = opaque; 1967 1968 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1969 /* Dmar Scope Type: 0x02 for PCI Bridge */ 1970 build_append_int_noprefix(scope_blob, 0x02, 1); 1971 } else { 1972 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 1973 build_append_int_noprefix(scope_blob, 0x01, 1); 1974 } 1975 1976 /* length */ 1977 build_append_int_noprefix(scope_blob, device_scope_size, 1); 1978 /* reserved */ 1979 build_append_int_noprefix(scope_blob, 0, 2); 1980 /* enumeration_id */ 1981 build_append_int_noprefix(scope_blob, 0, 1); 1982 /* bus */ 1983 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 1984 /* device */ 1985 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 1986 /* function */ 1987 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 1988 } 1989 1990 /* For a given PCI host bridge, walk and insert DMAR scope */ 1991 static int 1992 dmar_host_bridges(Object *obj, void *opaque) 1993 { 1994 GArray *scope_blob = opaque; 1995 1996 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 1997 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 1998 1999 if (bus && !pci_bus_bypass_iommu(bus)) { 2000 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2001 } 2002 } 2003 2004 return 0; 2005 } 2006 2007 /* 2008 * Intel ® Virtualization Technology for Directed I/O 2009 * Architecture Specification. Revision 3.3 2010 * 8.1 DMA Remapping Reporting Structure 2011 */ 2012 static void 2013 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2014 const char *oem_table_id) 2015 { 2016 uint8_t dmar_flags = 0; 2017 uint8_t rsvd10[10] = {}; 2018 /* Root complex IOAPIC uses one path only */ 2019 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2020 2 /* 1 path entry */; 2021 X86IOMMUState *iommu = x86_iommu_get_default(); 2022 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2023 GArray *scope_blob = g_array_new(false, true, 1); 2024 2025 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2026 .oem_table_id = oem_table_id }; 2027 2028 /* 2029 * A PCI bus walk, for each PCI host bridge. 2030 * Insert scope for each PCI bridge and endpoint device which 2031 * is attached to a bus with iommu enabled. 2032 */ 2033 object_child_foreach_recursive(object_get_root(), 2034 dmar_host_bridges, scope_blob); 2035 2036 assert(iommu); 2037 if (x86_iommu_ir_supported(iommu)) { 2038 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2039 } 2040 2041 acpi_table_begin(&table, table_data); 2042 /* Host Address Width */ 2043 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2044 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2045 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2046 2047 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2048 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2049 /* Length */ 2050 build_append_int_noprefix(table_data, 2051 16 + ioapic_scope_size + scope_blob->len, 2); 2052 /* Flags */ 2053 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2054 1); 2055 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2056 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2057 /* Register Base Address */ 2058 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2059 2060 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2061 * 8.3.1 (version Oct. 2014 or later). */ 2062 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2063 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2064 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2065 /* Enumeration ID */ 2066 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2067 /* Start Bus Number */ 2068 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2069 /* Path, {Device, Function} pair */ 2070 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2071 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2072 2073 /* Add scope found above */ 2074 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2075 g_array_free(scope_blob, true); 2076 2077 if (iommu->dt_supported) { 2078 /* 8.5 Root Port ATS Capability Reporting Structure */ 2079 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2080 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2081 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2082 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2083 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2084 } 2085 2086 acpi_table_end(linker, &table); 2087 } 2088 2089 /* 2090 * Windows ACPI Emulated Devices Table 2091 * (Version 1.0 - April 6, 2009) 2092 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2093 * 2094 * Helpful to speedup Windows guests and ignored by others. 2095 */ 2096 static void 2097 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2098 const char *oem_table_id) 2099 { 2100 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2101 .oem_table_id = oem_table_id }; 2102 2103 acpi_table_begin(&table, table_data); 2104 /* 2105 * Set "ACPI PM timer good" flag. 2106 * 2107 * Tells Windows guests that our ACPI PM timer is reliable in the 2108 * sense that guest can read it only once to obtain a reliable value. 2109 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2110 */ 2111 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2112 acpi_table_end(linker, &table); 2113 } 2114 2115 /* 2116 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2117 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2118 */ 2119 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2120 2121 /* 2122 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2123 * necessary for the PCI topology. 2124 */ 2125 static void 2126 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2127 { 2128 GArray *table_data = opaque; 2129 uint32_t entry; 2130 2131 /* "Select" IVHD entry, type 0x2 */ 2132 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2133 build_append_int_noprefix(table_data, entry, 4); 2134 2135 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2136 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2137 uint8_t sec = pci_bus_num(sec_bus); 2138 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2139 2140 if (pci_bus_is_express(sec_bus)) { 2141 /* 2142 * Walk the bus if there are subordinates, otherwise use a range 2143 * to cover an entire leaf bus. We could potentially also use a 2144 * range for traversed buses, but we'd need to take care not to 2145 * create both Select and Range entries covering the same device. 2146 * This is easier and potentially more compact. 2147 * 2148 * An example bare metal system seems to use Select entries for 2149 * root ports without a slot (ie. built-ins) and Range entries 2150 * when there is a slot. The same system also only hard-codes 2151 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2152 * making no effort to support nested bridges. We attempt to 2153 * be more thorough here. 2154 */ 2155 if (sec == sub) { /* leaf bus */ 2156 /* "Start of Range" IVHD entry, type 0x3 */ 2157 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2158 build_append_int_noprefix(table_data, entry, 4); 2159 /* "End of Range" IVHD entry, type 0x4 */ 2160 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2161 build_append_int_noprefix(table_data, entry, 4); 2162 } else { 2163 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2164 } 2165 } else { 2166 /* 2167 * If the secondary bus is conventional, then we need to create an 2168 * Alias range for everything downstream. The range covers the 2169 * first devfn on the secondary bus to the last devfn on the 2170 * subordinate bus. The alias target depends on legacy versus 2171 * express bridges, just as in pci_device_iommu_address_space(). 2172 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2173 */ 2174 uint16_t dev_id_a, dev_id_b; 2175 2176 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2177 2178 if (pci_is_express(dev) && 2179 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2180 dev_id_b = dev_id_a; 2181 } else { 2182 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2183 } 2184 2185 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2186 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2187 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2188 2189 /* "End of Range" IVHD entry, type 0x4 */ 2190 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2191 build_append_int_noprefix(table_data, entry, 4); 2192 } 2193 } 2194 } 2195 2196 /* For all PCI host bridges, walk and insert IVHD entries */ 2197 static int 2198 ivrs_host_bridges(Object *obj, void *opaque) 2199 { 2200 GArray *ivhd_blob = opaque; 2201 2202 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2203 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2204 2205 if (bus && !pci_bus_bypass_iommu(bus)) { 2206 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2207 } 2208 } 2209 2210 return 0; 2211 } 2212 2213 static void 2214 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2215 const char *oem_table_id) 2216 { 2217 int ivhd_table_len = 24; 2218 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2219 GArray *ivhd_blob = g_array_new(false, true, 1); 2220 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2221 .oem_table_id = oem_table_id }; 2222 2223 acpi_table_begin(&table, table_data); 2224 /* IVinfo - IO virtualization information common to all 2225 * IOMMU units in a system 2226 */ 2227 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2228 /* reserved */ 2229 build_append_int_noprefix(table_data, 0, 8); 2230 2231 /* IVHD definition - type 10h */ 2232 build_append_int_noprefix(table_data, 0x10, 1); 2233 /* virtualization flags */ 2234 build_append_int_noprefix(table_data, 2235 (1UL << 0) | /* HtTunEn */ 2236 (1UL << 4) | /* iotblSup */ 2237 (1UL << 6) | /* PrefSup */ 2238 (1UL << 7), /* PPRSup */ 2239 1); 2240 2241 /* 2242 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2243 * complete set of IVHD entries. Do this into a separate blob so that we 2244 * can calculate the total IVRS table length here and then append the new 2245 * blob further below. Fall back to an entry covering all devices, which 2246 * is sufficient when no aliases are present. 2247 */ 2248 object_child_foreach_recursive(object_get_root(), 2249 ivrs_host_bridges, ivhd_blob); 2250 2251 if (!ivhd_blob->len) { 2252 /* 2253 * Type 1 device entry reporting all devices 2254 * These are 4-byte device entries currently reporting the range of 2255 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2256 */ 2257 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2258 } 2259 2260 ivhd_table_len += ivhd_blob->len; 2261 2262 /* 2263 * When interrupt remapping is supported, we add a special IVHD device 2264 * for type IO-APIC. 2265 */ 2266 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2267 ivhd_table_len += 8; 2268 } 2269 2270 /* IVHD length */ 2271 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2272 /* DeviceID */ 2273 build_append_int_noprefix(table_data, s->devid, 2); 2274 /* Capability offset */ 2275 build_append_int_noprefix(table_data, s->capab_offset, 2); 2276 /* IOMMU base address */ 2277 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2278 /* PCI Segment Group */ 2279 build_append_int_noprefix(table_data, 0, 2); 2280 /* IOMMU info */ 2281 build_append_int_noprefix(table_data, 0, 2); 2282 /* IOMMU Feature Reporting */ 2283 build_append_int_noprefix(table_data, 2284 (48UL << 30) | /* HATS */ 2285 (48UL << 28) | /* GATS */ 2286 (1UL << 2) | /* GTSup */ 2287 (1UL << 6), /* GASup */ 2288 4); 2289 2290 /* IVHD entries as found above */ 2291 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2292 g_array_free(ivhd_blob, TRUE); 2293 2294 /* 2295 * Add a special IVHD device type. 2296 * Refer to spec - Table 95: IVHD device entry type codes 2297 * 2298 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2299 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2300 */ 2301 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2302 build_append_int_noprefix(table_data, 2303 (0x1ull << 56) | /* type IOAPIC */ 2304 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2305 0x48, /* special device */ 2306 8); 2307 } 2308 acpi_table_end(linker, &table); 2309 } 2310 2311 typedef 2312 struct AcpiBuildState { 2313 /* Copy of table in RAM (for patching). */ 2314 MemoryRegion *table_mr; 2315 /* Is table patched? */ 2316 uint8_t patched; 2317 void *rsdp; 2318 MemoryRegion *rsdp_mr; 2319 MemoryRegion *linker_mr; 2320 } AcpiBuildState; 2321 2322 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2323 { 2324 Object *pci_host; 2325 QObject *o; 2326 2327 pci_host = acpi_get_i386_pci_host(); 2328 if (!pci_host) { 2329 return false; 2330 } 2331 2332 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2333 if (!o) { 2334 return false; 2335 } 2336 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2337 qobject_unref(o); 2338 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2339 return false; 2340 } 2341 2342 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2343 assert(o); 2344 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2345 qobject_unref(o); 2346 return true; 2347 } 2348 2349 static 2350 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2351 { 2352 PCMachineState *pcms = PC_MACHINE(machine); 2353 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2354 X86MachineState *x86ms = X86_MACHINE(machine); 2355 DeviceState *iommu = pcms->iommu; 2356 GArray *table_offsets; 2357 unsigned facs, dsdt, rsdt, fadt; 2358 AcpiPmInfo pm; 2359 AcpiMiscInfo misc; 2360 AcpiMcfgInfo mcfg; 2361 Range pci_hole = {}, pci_hole64 = {}; 2362 uint8_t *u; 2363 size_t aml_len = 0; 2364 GArray *tables_blob = tables->table_data; 2365 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2366 Object *vmgenid_dev; 2367 char *oem_id; 2368 char *oem_table_id; 2369 2370 acpi_get_pm_info(machine, &pm); 2371 acpi_get_misc_info(&misc); 2372 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2373 acpi_get_slic_oem(&slic_oem); 2374 2375 if (slic_oem.id) { 2376 oem_id = slic_oem.id; 2377 } else { 2378 oem_id = x86ms->oem_id; 2379 } 2380 2381 if (slic_oem.table_id) { 2382 oem_table_id = slic_oem.table_id; 2383 } else { 2384 oem_table_id = x86ms->oem_table_id; 2385 } 2386 2387 table_offsets = g_array_new(false, true /* clear */, 2388 sizeof(uint32_t)); 2389 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2390 2391 bios_linker_loader_alloc(tables->linker, 2392 ACPI_BUILD_TABLE_FILE, tables_blob, 2393 64 /* Ensure FACS is aligned */, 2394 false /* high memory */); 2395 2396 /* 2397 * FACS is pointed to by FADT. 2398 * We place it first since it's the only table that has alignment 2399 * requirements. 2400 */ 2401 facs = tables_blob->len; 2402 build_facs(tables_blob); 2403 2404 /* DSDT is pointed to by FADT */ 2405 dsdt = tables_blob->len; 2406 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2407 &pci_hole, &pci_hole64, machine); 2408 2409 /* Count the size of the DSDT and SSDT, we will need it for legacy 2410 * sizing of ACPI tables. 2411 */ 2412 aml_len += tables_blob->len - dsdt; 2413 2414 /* ACPI tables pointed to by RSDT */ 2415 fadt = tables_blob->len; 2416 acpi_add_table(table_offsets, tables_blob); 2417 pm.fadt.facs_tbl_offset = &facs; 2418 pm.fadt.dsdt_tbl_offset = &dsdt; 2419 pm.fadt.xdsdt_tbl_offset = &dsdt; 2420 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2421 aml_len += tables_blob->len - fadt; 2422 2423 acpi_add_table(table_offsets, tables_blob); 2424 acpi_build_madt(tables_blob, tables->linker, x86ms, 2425 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2426 x86ms->oem_table_id); 2427 2428 #ifdef CONFIG_ACPI_ERST 2429 { 2430 Object *erst_dev; 2431 erst_dev = find_erst_dev(); 2432 if (erst_dev) { 2433 acpi_add_table(table_offsets, tables_blob); 2434 build_erst(tables_blob, tables->linker, erst_dev, 2435 x86ms->oem_id, x86ms->oem_table_id); 2436 } 2437 } 2438 #endif 2439 2440 vmgenid_dev = find_vmgenid_dev(); 2441 if (vmgenid_dev) { 2442 acpi_add_table(table_offsets, tables_blob); 2443 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2444 tables->vmgenid, tables->linker, x86ms->oem_id); 2445 } 2446 2447 if (misc.has_hpet) { 2448 acpi_add_table(table_offsets, tables_blob); 2449 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2450 x86ms->oem_table_id); 2451 } 2452 #ifdef CONFIG_TPM 2453 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2454 if (misc.tpm_version == TPM_VERSION_1_2) { 2455 acpi_add_table(table_offsets, tables_blob); 2456 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2457 x86ms->oem_id, x86ms->oem_table_id); 2458 } else { /* TPM_VERSION_2_0 */ 2459 acpi_add_table(table_offsets, tables_blob); 2460 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2461 x86ms->oem_id, x86ms->oem_table_id); 2462 } 2463 } 2464 #endif 2465 if (machine->numa_state->num_nodes) { 2466 acpi_add_table(table_offsets, tables_blob); 2467 build_srat(tables_blob, tables->linker, machine); 2468 if (machine->numa_state->have_numa_distance) { 2469 acpi_add_table(table_offsets, tables_blob); 2470 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2471 x86ms->oem_table_id); 2472 } 2473 if (machine->numa_state->hmat_enabled) { 2474 acpi_add_table(table_offsets, tables_blob); 2475 build_hmat(tables_blob, tables->linker, machine->numa_state, 2476 x86ms->oem_id, x86ms->oem_table_id); 2477 } 2478 } 2479 if (acpi_get_mcfg(&mcfg)) { 2480 acpi_add_table(table_offsets, tables_blob); 2481 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2482 x86ms->oem_table_id); 2483 } 2484 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2485 acpi_add_table(table_offsets, tables_blob); 2486 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2487 x86ms->oem_table_id); 2488 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2489 acpi_add_table(table_offsets, tables_blob); 2490 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2491 x86ms->oem_table_id); 2492 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2493 PCIDevice *pdev = PCI_DEVICE(iommu); 2494 2495 acpi_add_table(table_offsets, tables_blob); 2496 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2497 x86ms->oem_id, x86ms->oem_table_id); 2498 } 2499 if (machine->nvdimms_state->is_enabled) { 2500 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2501 machine->nvdimms_state, machine->ram_slots, 2502 x86ms->oem_id, x86ms->oem_table_id); 2503 } 2504 if (pcms->cxl_devices_state.is_enabled) { 2505 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2506 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2507 } 2508 2509 acpi_add_table(table_offsets, tables_blob); 2510 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2511 2512 /* Add tables supplied by user (if any) */ 2513 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2514 unsigned len = acpi_table_len(u); 2515 2516 acpi_add_table(table_offsets, tables_blob); 2517 g_array_append_vals(tables_blob, u, len); 2518 } 2519 2520 /* RSDT is pointed to by RSDP */ 2521 rsdt = tables_blob->len; 2522 build_rsdt(tables_blob, tables->linker, table_offsets, 2523 oem_id, oem_table_id); 2524 2525 /* RSDP is in FSEG memory, so allocate it separately */ 2526 { 2527 AcpiRsdpData rsdp_data = { 2528 .revision = 0, 2529 .oem_id = x86ms->oem_id, 2530 .xsdt_tbl_offset = NULL, 2531 .rsdt_tbl_offset = &rsdt, 2532 }; 2533 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2534 if (!pcmc->rsdp_in_ram) { 2535 /* We used to allocate some extra space for RSDP revision 2 but 2536 * only used the RSDP revision 0 space. The extra bytes were 2537 * zeroed out and not used. 2538 * Here we continue wasting those extra 16 bytes to make sure we 2539 * don't break migration for machine types 2.2 and older due to 2540 * RSDP blob size mismatch. 2541 */ 2542 build_append_int_noprefix(tables->rsdp, 0, 16); 2543 } 2544 } 2545 2546 /* We'll expose it all to Guest so we want to reduce 2547 * chance of size changes. 2548 * 2549 * We used to align the tables to 4k, but of course this would 2550 * too simple to be enough. 4k turned out to be too small an 2551 * alignment very soon, and in fact it is almost impossible to 2552 * keep the table size stable for all (max_cpus, max_memory_slots) 2553 * combinations. So the table size is always 64k for pc-i440fx-2.1 2554 * and we give an error if the table grows beyond that limit. 2555 * 2556 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2557 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2558 * than 2.0 and we can always pad the smaller tables with zeros. We can 2559 * then use the exact size of the 2.0 tables. 2560 * 2561 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2562 */ 2563 if (pcmc->legacy_acpi_table_size) { 2564 /* Subtracting aml_len gives the size of fixed tables. Then add the 2565 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2566 */ 2567 int legacy_aml_len = 2568 pcmc->legacy_acpi_table_size + 2569 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2570 int legacy_table_size = 2571 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2572 ACPI_BUILD_ALIGN_SIZE); 2573 if (tables_blob->len > legacy_table_size) { 2574 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2575 warn_report("ACPI table size %u exceeds %d bytes," 2576 " migration may not work", 2577 tables_blob->len, legacy_table_size); 2578 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2579 " or PCI bridges."); 2580 } 2581 g_array_set_size(tables_blob, legacy_table_size); 2582 } else { 2583 /* Make sure we have a buffer in case we need to resize the tables. */ 2584 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2585 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2586 warn_report("ACPI table size %u exceeds %d bytes," 2587 " migration may not work", 2588 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2589 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2590 " or PCI bridges."); 2591 } 2592 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2593 } 2594 2595 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2596 2597 /* Cleanup memory that's no longer used. */ 2598 g_array_free(table_offsets, true); 2599 g_free(slic_oem.id); 2600 g_free(slic_oem.table_id); 2601 } 2602 2603 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2604 { 2605 uint32_t size = acpi_data_len(data); 2606 2607 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2608 memory_region_ram_resize(mr, size, &error_abort); 2609 2610 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2611 memory_region_set_dirty(mr, 0, size); 2612 } 2613 2614 static void acpi_build_update(void *build_opaque) 2615 { 2616 AcpiBuildState *build_state = build_opaque; 2617 AcpiBuildTables tables; 2618 2619 /* No state to update or already patched? Nothing to do. */ 2620 if (!build_state || build_state->patched) { 2621 return; 2622 } 2623 build_state->patched = 1; 2624 2625 acpi_build_tables_init(&tables); 2626 2627 acpi_build(&tables, MACHINE(qdev_get_machine())); 2628 2629 acpi_ram_update(build_state->table_mr, tables.table_data); 2630 2631 if (build_state->rsdp) { 2632 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2633 } else { 2634 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2635 } 2636 2637 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2638 acpi_build_tables_cleanup(&tables, true); 2639 } 2640 2641 static void acpi_build_reset(void *build_opaque) 2642 { 2643 AcpiBuildState *build_state = build_opaque; 2644 build_state->patched = 0; 2645 } 2646 2647 static const VMStateDescription vmstate_acpi_build = { 2648 .name = "acpi_build", 2649 .version_id = 1, 2650 .minimum_version_id = 1, 2651 .fields = (VMStateField[]) { 2652 VMSTATE_UINT8(patched, AcpiBuildState), 2653 VMSTATE_END_OF_LIST() 2654 }, 2655 }; 2656 2657 void acpi_setup(void) 2658 { 2659 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2660 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2661 X86MachineState *x86ms = X86_MACHINE(pcms); 2662 AcpiBuildTables tables; 2663 AcpiBuildState *build_state; 2664 Object *vmgenid_dev; 2665 #ifdef CONFIG_TPM 2666 TPMIf *tpm; 2667 static FwCfgTPMConfig tpm_config; 2668 #endif 2669 2670 if (!x86ms->fw_cfg) { 2671 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2672 return; 2673 } 2674 2675 if (!pcms->acpi_build_enabled) { 2676 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2677 return; 2678 } 2679 2680 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2681 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2682 return; 2683 } 2684 2685 build_state = g_malloc0(sizeof *build_state); 2686 2687 acpi_build_tables_init(&tables); 2688 acpi_build(&tables, MACHINE(pcms)); 2689 2690 /* Now expose it all to Guest */ 2691 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2692 build_state, tables.table_data, 2693 ACPI_BUILD_TABLE_FILE); 2694 assert(build_state->table_mr != NULL); 2695 2696 build_state->linker_mr = 2697 acpi_add_rom_blob(acpi_build_update, build_state, 2698 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2699 2700 #ifdef CONFIG_TPM 2701 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2702 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2703 2704 tpm = tpm_find(); 2705 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2706 tpm_config = (FwCfgTPMConfig) { 2707 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2708 .tpm_version = tpm_get_version(tpm), 2709 .tpmppi_version = TPM_PPI_VERSION_1_30 2710 }; 2711 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2712 &tpm_config, sizeof tpm_config); 2713 } 2714 #endif 2715 2716 vmgenid_dev = find_vmgenid_dev(); 2717 if (vmgenid_dev) { 2718 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2719 tables.vmgenid); 2720 } 2721 2722 if (!pcmc->rsdp_in_ram) { 2723 /* 2724 * Keep for compatibility with old machine types. 2725 * Though RSDP is small, its contents isn't immutable, so 2726 * we'll update it along with the rest of tables on guest access. 2727 */ 2728 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2729 2730 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2731 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2732 acpi_build_update, NULL, build_state, 2733 build_state->rsdp, rsdp_size, true); 2734 build_state->rsdp_mr = NULL; 2735 } else { 2736 build_state->rsdp = NULL; 2737 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2738 build_state, tables.rsdp, 2739 ACPI_BUILD_RSDP_FILE); 2740 } 2741 2742 qemu_register_reset(acpi_build_reset, build_state); 2743 acpi_build_reset(build_state); 2744 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2745 2746 /* Cleanup tables but don't free the memory: we track it 2747 * in build_state. 2748 */ 2749 acpi_build_tables_cleanup(&tables, false); 2750 } 2751