1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/range.h" 30 #include "qemu/error-report.h" 31 #include "hw/pci/pci.h" 32 #include "qom/cpu.h" 33 #include "hw/i386/pc.h" 34 #include "target-i386/cpu.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/i386/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 46 /* Supported chipsets: */ 47 #include "hw/acpi/piix4.h" 48 #include "hw/acpi/pcihp.h" 49 #include "hw/i386/ich9.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/q35.h" 52 #include "hw/i386/intel_iommu.h" 53 54 #include "hw/i386/q35-acpi-dsdt.hex" 55 #include "hw/i386/acpi-dsdt.hex" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 64 * a little bit, there should be plenty of free space since the DSDT 65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 66 */ 67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 68 #define ACPI_BUILD_ALIGN_SIZE 0x1000 69 70 #define ACPI_BUILD_TABLE_SIZE 0x20000 71 72 /* Reserve RAM space for tables: add another order of magnitude. */ 73 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000 74 75 /* #define DEBUG_ACPI_BUILD */ 76 #ifdef DEBUG_ACPI_BUILD 77 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 78 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 79 #else 80 #define ACPI_BUILD_DPRINTF(fmt, ...) 81 #endif 82 83 typedef struct AcpiCpuInfo { 84 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 85 } AcpiCpuInfo; 86 87 typedef struct AcpiMcfgInfo { 88 uint64_t mcfg_base; 89 uint32_t mcfg_size; 90 } AcpiMcfgInfo; 91 92 typedef struct AcpiPmInfo { 93 bool s3_disabled; 94 bool s4_disabled; 95 bool pcihp_bridge_en; 96 uint8_t s4_val; 97 uint16_t sci_int; 98 uint8_t acpi_enable_cmd; 99 uint8_t acpi_disable_cmd; 100 uint32_t gpe0_blk; 101 uint32_t gpe0_blk_len; 102 uint32_t io_base; 103 uint16_t cpu_hp_io_base; 104 uint16_t cpu_hp_io_len; 105 uint16_t mem_hp_io_base; 106 uint16_t mem_hp_io_len; 107 uint16_t pcihp_io_base; 108 uint16_t pcihp_io_len; 109 } AcpiPmInfo; 110 111 typedef struct AcpiMiscInfo { 112 bool has_hpet; 113 bool has_tpm; 114 const unsigned char *dsdt_code; 115 unsigned dsdt_size; 116 uint16_t pvpanic_port; 117 uint16_t applesmc_io_base; 118 } AcpiMiscInfo; 119 120 typedef struct AcpiBuildPciBusHotplugState { 121 GArray *device_table; 122 GArray *notify_table; 123 struct AcpiBuildPciBusHotplugState *parent; 124 bool pcihp_bridge_en; 125 } AcpiBuildPciBusHotplugState; 126 127 static void acpi_get_dsdt(AcpiMiscInfo *info) 128 { 129 Object *piix = piix4_pm_find(); 130 Object *lpc = ich9_lpc_find(); 131 assert(!!piix != !!lpc); 132 133 if (piix) { 134 info->dsdt_code = AcpiDsdtAmlCode; 135 info->dsdt_size = sizeof AcpiDsdtAmlCode; 136 } 137 if (lpc) { 138 info->dsdt_code = Q35AcpiDsdtAmlCode; 139 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 140 } 141 } 142 143 static 144 int acpi_add_cpu_info(Object *o, void *opaque) 145 { 146 AcpiCpuInfo *cpu = opaque; 147 uint64_t apic_id; 148 149 if (object_dynamic_cast(o, TYPE_CPU)) { 150 apic_id = object_property_get_int(o, "apic-id", NULL); 151 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 152 153 set_bit(apic_id, cpu->found_cpus); 154 } 155 156 object_child_foreach(o, acpi_add_cpu_info, opaque); 157 return 0; 158 } 159 160 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 161 { 162 Object *root = object_get_root(); 163 164 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 165 object_child_foreach(root, acpi_add_cpu_info, cpu); 166 } 167 168 static void acpi_get_pm_info(AcpiPmInfo *pm) 169 { 170 Object *piix = piix4_pm_find(); 171 Object *lpc = ich9_lpc_find(); 172 Object *obj = NULL; 173 QObject *o; 174 175 pm->pcihp_io_base = 0; 176 pm->pcihp_io_len = 0; 177 if (piix) { 178 obj = piix; 179 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 180 pm->pcihp_io_base = 181 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 182 pm->pcihp_io_len = 183 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 184 } 185 if (lpc) { 186 obj = lpc; 187 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 188 } 189 assert(obj); 190 191 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 192 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 193 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 194 195 /* Fill in optional s3/s4 related properties */ 196 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 197 if (o) { 198 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 199 } else { 200 pm->s3_disabled = false; 201 } 202 qobject_decref(o); 203 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 204 if (o) { 205 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 206 } else { 207 pm->s4_disabled = false; 208 } 209 qobject_decref(o); 210 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 211 if (o) { 212 pm->s4_val = qint_get_int(qobject_to_qint(o)); 213 } else { 214 pm->s4_val = false; 215 } 216 qobject_decref(o); 217 218 /* Fill in mandatory properties */ 219 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 220 221 pm->acpi_enable_cmd = object_property_get_int(obj, 222 ACPI_PM_PROP_ACPI_ENABLE_CMD, 223 NULL); 224 pm->acpi_disable_cmd = object_property_get_int(obj, 225 ACPI_PM_PROP_ACPI_DISABLE_CMD, 226 NULL); 227 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 228 NULL); 229 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 230 NULL); 231 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 232 NULL); 233 pm->pcihp_bridge_en = 234 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 235 NULL); 236 } 237 238 static void acpi_get_misc_info(AcpiMiscInfo *info) 239 { 240 info->has_hpet = hpet_find(); 241 info->has_tpm = tpm_find(); 242 info->pvpanic_port = pvpanic_port(); 243 info->applesmc_io_base = applesmc_port(); 244 } 245 246 static void acpi_get_pci_info(PcPciInfo *info) 247 { 248 Object *pci_host; 249 bool ambiguous; 250 251 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 252 g_assert(!ambiguous); 253 g_assert(pci_host); 254 255 info->w32.begin = object_property_get_int(pci_host, 256 PCI_HOST_PROP_PCI_HOLE_START, 257 NULL); 258 info->w32.end = object_property_get_int(pci_host, 259 PCI_HOST_PROP_PCI_HOLE_END, 260 NULL); 261 info->w64.begin = object_property_get_int(pci_host, 262 PCI_HOST_PROP_PCI_HOLE64_START, 263 NULL); 264 info->w64.end = object_property_get_int(pci_host, 265 PCI_HOST_PROP_PCI_HOLE64_END, 266 NULL); 267 } 268 269 #define ACPI_BUILD_APPNAME "Bochs" 270 #define ACPI_BUILD_APPNAME6 "BOCHS " 271 #define ACPI_BUILD_APPNAME4 "BXPC" 272 273 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables" 274 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp" 275 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log" 276 277 static void 278 build_header(GArray *linker, GArray *table_data, 279 AcpiTableHeader *h, const char *sig, int len, uint8_t rev) 280 { 281 memcpy(&h->signature, sig, 4); 282 h->length = cpu_to_le32(len); 283 h->revision = rev; 284 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6); 285 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4); 286 memcpy(h->oem_table_id + 4, sig, 4); 287 h->oem_revision = cpu_to_le32(1); 288 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4); 289 h->asl_compiler_revision = cpu_to_le32(1); 290 h->checksum = 0; 291 /* Checksum to be filled in by Guest linker */ 292 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE, 293 table_data->data, h, len, &h->checksum); 294 } 295 296 /* End here */ 297 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 298 299 static inline void *acpi_data_push(GArray *table_data, unsigned size) 300 { 301 unsigned off = table_data->len; 302 g_array_set_size(table_data, off + size); 303 return table_data->data + off; 304 } 305 306 static unsigned acpi_data_len(GArray *table) 307 { 308 #if GLIB_CHECK_VERSION(2, 22, 0) 309 assert(g_array_get_element_size(table) == 1); 310 #endif 311 return table->len; 312 } 313 314 static void acpi_align_size(GArray *blob, unsigned align) 315 { 316 /* Align size to multiple of given size. This reduces the chance 317 * we need to change size in the future (breaking cross version migration). 318 */ 319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 320 } 321 322 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data) 323 { 324 uint32_t offset = cpu_to_le32(table_data->len); 325 g_array_append_val(table_offsets, offset); 326 } 327 328 /* FACS */ 329 static void 330 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 331 { 332 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 333 memcpy(&facs->signature, "FACS", 4); 334 facs->length = cpu_to_le32(sizeof(*facs)); 335 } 336 337 /* Load chipset information in FADT */ 338 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 339 { 340 fadt->model = 1; 341 fadt->reserved1 = 0; 342 fadt->sci_int = cpu_to_le16(pm->sci_int); 343 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 344 fadt->acpi_enable = pm->acpi_enable_cmd; 345 fadt->acpi_disable = pm->acpi_disable_cmd; 346 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 347 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 348 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 349 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 350 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 351 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 352 fadt->pm1_evt_len = 4; 353 fadt->pm1_cnt_len = 2; 354 fadt->pm_tmr_len = 4; 355 fadt->gpe0_blk_len = pm->gpe0_blk_len; 356 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 357 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 358 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 359 (1 << ACPI_FADT_F_PROC_C1) | 360 (1 << ACPI_FADT_F_SLP_BUTTON) | 361 (1 << ACPI_FADT_F_RTC_S4)); 362 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 363 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 364 * For more than 8 CPUs, "Clustered Logical" mode has to be used 365 */ 366 if (max_cpus > 8) { 367 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 368 } 369 } 370 371 372 /* FADT */ 373 static void 374 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 375 unsigned facs, unsigned dsdt) 376 { 377 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 378 379 fadt->firmware_ctrl = cpu_to_le32(facs); 380 /* FACS address to be filled by Guest linker */ 381 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 382 ACPI_BUILD_TABLE_FILE, 383 table_data, &fadt->firmware_ctrl, 384 sizeof fadt->firmware_ctrl); 385 386 fadt->dsdt = cpu_to_le32(dsdt); 387 /* DSDT address to be filled by Guest linker */ 388 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 389 ACPI_BUILD_TABLE_FILE, 390 table_data, &fadt->dsdt, 391 sizeof fadt->dsdt); 392 393 fadt_setup(fadt, pm); 394 395 build_header(linker, table_data, 396 (void *)fadt, "FACP", sizeof(*fadt), 1); 397 } 398 399 static void 400 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 401 PcGuestInfo *guest_info) 402 { 403 int madt_start = table_data->len; 404 405 AcpiMultipleApicTable *madt; 406 AcpiMadtIoApic *io_apic; 407 AcpiMadtIntsrcovr *intsrcovr; 408 AcpiMadtLocalNmi *local_nmi; 409 int i; 410 411 madt = acpi_data_push(table_data, sizeof *madt); 412 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 413 madt->flags = cpu_to_le32(1); 414 415 for (i = 0; i < guest_info->apic_id_limit; i++) { 416 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 417 apic->type = ACPI_APIC_PROCESSOR; 418 apic->length = sizeof(*apic); 419 apic->processor_id = i; 420 apic->local_apic_id = i; 421 if (test_bit(i, cpu->found_cpus)) { 422 apic->flags = cpu_to_le32(1); 423 } else { 424 apic->flags = cpu_to_le32(0); 425 } 426 } 427 io_apic = acpi_data_push(table_data, sizeof *io_apic); 428 io_apic->type = ACPI_APIC_IO; 429 io_apic->length = sizeof(*io_apic); 430 #define ACPI_BUILD_IOAPIC_ID 0x0 431 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 432 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 433 io_apic->interrupt = cpu_to_le32(0); 434 435 if (guest_info->apic_xrupt_override) { 436 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 437 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 438 intsrcovr->length = sizeof(*intsrcovr); 439 intsrcovr->source = 0; 440 intsrcovr->gsi = cpu_to_le32(2); 441 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 442 } 443 for (i = 1; i < 16; i++) { 444 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 445 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 446 /* No need for a INT source override structure. */ 447 continue; 448 } 449 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 450 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 451 intsrcovr->length = sizeof(*intsrcovr); 452 intsrcovr->source = i; 453 intsrcovr->gsi = cpu_to_le32(i); 454 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 455 } 456 457 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 458 local_nmi->type = ACPI_APIC_LOCAL_NMI; 459 local_nmi->length = sizeof(*local_nmi); 460 local_nmi->processor_id = 0xff; /* all processors */ 461 local_nmi->flags = cpu_to_le16(0); 462 local_nmi->lint = 1; /* ACPI_LINT1 */ 463 464 build_header(linker, table_data, 465 (void *)(table_data->data + madt_start), "APIC", 466 table_data->len - madt_start, 1); 467 } 468 469 #include "hw/i386/ssdt-tpm.hex" 470 471 /* Assign BSEL property to all buses. In the future, this can be changed 472 * to only assign to buses that support hotplug. 473 */ 474 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 475 { 476 unsigned *bsel_alloc = opaque; 477 unsigned *bus_bsel; 478 479 if (qbus_is_hotpluggable(BUS(bus))) { 480 bus_bsel = g_malloc(sizeof *bus_bsel); 481 482 *bus_bsel = (*bsel_alloc)++; 483 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 484 bus_bsel, NULL); 485 } 486 487 return bsel_alloc; 488 } 489 490 static void acpi_set_pci_info(void) 491 { 492 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 493 unsigned bsel_alloc = 0; 494 495 if (bus) { 496 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 497 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 498 } 499 } 500 501 static void build_append_pcihp_notify_entry(Aml *method, int slot) 502 { 503 Aml *if_ctx; 504 int32_t devfn = PCI_DEVFN(slot, 0); 505 506 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); 507 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 508 aml_append(method, if_ctx); 509 } 510 511 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 512 bool pcihp_bridge_en) 513 { 514 Aml *dev, *notify_method, *method; 515 QObject *bsel; 516 PCIBus *sec; 517 int i; 518 519 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 520 if (bsel) { 521 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 522 523 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 524 notify_method = aml_method("DVNT", 2); 525 } 526 527 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 528 DeviceClass *dc; 529 PCIDeviceClass *pc; 530 PCIDevice *pdev = bus->devices[i]; 531 int slot = PCI_SLOT(i); 532 bool hotplug_enabled_dev; 533 bool bridge_in_acpi; 534 535 if (!pdev) { 536 if (bsel) { /* add hotplug slots for non present devices */ 537 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 538 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 539 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 540 method = aml_method("_EJ0", 1); 541 aml_append(method, 542 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 543 ); 544 aml_append(dev, method); 545 aml_append(parent_scope, dev); 546 547 build_append_pcihp_notify_entry(notify_method, slot); 548 } 549 continue; 550 } 551 552 pc = PCI_DEVICE_GET_CLASS(pdev); 553 dc = DEVICE_GET_CLASS(pdev); 554 555 /* When hotplug for bridges is enabled, bridges are 556 * described in ACPI separately (see build_pci_bus_end). 557 * In this case they aren't themselves hot-pluggable. 558 * Hotplugged bridges *are* hot-pluggable. 559 */ 560 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 561 !DEVICE(pdev)->hotplugged; 562 563 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 564 565 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 566 continue; 567 } 568 569 /* start to compose PCI slot descriptor */ 570 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 571 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 572 573 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 574 /* add VGA specific AML methods */ 575 int s3d; 576 577 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 578 s3d = 3; 579 } else { 580 s3d = 0; 581 } 582 583 method = aml_method("_S1D", 0); 584 aml_append(method, aml_return(aml_int(0))); 585 aml_append(dev, method); 586 587 method = aml_method("_S2D", 0); 588 aml_append(method, aml_return(aml_int(0))); 589 aml_append(dev, method); 590 591 method = aml_method("_S3D", 0); 592 aml_append(method, aml_return(aml_int(s3d))); 593 aml_append(dev, method); 594 } else if (hotplug_enabled_dev) { 595 /* add _SUN/_EJ0 to make slot hotpluggable */ 596 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 597 598 method = aml_method("_EJ0", 1); 599 aml_append(method, 600 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 601 ); 602 aml_append(dev, method); 603 604 if (bsel) { 605 build_append_pcihp_notify_entry(notify_method, slot); 606 } 607 } else if (bridge_in_acpi) { 608 /* 609 * device is coldplugged bridge, 610 * add child device descriptions into its scope 611 */ 612 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 613 614 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 615 } 616 /* slot descriptor has been composed, add it into parent context */ 617 aml_append(parent_scope, dev); 618 } 619 620 if (bsel) { 621 aml_append(parent_scope, notify_method); 622 } 623 624 /* Append PCNT method to notify about events on local and child buses. 625 * Add unconditionally for root since DSDT expects it. 626 */ 627 method = aml_method("PCNT", 0); 628 629 /* If bus supports hotplug select it and notify about local events */ 630 if (bsel) { 631 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 632 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 633 aml_append(method, 634 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 635 ); 636 aml_append(method, 637 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 638 ); 639 } 640 641 /* Notify about child bus events in any case */ 642 if (pcihp_bridge_en) { 643 QLIST_FOREACH(sec, &bus->child, sibling) { 644 int32_t devfn = sec->parent_dev->devfn; 645 646 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 647 } 648 } 649 aml_append(parent_scope, method); 650 } 651 652 static void 653 build_ssdt(GArray *table_data, GArray *linker, 654 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 655 PcPciInfo *pci, PcGuestInfo *guest_info) 656 { 657 MachineState *machine = MACHINE(qdev_get_machine()); 658 uint32_t nr_mem = machine->ram_slots; 659 unsigned acpi_cpus = guest_info->apic_id_limit; 660 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 661 int i; 662 663 ssdt = init_aml_allocator(); 664 /* The current AML generator can cover the APIC ID range [0..255], 665 * inclusive, for VCPU hotplug. */ 666 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 667 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 668 669 /* Reserve space for header */ 670 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 671 672 scope = aml_scope("\\_SB.PCI0"); 673 /* build PCI0._CRS */ 674 crs = aml_resource_template(); 675 aml_append(crs, 676 aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, 677 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); 678 aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 679 680 aml_append(crs, 681 aml_word_io(aml_min_fixed, aml_max_fixed, 682 aml_pos_decode, aml_entire_range, 683 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 684 aml_append(crs, 685 aml_word_io(aml_min_fixed, aml_max_fixed, 686 aml_pos_decode, aml_entire_range, 687 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 688 aml_append(crs, 689 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 690 aml_cacheable, aml_ReadWrite, 691 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 692 aml_append(crs, 693 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 694 aml_non_cacheable, aml_ReadWrite, 695 0, pci->w32.begin, pci->w32.end - 1, 0, 696 pci->w32.end - pci->w32.begin)); 697 if (pci->w64.begin) { 698 aml_append(crs, 699 aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 700 aml_cacheable, aml_ReadWrite, 701 0, pci->w64.begin, pci->w64.end - 1, 0, 702 pci->w64.end - pci->w64.begin)); 703 } 704 aml_append(scope, aml_name_decl("_CRS", crs)); 705 706 /* reserve GPE0 block resources */ 707 dev = aml_device("GPE0"); 708 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 709 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 710 /* device present, functioning, decoding, not shown in UI */ 711 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 712 crs = aml_resource_template(); 713 aml_append(crs, 714 aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 715 ); 716 aml_append(dev, aml_name_decl("_CRS", crs)); 717 aml_append(scope, dev); 718 719 /* reserve PCIHP resources */ 720 if (pm->pcihp_io_len) { 721 dev = aml_device("PHPR"); 722 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 723 aml_append(dev, 724 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 725 /* device present, functioning, decoding, not shown in UI */ 726 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 727 crs = aml_resource_template(); 728 aml_append(crs, 729 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 730 pm->pcihp_io_len) 731 ); 732 aml_append(dev, aml_name_decl("_CRS", crs)); 733 aml_append(scope, dev); 734 } 735 aml_append(ssdt, scope); 736 737 /* create S3_ / S4_ / S5_ packages if necessary */ 738 scope = aml_scope("\\"); 739 if (!pm->s3_disabled) { 740 pkg = aml_package(4); 741 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 742 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 743 aml_append(pkg, aml_int(0)); /* reserved */ 744 aml_append(pkg, aml_int(0)); /* reserved */ 745 aml_append(scope, aml_name_decl("_S3", pkg)); 746 } 747 748 if (!pm->s4_disabled) { 749 pkg = aml_package(4); 750 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 751 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 752 aml_append(pkg, aml_int(pm->s4_val)); 753 aml_append(pkg, aml_int(0)); /* reserved */ 754 aml_append(pkg, aml_int(0)); /* reserved */ 755 aml_append(scope, aml_name_decl("_S4", pkg)); 756 } 757 758 pkg = aml_package(4); 759 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 760 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 761 aml_append(pkg, aml_int(0)); /* reserved */ 762 aml_append(pkg, aml_int(0)); /* reserved */ 763 aml_append(scope, aml_name_decl("_S5", pkg)); 764 aml_append(ssdt, scope); 765 766 if (misc->applesmc_io_base) { 767 scope = aml_scope("\\_SB.PCI0.ISA"); 768 dev = aml_device("SMC"); 769 770 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 771 /* device present, functioning, decoding, not shown in UI */ 772 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 773 774 crs = aml_resource_template(); 775 aml_append(crs, 776 aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base, 777 0x01, APPLESMC_MAX_DATA_LENGTH) 778 ); 779 aml_append(crs, aml_irq_no_flags(6)); 780 aml_append(dev, aml_name_decl("_CRS", crs)); 781 782 aml_append(scope, dev); 783 aml_append(ssdt, scope); 784 } 785 786 if (misc->pvpanic_port) { 787 scope = aml_scope("\\_SB.PCI0.ISA"); 788 789 dev = aml_device("PEVR"); 790 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 791 792 crs = aml_resource_template(); 793 aml_append(crs, 794 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 795 ); 796 aml_append(dev, aml_name_decl("_CRS", crs)); 797 798 aml_append(dev, aml_operation_region("PEOR", aml_system_io, 799 misc->pvpanic_port, 1)); 800 field = aml_field("PEOR", aml_byte_acc); 801 aml_append(field, aml_named_field("PEPT", 8)); 802 aml_append(dev, field); 803 804 method = aml_method("RDPT", 0); 805 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 806 aml_append(method, aml_return(aml_local(0))); 807 aml_append(dev, method); 808 809 method = aml_method("WRPT", 1); 810 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 811 aml_append(dev, method); 812 813 aml_append(scope, dev); 814 aml_append(ssdt, scope); 815 } 816 817 sb_scope = aml_scope("_SB"); 818 { 819 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 820 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 821 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 822 aml_append(dev, 823 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 824 ); 825 /* device present, functioning, decoding, not shown in UI */ 826 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 827 crs = aml_resource_template(); 828 aml_append(crs, 829 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 830 pm->cpu_hp_io_len) 831 ); 832 aml_append(dev, aml_name_decl("_CRS", crs)); 833 aml_append(sb_scope, dev); 834 /* declare CPU hotplug MMIO region and PRS field to access it */ 835 aml_append(sb_scope, aml_operation_region( 836 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 837 field = aml_field("PRST", aml_byte_acc); 838 aml_append(field, aml_named_field("PRS", 256)); 839 aml_append(sb_scope, field); 840 841 /* build Processor object for each processor */ 842 for (i = 0; i < acpi_cpus; i++) { 843 dev = aml_processor(i, 0, 0, "CP%.02X", i); 844 845 method = aml_method("_MAT", 0); 846 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 847 aml_append(dev, method); 848 849 method = aml_method("_STA", 0); 850 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 851 aml_append(dev, method); 852 853 method = aml_method("_EJ0", 1); 854 aml_append(method, 855 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 856 ); 857 aml_append(dev, method); 858 859 aml_append(sb_scope, dev); 860 } 861 862 /* build this code: 863 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 864 */ 865 /* Arg0 = Processor ID = APIC ID */ 866 method = aml_method("NTFY", 2); 867 for (i = 0; i < acpi_cpus; i++) { 868 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 869 aml_append(ifctx, 870 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 871 ); 872 aml_append(method, ifctx); 873 } 874 aml_append(sb_scope, method); 875 876 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 877 * 878 * Note: The ability to create variable-sized packages was first 879 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 880 * ith up to 255 elements. Windows guests up to win2k8 fail when 881 * VarPackageOp is used. 882 */ 883 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 884 aml_varpackage(acpi_cpus); 885 886 for (i = 0; i < acpi_cpus; i++) { 887 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 888 aml_append(pkg, aml_int(b)); 889 } 890 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 891 892 /* build memory devices */ 893 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 894 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 895 aml_append(scope, 896 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 897 ); 898 899 crs = aml_resource_template(); 900 aml_append(crs, 901 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 902 pm->mem_hp_io_len) 903 ); 904 aml_append(scope, aml_name_decl("_CRS", crs)); 905 906 aml_append(scope, aml_operation_region( 907 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io, 908 pm->mem_hp_io_base, pm->mem_hp_io_len) 909 ); 910 911 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); 912 aml_append(field, /* read only */ 913 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 914 aml_append(field, /* read only */ 915 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 916 aml_append(field, /* read only */ 917 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 918 aml_append(field, /* read only */ 919 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 920 aml_append(field, /* read only */ 921 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 922 aml_append(scope, field); 923 924 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc); 925 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 926 aml_append(field, /* 1 if enabled, read only */ 927 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 928 aml_append(field, 929 /*(read) 1 if has a insert event. (write) 1 to clear event */ 930 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 931 aml_append(scope, field); 932 933 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); 934 aml_append(field, /* DIMM selector, write only */ 935 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 936 aml_append(field, /* _OST event code, write only */ 937 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 938 aml_append(field, /* _OST status code, write only */ 939 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 940 aml_append(scope, field); 941 942 aml_append(sb_scope, scope); 943 944 for (i = 0; i < nr_mem; i++) { 945 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 946 const char *s; 947 948 dev = aml_device("MP%02X", i); 949 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 950 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 951 952 method = aml_method("_CRS", 0); 953 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 954 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 955 aml_append(dev, method); 956 957 method = aml_method("_STA", 0); 958 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 959 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 960 aml_append(dev, method); 961 962 method = aml_method("_PXM", 0); 963 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 964 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 965 aml_append(dev, method); 966 967 method = aml_method("_OST", 3); 968 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 969 aml_append(method, aml_return(aml_call4( 970 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 971 ))); 972 aml_append(dev, method); 973 974 aml_append(sb_scope, dev); 975 } 976 977 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 978 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... 979 */ 980 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); 981 for (i = 0; i < nr_mem; i++) { 982 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 983 aml_append(ifctx, 984 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 985 ); 986 aml_append(method, ifctx); 987 } 988 aml_append(sb_scope, method); 989 990 { 991 Object *pci_host; 992 PCIBus *bus = NULL; 993 bool ambiguous; 994 995 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 996 if (!ambiguous && pci_host) { 997 bus = PCI_HOST_BRIDGE(pci_host)->bus; 998 } 999 1000 if (bus) { 1001 Aml *scope = aml_scope("PCI0"); 1002 /* Scan all PCI buses. Generate tables to support hotplug. */ 1003 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1004 aml_append(sb_scope, scope); 1005 } 1006 } 1007 aml_append(ssdt, sb_scope); 1008 } 1009 1010 /* copy AML table into ACPI tables blob and patch header there */ 1011 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 1012 build_header(linker, table_data, 1013 (void *)(table_data->data + table_data->len - ssdt->buf->len), 1014 "SSDT", ssdt->buf->len, 1); 1015 free_aml_allocator(); 1016 } 1017 1018 static void 1019 build_hpet(GArray *table_data, GArray *linker) 1020 { 1021 Acpi20Hpet *hpet; 1022 1023 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1024 /* Note timer_block_id value must be kept in sync with value advertised by 1025 * emulated hpet 1026 */ 1027 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1028 hpet->addr.address = cpu_to_le64(HPET_BASE); 1029 build_header(linker, table_data, 1030 (void *)hpet, "HPET", sizeof(*hpet), 1); 1031 } 1032 1033 static void 1034 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 1035 { 1036 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1037 uint64_t log_area_start_address = acpi_data_len(tcpalog); 1038 1039 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1040 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1041 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 1042 1043 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 1044 false /* high memory */); 1045 1046 /* log area start address to be filled by Guest linker */ 1047 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1048 ACPI_BUILD_TPMLOG_FILE, 1049 table_data, &tcpa->log_area_start_address, 1050 sizeof(tcpa->log_area_start_address)); 1051 1052 build_header(linker, table_data, 1053 (void *)tcpa, "TCPA", sizeof(*tcpa), 2); 1054 1055 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1056 } 1057 1058 static void 1059 build_tpm_ssdt(GArray *table_data, GArray *linker) 1060 { 1061 void *tpm_ptr; 1062 1063 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); 1064 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); 1065 } 1066 1067 typedef enum { 1068 MEM_AFFINITY_NOFLAGS = 0, 1069 MEM_AFFINITY_ENABLED = (1 << 0), 1070 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1071 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1072 } MemoryAffinityFlags; 1073 1074 static void 1075 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1076 uint64_t len, int node, MemoryAffinityFlags flags) 1077 { 1078 numamem->type = ACPI_SRAT_MEMORY; 1079 numamem->length = sizeof(*numamem); 1080 memset(numamem->proximity, 0, 4); 1081 numamem->proximity[0] = node; 1082 numamem->flags = cpu_to_le32(flags); 1083 numamem->base_addr = cpu_to_le64(base); 1084 numamem->range_length = cpu_to_le64(len); 1085 } 1086 1087 static void 1088 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1089 { 1090 AcpiSystemResourceAffinityTable *srat; 1091 AcpiSratProcessorAffinity *core; 1092 AcpiSratMemoryAffinity *numamem; 1093 1094 int i; 1095 uint64_t curnode; 1096 int srat_start, numa_start, slots; 1097 uint64_t mem_len, mem_base, next_base; 1098 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1099 ram_addr_t hotplugabble_address_space_size = 1100 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1101 NULL); 1102 1103 srat_start = table_data->len; 1104 1105 srat = acpi_data_push(table_data, sizeof *srat); 1106 srat->reserved1 = cpu_to_le32(1); 1107 core = (void *)(srat + 1); 1108 1109 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1110 core = acpi_data_push(table_data, sizeof *core); 1111 core->type = ACPI_SRAT_PROCESSOR; 1112 core->length = sizeof(*core); 1113 core->local_apic_id = i; 1114 curnode = guest_info->node_cpu[i]; 1115 core->proximity_lo = curnode; 1116 memset(core->proximity_hi, 0, 3); 1117 core->local_sapic_eid = 0; 1118 core->flags = cpu_to_le32(1); 1119 } 1120 1121 1122 /* the memory map is a bit tricky, it contains at least one hole 1123 * from 640k-1M and possibly another one from 3.5G-4G. 1124 */ 1125 next_base = 0; 1126 numa_start = table_data->len; 1127 1128 numamem = acpi_data_push(table_data, sizeof *numamem); 1129 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1130 next_base = 1024 * 1024; 1131 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1132 mem_base = next_base; 1133 mem_len = guest_info->node_mem[i - 1]; 1134 if (i == 1) { 1135 mem_len -= 1024 * 1024; 1136 } 1137 next_base = mem_base + mem_len; 1138 1139 /* Cut out the ACPI_PCI hole */ 1140 if (mem_base <= guest_info->ram_size_below_4g && 1141 next_base > guest_info->ram_size_below_4g) { 1142 mem_len -= next_base - guest_info->ram_size_below_4g; 1143 if (mem_len > 0) { 1144 numamem = acpi_data_push(table_data, sizeof *numamem); 1145 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1146 MEM_AFFINITY_ENABLED); 1147 } 1148 mem_base = 1ULL << 32; 1149 mem_len = next_base - guest_info->ram_size_below_4g; 1150 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1151 } 1152 numamem = acpi_data_push(table_data, sizeof *numamem); 1153 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1154 MEM_AFFINITY_ENABLED); 1155 } 1156 slots = (table_data->len - numa_start) / sizeof *numamem; 1157 for (; slots < guest_info->numa_nodes + 2; slots++) { 1158 numamem = acpi_data_push(table_data, sizeof *numamem); 1159 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1160 } 1161 1162 /* 1163 * Entry is required for Windows to enable memory hotplug in OS. 1164 * Memory devices may override proximity set by this entry, 1165 * providing _PXM method if necessary. 1166 */ 1167 if (hotplugabble_address_space_size) { 1168 numamem = acpi_data_push(table_data, sizeof *numamem); 1169 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, 1170 hotplugabble_address_space_size, 0, 1171 MEM_AFFINITY_HOTPLUGGABLE | 1172 MEM_AFFINITY_ENABLED); 1173 } 1174 1175 build_header(linker, table_data, 1176 (void *)(table_data->data + srat_start), 1177 "SRAT", 1178 table_data->len - srat_start, 1); 1179 } 1180 1181 static void 1182 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1183 { 1184 AcpiTableMcfg *mcfg; 1185 const char *sig; 1186 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1187 1188 mcfg = acpi_data_push(table_data, len); 1189 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1190 /* Only a single allocation so no need to play with segments */ 1191 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1192 mcfg->allocation[0].start_bus_number = 0; 1193 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1194 1195 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1196 * To avoid table size changes (which create migration issues), 1197 * always create the table even if there are no allocations, 1198 * but set the signature to a reserved value in this case. 1199 * ACPI spec requires OSPMs to ignore such tables. 1200 */ 1201 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1202 /* Reserved signature: ignored by OSPM */ 1203 sig = "QEMU"; 1204 } else { 1205 sig = "MCFG"; 1206 } 1207 build_header(linker, table_data, (void *)mcfg, sig, len, 1); 1208 } 1209 1210 static void 1211 build_dmar_q35(GArray *table_data, GArray *linker) 1212 { 1213 int dmar_start = table_data->len; 1214 1215 AcpiTableDmar *dmar; 1216 AcpiDmarHardwareUnit *drhd; 1217 1218 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1219 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1220 dmar->flags = 0; /* No intr_remap for now */ 1221 1222 /* DMAR Remapping Hardware Unit Definition structure */ 1223 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1224 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1225 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1226 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1227 drhd->pci_segment = cpu_to_le16(0); 1228 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1229 1230 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1231 "DMAR", table_data->len - dmar_start, 1); 1232 } 1233 1234 static void 1235 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1236 { 1237 AcpiTableHeader *dsdt; 1238 1239 assert(misc->dsdt_code && misc->dsdt_size); 1240 1241 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1242 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1243 1244 memset(dsdt, 0, sizeof *dsdt); 1245 build_header(linker, table_data, dsdt, "DSDT", 1246 misc->dsdt_size, 1); 1247 } 1248 1249 /* Build final rsdt table */ 1250 static void 1251 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets) 1252 { 1253 AcpiRsdtDescriptorRev1 *rsdt; 1254 size_t rsdt_len; 1255 int i; 1256 1257 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len; 1258 rsdt = acpi_data_push(table_data, rsdt_len); 1259 memcpy(rsdt->table_offset_entry, table_offsets->data, 1260 sizeof(uint32_t) * table_offsets->len); 1261 for (i = 0; i < table_offsets->len; ++i) { 1262 /* rsdt->table_offset_entry to be filled by Guest linker */ 1263 bios_linker_loader_add_pointer(linker, 1264 ACPI_BUILD_TABLE_FILE, 1265 ACPI_BUILD_TABLE_FILE, 1266 table_data, &rsdt->table_offset_entry[i], 1267 sizeof(uint32_t)); 1268 } 1269 build_header(linker, table_data, 1270 (void *)rsdt, "RSDT", rsdt_len, 1); 1271 } 1272 1273 static GArray * 1274 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1275 { 1276 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1277 1278 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1279 true /* fseg memory */); 1280 1281 memcpy(&rsdp->signature, "RSD PTR ", 8); 1282 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1283 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1284 /* Address to be filled by Guest linker */ 1285 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1286 ACPI_BUILD_TABLE_FILE, 1287 rsdp_table, &rsdp->rsdt_physical_address, 1288 sizeof rsdp->rsdt_physical_address); 1289 rsdp->checksum = 0; 1290 /* Checksum to be filled by Guest linker */ 1291 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1292 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1293 1294 return rsdp_table; 1295 } 1296 1297 typedef 1298 struct AcpiBuildTables { 1299 GArray *table_data; 1300 GArray *rsdp; 1301 GArray *tcpalog; 1302 GArray *linker; 1303 } AcpiBuildTables; 1304 1305 static inline void acpi_build_tables_init(AcpiBuildTables *tables) 1306 { 1307 tables->rsdp = g_array_new(false, true /* clear */, 1); 1308 tables->table_data = g_array_new(false, true /* clear */, 1); 1309 tables->tcpalog = g_array_new(false, true /* clear */, 1); 1310 tables->linker = bios_linker_loader_init(); 1311 } 1312 1313 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) 1314 { 1315 void *linker_data = bios_linker_loader_cleanup(tables->linker); 1316 g_free(linker_data); 1317 g_array_free(tables->rsdp, true); 1318 g_array_free(tables->table_data, true); 1319 g_array_free(tables->tcpalog, mfre); 1320 } 1321 1322 typedef 1323 struct AcpiBuildState { 1324 /* Copy of table in RAM (for patching). */ 1325 MemoryRegion *table_mr; 1326 /* Is table patched? */ 1327 uint8_t patched; 1328 PcGuestInfo *guest_info; 1329 void *rsdp; 1330 MemoryRegion *rsdp_mr; 1331 MemoryRegion *linker_mr; 1332 } AcpiBuildState; 1333 1334 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1335 { 1336 Object *pci_host; 1337 QObject *o; 1338 bool ambiguous; 1339 1340 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1341 g_assert(!ambiguous); 1342 g_assert(pci_host); 1343 1344 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1345 if (!o) { 1346 return false; 1347 } 1348 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1349 qobject_decref(o); 1350 1351 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1352 assert(o); 1353 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1354 qobject_decref(o); 1355 return true; 1356 } 1357 1358 static bool acpi_has_iommu(void) 1359 { 1360 bool ambiguous; 1361 Object *intel_iommu; 1362 1363 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1364 &ambiguous); 1365 return intel_iommu && !ambiguous; 1366 } 1367 1368 static 1369 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1370 { 1371 GArray *table_offsets; 1372 unsigned facs, ssdt, dsdt, rsdt; 1373 AcpiCpuInfo cpu; 1374 AcpiPmInfo pm; 1375 AcpiMiscInfo misc; 1376 AcpiMcfgInfo mcfg; 1377 PcPciInfo pci; 1378 uint8_t *u; 1379 size_t aml_len = 0; 1380 GArray *tables_blob = tables->table_data; 1381 1382 acpi_get_cpu_info(&cpu); 1383 acpi_get_pm_info(&pm); 1384 acpi_get_dsdt(&misc); 1385 acpi_get_misc_info(&misc); 1386 acpi_get_pci_info(&pci); 1387 1388 table_offsets = g_array_new(false, true /* clear */, 1389 sizeof(uint32_t)); 1390 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1391 1392 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1393 64 /* Ensure FACS is aligned */, 1394 false /* high memory */); 1395 1396 /* 1397 * FACS is pointed to by FADT. 1398 * We place it first since it's the only table that has alignment 1399 * requirements. 1400 */ 1401 facs = tables_blob->len; 1402 build_facs(tables_blob, tables->linker, guest_info); 1403 1404 /* DSDT is pointed to by FADT */ 1405 dsdt = tables_blob->len; 1406 build_dsdt(tables_blob, tables->linker, &misc); 1407 1408 /* Count the size of the DSDT and SSDT, we will need it for legacy 1409 * sizing of ACPI tables. 1410 */ 1411 aml_len += tables_blob->len - dsdt; 1412 1413 /* ACPI tables pointed to by RSDT */ 1414 acpi_add_table(table_offsets, tables_blob); 1415 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1416 1417 ssdt = tables_blob->len; 1418 acpi_add_table(table_offsets, tables_blob); 1419 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1420 guest_info); 1421 aml_len += tables_blob->len - ssdt; 1422 1423 acpi_add_table(table_offsets, tables_blob); 1424 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1425 1426 if (misc.has_hpet) { 1427 acpi_add_table(table_offsets, tables_blob); 1428 build_hpet(tables_blob, tables->linker); 1429 } 1430 if (misc.has_tpm) { 1431 acpi_add_table(table_offsets, tables_blob); 1432 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1433 1434 acpi_add_table(table_offsets, tables_blob); 1435 build_tpm_ssdt(tables_blob, tables->linker); 1436 } 1437 if (guest_info->numa_nodes) { 1438 acpi_add_table(table_offsets, tables_blob); 1439 build_srat(tables_blob, tables->linker, guest_info); 1440 } 1441 if (acpi_get_mcfg(&mcfg)) { 1442 acpi_add_table(table_offsets, tables_blob); 1443 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1444 } 1445 if (acpi_has_iommu()) { 1446 acpi_add_table(table_offsets, tables_blob); 1447 build_dmar_q35(tables_blob, tables->linker); 1448 } 1449 1450 /* Add tables supplied by user (if any) */ 1451 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1452 unsigned len = acpi_table_len(u); 1453 1454 acpi_add_table(table_offsets, tables_blob); 1455 g_array_append_vals(tables_blob, u, len); 1456 } 1457 1458 /* RSDT is pointed to by RSDP */ 1459 rsdt = tables_blob->len; 1460 build_rsdt(tables_blob, tables->linker, table_offsets); 1461 1462 /* RSDP is in FSEG memory, so allocate it separately */ 1463 build_rsdp(tables->rsdp, tables->linker, rsdt); 1464 1465 /* We'll expose it all to Guest so we want to reduce 1466 * chance of size changes. 1467 * 1468 * We used to align the tables to 4k, but of course this would 1469 * too simple to be enough. 4k turned out to be too small an 1470 * alignment very soon, and in fact it is almost impossible to 1471 * keep the table size stable for all (max_cpus, max_memory_slots) 1472 * combinations. So the table size is always 64k for pc-i440fx-2.1 1473 * and we give an error if the table grows beyond that limit. 1474 * 1475 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1476 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1477 * than 2.0 and we can always pad the smaller tables with zeros. We can 1478 * then use the exact size of the 2.0 tables. 1479 * 1480 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1481 */ 1482 if (guest_info->legacy_acpi_table_size) { 1483 /* Subtracting aml_len gives the size of fixed tables. Then add the 1484 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1485 */ 1486 int legacy_aml_len = 1487 guest_info->legacy_acpi_table_size + 1488 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1489 int legacy_table_size = 1490 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1491 ACPI_BUILD_ALIGN_SIZE); 1492 if (tables_blob->len > legacy_table_size) { 1493 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1494 error_report("Warning: migration may not work."); 1495 } 1496 g_array_set_size(tables_blob, legacy_table_size); 1497 } else { 1498 /* Make sure we have a buffer in case we need to resize the tables. */ 1499 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1500 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1501 error_report("Warning: ACPI tables are larger than 64k."); 1502 error_report("Warning: migration may not work."); 1503 error_report("Warning: please remove CPUs, NUMA nodes, " 1504 "memory slots or PCI bridges."); 1505 } 1506 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1507 } 1508 1509 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1510 1511 /* Cleanup memory that's no longer used. */ 1512 g_array_free(table_offsets, true); 1513 } 1514 1515 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1516 { 1517 uint32_t size = acpi_data_len(data); 1518 1519 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1520 memory_region_ram_resize(mr, size, &error_abort); 1521 1522 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1523 memory_region_set_dirty(mr, 0, size); 1524 } 1525 1526 static void acpi_build_update(void *build_opaque, uint32_t offset) 1527 { 1528 AcpiBuildState *build_state = build_opaque; 1529 AcpiBuildTables tables; 1530 1531 /* No state to update or already patched? Nothing to do. */ 1532 if (!build_state || build_state->patched) { 1533 return; 1534 } 1535 build_state->patched = 1; 1536 1537 acpi_build_tables_init(&tables); 1538 1539 acpi_build(build_state->guest_info, &tables); 1540 1541 acpi_ram_update(build_state->table_mr, tables.table_data); 1542 1543 if (build_state->rsdp) { 1544 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1545 } else { 1546 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1547 } 1548 1549 acpi_ram_update(build_state->linker_mr, tables.linker); 1550 acpi_build_tables_cleanup(&tables, true); 1551 } 1552 1553 static void acpi_build_reset(void *build_opaque) 1554 { 1555 AcpiBuildState *build_state = build_opaque; 1556 build_state->patched = 0; 1557 } 1558 1559 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 1560 GArray *blob, const char *name, 1561 uint64_t max_size) 1562 { 1563 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1564 name, acpi_build_update, build_state); 1565 } 1566 1567 static const VMStateDescription vmstate_acpi_build = { 1568 .name = "acpi_build", 1569 .version_id = 1, 1570 .minimum_version_id = 1, 1571 .fields = (VMStateField[]) { 1572 VMSTATE_UINT8(patched, AcpiBuildState), 1573 VMSTATE_END_OF_LIST() 1574 }, 1575 }; 1576 1577 void acpi_setup(PcGuestInfo *guest_info) 1578 { 1579 AcpiBuildTables tables; 1580 AcpiBuildState *build_state; 1581 1582 if (!guest_info->fw_cfg) { 1583 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1584 return; 1585 } 1586 1587 if (!guest_info->has_acpi_build) { 1588 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1589 return; 1590 } 1591 1592 if (!acpi_enabled) { 1593 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1594 return; 1595 } 1596 1597 build_state = g_malloc0(sizeof *build_state); 1598 1599 build_state->guest_info = guest_info; 1600 1601 acpi_set_pci_info(); 1602 1603 acpi_build_tables_init(&tables); 1604 acpi_build(build_state->guest_info, &tables); 1605 1606 /* Now expose it all to Guest */ 1607 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 1608 ACPI_BUILD_TABLE_FILE, 1609 ACPI_BUILD_TABLE_MAX_SIZE); 1610 assert(build_state->table_mr != NULL); 1611 1612 build_state->linker_mr = 1613 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1614 1615 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1616 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1617 1618 if (!guest_info->rsdp_in_ram) { 1619 /* 1620 * Keep for compatibility with old machine types. 1621 * Though RSDP is small, its contents isn't immutable, so 1622 * we'll update it along with the rest of tables on guest access. 1623 */ 1624 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1625 1626 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1627 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1628 acpi_build_update, build_state, 1629 build_state->rsdp, rsdp_size); 1630 build_state->rsdp_mr = NULL; 1631 } else { 1632 build_state->rsdp = NULL; 1633 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 1634 ACPI_BUILD_RSDP_FILE, 0); 1635 } 1636 1637 qemu_register_reset(acpi_build_reset, build_state); 1638 acpi_build_reset(build_state); 1639 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1640 1641 /* Cleanup tables but don't free the memory: we track it 1642 * in build_state. 1643 */ 1644 acpi_build_tables_cleanup(&tables, false); 1645 } 1646