1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "qom/cpu.h" 32 #include "hw/i386/pc.h" 33 #include "target-i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "sysemu/tpm.h" 43 #include "hw/acpi/tpm.h" 44 #include "sysemu/tpm_backend.h" 45 46 /* Supported chipsets: */ 47 #include "hw/acpi/piix4.h" 48 #include "hw/acpi/pcihp.h" 49 #include "hw/i386/ich9.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/q35.h" 52 #include "hw/i386/intel_iommu.h" 53 54 #include "hw/i386/q35-acpi-dsdt.hex" 55 #include "hw/i386/acpi-dsdt.hex" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 64 * a little bit, there should be plenty of free space since the DSDT 65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 66 */ 67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 68 #define ACPI_BUILD_ALIGN_SIZE 0x1000 69 70 #define ACPI_BUILD_TABLE_SIZE 0x20000 71 72 /* #define DEBUG_ACPI_BUILD */ 73 #ifdef DEBUG_ACPI_BUILD 74 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 76 #else 77 #define ACPI_BUILD_DPRINTF(fmt, ...) 78 #endif 79 80 typedef struct AcpiCpuInfo { 81 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 82 } AcpiCpuInfo; 83 84 typedef struct AcpiMcfgInfo { 85 uint64_t mcfg_base; 86 uint32_t mcfg_size; 87 } AcpiMcfgInfo; 88 89 typedef struct AcpiPmInfo { 90 bool s3_disabled; 91 bool s4_disabled; 92 bool pcihp_bridge_en; 93 uint8_t s4_val; 94 uint16_t sci_int; 95 uint8_t acpi_enable_cmd; 96 uint8_t acpi_disable_cmd; 97 uint32_t gpe0_blk; 98 uint32_t gpe0_blk_len; 99 uint32_t io_base; 100 uint16_t cpu_hp_io_base; 101 uint16_t cpu_hp_io_len; 102 uint16_t mem_hp_io_base; 103 uint16_t mem_hp_io_len; 104 uint16_t pcihp_io_base; 105 uint16_t pcihp_io_len; 106 } AcpiPmInfo; 107 108 typedef struct AcpiMiscInfo { 109 bool has_hpet; 110 TPMVersion tpm_version; 111 const unsigned char *dsdt_code; 112 unsigned dsdt_size; 113 uint16_t pvpanic_port; 114 uint16_t applesmc_io_base; 115 } AcpiMiscInfo; 116 117 typedef struct AcpiBuildPciBusHotplugState { 118 GArray *device_table; 119 GArray *notify_table; 120 struct AcpiBuildPciBusHotplugState *parent; 121 bool pcihp_bridge_en; 122 } AcpiBuildPciBusHotplugState; 123 124 static void acpi_get_dsdt(AcpiMiscInfo *info) 125 { 126 Object *piix = piix4_pm_find(); 127 Object *lpc = ich9_lpc_find(); 128 assert(!!piix != !!lpc); 129 130 if (piix) { 131 info->dsdt_code = AcpiDsdtAmlCode; 132 info->dsdt_size = sizeof AcpiDsdtAmlCode; 133 } 134 if (lpc) { 135 info->dsdt_code = Q35AcpiDsdtAmlCode; 136 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 137 } 138 } 139 140 static 141 int acpi_add_cpu_info(Object *o, void *opaque) 142 { 143 AcpiCpuInfo *cpu = opaque; 144 uint64_t apic_id; 145 146 if (object_dynamic_cast(o, TYPE_CPU)) { 147 apic_id = object_property_get_int(o, "apic-id", NULL); 148 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 149 150 set_bit(apic_id, cpu->found_cpus); 151 } 152 153 object_child_foreach(o, acpi_add_cpu_info, opaque); 154 return 0; 155 } 156 157 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 158 { 159 Object *root = object_get_root(); 160 161 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 162 object_child_foreach(root, acpi_add_cpu_info, cpu); 163 } 164 165 static void acpi_get_pm_info(AcpiPmInfo *pm) 166 { 167 Object *piix = piix4_pm_find(); 168 Object *lpc = ich9_lpc_find(); 169 Object *obj = NULL; 170 QObject *o; 171 172 pm->pcihp_io_base = 0; 173 pm->pcihp_io_len = 0; 174 if (piix) { 175 obj = piix; 176 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 177 pm->pcihp_io_base = 178 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 179 pm->pcihp_io_len = 180 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 181 } 182 if (lpc) { 183 obj = lpc; 184 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 185 } 186 assert(obj); 187 188 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 189 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 190 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 191 192 /* Fill in optional s3/s4 related properties */ 193 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 194 if (o) { 195 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 196 } else { 197 pm->s3_disabled = false; 198 } 199 qobject_decref(o); 200 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 201 if (o) { 202 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 203 } else { 204 pm->s4_disabled = false; 205 } 206 qobject_decref(o); 207 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 208 if (o) { 209 pm->s4_val = qint_get_int(qobject_to_qint(o)); 210 } else { 211 pm->s4_val = false; 212 } 213 qobject_decref(o); 214 215 /* Fill in mandatory properties */ 216 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 217 218 pm->acpi_enable_cmd = object_property_get_int(obj, 219 ACPI_PM_PROP_ACPI_ENABLE_CMD, 220 NULL); 221 pm->acpi_disable_cmd = object_property_get_int(obj, 222 ACPI_PM_PROP_ACPI_DISABLE_CMD, 223 NULL); 224 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 225 NULL); 226 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 227 NULL); 228 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 229 NULL); 230 pm->pcihp_bridge_en = 231 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 232 NULL); 233 } 234 235 static void acpi_get_misc_info(AcpiMiscInfo *info) 236 { 237 info->has_hpet = hpet_find(); 238 info->tpm_version = tpm_get_version(); 239 info->pvpanic_port = pvpanic_port(); 240 info->applesmc_io_base = applesmc_port(); 241 } 242 243 static void acpi_get_pci_info(PcPciInfo *info) 244 { 245 Object *pci_host; 246 bool ambiguous; 247 248 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 249 g_assert(!ambiguous); 250 g_assert(pci_host); 251 252 info->w32.begin = object_property_get_int(pci_host, 253 PCI_HOST_PROP_PCI_HOLE_START, 254 NULL); 255 info->w32.end = object_property_get_int(pci_host, 256 PCI_HOST_PROP_PCI_HOLE_END, 257 NULL); 258 info->w64.begin = object_property_get_int(pci_host, 259 PCI_HOST_PROP_PCI_HOLE64_START, 260 NULL); 261 info->w64.end = object_property_get_int(pci_host, 262 PCI_HOST_PROP_PCI_HOLE64_END, 263 NULL); 264 } 265 266 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 267 268 static void acpi_align_size(GArray *blob, unsigned align) 269 { 270 /* Align size to multiple of given size. This reduces the chance 271 * we need to change size in the future (breaking cross version migration). 272 */ 273 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 274 } 275 276 /* FACS */ 277 static void 278 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 279 { 280 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 281 memcpy(&facs->signature, "FACS", 4); 282 facs->length = cpu_to_le32(sizeof(*facs)); 283 } 284 285 /* Load chipset information in FADT */ 286 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 287 { 288 fadt->model = 1; 289 fadt->reserved1 = 0; 290 fadt->sci_int = cpu_to_le16(pm->sci_int); 291 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 292 fadt->acpi_enable = pm->acpi_enable_cmd; 293 fadt->acpi_disable = pm->acpi_disable_cmd; 294 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 295 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 296 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 297 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 298 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 299 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 300 fadt->pm1_evt_len = 4; 301 fadt->pm1_cnt_len = 2; 302 fadt->pm_tmr_len = 4; 303 fadt->gpe0_blk_len = pm->gpe0_blk_len; 304 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 305 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 306 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 307 (1 << ACPI_FADT_F_PROC_C1) | 308 (1 << ACPI_FADT_F_SLP_BUTTON) | 309 (1 << ACPI_FADT_F_RTC_S4)); 310 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 311 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 312 * For more than 8 CPUs, "Clustered Logical" mode has to be used 313 */ 314 if (max_cpus > 8) { 315 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 316 } 317 } 318 319 320 /* FADT */ 321 static void 322 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 323 unsigned facs, unsigned dsdt) 324 { 325 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 326 327 fadt->firmware_ctrl = cpu_to_le32(facs); 328 /* FACS address to be filled by Guest linker */ 329 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 330 ACPI_BUILD_TABLE_FILE, 331 table_data, &fadt->firmware_ctrl, 332 sizeof fadt->firmware_ctrl); 333 334 fadt->dsdt = cpu_to_le32(dsdt); 335 /* DSDT address to be filled by Guest linker */ 336 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 337 ACPI_BUILD_TABLE_FILE, 338 table_data, &fadt->dsdt, 339 sizeof fadt->dsdt); 340 341 fadt_setup(fadt, pm); 342 343 build_header(linker, table_data, 344 (void *)fadt, "FACP", sizeof(*fadt), 1); 345 } 346 347 static void 348 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 349 PcGuestInfo *guest_info) 350 { 351 int madt_start = table_data->len; 352 353 AcpiMultipleApicTable *madt; 354 AcpiMadtIoApic *io_apic; 355 AcpiMadtIntsrcovr *intsrcovr; 356 AcpiMadtLocalNmi *local_nmi; 357 int i; 358 359 madt = acpi_data_push(table_data, sizeof *madt); 360 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 361 madt->flags = cpu_to_le32(1); 362 363 for (i = 0; i < guest_info->apic_id_limit; i++) { 364 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 365 apic->type = ACPI_APIC_PROCESSOR; 366 apic->length = sizeof(*apic); 367 apic->processor_id = i; 368 apic->local_apic_id = i; 369 if (test_bit(i, cpu->found_cpus)) { 370 apic->flags = cpu_to_le32(1); 371 } else { 372 apic->flags = cpu_to_le32(0); 373 } 374 } 375 io_apic = acpi_data_push(table_data, sizeof *io_apic); 376 io_apic->type = ACPI_APIC_IO; 377 io_apic->length = sizeof(*io_apic); 378 #define ACPI_BUILD_IOAPIC_ID 0x0 379 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 380 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 381 io_apic->interrupt = cpu_to_le32(0); 382 383 if (guest_info->apic_xrupt_override) { 384 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 385 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 386 intsrcovr->length = sizeof(*intsrcovr); 387 intsrcovr->source = 0; 388 intsrcovr->gsi = cpu_to_le32(2); 389 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 390 } 391 for (i = 1; i < 16; i++) { 392 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 393 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 394 /* No need for a INT source override structure. */ 395 continue; 396 } 397 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 398 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 399 intsrcovr->length = sizeof(*intsrcovr); 400 intsrcovr->source = i; 401 intsrcovr->gsi = cpu_to_le32(i); 402 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 403 } 404 405 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 406 local_nmi->type = ACPI_APIC_LOCAL_NMI; 407 local_nmi->length = sizeof(*local_nmi); 408 local_nmi->processor_id = 0xff; /* all processors */ 409 local_nmi->flags = cpu_to_le16(0); 410 local_nmi->lint = 1; /* ACPI_LINT1 */ 411 412 build_header(linker, table_data, 413 (void *)(table_data->data + madt_start), "APIC", 414 table_data->len - madt_start, 1); 415 } 416 417 #include "hw/i386/ssdt-tpm.hex" 418 #include "hw/i386/ssdt-tpm2.hex" 419 420 /* Assign BSEL property to all buses. In the future, this can be changed 421 * to only assign to buses that support hotplug. 422 */ 423 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 424 { 425 unsigned *bsel_alloc = opaque; 426 unsigned *bus_bsel; 427 428 if (qbus_is_hotpluggable(BUS(bus))) { 429 bus_bsel = g_malloc(sizeof *bus_bsel); 430 431 *bus_bsel = (*bsel_alloc)++; 432 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 433 bus_bsel, NULL); 434 } 435 436 return bsel_alloc; 437 } 438 439 static void acpi_set_pci_info(void) 440 { 441 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 442 unsigned bsel_alloc = 0; 443 444 if (bus) { 445 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 446 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 447 } 448 } 449 450 static void build_append_pcihp_notify_entry(Aml *method, int slot) 451 { 452 Aml *if_ctx; 453 int32_t devfn = PCI_DEVFN(slot, 0); 454 455 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); 456 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 457 aml_append(method, if_ctx); 458 } 459 460 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 461 bool pcihp_bridge_en) 462 { 463 Aml *dev, *notify_method, *method; 464 QObject *bsel; 465 PCIBus *sec; 466 int i; 467 468 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 469 if (bsel) { 470 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 471 472 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 473 notify_method = aml_method("DVNT", 2); 474 } 475 476 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 477 DeviceClass *dc; 478 PCIDeviceClass *pc; 479 PCIDevice *pdev = bus->devices[i]; 480 int slot = PCI_SLOT(i); 481 bool hotplug_enabled_dev; 482 bool bridge_in_acpi; 483 484 if (!pdev) { 485 if (bsel) { /* add hotplug slots for non present devices */ 486 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 487 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 488 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 489 method = aml_method("_EJ0", 1); 490 aml_append(method, 491 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 492 ); 493 aml_append(dev, method); 494 aml_append(parent_scope, dev); 495 496 build_append_pcihp_notify_entry(notify_method, slot); 497 } 498 continue; 499 } 500 501 pc = PCI_DEVICE_GET_CLASS(pdev); 502 dc = DEVICE_GET_CLASS(pdev); 503 504 /* When hotplug for bridges is enabled, bridges are 505 * described in ACPI separately (see build_pci_bus_end). 506 * In this case they aren't themselves hot-pluggable. 507 * Hotplugged bridges *are* hot-pluggable. 508 */ 509 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 510 !DEVICE(pdev)->hotplugged; 511 512 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 513 514 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 515 continue; 516 } 517 518 /* start to compose PCI slot descriptor */ 519 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 520 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 521 522 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 523 /* add VGA specific AML methods */ 524 int s3d; 525 526 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 527 s3d = 3; 528 } else { 529 s3d = 0; 530 } 531 532 method = aml_method("_S1D", 0); 533 aml_append(method, aml_return(aml_int(0))); 534 aml_append(dev, method); 535 536 method = aml_method("_S2D", 0); 537 aml_append(method, aml_return(aml_int(0))); 538 aml_append(dev, method); 539 540 method = aml_method("_S3D", 0); 541 aml_append(method, aml_return(aml_int(s3d))); 542 aml_append(dev, method); 543 } else if (hotplug_enabled_dev) { 544 /* add _SUN/_EJ0 to make slot hotpluggable */ 545 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 546 547 method = aml_method("_EJ0", 1); 548 aml_append(method, 549 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 550 ); 551 aml_append(dev, method); 552 553 if (bsel) { 554 build_append_pcihp_notify_entry(notify_method, slot); 555 } 556 } else if (bridge_in_acpi) { 557 /* 558 * device is coldplugged bridge, 559 * add child device descriptions into its scope 560 */ 561 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 562 563 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 564 } 565 /* slot descriptor has been composed, add it into parent context */ 566 aml_append(parent_scope, dev); 567 } 568 569 if (bsel) { 570 aml_append(parent_scope, notify_method); 571 } 572 573 /* Append PCNT method to notify about events on local and child buses. 574 * Add unconditionally for root since DSDT expects it. 575 */ 576 method = aml_method("PCNT", 0); 577 578 /* If bus supports hotplug select it and notify about local events */ 579 if (bsel) { 580 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 581 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 582 aml_append(method, 583 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 584 ); 585 aml_append(method, 586 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 587 ); 588 } 589 590 /* Notify about child bus events in any case */ 591 if (pcihp_bridge_en) { 592 QLIST_FOREACH(sec, &bus->child, sibling) { 593 int32_t devfn = sec->parent_dev->devfn; 594 595 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 596 } 597 } 598 aml_append(parent_scope, method); 599 qobject_decref(bsel); 600 } 601 602 static void 603 build_ssdt(GArray *table_data, GArray *linker, 604 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 605 PcPciInfo *pci, PcGuestInfo *guest_info) 606 { 607 MachineState *machine = MACHINE(qdev_get_machine()); 608 uint32_t nr_mem = machine->ram_slots; 609 unsigned acpi_cpus = guest_info->apic_id_limit; 610 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 611 int i; 612 613 ssdt = init_aml_allocator(); 614 /* The current AML generator can cover the APIC ID range [0..255], 615 * inclusive, for VCPU hotplug. */ 616 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 617 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 618 619 /* Reserve space for header */ 620 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 621 622 scope = aml_scope("\\_SB.PCI0"); 623 /* build PCI0._CRS */ 624 crs = aml_resource_template(); 625 aml_append(crs, 626 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 627 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); 628 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 629 630 aml_append(crs, 631 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 632 AML_POS_DECODE, AML_ENTIRE_RANGE, 633 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 634 aml_append(crs, 635 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 636 AML_POS_DECODE, AML_ENTIRE_RANGE, 637 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 638 aml_append(crs, 639 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 640 AML_CACHEABLE, AML_READ_WRITE, 641 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 642 aml_append(crs, 643 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 644 AML_NON_CACHEABLE, AML_READ_WRITE, 645 0, pci->w32.begin, pci->w32.end - 1, 0, 646 pci->w32.end - pci->w32.begin)); 647 if (pci->w64.begin) { 648 aml_append(crs, 649 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 650 AML_CACHEABLE, AML_READ_WRITE, 651 0, pci->w64.begin, pci->w64.end - 1, 0, 652 pci->w64.end - pci->w64.begin)); 653 } 654 aml_append(scope, aml_name_decl("_CRS", crs)); 655 656 /* reserve GPE0 block resources */ 657 dev = aml_device("GPE0"); 658 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 659 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 660 /* device present, functioning, decoding, not shown in UI */ 661 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 662 crs = aml_resource_template(); 663 aml_append(crs, 664 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 665 ); 666 aml_append(dev, aml_name_decl("_CRS", crs)); 667 aml_append(scope, dev); 668 669 /* reserve PCIHP resources */ 670 if (pm->pcihp_io_len) { 671 dev = aml_device("PHPR"); 672 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 673 aml_append(dev, 674 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 675 /* device present, functioning, decoding, not shown in UI */ 676 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 677 crs = aml_resource_template(); 678 aml_append(crs, 679 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 680 pm->pcihp_io_len) 681 ); 682 aml_append(dev, aml_name_decl("_CRS", crs)); 683 aml_append(scope, dev); 684 } 685 aml_append(ssdt, scope); 686 687 /* create S3_ / S4_ / S5_ packages if necessary */ 688 scope = aml_scope("\\"); 689 if (!pm->s3_disabled) { 690 pkg = aml_package(4); 691 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 692 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 693 aml_append(pkg, aml_int(0)); /* reserved */ 694 aml_append(pkg, aml_int(0)); /* reserved */ 695 aml_append(scope, aml_name_decl("_S3", pkg)); 696 } 697 698 if (!pm->s4_disabled) { 699 pkg = aml_package(4); 700 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 701 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 702 aml_append(pkg, aml_int(pm->s4_val)); 703 aml_append(pkg, aml_int(0)); /* reserved */ 704 aml_append(pkg, aml_int(0)); /* reserved */ 705 aml_append(scope, aml_name_decl("_S4", pkg)); 706 } 707 708 pkg = aml_package(4); 709 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 710 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 711 aml_append(pkg, aml_int(0)); /* reserved */ 712 aml_append(pkg, aml_int(0)); /* reserved */ 713 aml_append(scope, aml_name_decl("_S5", pkg)); 714 aml_append(ssdt, scope); 715 716 if (misc->applesmc_io_base) { 717 scope = aml_scope("\\_SB.PCI0.ISA"); 718 dev = aml_device("SMC"); 719 720 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 721 /* device present, functioning, decoding, not shown in UI */ 722 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 723 724 crs = aml_resource_template(); 725 aml_append(crs, 726 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 727 0x01, APPLESMC_MAX_DATA_LENGTH) 728 ); 729 aml_append(crs, aml_irq_no_flags(6)); 730 aml_append(dev, aml_name_decl("_CRS", crs)); 731 732 aml_append(scope, dev); 733 aml_append(ssdt, scope); 734 } 735 736 if (misc->pvpanic_port) { 737 scope = aml_scope("\\_SB.PCI0.ISA"); 738 739 dev = aml_device("PEVT"); 740 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 741 742 crs = aml_resource_template(); 743 aml_append(crs, 744 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 745 ); 746 aml_append(dev, aml_name_decl("_CRS", crs)); 747 748 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 749 misc->pvpanic_port, 1)); 750 field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); 751 aml_append(field, aml_named_field("PEPT", 8)); 752 aml_append(dev, field); 753 754 /* device present, functioning, decoding, not shown in UI */ 755 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 756 757 method = aml_method("RDPT", 0); 758 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 759 aml_append(method, aml_return(aml_local(0))); 760 aml_append(dev, method); 761 762 method = aml_method("WRPT", 1); 763 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 764 aml_append(dev, method); 765 766 aml_append(scope, dev); 767 aml_append(ssdt, scope); 768 } 769 770 sb_scope = aml_scope("\\_SB"); 771 { 772 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 773 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 774 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 775 aml_append(dev, 776 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 777 ); 778 /* device present, functioning, decoding, not shown in UI */ 779 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 780 crs = aml_resource_template(); 781 aml_append(crs, 782 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 783 pm->cpu_hp_io_len) 784 ); 785 aml_append(dev, aml_name_decl("_CRS", crs)); 786 aml_append(sb_scope, dev); 787 /* declare CPU hotplug MMIO region and PRS field to access it */ 788 aml_append(sb_scope, aml_operation_region( 789 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 790 field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); 791 aml_append(field, aml_named_field("PRS", 256)); 792 aml_append(sb_scope, field); 793 794 /* build Processor object for each processor */ 795 for (i = 0; i < acpi_cpus; i++) { 796 dev = aml_processor(i, 0, 0, "CP%.02X", i); 797 798 method = aml_method("_MAT", 0); 799 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 800 aml_append(dev, method); 801 802 method = aml_method("_STA", 0); 803 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 804 aml_append(dev, method); 805 806 method = aml_method("_EJ0", 1); 807 aml_append(method, 808 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 809 ); 810 aml_append(dev, method); 811 812 aml_append(sb_scope, dev); 813 } 814 815 /* build this code: 816 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 817 */ 818 /* Arg0 = Processor ID = APIC ID */ 819 method = aml_method("NTFY", 2); 820 for (i = 0; i < acpi_cpus; i++) { 821 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 822 aml_append(ifctx, 823 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 824 ); 825 aml_append(method, ifctx); 826 } 827 aml_append(sb_scope, method); 828 829 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 830 * 831 * Note: The ability to create variable-sized packages was first 832 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 833 * ith up to 255 elements. Windows guests up to win2k8 fail when 834 * VarPackageOp is used. 835 */ 836 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 837 aml_varpackage(acpi_cpus); 838 839 for (i = 0; i < acpi_cpus; i++) { 840 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 841 aml_append(pkg, aml_int(b)); 842 } 843 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 844 845 /* build memory devices */ 846 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 847 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 848 aml_append(scope, 849 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 850 ); 851 852 crs = aml_resource_template(); 853 aml_append(crs, 854 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 855 pm->mem_hp_io_len) 856 ); 857 aml_append(scope, aml_name_decl("_CRS", crs)); 858 859 aml_append(scope, aml_operation_region( 860 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, 861 pm->mem_hp_io_base, pm->mem_hp_io_len) 862 ); 863 864 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 865 AML_PRESERVE); 866 aml_append(field, /* read only */ 867 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 868 aml_append(field, /* read only */ 869 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 870 aml_append(field, /* read only */ 871 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 872 aml_append(field, /* read only */ 873 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 874 aml_append(field, /* read only */ 875 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 876 aml_append(scope, field); 877 878 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, 879 AML_WRITE_AS_ZEROS); 880 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 881 aml_append(field, /* 1 if enabled, read only */ 882 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 883 aml_append(field, 884 /*(read) 1 if has a insert event. (write) 1 to clear event */ 885 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 886 aml_append(field, 887 /* (read) 1 if has a remove event. (write) 1 to clear event */ 888 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); 889 aml_append(field, 890 /* initiates device eject, write only */ 891 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); 892 aml_append(scope, field); 893 894 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 895 AML_PRESERVE); 896 aml_append(field, /* DIMM selector, write only */ 897 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 898 aml_append(field, /* _OST event code, write only */ 899 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 900 aml_append(field, /* _OST status code, write only */ 901 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 902 aml_append(scope, field); 903 904 aml_append(sb_scope, scope); 905 906 for (i = 0; i < nr_mem; i++) { 907 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 908 const char *s; 909 910 dev = aml_device("MP%02X", i); 911 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 912 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 913 914 method = aml_method("_CRS", 0); 915 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 916 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 917 aml_append(dev, method); 918 919 method = aml_method("_STA", 0); 920 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 921 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 922 aml_append(dev, method); 923 924 method = aml_method("_PXM", 0); 925 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 926 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 927 aml_append(dev, method); 928 929 method = aml_method("_OST", 3); 930 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 931 aml_append(method, aml_return(aml_call4( 932 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 933 ))); 934 aml_append(dev, method); 935 936 method = aml_method("_EJ0", 1); 937 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); 938 aml_append(method, aml_return(aml_call2( 939 s, aml_name("_UID"), aml_arg(0)))); 940 aml_append(dev, method); 941 942 aml_append(sb_scope, dev); 943 } 944 945 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 946 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 947 */ 948 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); 949 for (i = 0; i < nr_mem; i++) { 950 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 951 aml_append(ifctx, 952 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 953 ); 954 aml_append(method, ifctx); 955 } 956 aml_append(sb_scope, method); 957 958 { 959 Object *pci_host; 960 PCIBus *bus = NULL; 961 bool ambiguous; 962 963 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 964 if (!ambiguous && pci_host) { 965 bus = PCI_HOST_BRIDGE(pci_host)->bus; 966 } 967 968 if (bus) { 969 Aml *scope = aml_scope("PCI0"); 970 /* Scan all PCI buses. Generate tables to support hotplug. */ 971 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 972 aml_append(sb_scope, scope); 973 } 974 } 975 aml_append(ssdt, sb_scope); 976 } 977 978 /* copy AML table into ACPI tables blob and patch header there */ 979 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 980 build_header(linker, table_data, 981 (void *)(table_data->data + table_data->len - ssdt->buf->len), 982 "SSDT", ssdt->buf->len, 1); 983 free_aml_allocator(); 984 } 985 986 static void 987 build_hpet(GArray *table_data, GArray *linker) 988 { 989 Acpi20Hpet *hpet; 990 991 hpet = acpi_data_push(table_data, sizeof(*hpet)); 992 /* Note timer_block_id value must be kept in sync with value advertised by 993 * emulated hpet 994 */ 995 hpet->timer_block_id = cpu_to_le32(0x8086a201); 996 hpet->addr.address = cpu_to_le64(HPET_BASE); 997 build_header(linker, table_data, 998 (void *)hpet, "HPET", sizeof(*hpet), 1); 999 } 1000 1001 static void 1002 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 1003 { 1004 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1005 uint64_t log_area_start_address = acpi_data_len(tcpalog); 1006 1007 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1008 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1009 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 1010 1011 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 1012 false /* high memory */); 1013 1014 /* log area start address to be filled by Guest linker */ 1015 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1016 ACPI_BUILD_TPMLOG_FILE, 1017 table_data, &tcpa->log_area_start_address, 1018 sizeof(tcpa->log_area_start_address)); 1019 1020 build_header(linker, table_data, 1021 (void *)tcpa, "TCPA", sizeof(*tcpa), 2); 1022 1023 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1024 } 1025 1026 static void 1027 build_tpm_ssdt(GArray *table_data, GArray *linker) 1028 { 1029 void *tpm_ptr; 1030 1031 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); 1032 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); 1033 } 1034 1035 static void 1036 build_tpm2(GArray *table_data, GArray *linker) 1037 { 1038 Acpi20TPM2 *tpm2_ptr; 1039 void *tpm_ptr; 1040 1041 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm2_aml)); 1042 memcpy(tpm_ptr, ssdt_tpm2_aml, sizeof(ssdt_tpm2_aml)); 1043 1044 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 1045 1046 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 1047 tpm2_ptr->control_area_address = cpu_to_le64(0); 1048 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 1049 1050 build_header(linker, table_data, 1051 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4); 1052 } 1053 1054 typedef enum { 1055 MEM_AFFINITY_NOFLAGS = 0, 1056 MEM_AFFINITY_ENABLED = (1 << 0), 1057 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1058 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1059 } MemoryAffinityFlags; 1060 1061 static void 1062 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1063 uint64_t len, int node, MemoryAffinityFlags flags) 1064 { 1065 numamem->type = ACPI_SRAT_MEMORY; 1066 numamem->length = sizeof(*numamem); 1067 memset(numamem->proximity, 0, 4); 1068 numamem->proximity[0] = node; 1069 numamem->flags = cpu_to_le32(flags); 1070 numamem->base_addr = cpu_to_le64(base); 1071 numamem->range_length = cpu_to_le64(len); 1072 } 1073 1074 static void 1075 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1076 { 1077 AcpiSystemResourceAffinityTable *srat; 1078 AcpiSratProcessorAffinity *core; 1079 AcpiSratMemoryAffinity *numamem; 1080 1081 int i; 1082 uint64_t curnode; 1083 int srat_start, numa_start, slots; 1084 uint64_t mem_len, mem_base, next_base; 1085 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1086 ram_addr_t hotplugabble_address_space_size = 1087 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1088 NULL); 1089 1090 srat_start = table_data->len; 1091 1092 srat = acpi_data_push(table_data, sizeof *srat); 1093 srat->reserved1 = cpu_to_le32(1); 1094 core = (void *)(srat + 1); 1095 1096 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1097 core = acpi_data_push(table_data, sizeof *core); 1098 core->type = ACPI_SRAT_PROCESSOR; 1099 core->length = sizeof(*core); 1100 core->local_apic_id = i; 1101 curnode = guest_info->node_cpu[i]; 1102 core->proximity_lo = curnode; 1103 memset(core->proximity_hi, 0, 3); 1104 core->local_sapic_eid = 0; 1105 core->flags = cpu_to_le32(1); 1106 } 1107 1108 1109 /* the memory map is a bit tricky, it contains at least one hole 1110 * from 640k-1M and possibly another one from 3.5G-4G. 1111 */ 1112 next_base = 0; 1113 numa_start = table_data->len; 1114 1115 numamem = acpi_data_push(table_data, sizeof *numamem); 1116 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1117 next_base = 1024 * 1024; 1118 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1119 mem_base = next_base; 1120 mem_len = guest_info->node_mem[i - 1]; 1121 if (i == 1) { 1122 mem_len -= 1024 * 1024; 1123 } 1124 next_base = mem_base + mem_len; 1125 1126 /* Cut out the ACPI_PCI hole */ 1127 if (mem_base <= guest_info->ram_size_below_4g && 1128 next_base > guest_info->ram_size_below_4g) { 1129 mem_len -= next_base - guest_info->ram_size_below_4g; 1130 if (mem_len > 0) { 1131 numamem = acpi_data_push(table_data, sizeof *numamem); 1132 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1133 MEM_AFFINITY_ENABLED); 1134 } 1135 mem_base = 1ULL << 32; 1136 mem_len = next_base - guest_info->ram_size_below_4g; 1137 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1138 } 1139 numamem = acpi_data_push(table_data, sizeof *numamem); 1140 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1141 MEM_AFFINITY_ENABLED); 1142 } 1143 slots = (table_data->len - numa_start) / sizeof *numamem; 1144 for (; slots < guest_info->numa_nodes + 2; slots++) { 1145 numamem = acpi_data_push(table_data, sizeof *numamem); 1146 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1147 } 1148 1149 /* 1150 * Entry is required for Windows to enable memory hotplug in OS. 1151 * Memory devices may override proximity set by this entry, 1152 * providing _PXM method if necessary. 1153 */ 1154 if (hotplugabble_address_space_size) { 1155 numamem = acpi_data_push(table_data, sizeof *numamem); 1156 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, 1157 hotplugabble_address_space_size, 0, 1158 MEM_AFFINITY_HOTPLUGGABLE | 1159 MEM_AFFINITY_ENABLED); 1160 } 1161 1162 build_header(linker, table_data, 1163 (void *)(table_data->data + srat_start), 1164 "SRAT", 1165 table_data->len - srat_start, 1); 1166 } 1167 1168 static void 1169 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1170 { 1171 AcpiTableMcfg *mcfg; 1172 const char *sig; 1173 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1174 1175 mcfg = acpi_data_push(table_data, len); 1176 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1177 /* Only a single allocation so no need to play with segments */ 1178 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1179 mcfg->allocation[0].start_bus_number = 0; 1180 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1181 1182 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1183 * To avoid table size changes (which create migration issues), 1184 * always create the table even if there are no allocations, 1185 * but set the signature to a reserved value in this case. 1186 * ACPI spec requires OSPMs to ignore such tables. 1187 */ 1188 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1189 /* Reserved signature: ignored by OSPM */ 1190 sig = "QEMU"; 1191 } else { 1192 sig = "MCFG"; 1193 } 1194 build_header(linker, table_data, (void *)mcfg, sig, len, 1); 1195 } 1196 1197 static void 1198 build_dmar_q35(GArray *table_data, GArray *linker) 1199 { 1200 int dmar_start = table_data->len; 1201 1202 AcpiTableDmar *dmar; 1203 AcpiDmarHardwareUnit *drhd; 1204 1205 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1206 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1207 dmar->flags = 0; /* No intr_remap for now */ 1208 1209 /* DMAR Remapping Hardware Unit Definition structure */ 1210 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1211 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1212 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1213 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1214 drhd->pci_segment = cpu_to_le16(0); 1215 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1216 1217 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1218 "DMAR", table_data->len - dmar_start, 1); 1219 } 1220 1221 static void 1222 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1223 { 1224 AcpiTableHeader *dsdt; 1225 1226 assert(misc->dsdt_code && misc->dsdt_size); 1227 1228 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1229 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1230 1231 memset(dsdt, 0, sizeof *dsdt); 1232 build_header(linker, table_data, dsdt, "DSDT", 1233 misc->dsdt_size, 1); 1234 } 1235 1236 static GArray * 1237 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1238 { 1239 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1240 1241 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1242 true /* fseg memory */); 1243 1244 memcpy(&rsdp->signature, "RSD PTR ", 8); 1245 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1246 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1247 /* Address to be filled by Guest linker */ 1248 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1249 ACPI_BUILD_TABLE_FILE, 1250 rsdp_table, &rsdp->rsdt_physical_address, 1251 sizeof rsdp->rsdt_physical_address); 1252 rsdp->checksum = 0; 1253 /* Checksum to be filled by Guest linker */ 1254 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1255 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1256 1257 return rsdp_table; 1258 } 1259 1260 typedef 1261 struct AcpiBuildState { 1262 /* Copy of table in RAM (for patching). */ 1263 MemoryRegion *table_mr; 1264 /* Is table patched? */ 1265 uint8_t patched; 1266 PcGuestInfo *guest_info; 1267 void *rsdp; 1268 MemoryRegion *rsdp_mr; 1269 MemoryRegion *linker_mr; 1270 } AcpiBuildState; 1271 1272 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1273 { 1274 Object *pci_host; 1275 QObject *o; 1276 bool ambiguous; 1277 1278 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1279 g_assert(!ambiguous); 1280 g_assert(pci_host); 1281 1282 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1283 if (!o) { 1284 return false; 1285 } 1286 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1287 qobject_decref(o); 1288 1289 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1290 assert(o); 1291 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1292 qobject_decref(o); 1293 return true; 1294 } 1295 1296 static bool acpi_has_iommu(void) 1297 { 1298 bool ambiguous; 1299 Object *intel_iommu; 1300 1301 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1302 &ambiguous); 1303 return intel_iommu && !ambiguous; 1304 } 1305 1306 static 1307 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1308 { 1309 GArray *table_offsets; 1310 unsigned facs, ssdt, dsdt, rsdt; 1311 AcpiCpuInfo cpu; 1312 AcpiPmInfo pm; 1313 AcpiMiscInfo misc; 1314 AcpiMcfgInfo mcfg; 1315 PcPciInfo pci; 1316 uint8_t *u; 1317 size_t aml_len = 0; 1318 GArray *tables_blob = tables->table_data; 1319 1320 acpi_get_cpu_info(&cpu); 1321 acpi_get_pm_info(&pm); 1322 acpi_get_dsdt(&misc); 1323 acpi_get_misc_info(&misc); 1324 acpi_get_pci_info(&pci); 1325 1326 table_offsets = g_array_new(false, true /* clear */, 1327 sizeof(uint32_t)); 1328 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1329 1330 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1331 64 /* Ensure FACS is aligned */, 1332 false /* high memory */); 1333 1334 /* 1335 * FACS is pointed to by FADT. 1336 * We place it first since it's the only table that has alignment 1337 * requirements. 1338 */ 1339 facs = tables_blob->len; 1340 build_facs(tables_blob, tables->linker, guest_info); 1341 1342 /* DSDT is pointed to by FADT */ 1343 dsdt = tables_blob->len; 1344 build_dsdt(tables_blob, tables->linker, &misc); 1345 1346 /* Count the size of the DSDT and SSDT, we will need it for legacy 1347 * sizing of ACPI tables. 1348 */ 1349 aml_len += tables_blob->len - dsdt; 1350 1351 /* ACPI tables pointed to by RSDT */ 1352 acpi_add_table(table_offsets, tables_blob); 1353 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1354 1355 ssdt = tables_blob->len; 1356 acpi_add_table(table_offsets, tables_blob); 1357 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1358 guest_info); 1359 aml_len += tables_blob->len - ssdt; 1360 1361 acpi_add_table(table_offsets, tables_blob); 1362 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1363 1364 if (misc.has_hpet) { 1365 acpi_add_table(table_offsets, tables_blob); 1366 build_hpet(tables_blob, tables->linker); 1367 } 1368 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 1369 acpi_add_table(table_offsets, tables_blob); 1370 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1371 1372 acpi_add_table(table_offsets, tables_blob); 1373 switch (misc.tpm_version) { 1374 case TPM_VERSION_1_2: 1375 build_tpm_ssdt(tables_blob, tables->linker); 1376 break; 1377 case TPM_VERSION_2_0: 1378 build_tpm2(tables_blob, tables->linker); 1379 break; 1380 default: 1381 assert(false); 1382 } 1383 } 1384 if (guest_info->numa_nodes) { 1385 acpi_add_table(table_offsets, tables_blob); 1386 build_srat(tables_blob, tables->linker, guest_info); 1387 } 1388 if (acpi_get_mcfg(&mcfg)) { 1389 acpi_add_table(table_offsets, tables_blob); 1390 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1391 } 1392 if (acpi_has_iommu()) { 1393 acpi_add_table(table_offsets, tables_blob); 1394 build_dmar_q35(tables_blob, tables->linker); 1395 } 1396 1397 /* Add tables supplied by user (if any) */ 1398 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1399 unsigned len = acpi_table_len(u); 1400 1401 acpi_add_table(table_offsets, tables_blob); 1402 g_array_append_vals(tables_blob, u, len); 1403 } 1404 1405 /* RSDT is pointed to by RSDP */ 1406 rsdt = tables_blob->len; 1407 build_rsdt(tables_blob, tables->linker, table_offsets); 1408 1409 /* RSDP is in FSEG memory, so allocate it separately */ 1410 build_rsdp(tables->rsdp, tables->linker, rsdt); 1411 1412 /* We'll expose it all to Guest so we want to reduce 1413 * chance of size changes. 1414 * 1415 * We used to align the tables to 4k, but of course this would 1416 * too simple to be enough. 4k turned out to be too small an 1417 * alignment very soon, and in fact it is almost impossible to 1418 * keep the table size stable for all (max_cpus, max_memory_slots) 1419 * combinations. So the table size is always 64k for pc-i440fx-2.1 1420 * and we give an error if the table grows beyond that limit. 1421 * 1422 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1423 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1424 * than 2.0 and we can always pad the smaller tables with zeros. We can 1425 * then use the exact size of the 2.0 tables. 1426 * 1427 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1428 */ 1429 if (guest_info->legacy_acpi_table_size) { 1430 /* Subtracting aml_len gives the size of fixed tables. Then add the 1431 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1432 */ 1433 int legacy_aml_len = 1434 guest_info->legacy_acpi_table_size + 1435 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1436 int legacy_table_size = 1437 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1438 ACPI_BUILD_ALIGN_SIZE); 1439 if (tables_blob->len > legacy_table_size) { 1440 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1441 error_report("Warning: migration may not work."); 1442 } 1443 g_array_set_size(tables_blob, legacy_table_size); 1444 } else { 1445 /* Make sure we have a buffer in case we need to resize the tables. */ 1446 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1447 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1448 error_report("Warning: ACPI tables are larger than 64k."); 1449 error_report("Warning: migration may not work."); 1450 error_report("Warning: please remove CPUs, NUMA nodes, " 1451 "memory slots or PCI bridges."); 1452 } 1453 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1454 } 1455 1456 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1457 1458 /* Cleanup memory that's no longer used. */ 1459 g_array_free(table_offsets, true); 1460 } 1461 1462 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1463 { 1464 uint32_t size = acpi_data_len(data); 1465 1466 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1467 memory_region_ram_resize(mr, size, &error_abort); 1468 1469 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1470 memory_region_set_dirty(mr, 0, size); 1471 } 1472 1473 static void acpi_build_update(void *build_opaque, uint32_t offset) 1474 { 1475 AcpiBuildState *build_state = build_opaque; 1476 AcpiBuildTables tables; 1477 1478 /* No state to update or already patched? Nothing to do. */ 1479 if (!build_state || build_state->patched) { 1480 return; 1481 } 1482 build_state->patched = 1; 1483 1484 acpi_build_tables_init(&tables); 1485 1486 acpi_build(build_state->guest_info, &tables); 1487 1488 acpi_ram_update(build_state->table_mr, tables.table_data); 1489 1490 if (build_state->rsdp) { 1491 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1492 } else { 1493 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1494 } 1495 1496 acpi_ram_update(build_state->linker_mr, tables.linker); 1497 acpi_build_tables_cleanup(&tables, true); 1498 } 1499 1500 static void acpi_build_reset(void *build_opaque) 1501 { 1502 AcpiBuildState *build_state = build_opaque; 1503 build_state->patched = 0; 1504 } 1505 1506 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 1507 GArray *blob, const char *name, 1508 uint64_t max_size) 1509 { 1510 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1511 name, acpi_build_update, build_state); 1512 } 1513 1514 static const VMStateDescription vmstate_acpi_build = { 1515 .name = "acpi_build", 1516 .version_id = 1, 1517 .minimum_version_id = 1, 1518 .fields = (VMStateField[]) { 1519 VMSTATE_UINT8(patched, AcpiBuildState), 1520 VMSTATE_END_OF_LIST() 1521 }, 1522 }; 1523 1524 void acpi_setup(PcGuestInfo *guest_info) 1525 { 1526 AcpiBuildTables tables; 1527 AcpiBuildState *build_state; 1528 1529 if (!guest_info->fw_cfg) { 1530 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1531 return; 1532 } 1533 1534 if (!guest_info->has_acpi_build) { 1535 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1536 return; 1537 } 1538 1539 if (!acpi_enabled) { 1540 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1541 return; 1542 } 1543 1544 build_state = g_malloc0(sizeof *build_state); 1545 1546 build_state->guest_info = guest_info; 1547 1548 acpi_set_pci_info(); 1549 1550 acpi_build_tables_init(&tables); 1551 acpi_build(build_state->guest_info, &tables); 1552 1553 /* Now expose it all to Guest */ 1554 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 1555 ACPI_BUILD_TABLE_FILE, 1556 ACPI_BUILD_TABLE_MAX_SIZE); 1557 assert(build_state->table_mr != NULL); 1558 1559 build_state->linker_mr = 1560 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1561 1562 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1563 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1564 1565 if (!guest_info->rsdp_in_ram) { 1566 /* 1567 * Keep for compatibility with old machine types. 1568 * Though RSDP is small, its contents isn't immutable, so 1569 * we'll update it along with the rest of tables on guest access. 1570 */ 1571 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1572 1573 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1574 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1575 acpi_build_update, build_state, 1576 build_state->rsdp, rsdp_size); 1577 build_state->rsdp_mr = NULL; 1578 } else { 1579 build_state->rsdp = NULL; 1580 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 1581 ACPI_BUILD_RSDP_FILE, 0); 1582 } 1583 1584 qemu_register_reset(acpi_build_reset, build_state); 1585 acpi_build_reset(build_state); 1586 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1587 1588 /* Cleanup tables but don't free the memory: we track it 1589 * in build_state. 1590 */ 1591 acpi_build_tables_cleanup(&tables, false); 1592 } 1593