1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "qom/cpu.h" 32 #include "hw/i386/pc.h" 33 #include "target-i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "hw/mem/nvdimm.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "sysemu/tpm_backend.h" 46 47 /* Supported chipsets: */ 48 #include "hw/acpi/piix4.h" 49 #include "hw/acpi/pcihp.h" 50 #include "hw/i386/ich9.h" 51 #include "hw/pci/pci_bus.h" 52 #include "hw/pci-host/q35.h" 53 #include "hw/i386/intel_iommu.h" 54 55 #include "hw/i386/q35-acpi-dsdt.hex" 56 #include "hw/i386/acpi-dsdt.hex" 57 58 #include "hw/acpi/aml-build.h" 59 60 #include "qapi/qmp/qint.h" 61 #include "qom/qom-qobject.h" 62 63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 65 * a little bit, there should be plenty of free space since the DSDT 66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 67 */ 68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 69 #define ACPI_BUILD_ALIGN_SIZE 0x1000 70 71 #define ACPI_BUILD_TABLE_SIZE 0x20000 72 73 /* #define DEBUG_ACPI_BUILD */ 74 #ifdef DEBUG_ACPI_BUILD 75 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 76 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 77 #else 78 #define ACPI_BUILD_DPRINTF(fmt, ...) 79 #endif 80 81 typedef struct AcpiCpuInfo { 82 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 83 } AcpiCpuInfo; 84 85 typedef struct AcpiMcfgInfo { 86 uint64_t mcfg_base; 87 uint32_t mcfg_size; 88 } AcpiMcfgInfo; 89 90 typedef struct AcpiPmInfo { 91 bool s3_disabled; 92 bool s4_disabled; 93 bool pcihp_bridge_en; 94 uint8_t s4_val; 95 uint16_t sci_int; 96 uint8_t acpi_enable_cmd; 97 uint8_t acpi_disable_cmd; 98 uint32_t gpe0_blk; 99 uint32_t gpe0_blk_len; 100 uint32_t io_base; 101 uint16_t cpu_hp_io_base; 102 uint16_t cpu_hp_io_len; 103 uint16_t mem_hp_io_base; 104 uint16_t mem_hp_io_len; 105 uint16_t pcihp_io_base; 106 uint16_t pcihp_io_len; 107 } AcpiPmInfo; 108 109 typedef struct AcpiMiscInfo { 110 bool has_hpet; 111 TPMVersion tpm_version; 112 const unsigned char *dsdt_code; 113 unsigned dsdt_size; 114 uint16_t pvpanic_port; 115 uint16_t applesmc_io_base; 116 } AcpiMiscInfo; 117 118 typedef struct AcpiBuildPciBusHotplugState { 119 GArray *device_table; 120 GArray *notify_table; 121 struct AcpiBuildPciBusHotplugState *parent; 122 bool pcihp_bridge_en; 123 } AcpiBuildPciBusHotplugState; 124 125 static void acpi_get_dsdt(AcpiMiscInfo *info) 126 { 127 Object *piix = piix4_pm_find(); 128 Object *lpc = ich9_lpc_find(); 129 assert(!!piix != !!lpc); 130 131 if (piix) { 132 info->dsdt_code = AcpiDsdtAmlCode; 133 info->dsdt_size = sizeof AcpiDsdtAmlCode; 134 } 135 if (lpc) { 136 info->dsdt_code = Q35AcpiDsdtAmlCode; 137 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 138 } 139 } 140 141 static 142 int acpi_add_cpu_info(Object *o, void *opaque) 143 { 144 AcpiCpuInfo *cpu = opaque; 145 uint64_t apic_id; 146 147 if (object_dynamic_cast(o, TYPE_CPU)) { 148 apic_id = object_property_get_int(o, "apic-id", NULL); 149 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 150 151 set_bit(apic_id, cpu->found_cpus); 152 } 153 154 object_child_foreach(o, acpi_add_cpu_info, opaque); 155 return 0; 156 } 157 158 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 159 { 160 Object *root = object_get_root(); 161 162 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 163 object_child_foreach(root, acpi_add_cpu_info, cpu); 164 } 165 166 static void acpi_get_pm_info(AcpiPmInfo *pm) 167 { 168 Object *piix = piix4_pm_find(); 169 Object *lpc = ich9_lpc_find(); 170 Object *obj = NULL; 171 QObject *o; 172 173 pm->cpu_hp_io_base = 0; 174 pm->pcihp_io_base = 0; 175 pm->pcihp_io_len = 0; 176 if (piix) { 177 obj = piix; 178 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 179 pm->pcihp_io_base = 180 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 181 pm->pcihp_io_len = 182 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 183 } 184 if (lpc) { 185 obj = lpc; 186 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 187 } 188 assert(obj); 189 190 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 191 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 192 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 193 194 /* Fill in optional s3/s4 related properties */ 195 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 196 if (o) { 197 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 198 } else { 199 pm->s3_disabled = false; 200 } 201 qobject_decref(o); 202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 203 if (o) { 204 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 205 } else { 206 pm->s4_disabled = false; 207 } 208 qobject_decref(o); 209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 210 if (o) { 211 pm->s4_val = qint_get_int(qobject_to_qint(o)); 212 } else { 213 pm->s4_val = false; 214 } 215 qobject_decref(o); 216 217 /* Fill in mandatory properties */ 218 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 219 220 pm->acpi_enable_cmd = object_property_get_int(obj, 221 ACPI_PM_PROP_ACPI_ENABLE_CMD, 222 NULL); 223 pm->acpi_disable_cmd = object_property_get_int(obj, 224 ACPI_PM_PROP_ACPI_DISABLE_CMD, 225 NULL); 226 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 227 NULL); 228 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 229 NULL); 230 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 231 NULL); 232 pm->pcihp_bridge_en = 233 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 234 NULL); 235 } 236 237 static void acpi_get_misc_info(AcpiMiscInfo *info) 238 { 239 info->has_hpet = hpet_find(); 240 info->tpm_version = tpm_get_version(); 241 info->pvpanic_port = pvpanic_port(); 242 info->applesmc_io_base = applesmc_port(); 243 } 244 245 /* 246 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 247 * On i386 arch we only have two pci hosts, so we can look only for them. 248 */ 249 static Object *acpi_get_i386_pci_host(void) 250 { 251 PCIHostState *host; 252 253 host = OBJECT_CHECK(PCIHostState, 254 object_resolve_path("/machine/i440fx", NULL), 255 TYPE_PCI_HOST_BRIDGE); 256 if (!host) { 257 host = OBJECT_CHECK(PCIHostState, 258 object_resolve_path("/machine/q35", NULL), 259 TYPE_PCI_HOST_BRIDGE); 260 } 261 262 return OBJECT(host); 263 } 264 265 static void acpi_get_pci_info(PcPciInfo *info) 266 { 267 Object *pci_host; 268 269 270 pci_host = acpi_get_i386_pci_host(); 271 g_assert(pci_host); 272 273 info->w32.begin = object_property_get_int(pci_host, 274 PCI_HOST_PROP_PCI_HOLE_START, 275 NULL); 276 info->w32.end = object_property_get_int(pci_host, 277 PCI_HOST_PROP_PCI_HOLE_END, 278 NULL); 279 info->w64.begin = object_property_get_int(pci_host, 280 PCI_HOST_PROP_PCI_HOLE64_START, 281 NULL); 282 info->w64.end = object_property_get_int(pci_host, 283 PCI_HOST_PROP_PCI_HOLE64_END, 284 NULL); 285 } 286 287 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 288 289 static void acpi_align_size(GArray *blob, unsigned align) 290 { 291 /* Align size to multiple of given size. This reduces the chance 292 * we need to change size in the future (breaking cross version migration). 293 */ 294 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 295 } 296 297 /* FACS */ 298 static void 299 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 300 { 301 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 302 memcpy(&facs->signature, "FACS", 4); 303 facs->length = cpu_to_le32(sizeof(*facs)); 304 } 305 306 /* Load chipset information in FADT */ 307 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 308 { 309 fadt->model = 1; 310 fadt->reserved1 = 0; 311 fadt->sci_int = cpu_to_le16(pm->sci_int); 312 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 313 fadt->acpi_enable = pm->acpi_enable_cmd; 314 fadt->acpi_disable = pm->acpi_disable_cmd; 315 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 316 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 317 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 318 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 319 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 320 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 321 fadt->pm1_evt_len = 4; 322 fadt->pm1_cnt_len = 2; 323 fadt->pm_tmr_len = 4; 324 fadt->gpe0_blk_len = pm->gpe0_blk_len; 325 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 326 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 327 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 328 (1 << ACPI_FADT_F_PROC_C1) | 329 (1 << ACPI_FADT_F_SLP_BUTTON) | 330 (1 << ACPI_FADT_F_RTC_S4)); 331 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 332 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 333 * For more than 8 CPUs, "Clustered Logical" mode has to be used 334 */ 335 if (max_cpus > 8) { 336 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 337 } 338 } 339 340 341 /* FADT */ 342 static void 343 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 344 unsigned facs, unsigned dsdt) 345 { 346 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 347 348 fadt->firmware_ctrl = cpu_to_le32(facs); 349 /* FACS address to be filled by Guest linker */ 350 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 351 ACPI_BUILD_TABLE_FILE, 352 table_data, &fadt->firmware_ctrl, 353 sizeof fadt->firmware_ctrl); 354 355 fadt->dsdt = cpu_to_le32(dsdt); 356 /* DSDT address to be filled by Guest linker */ 357 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 358 ACPI_BUILD_TABLE_FILE, 359 table_data, &fadt->dsdt, 360 sizeof fadt->dsdt); 361 362 fadt_setup(fadt, pm); 363 364 build_header(linker, table_data, 365 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL); 366 } 367 368 static void 369 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 370 PcGuestInfo *guest_info) 371 { 372 int madt_start = table_data->len; 373 374 AcpiMultipleApicTable *madt; 375 AcpiMadtIoApic *io_apic; 376 AcpiMadtIntsrcovr *intsrcovr; 377 AcpiMadtLocalNmi *local_nmi; 378 int i; 379 380 madt = acpi_data_push(table_data, sizeof *madt); 381 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 382 madt->flags = cpu_to_le32(1); 383 384 for (i = 0; i < guest_info->apic_id_limit; i++) { 385 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 386 apic->type = ACPI_APIC_PROCESSOR; 387 apic->length = sizeof(*apic); 388 apic->processor_id = i; 389 apic->local_apic_id = i; 390 if (test_bit(i, cpu->found_cpus)) { 391 apic->flags = cpu_to_le32(1); 392 } else { 393 apic->flags = cpu_to_le32(0); 394 } 395 } 396 io_apic = acpi_data_push(table_data, sizeof *io_apic); 397 io_apic->type = ACPI_APIC_IO; 398 io_apic->length = sizeof(*io_apic); 399 #define ACPI_BUILD_IOAPIC_ID 0x0 400 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 401 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 402 io_apic->interrupt = cpu_to_le32(0); 403 404 if (guest_info->apic_xrupt_override) { 405 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 406 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 407 intsrcovr->length = sizeof(*intsrcovr); 408 intsrcovr->source = 0; 409 intsrcovr->gsi = cpu_to_le32(2); 410 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 411 } 412 for (i = 1; i < 16; i++) { 413 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 414 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 415 /* No need for a INT source override structure. */ 416 continue; 417 } 418 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 419 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 420 intsrcovr->length = sizeof(*intsrcovr); 421 intsrcovr->source = i; 422 intsrcovr->gsi = cpu_to_le32(i); 423 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 424 } 425 426 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 427 local_nmi->type = ACPI_APIC_LOCAL_NMI; 428 local_nmi->length = sizeof(*local_nmi); 429 local_nmi->processor_id = 0xff; /* all processors */ 430 local_nmi->flags = cpu_to_le16(0); 431 local_nmi->lint = 1; /* ACPI_LINT1 */ 432 433 build_header(linker, table_data, 434 (void *)(table_data->data + madt_start), "APIC", 435 table_data->len - madt_start, 1, NULL); 436 } 437 438 /* Assign BSEL property to all buses. In the future, this can be changed 439 * to only assign to buses that support hotplug. 440 */ 441 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 442 { 443 unsigned *bsel_alloc = opaque; 444 unsigned *bus_bsel; 445 446 if (qbus_is_hotpluggable(BUS(bus))) { 447 bus_bsel = g_malloc(sizeof *bus_bsel); 448 449 *bus_bsel = (*bsel_alloc)++; 450 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 451 bus_bsel, NULL); 452 } 453 454 return bsel_alloc; 455 } 456 457 static void acpi_set_pci_info(void) 458 { 459 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 460 unsigned bsel_alloc = 0; 461 462 if (bus) { 463 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 464 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 465 } 466 } 467 468 static void build_append_pcihp_notify_entry(Aml *method, int slot) 469 { 470 Aml *if_ctx; 471 int32_t devfn = PCI_DEVFN(slot, 0); 472 473 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 474 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 475 aml_append(method, if_ctx); 476 } 477 478 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 479 bool pcihp_bridge_en) 480 { 481 Aml *dev, *notify_method, *method; 482 QObject *bsel; 483 PCIBus *sec; 484 int i; 485 486 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 487 if (bsel) { 488 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 489 490 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 491 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 492 } 493 494 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 495 DeviceClass *dc; 496 PCIDeviceClass *pc; 497 PCIDevice *pdev = bus->devices[i]; 498 int slot = PCI_SLOT(i); 499 bool hotplug_enabled_dev; 500 bool bridge_in_acpi; 501 502 if (!pdev) { 503 if (bsel) { /* add hotplug slots for non present devices */ 504 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 505 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 506 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 507 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 508 aml_append(method, 509 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 510 ); 511 aml_append(dev, method); 512 aml_append(parent_scope, dev); 513 514 build_append_pcihp_notify_entry(notify_method, slot); 515 } 516 continue; 517 } 518 519 pc = PCI_DEVICE_GET_CLASS(pdev); 520 dc = DEVICE_GET_CLASS(pdev); 521 522 /* When hotplug for bridges is enabled, bridges are 523 * described in ACPI separately (see build_pci_bus_end). 524 * In this case they aren't themselves hot-pluggable. 525 * Hotplugged bridges *are* hot-pluggable. 526 */ 527 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 528 !DEVICE(pdev)->hotplugged; 529 530 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 531 532 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 533 continue; 534 } 535 536 /* start to compose PCI slot descriptor */ 537 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 538 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 539 540 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 541 /* add VGA specific AML methods */ 542 int s3d; 543 544 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 545 s3d = 3; 546 } else { 547 s3d = 0; 548 } 549 550 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 551 aml_append(method, aml_return(aml_int(0))); 552 aml_append(dev, method); 553 554 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 555 aml_append(method, aml_return(aml_int(0))); 556 aml_append(dev, method); 557 558 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 559 aml_append(method, aml_return(aml_int(s3d))); 560 aml_append(dev, method); 561 } else if (hotplug_enabled_dev) { 562 /* add _SUN/_EJ0 to make slot hotpluggable */ 563 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 564 565 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 566 aml_append(method, 567 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 568 ); 569 aml_append(dev, method); 570 571 if (bsel) { 572 build_append_pcihp_notify_entry(notify_method, slot); 573 } 574 } else if (bridge_in_acpi) { 575 /* 576 * device is coldplugged bridge, 577 * add child device descriptions into its scope 578 */ 579 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 580 581 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 582 } 583 /* slot descriptor has been composed, add it into parent context */ 584 aml_append(parent_scope, dev); 585 } 586 587 if (bsel) { 588 aml_append(parent_scope, notify_method); 589 } 590 591 /* Append PCNT method to notify about events on local and child buses. 592 * Add unconditionally for root since DSDT expects it. 593 */ 594 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 595 596 /* If bus supports hotplug select it and notify about local events */ 597 if (bsel) { 598 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 599 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 600 aml_append(method, 601 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 602 ); 603 aml_append(method, 604 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 605 ); 606 } 607 608 /* Notify about child bus events in any case */ 609 if (pcihp_bridge_en) { 610 QLIST_FOREACH(sec, &bus->child, sibling) { 611 int32_t devfn = sec->parent_dev->devfn; 612 613 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 614 } 615 } 616 aml_append(parent_scope, method); 617 qobject_decref(bsel); 618 } 619 620 /* 621 * initialize_route - Initialize the interrupt routing rule 622 * through a specific LINK: 623 * if (lnk_idx == idx) 624 * route using link 'link_name' 625 */ 626 static Aml *initialize_route(Aml *route, const char *link_name, 627 Aml *lnk_idx, int idx) 628 { 629 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 630 Aml *pkg = aml_package(4); 631 632 aml_append(pkg, aml_int(0)); 633 aml_append(pkg, aml_int(0)); 634 aml_append(pkg, aml_name("%s", link_name)); 635 aml_append(pkg, aml_int(0)); 636 aml_append(if_ctx, aml_store(pkg, route)); 637 638 return if_ctx; 639 } 640 641 /* 642 * build_prt - Define interrupt rounting rules 643 * 644 * Returns an array of 128 routes, one for each device, 645 * based on device location. 646 * The main goal is to equaly distribute the interrupts 647 * over the 4 existing ACPI links (works only for i440fx). 648 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 649 * 650 */ 651 static Aml *build_prt(void) 652 { 653 Aml *method, *while_ctx, *pin, *res; 654 655 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 656 res = aml_local(0); 657 pin = aml_local(1); 658 aml_append(method, aml_store(aml_package(128), res)); 659 aml_append(method, aml_store(aml_int(0), pin)); 660 661 /* while (pin < 128) */ 662 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 663 { 664 Aml *slot = aml_local(2); 665 Aml *lnk_idx = aml_local(3); 666 Aml *route = aml_local(4); 667 668 /* slot = pin >> 2 */ 669 aml_append(while_ctx, 670 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 671 /* lnk_idx = (slot + pin) & 3 */ 672 aml_append(while_ctx, 673 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 674 lnk_idx)); 675 676 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 677 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 678 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 679 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 680 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 681 682 /* route[0] = 0x[slot]FFFF */ 683 aml_append(while_ctx, 684 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 685 NULL), 686 aml_index(route, aml_int(0)))); 687 /* route[1] = pin & 3 */ 688 aml_append(while_ctx, 689 aml_store(aml_and(pin, aml_int(3), NULL), 690 aml_index(route, aml_int(1)))); 691 /* res[pin] = route */ 692 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 693 /* pin++ */ 694 aml_append(while_ctx, aml_increment(pin)); 695 } 696 aml_append(method, while_ctx); 697 /* return res*/ 698 aml_append(method, aml_return(res)); 699 700 return method; 701 } 702 703 typedef struct CrsRangeEntry { 704 uint64_t base; 705 uint64_t limit; 706 } CrsRangeEntry; 707 708 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 709 { 710 CrsRangeEntry *entry; 711 712 entry = g_malloc(sizeof(*entry)); 713 entry->base = base; 714 entry->limit = limit; 715 716 g_ptr_array_add(ranges, entry); 717 } 718 719 static void crs_range_free(gpointer data) 720 { 721 CrsRangeEntry *entry = (CrsRangeEntry *)data; 722 g_free(entry); 723 } 724 725 static gint crs_range_compare(gconstpointer a, gconstpointer b) 726 { 727 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 728 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 729 730 return (int64_t)entry_a->base - (int64_t)entry_b->base; 731 } 732 733 /* 734 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 735 * interval, computes the 'free' ranges from the same interval. 736 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 737 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 738 */ 739 static void crs_replace_with_free_ranges(GPtrArray *ranges, 740 uint64_t start, uint64_t end) 741 { 742 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free); 743 uint64_t free_base = start; 744 int i; 745 746 g_ptr_array_sort(ranges, crs_range_compare); 747 for (i = 0; i < ranges->len; i++) { 748 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 749 750 if (free_base < used->base) { 751 crs_range_insert(free_ranges, free_base, used->base - 1); 752 } 753 754 free_base = used->limit + 1; 755 } 756 757 if (free_base < end) { 758 crs_range_insert(free_ranges, free_base, end); 759 } 760 761 g_ptr_array_set_size(ranges, 0); 762 for (i = 0; i < free_ranges->len; i++) { 763 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 764 } 765 766 g_ptr_array_free(free_ranges, false); 767 } 768 769 /* 770 * crs_range_merge - merges adjacent ranges in the given array. 771 * Array elements are deleted and replaced with the merged ranges. 772 */ 773 static void crs_range_merge(GPtrArray *range) 774 { 775 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 776 CrsRangeEntry *entry; 777 uint64_t range_base, range_limit; 778 int i; 779 780 if (!range->len) { 781 return; 782 } 783 784 g_ptr_array_sort(range, crs_range_compare); 785 786 entry = g_ptr_array_index(range, 0); 787 range_base = entry->base; 788 range_limit = entry->limit; 789 for (i = 1; i < range->len; i++) { 790 entry = g_ptr_array_index(range, i); 791 if (entry->base - 1 == range_limit) { 792 range_limit = entry->limit; 793 } else { 794 crs_range_insert(tmp, range_base, range_limit); 795 range_base = entry->base; 796 range_limit = entry->limit; 797 } 798 } 799 crs_range_insert(tmp, range_base, range_limit); 800 801 g_ptr_array_set_size(range, 0); 802 for (i = 0; i < tmp->len; i++) { 803 entry = g_ptr_array_index(tmp, i); 804 crs_range_insert(range, entry->base, entry->limit); 805 } 806 g_ptr_array_free(tmp, true); 807 } 808 809 static Aml *build_crs(PCIHostState *host, 810 GPtrArray *io_ranges, GPtrArray *mem_ranges) 811 { 812 Aml *crs = aml_resource_template(); 813 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 814 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 815 CrsRangeEntry *entry; 816 uint8_t max_bus = pci_bus_num(host->bus); 817 uint8_t type; 818 int devfn; 819 int i; 820 821 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 822 uint64_t range_base, range_limit; 823 PCIDevice *dev = host->bus->devices[devfn]; 824 825 if (!dev) { 826 continue; 827 } 828 829 for (i = 0; i < PCI_NUM_REGIONS; i++) { 830 PCIIORegion *r = &dev->io_regions[i]; 831 832 range_base = r->addr; 833 range_limit = r->addr + r->size - 1; 834 835 /* 836 * Work-around for old bioses 837 * that do not support multiple root buses 838 */ 839 if (!range_base || range_base > range_limit) { 840 continue; 841 } 842 843 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 844 crs_range_insert(host_io_ranges, range_base, range_limit); 845 } else { /* "memory" */ 846 crs_range_insert(host_mem_ranges, range_base, range_limit); 847 } 848 } 849 850 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 851 if (type == PCI_HEADER_TYPE_BRIDGE) { 852 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 853 if (subordinate > max_bus) { 854 max_bus = subordinate; 855 } 856 857 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 858 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 859 860 /* 861 * Work-around for old bioses 862 * that do not support multiple root buses 863 */ 864 if (range_base && range_base <= range_limit) { 865 crs_range_insert(host_io_ranges, range_base, range_limit); 866 } 867 868 range_base = 869 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 870 range_limit = 871 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 872 873 /* 874 * Work-around for old bioses 875 * that do not support multiple root buses 876 */ 877 if (range_base && range_base <= range_limit) { 878 crs_range_insert(host_mem_ranges, range_base, range_limit); 879 } 880 881 range_base = 882 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 883 range_limit = 884 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 885 886 /* 887 * Work-around for old bioses 888 * that do not support multiple root buses 889 */ 890 if (range_base && range_base <= range_limit) { 891 crs_range_insert(host_mem_ranges, range_base, range_limit); 892 } 893 } 894 } 895 896 crs_range_merge(host_io_ranges); 897 for (i = 0; i < host_io_ranges->len; i++) { 898 entry = g_ptr_array_index(host_io_ranges, i); 899 aml_append(crs, 900 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 901 AML_POS_DECODE, AML_ENTIRE_RANGE, 902 0, entry->base, entry->limit, 0, 903 entry->limit - entry->base + 1)); 904 crs_range_insert(io_ranges, entry->base, entry->limit); 905 } 906 g_ptr_array_free(host_io_ranges, true); 907 908 crs_range_merge(host_mem_ranges); 909 for (i = 0; i < host_mem_ranges->len; i++) { 910 entry = g_ptr_array_index(host_mem_ranges, i); 911 aml_append(crs, 912 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 913 AML_MAX_FIXED, AML_NON_CACHEABLE, 914 AML_READ_WRITE, 915 0, entry->base, entry->limit, 0, 916 entry->limit - entry->base + 1)); 917 crs_range_insert(mem_ranges, entry->base, entry->limit); 918 } 919 g_ptr_array_free(host_mem_ranges, true); 920 921 aml_append(crs, 922 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 923 0, 924 pci_bus_num(host->bus), 925 max_bus, 926 0, 927 max_bus - pci_bus_num(host->bus) + 1)); 928 929 return crs; 930 } 931 932 static void 933 build_ssdt(GArray *table_data, GArray *linker, 934 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 935 PcPciInfo *pci, PcGuestInfo *guest_info) 936 { 937 MachineState *machine = MACHINE(qdev_get_machine()); 938 uint32_t nr_mem = machine->ram_slots; 939 unsigned acpi_cpus = guest_info->apic_id_limit; 940 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 941 PCIBus *bus = NULL; 942 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 943 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 944 CrsRangeEntry *entry; 945 int root_bus_limit = 0xFF; 946 int i; 947 948 ssdt = init_aml_allocator(); 949 /* The current AML generator can cover the APIC ID range [0..255], 950 * inclusive, for VCPU hotplug. */ 951 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 952 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 953 954 /* Reserve space for header */ 955 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 956 957 bus = PC_MACHINE(machine)->bus; 958 if (bus) { 959 QLIST_FOREACH(bus, &bus->child, sibling) { 960 uint8_t bus_num = pci_bus_num(bus); 961 uint8_t numa_node = pci_bus_numa_node(bus); 962 963 /* look only for expander root buses */ 964 if (!pci_bus_is_root(bus)) { 965 continue; 966 } 967 968 if (bus_num < root_bus_limit) { 969 root_bus_limit = bus_num - 1; 970 } 971 972 scope = aml_scope("\\_SB"); 973 dev = aml_device("PC%.02X", bus_num); 974 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 975 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 976 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 977 978 if (numa_node != NUMA_NODE_UNASSIGNED) { 979 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 980 } 981 982 aml_append(dev, build_prt()); 983 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), 984 io_ranges, mem_ranges); 985 aml_append(dev, aml_name_decl("_CRS", crs)); 986 aml_append(scope, dev); 987 aml_append(ssdt, scope); 988 } 989 } 990 991 scope = aml_scope("\\_SB.PCI0"); 992 /* build PCI0._CRS */ 993 crs = aml_resource_template(); 994 aml_append(crs, 995 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 996 0x0000, 0x0, root_bus_limit, 997 0x0000, root_bus_limit + 1)); 998 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 999 1000 aml_append(crs, 1001 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1002 AML_POS_DECODE, AML_ENTIRE_RANGE, 1003 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1004 1005 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF); 1006 for (i = 0; i < io_ranges->len; i++) { 1007 entry = g_ptr_array_index(io_ranges, i); 1008 aml_append(crs, 1009 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1010 AML_POS_DECODE, AML_ENTIRE_RANGE, 1011 0x0000, entry->base, entry->limit, 1012 0x0000, entry->limit - entry->base + 1)); 1013 } 1014 1015 aml_append(crs, 1016 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1017 AML_CACHEABLE, AML_READ_WRITE, 1018 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1019 1020 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1); 1021 for (i = 0; i < mem_ranges->len; i++) { 1022 entry = g_ptr_array_index(mem_ranges, i); 1023 aml_append(crs, 1024 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1025 AML_NON_CACHEABLE, AML_READ_WRITE, 1026 0, entry->base, entry->limit, 1027 0, entry->limit - entry->base + 1)); 1028 } 1029 1030 if (pci->w64.begin) { 1031 aml_append(crs, 1032 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1033 AML_CACHEABLE, AML_READ_WRITE, 1034 0, pci->w64.begin, pci->w64.end - 1, 0, 1035 pci->w64.end - pci->w64.begin)); 1036 } 1037 aml_append(scope, aml_name_decl("_CRS", crs)); 1038 1039 /* reserve GPE0 block resources */ 1040 dev = aml_device("GPE0"); 1041 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1042 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1043 /* device present, functioning, decoding, not shown in UI */ 1044 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1045 crs = aml_resource_template(); 1046 aml_append(crs, 1047 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 1048 ); 1049 aml_append(dev, aml_name_decl("_CRS", crs)); 1050 aml_append(scope, dev); 1051 1052 g_ptr_array_free(io_ranges, true); 1053 g_ptr_array_free(mem_ranges, true); 1054 1055 /* reserve PCIHP resources */ 1056 if (pm->pcihp_io_len) { 1057 dev = aml_device("PHPR"); 1058 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1059 aml_append(dev, 1060 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1061 /* device present, functioning, decoding, not shown in UI */ 1062 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1063 crs = aml_resource_template(); 1064 aml_append(crs, 1065 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1066 pm->pcihp_io_len) 1067 ); 1068 aml_append(dev, aml_name_decl("_CRS", crs)); 1069 aml_append(scope, dev); 1070 } 1071 aml_append(ssdt, scope); 1072 1073 /* create S3_ / S4_ / S5_ packages if necessary */ 1074 scope = aml_scope("\\"); 1075 if (!pm->s3_disabled) { 1076 pkg = aml_package(4); 1077 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1078 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1079 aml_append(pkg, aml_int(0)); /* reserved */ 1080 aml_append(pkg, aml_int(0)); /* reserved */ 1081 aml_append(scope, aml_name_decl("_S3", pkg)); 1082 } 1083 1084 if (!pm->s4_disabled) { 1085 pkg = aml_package(4); 1086 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1087 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1088 aml_append(pkg, aml_int(pm->s4_val)); 1089 aml_append(pkg, aml_int(0)); /* reserved */ 1090 aml_append(pkg, aml_int(0)); /* reserved */ 1091 aml_append(scope, aml_name_decl("_S4", pkg)); 1092 } 1093 1094 pkg = aml_package(4); 1095 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1096 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1097 aml_append(pkg, aml_int(0)); /* reserved */ 1098 aml_append(pkg, aml_int(0)); /* reserved */ 1099 aml_append(scope, aml_name_decl("_S5", pkg)); 1100 aml_append(ssdt, scope); 1101 1102 if (misc->applesmc_io_base) { 1103 scope = aml_scope("\\_SB.PCI0.ISA"); 1104 dev = aml_device("SMC"); 1105 1106 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1107 /* device present, functioning, decoding, not shown in UI */ 1108 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1109 1110 crs = aml_resource_template(); 1111 aml_append(crs, 1112 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1113 0x01, APPLESMC_MAX_DATA_LENGTH) 1114 ); 1115 aml_append(crs, aml_irq_no_flags(6)); 1116 aml_append(dev, aml_name_decl("_CRS", crs)); 1117 1118 aml_append(scope, dev); 1119 aml_append(ssdt, scope); 1120 } 1121 1122 if (misc->pvpanic_port) { 1123 scope = aml_scope("\\_SB.PCI0.ISA"); 1124 1125 dev = aml_device("PEVT"); 1126 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1127 1128 crs = aml_resource_template(); 1129 aml_append(crs, 1130 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1131 ); 1132 aml_append(dev, aml_name_decl("_CRS", crs)); 1133 1134 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1135 misc->pvpanic_port, 1)); 1136 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1137 aml_append(field, aml_named_field("PEPT", 8)); 1138 aml_append(dev, field); 1139 1140 /* device present, functioning, decoding, shown in UI */ 1141 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1142 1143 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1144 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1145 aml_append(method, aml_return(aml_local(0))); 1146 aml_append(dev, method); 1147 1148 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1149 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1150 aml_append(dev, method); 1151 1152 aml_append(scope, dev); 1153 aml_append(ssdt, scope); 1154 } 1155 1156 sb_scope = aml_scope("\\_SB"); 1157 { 1158 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 1159 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 1160 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1161 aml_append(dev, 1162 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 1163 ); 1164 /* device present, functioning, decoding, not shown in UI */ 1165 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1166 crs = aml_resource_template(); 1167 aml_append(crs, 1168 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 1169 pm->cpu_hp_io_len) 1170 ); 1171 aml_append(dev, aml_name_decl("_CRS", crs)); 1172 aml_append(sb_scope, dev); 1173 /* declare CPU hotplug MMIO region and PRS field to access it */ 1174 aml_append(sb_scope, aml_operation_region( 1175 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 1176 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1177 aml_append(field, aml_named_field("PRS", 256)); 1178 aml_append(sb_scope, field); 1179 1180 /* build Processor object for each processor */ 1181 for (i = 0; i < acpi_cpus; i++) { 1182 dev = aml_processor(i, 0, 0, "CP%.02X", i); 1183 1184 method = aml_method("_MAT", 0, AML_NOTSERIALIZED); 1185 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 1186 aml_append(dev, method); 1187 1188 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1189 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 1190 aml_append(dev, method); 1191 1192 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1193 aml_append(method, 1194 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 1195 ); 1196 aml_append(dev, method); 1197 1198 aml_append(sb_scope, dev); 1199 } 1200 1201 /* build this code: 1202 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 1203 */ 1204 /* Arg0 = Processor ID = APIC ID */ 1205 method = aml_method("NTFY", 2, AML_NOTSERIALIZED); 1206 for (i = 0; i < acpi_cpus; i++) { 1207 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1208 aml_append(ifctx, 1209 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 1210 ); 1211 aml_append(method, ifctx); 1212 } 1213 aml_append(sb_scope, method); 1214 1215 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 1216 * 1217 * Note: The ability to create variable-sized packages was first 1218 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 1219 * ith up to 255 elements. Windows guests up to win2k8 fail when 1220 * VarPackageOp is used. 1221 */ 1222 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 1223 aml_varpackage(acpi_cpus); 1224 1225 for (i = 0; i < acpi_cpus; i++) { 1226 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 1227 aml_append(pkg, aml_int(b)); 1228 } 1229 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 1230 1231 /* build memory devices */ 1232 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 1233 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 1234 aml_append(scope, 1235 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 1236 ); 1237 1238 crs = aml_resource_template(); 1239 aml_append(crs, 1240 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 1241 pm->mem_hp_io_len) 1242 ); 1243 aml_append(scope, aml_name_decl("_CRS", crs)); 1244 1245 aml_append(scope, aml_operation_region( 1246 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, 1247 pm->mem_hp_io_base, pm->mem_hp_io_len) 1248 ); 1249 1250 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 1251 AML_NOLOCK, AML_PRESERVE); 1252 aml_append(field, /* read only */ 1253 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 1254 aml_append(field, /* read only */ 1255 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 1256 aml_append(field, /* read only */ 1257 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 1258 aml_append(field, /* read only */ 1259 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 1260 aml_append(field, /* read only */ 1261 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 1262 aml_append(scope, field); 1263 1264 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, 1265 AML_NOLOCK, AML_WRITE_AS_ZEROS); 1266 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 1267 aml_append(field, /* 1 if enabled, read only */ 1268 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 1269 aml_append(field, 1270 /*(read) 1 if has a insert event. (write) 1 to clear event */ 1271 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 1272 aml_append(field, 1273 /* (read) 1 if has a remove event. (write) 1 to clear event */ 1274 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); 1275 aml_append(field, 1276 /* initiates device eject, write only */ 1277 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); 1278 aml_append(scope, field); 1279 1280 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, 1281 AML_NOLOCK, AML_PRESERVE); 1282 aml_append(field, /* DIMM selector, write only */ 1283 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 1284 aml_append(field, /* _OST event code, write only */ 1285 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 1286 aml_append(field, /* _OST status code, write only */ 1287 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 1288 aml_append(scope, field); 1289 1290 aml_append(sb_scope, scope); 1291 1292 for (i = 0; i < nr_mem; i++) { 1293 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 1294 const char *s; 1295 1296 dev = aml_device("MP%02X", i); 1297 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 1298 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 1299 1300 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1301 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 1302 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1303 aml_append(dev, method); 1304 1305 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1306 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 1307 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1308 aml_append(dev, method); 1309 1310 method = aml_method("_PXM", 0, AML_NOTSERIALIZED); 1311 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 1312 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1313 aml_append(dev, method); 1314 1315 method = aml_method("_OST", 3, AML_NOTSERIALIZED); 1316 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 1317 aml_append(method, aml_return(aml_call4( 1318 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 1319 ))); 1320 aml_append(dev, method); 1321 1322 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1323 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); 1324 aml_append(method, aml_return(aml_call2( 1325 s, aml_name("_UID"), aml_arg(0)))); 1326 aml_append(dev, method); 1327 1328 aml_append(sb_scope, dev); 1329 } 1330 1331 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 1332 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 1333 */ 1334 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2, 1335 AML_NOTSERIALIZED); 1336 for (i = 0; i < nr_mem; i++) { 1337 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1338 aml_append(ifctx, 1339 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 1340 ); 1341 aml_append(method, ifctx); 1342 } 1343 aml_append(sb_scope, method); 1344 1345 { 1346 Object *pci_host; 1347 PCIBus *bus = NULL; 1348 1349 pci_host = acpi_get_i386_pci_host(); 1350 if (pci_host) { 1351 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1352 } 1353 1354 if (bus) { 1355 Aml *scope = aml_scope("PCI0"); 1356 /* Scan all PCI buses. Generate tables to support hotplug. */ 1357 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1358 1359 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 1360 dev = aml_device("ISA.TPM"); 1361 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 1362 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1363 crs = aml_resource_template(); 1364 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1365 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1366 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); 1367 aml_append(dev, aml_name_decl("_CRS", crs)); 1368 aml_append(scope, dev); 1369 } 1370 1371 aml_append(sb_scope, scope); 1372 } 1373 } 1374 aml_append(ssdt, sb_scope); 1375 } 1376 1377 /* copy AML table into ACPI tables blob and patch header there */ 1378 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 1379 build_header(linker, table_data, 1380 (void *)(table_data->data + table_data->len - ssdt->buf->len), 1381 "SSDT", ssdt->buf->len, 1, NULL); 1382 free_aml_allocator(); 1383 } 1384 1385 static void 1386 build_hpet(GArray *table_data, GArray *linker) 1387 { 1388 Acpi20Hpet *hpet; 1389 1390 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1391 /* Note timer_block_id value must be kept in sync with value advertised by 1392 * emulated hpet 1393 */ 1394 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1395 hpet->addr.address = cpu_to_le64(HPET_BASE); 1396 build_header(linker, table_data, 1397 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL); 1398 } 1399 1400 static void 1401 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 1402 { 1403 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1404 uint64_t log_area_start_address = acpi_data_len(tcpalog); 1405 1406 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1407 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1408 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 1409 1410 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 1411 false /* high memory */); 1412 1413 /* log area start address to be filled by Guest linker */ 1414 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1415 ACPI_BUILD_TPMLOG_FILE, 1416 table_data, &tcpa->log_area_start_address, 1417 sizeof(tcpa->log_area_start_address)); 1418 1419 build_header(linker, table_data, 1420 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL); 1421 1422 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1423 } 1424 1425 static void 1426 build_tpm2(GArray *table_data, GArray *linker) 1427 { 1428 Acpi20TPM2 *tpm2_ptr; 1429 1430 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 1431 1432 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 1433 tpm2_ptr->control_area_address = cpu_to_le64(0); 1434 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 1435 1436 build_header(linker, table_data, 1437 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL); 1438 } 1439 1440 typedef enum { 1441 MEM_AFFINITY_NOFLAGS = 0, 1442 MEM_AFFINITY_ENABLED = (1 << 0), 1443 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1444 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1445 } MemoryAffinityFlags; 1446 1447 static void 1448 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1449 uint64_t len, int node, MemoryAffinityFlags flags) 1450 { 1451 numamem->type = ACPI_SRAT_MEMORY; 1452 numamem->length = sizeof(*numamem); 1453 memset(numamem->proximity, 0, 4); 1454 numamem->proximity[0] = node; 1455 numamem->flags = cpu_to_le32(flags); 1456 numamem->base_addr = cpu_to_le64(base); 1457 numamem->range_length = cpu_to_le64(len); 1458 } 1459 1460 static void 1461 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1462 { 1463 AcpiSystemResourceAffinityTable *srat; 1464 AcpiSratProcessorAffinity *core; 1465 AcpiSratMemoryAffinity *numamem; 1466 1467 int i; 1468 uint64_t curnode; 1469 int srat_start, numa_start, slots; 1470 uint64_t mem_len, mem_base, next_base; 1471 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1472 ram_addr_t hotplugabble_address_space_size = 1473 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1474 NULL); 1475 1476 srat_start = table_data->len; 1477 1478 srat = acpi_data_push(table_data, sizeof *srat); 1479 srat->reserved1 = cpu_to_le32(1); 1480 core = (void *)(srat + 1); 1481 1482 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1483 core = acpi_data_push(table_data, sizeof *core); 1484 core->type = ACPI_SRAT_PROCESSOR; 1485 core->length = sizeof(*core); 1486 core->local_apic_id = i; 1487 curnode = guest_info->node_cpu[i]; 1488 core->proximity_lo = curnode; 1489 memset(core->proximity_hi, 0, 3); 1490 core->local_sapic_eid = 0; 1491 core->flags = cpu_to_le32(1); 1492 } 1493 1494 1495 /* the memory map is a bit tricky, it contains at least one hole 1496 * from 640k-1M and possibly another one from 3.5G-4G. 1497 */ 1498 next_base = 0; 1499 numa_start = table_data->len; 1500 1501 numamem = acpi_data_push(table_data, sizeof *numamem); 1502 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1503 next_base = 1024 * 1024; 1504 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1505 mem_base = next_base; 1506 mem_len = guest_info->node_mem[i - 1]; 1507 if (i == 1) { 1508 mem_len -= 1024 * 1024; 1509 } 1510 next_base = mem_base + mem_len; 1511 1512 /* Cut out the ACPI_PCI hole */ 1513 if (mem_base <= guest_info->ram_size_below_4g && 1514 next_base > guest_info->ram_size_below_4g) { 1515 mem_len -= next_base - guest_info->ram_size_below_4g; 1516 if (mem_len > 0) { 1517 numamem = acpi_data_push(table_data, sizeof *numamem); 1518 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1519 MEM_AFFINITY_ENABLED); 1520 } 1521 mem_base = 1ULL << 32; 1522 mem_len = next_base - guest_info->ram_size_below_4g; 1523 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1524 } 1525 numamem = acpi_data_push(table_data, sizeof *numamem); 1526 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1527 MEM_AFFINITY_ENABLED); 1528 } 1529 slots = (table_data->len - numa_start) / sizeof *numamem; 1530 for (; slots < guest_info->numa_nodes + 2; slots++) { 1531 numamem = acpi_data_push(table_data, sizeof *numamem); 1532 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1533 } 1534 1535 /* 1536 * Entry is required for Windows to enable memory hotplug in OS. 1537 * Memory devices may override proximity set by this entry, 1538 * providing _PXM method if necessary. 1539 */ 1540 if (hotplugabble_address_space_size) { 1541 numamem = acpi_data_push(table_data, sizeof *numamem); 1542 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base, 1543 hotplugabble_address_space_size, 0, 1544 MEM_AFFINITY_HOTPLUGGABLE | 1545 MEM_AFFINITY_ENABLED); 1546 } 1547 1548 build_header(linker, table_data, 1549 (void *)(table_data->data + srat_start), 1550 "SRAT", 1551 table_data->len - srat_start, 1, NULL); 1552 } 1553 1554 static void 1555 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1556 { 1557 AcpiTableMcfg *mcfg; 1558 const char *sig; 1559 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1560 1561 mcfg = acpi_data_push(table_data, len); 1562 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1563 /* Only a single allocation so no need to play with segments */ 1564 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1565 mcfg->allocation[0].start_bus_number = 0; 1566 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1567 1568 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1569 * To avoid table size changes (which create migration issues), 1570 * always create the table even if there are no allocations, 1571 * but set the signature to a reserved value in this case. 1572 * ACPI spec requires OSPMs to ignore such tables. 1573 */ 1574 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1575 /* Reserved signature: ignored by OSPM */ 1576 sig = "QEMU"; 1577 } else { 1578 sig = "MCFG"; 1579 } 1580 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL); 1581 } 1582 1583 static void 1584 build_dmar_q35(GArray *table_data, GArray *linker) 1585 { 1586 int dmar_start = table_data->len; 1587 1588 AcpiTableDmar *dmar; 1589 AcpiDmarHardwareUnit *drhd; 1590 1591 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1592 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1593 dmar->flags = 0; /* No intr_remap for now */ 1594 1595 /* DMAR Remapping Hardware Unit Definition structure */ 1596 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1597 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1598 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1599 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1600 drhd->pci_segment = cpu_to_le16(0); 1601 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1602 1603 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1604 "DMAR", table_data->len - dmar_start, 1, NULL); 1605 } 1606 1607 static void 1608 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1609 { 1610 AcpiTableHeader *dsdt; 1611 1612 assert(misc->dsdt_code && misc->dsdt_size); 1613 1614 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1615 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1616 1617 memset(dsdt, 0, sizeof *dsdt); 1618 build_header(linker, table_data, dsdt, "DSDT", 1619 misc->dsdt_size, 1, NULL); 1620 } 1621 1622 static GArray * 1623 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1624 { 1625 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1626 1627 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1628 true /* fseg memory */); 1629 1630 memcpy(&rsdp->signature, "RSD PTR ", 8); 1631 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1632 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1633 /* Address to be filled by Guest linker */ 1634 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1635 ACPI_BUILD_TABLE_FILE, 1636 rsdp_table, &rsdp->rsdt_physical_address, 1637 sizeof rsdp->rsdt_physical_address); 1638 rsdp->checksum = 0; 1639 /* Checksum to be filled by Guest linker */ 1640 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1641 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1642 1643 return rsdp_table; 1644 } 1645 1646 typedef 1647 struct AcpiBuildState { 1648 /* Copy of table in RAM (for patching). */ 1649 MemoryRegion *table_mr; 1650 /* Is table patched? */ 1651 uint8_t patched; 1652 PcGuestInfo *guest_info; 1653 void *rsdp; 1654 MemoryRegion *rsdp_mr; 1655 MemoryRegion *linker_mr; 1656 } AcpiBuildState; 1657 1658 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1659 { 1660 Object *pci_host; 1661 QObject *o; 1662 1663 pci_host = acpi_get_i386_pci_host(); 1664 g_assert(pci_host); 1665 1666 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1667 if (!o) { 1668 return false; 1669 } 1670 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1671 qobject_decref(o); 1672 1673 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1674 assert(o); 1675 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1676 qobject_decref(o); 1677 return true; 1678 } 1679 1680 static bool acpi_has_iommu(void) 1681 { 1682 bool ambiguous; 1683 Object *intel_iommu; 1684 1685 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1686 &ambiguous); 1687 return intel_iommu && !ambiguous; 1688 } 1689 1690 static bool acpi_has_nvdimm(void) 1691 { 1692 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1693 1694 return pcms->nvdimm; 1695 } 1696 1697 static 1698 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1699 { 1700 GArray *table_offsets; 1701 unsigned facs, ssdt, dsdt, rsdt; 1702 AcpiCpuInfo cpu; 1703 AcpiPmInfo pm; 1704 AcpiMiscInfo misc; 1705 AcpiMcfgInfo mcfg; 1706 PcPciInfo pci; 1707 uint8_t *u; 1708 size_t aml_len = 0; 1709 GArray *tables_blob = tables->table_data; 1710 1711 acpi_get_cpu_info(&cpu); 1712 acpi_get_pm_info(&pm); 1713 acpi_get_dsdt(&misc); 1714 acpi_get_misc_info(&misc); 1715 acpi_get_pci_info(&pci); 1716 1717 table_offsets = g_array_new(false, true /* clear */, 1718 sizeof(uint32_t)); 1719 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1720 1721 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1722 64 /* Ensure FACS is aligned */, 1723 false /* high memory */); 1724 1725 /* 1726 * FACS is pointed to by FADT. 1727 * We place it first since it's the only table that has alignment 1728 * requirements. 1729 */ 1730 facs = tables_blob->len; 1731 build_facs(tables_blob, tables->linker, guest_info); 1732 1733 /* DSDT is pointed to by FADT */ 1734 dsdt = tables_blob->len; 1735 build_dsdt(tables_blob, tables->linker, &misc); 1736 1737 /* Count the size of the DSDT and SSDT, we will need it for legacy 1738 * sizing of ACPI tables. 1739 */ 1740 aml_len += tables_blob->len - dsdt; 1741 1742 /* ACPI tables pointed to by RSDT */ 1743 acpi_add_table(table_offsets, tables_blob); 1744 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1745 1746 ssdt = tables_blob->len; 1747 acpi_add_table(table_offsets, tables_blob); 1748 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1749 guest_info); 1750 aml_len += tables_blob->len - ssdt; 1751 1752 acpi_add_table(table_offsets, tables_blob); 1753 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1754 1755 if (misc.has_hpet) { 1756 acpi_add_table(table_offsets, tables_blob); 1757 build_hpet(tables_blob, tables->linker); 1758 } 1759 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 1760 acpi_add_table(table_offsets, tables_blob); 1761 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1762 1763 if (misc.tpm_version == TPM_VERSION_2_0) { 1764 acpi_add_table(table_offsets, tables_blob); 1765 build_tpm2(tables_blob, tables->linker); 1766 } 1767 } 1768 if (guest_info->numa_nodes) { 1769 acpi_add_table(table_offsets, tables_blob); 1770 build_srat(tables_blob, tables->linker, guest_info); 1771 } 1772 if (acpi_get_mcfg(&mcfg)) { 1773 acpi_add_table(table_offsets, tables_blob); 1774 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1775 } 1776 if (acpi_has_iommu()) { 1777 acpi_add_table(table_offsets, tables_blob); 1778 build_dmar_q35(tables_blob, tables->linker); 1779 } 1780 1781 if (acpi_has_nvdimm()) { 1782 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); 1783 } 1784 1785 /* Add tables supplied by user (if any) */ 1786 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1787 unsigned len = acpi_table_len(u); 1788 1789 acpi_add_table(table_offsets, tables_blob); 1790 g_array_append_vals(tables_blob, u, len); 1791 } 1792 1793 /* RSDT is pointed to by RSDP */ 1794 rsdt = tables_blob->len; 1795 build_rsdt(tables_blob, tables->linker, table_offsets); 1796 1797 /* RSDP is in FSEG memory, so allocate it separately */ 1798 build_rsdp(tables->rsdp, tables->linker, rsdt); 1799 1800 /* We'll expose it all to Guest so we want to reduce 1801 * chance of size changes. 1802 * 1803 * We used to align the tables to 4k, but of course this would 1804 * too simple to be enough. 4k turned out to be too small an 1805 * alignment very soon, and in fact it is almost impossible to 1806 * keep the table size stable for all (max_cpus, max_memory_slots) 1807 * combinations. So the table size is always 64k for pc-i440fx-2.1 1808 * and we give an error if the table grows beyond that limit. 1809 * 1810 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1811 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1812 * than 2.0 and we can always pad the smaller tables with zeros. We can 1813 * then use the exact size of the 2.0 tables. 1814 * 1815 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1816 */ 1817 if (guest_info->legacy_acpi_table_size) { 1818 /* Subtracting aml_len gives the size of fixed tables. Then add the 1819 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1820 */ 1821 int legacy_aml_len = 1822 guest_info->legacy_acpi_table_size + 1823 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1824 int legacy_table_size = 1825 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1826 ACPI_BUILD_ALIGN_SIZE); 1827 if (tables_blob->len > legacy_table_size) { 1828 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1829 error_report("Warning: migration may not work."); 1830 } 1831 g_array_set_size(tables_blob, legacy_table_size); 1832 } else { 1833 /* Make sure we have a buffer in case we need to resize the tables. */ 1834 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1835 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1836 error_report("Warning: ACPI tables are larger than 64k."); 1837 error_report("Warning: migration may not work."); 1838 error_report("Warning: please remove CPUs, NUMA nodes, " 1839 "memory slots or PCI bridges."); 1840 } 1841 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1842 } 1843 1844 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1845 1846 /* Cleanup memory that's no longer used. */ 1847 g_array_free(table_offsets, true); 1848 } 1849 1850 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 1851 { 1852 uint32_t size = acpi_data_len(data); 1853 1854 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1855 memory_region_ram_resize(mr, size, &error_abort); 1856 1857 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 1858 memory_region_set_dirty(mr, 0, size); 1859 } 1860 1861 static void acpi_build_update(void *build_opaque) 1862 { 1863 AcpiBuildState *build_state = build_opaque; 1864 AcpiBuildTables tables; 1865 1866 /* No state to update or already patched? Nothing to do. */ 1867 if (!build_state || build_state->patched) { 1868 return; 1869 } 1870 build_state->patched = 1; 1871 1872 acpi_build_tables_init(&tables); 1873 1874 acpi_build(build_state->guest_info, &tables); 1875 1876 acpi_ram_update(build_state->table_mr, tables.table_data); 1877 1878 if (build_state->rsdp) { 1879 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1880 } else { 1881 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 1882 } 1883 1884 acpi_ram_update(build_state->linker_mr, tables.linker); 1885 acpi_build_tables_cleanup(&tables, true); 1886 } 1887 1888 static void acpi_build_reset(void *build_opaque) 1889 { 1890 AcpiBuildState *build_state = build_opaque; 1891 build_state->patched = 0; 1892 } 1893 1894 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 1895 GArray *blob, const char *name, 1896 uint64_t max_size) 1897 { 1898 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1899 name, acpi_build_update, build_state); 1900 } 1901 1902 static const VMStateDescription vmstate_acpi_build = { 1903 .name = "acpi_build", 1904 .version_id = 1, 1905 .minimum_version_id = 1, 1906 .fields = (VMStateField[]) { 1907 VMSTATE_UINT8(patched, AcpiBuildState), 1908 VMSTATE_END_OF_LIST() 1909 }, 1910 }; 1911 1912 void acpi_setup(PcGuestInfo *guest_info) 1913 { 1914 AcpiBuildTables tables; 1915 AcpiBuildState *build_state; 1916 1917 if (!guest_info->fw_cfg) { 1918 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1919 return; 1920 } 1921 1922 if (!guest_info->has_acpi_build) { 1923 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1924 return; 1925 } 1926 1927 if (!acpi_enabled) { 1928 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1929 return; 1930 } 1931 1932 build_state = g_malloc0(sizeof *build_state); 1933 1934 build_state->guest_info = guest_info; 1935 1936 acpi_set_pci_info(); 1937 1938 acpi_build_tables_init(&tables); 1939 acpi_build(build_state->guest_info, &tables); 1940 1941 /* Now expose it all to Guest */ 1942 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 1943 ACPI_BUILD_TABLE_FILE, 1944 ACPI_BUILD_TABLE_MAX_SIZE); 1945 assert(build_state->table_mr != NULL); 1946 1947 build_state->linker_mr = 1948 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1949 1950 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1951 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1952 1953 if (!guest_info->rsdp_in_ram) { 1954 /* 1955 * Keep for compatibility with old machine types. 1956 * Though RSDP is small, its contents isn't immutable, so 1957 * we'll update it along with the rest of tables on guest access. 1958 */ 1959 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1960 1961 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1962 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1963 acpi_build_update, build_state, 1964 build_state->rsdp, rsdp_size); 1965 build_state->rsdp_mr = NULL; 1966 } else { 1967 build_state->rsdp = NULL; 1968 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 1969 ACPI_BUILD_RSDP_FILE, 0); 1970 } 1971 1972 qemu_register_reset(acpi_build_reset, build_state); 1973 acpi_build_reset(build_state); 1974 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1975 1976 /* Cleanup tables but don't free the memory: we track it 1977 * in build_state. 1978 */ 1979 acpi_build_tables_cleanup(&tables, false); 1980 } 1981