1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 69 #include "qom/qom-qobject.h" 70 #include "hw/i386/amd_iommu.h" 71 #include "hw/i386/intel_iommu.h" 72 73 #include "hw/acpi/ipmi.h" 74 #include "hw/acpi/hmat.h" 75 76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 78 * a little bit, there should be plenty of free space since the DSDT 79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 80 */ 81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 82 #define ACPI_BUILD_ALIGN_SIZE 0x1000 83 84 #define ACPI_BUILD_TABLE_SIZE 0x20000 85 86 /* #define DEBUG_ACPI_BUILD */ 87 #ifdef DEBUG_ACPI_BUILD 88 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 90 #else 91 #define ACPI_BUILD_DPRINTF(fmt, ...) 92 #endif 93 94 typedef struct AcpiPmInfo { 95 bool s3_disabled; 96 bool s4_disabled; 97 bool pcihp_bridge_en; 98 bool smi_on_cpuhp; 99 bool pcihp_root_en; 100 uint8_t s4_val; 101 AcpiFadtData fadt; 102 uint16_t cpu_hp_io_base; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool is_piix4; 109 bool has_hpet; 110 TPMVersion tpm_version; 111 const unsigned char *dsdt_code; 112 unsigned dsdt_size; 113 uint16_t pvpanic_port; 114 uint16_t applesmc_io_base; 115 } AcpiMiscInfo; 116 117 typedef struct AcpiBuildPciBusHotplugState { 118 GArray *device_table; 119 GArray *notify_table; 120 struct AcpiBuildPciBusHotplugState *parent; 121 bool pcihp_bridge_en; 122 } AcpiBuildPciBusHotplugState; 123 124 typedef struct FwCfgTPMConfig { 125 uint32_t tpmppi_address; 126 uint8_t tpm_version; 127 uint8_t tpmppi_version; 128 } QEMU_PACKED FwCfgTPMConfig; 129 130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 131 132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 133 .space_id = AML_AS_SYSTEM_IO, 134 .address = NVDIMM_ACPI_IO_BASE, 135 .bit_width = NVDIMM_ACPI_IO_LEN << 3 136 }; 137 138 static void init_common_fadt_data(MachineState *ms, Object *o, 139 AcpiFadtData *data) 140 { 141 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 142 AmlAddressSpace as = AML_AS_SYSTEM_IO; 143 AcpiFadtData fadt = { 144 .rev = 3, 145 .flags = 146 (1 << ACPI_FADT_F_WBINVD) | 147 (1 << ACPI_FADT_F_PROC_C1) | 148 (1 << ACPI_FADT_F_SLP_BUTTON) | 149 (1 << ACPI_FADT_F_RTC_S4) | 150 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 151 /* APIC destination mode ("Flat Logical") has an upper limit of 8 152 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 153 * used 154 */ 155 ((ms->smp.max_cpus > 8) ? 156 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 157 .int_model = 1 /* Multiple APIC */, 158 .rtc_century = RTC_CENTURY, 159 .plvl2_lat = 0xfff /* C2 state not supported */, 160 .plvl3_lat = 0xfff /* C3 state not supported */, 161 .smi_cmd = ACPI_PORT_SMI_CMD, 162 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 163 .acpi_enable_cmd = 164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 165 .acpi_disable_cmd = 166 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 167 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 168 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 169 .address = io + 0x04 }, 170 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 171 .gpe0_blk = { .space_id = as, .bit_width = 172 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 173 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 174 }, 175 }; 176 *data = fadt; 177 } 178 179 static Object *object_resolve_type_unambiguous(const char *typename) 180 { 181 bool ambig; 182 Object *o = object_resolve_path_type("", typename, &ambig); 183 184 if (ambig || !o) { 185 return NULL; 186 } 187 return o; 188 } 189 190 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 191 { 192 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 193 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 194 Object *obj = piix ? piix : lpc; 195 QObject *o; 196 pm->cpu_hp_io_base = 0; 197 pm->pcihp_io_base = 0; 198 pm->pcihp_io_len = 0; 199 pm->smi_on_cpuhp = false; 200 201 assert(obj); 202 init_common_fadt_data(machine, obj, &pm->fadt); 203 if (piix) { 204 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 205 pm->fadt.rev = 1; 206 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 207 pm->pcihp_io_base = 208 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 209 pm->pcihp_io_len = 210 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 211 } 212 if (lpc) { 213 uint64_t smi_features = object_property_get_uint(lpc, 214 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 215 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 216 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 217 pm->fadt.reset_reg = r; 218 pm->fadt.reset_val = 0xf; 219 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 220 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 221 pm->smi_on_cpuhp = 222 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 223 } 224 225 /* The above need not be conditional on machine type because the reset port 226 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 227 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 228 229 /* Fill in optional s3/s4 related properties */ 230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 231 if (o) { 232 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 233 } else { 234 pm->s3_disabled = false; 235 } 236 qobject_unref(o); 237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 238 if (o) { 239 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 240 } else { 241 pm->s4_disabled = false; 242 } 243 qobject_unref(o); 244 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 245 if (o) { 246 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 247 } else { 248 pm->s4_val = false; 249 } 250 qobject_unref(o); 251 252 pm->pcihp_bridge_en = 253 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 254 NULL); 255 pm->pcihp_root_en = 256 object_property_get_bool(obj, "acpi-root-pci-hotplug", 257 NULL); 258 } 259 260 static void acpi_get_misc_info(AcpiMiscInfo *info) 261 { 262 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 263 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 264 assert(!!piix != !!lpc); 265 266 if (piix) { 267 info->is_piix4 = true; 268 } 269 if (lpc) { 270 info->is_piix4 = false; 271 } 272 273 info->has_hpet = hpet_find(); 274 info->tpm_version = tpm_get_version(tpm_find()); 275 info->pvpanic_port = pvpanic_port(); 276 info->applesmc_io_base = applesmc_port(); 277 } 278 279 /* 280 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 281 * On i386 arch we only have two pci hosts, so we can look only for them. 282 */ 283 static Object *acpi_get_i386_pci_host(void) 284 { 285 PCIHostState *host; 286 287 host = OBJECT_CHECK(PCIHostState, 288 object_resolve_path("/machine/i440fx", NULL), 289 TYPE_PCI_HOST_BRIDGE); 290 if (!host) { 291 host = OBJECT_CHECK(PCIHostState, 292 object_resolve_path("/machine/q35", NULL), 293 TYPE_PCI_HOST_BRIDGE); 294 } 295 296 return OBJECT(host); 297 } 298 299 static void acpi_get_pci_holes(Range *hole, Range *hole64) 300 { 301 Object *pci_host; 302 303 pci_host = acpi_get_i386_pci_host(); 304 g_assert(pci_host); 305 306 range_set_bounds1(hole, 307 object_property_get_uint(pci_host, 308 PCI_HOST_PROP_PCI_HOLE_START, 309 NULL), 310 object_property_get_uint(pci_host, 311 PCI_HOST_PROP_PCI_HOLE_END, 312 NULL)); 313 range_set_bounds1(hole64, 314 object_property_get_uint(pci_host, 315 PCI_HOST_PROP_PCI_HOLE64_START, 316 NULL), 317 object_property_get_uint(pci_host, 318 PCI_HOST_PROP_PCI_HOLE64_END, 319 NULL)); 320 } 321 322 static void acpi_align_size(GArray *blob, unsigned align) 323 { 324 /* Align size to multiple of given size. This reduces the chance 325 * we need to change size in the future (breaking cross version migration). 326 */ 327 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 328 } 329 330 /* FACS */ 331 static void 332 build_facs(GArray *table_data) 333 { 334 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 335 memcpy(&facs->signature, "FACS", 4); 336 facs->length = cpu_to_le32(sizeof(*facs)); 337 } 338 339 static void build_append_pcihp_notify_entry(Aml *method, int slot) 340 { 341 Aml *if_ctx; 342 int32_t devfn = PCI_DEVFN(slot, 0); 343 344 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 345 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 346 aml_append(method, if_ctx); 347 } 348 349 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 350 bool pcihp_bridge_en) 351 { 352 Aml *dev, *notify_method = NULL, *method; 353 QObject *bsel; 354 PCIBus *sec; 355 int i; 356 357 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 358 if (bsel) { 359 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 360 361 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 362 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 363 } 364 365 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 366 DeviceClass *dc; 367 PCIDeviceClass *pc; 368 PCIDevice *pdev = bus->devices[i]; 369 int slot = PCI_SLOT(i); 370 bool hotplug_enabled_dev; 371 bool bridge_in_acpi; 372 bool cold_plugged_bridge; 373 374 if (!pdev) { 375 if (bsel) { /* add hotplug slots for non present devices */ 376 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 377 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 378 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 379 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 380 aml_append(method, 381 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 382 ); 383 aml_append(dev, method); 384 aml_append(parent_scope, dev); 385 386 build_append_pcihp_notify_entry(notify_method, slot); 387 } 388 continue; 389 } 390 391 pc = PCI_DEVICE_GET_CLASS(pdev); 392 dc = DEVICE_GET_CLASS(pdev); 393 394 /* 395 * Cold plugged bridges aren't themselves hot-pluggable. 396 * Hotplugged bridges *are* hot-pluggable. 397 */ 398 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 399 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 400 401 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 402 403 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 404 continue; 405 } 406 407 /* start to compose PCI slot descriptor */ 408 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 409 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 410 411 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 412 /* add VGA specific AML methods */ 413 int s3d; 414 415 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 416 s3d = 3; 417 } else { 418 s3d = 0; 419 } 420 421 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 422 aml_append(method, aml_return(aml_int(0))); 423 aml_append(dev, method); 424 425 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 426 aml_append(method, aml_return(aml_int(0))); 427 aml_append(dev, method); 428 429 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 430 aml_append(method, aml_return(aml_int(s3d))); 431 aml_append(dev, method); 432 } else if (hotplug_enabled_dev) { 433 /* add _SUN/_EJ0 to make slot hotpluggable */ 434 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 435 436 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 437 aml_append(method, 438 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 439 ); 440 aml_append(dev, method); 441 442 if (bsel) { 443 build_append_pcihp_notify_entry(notify_method, slot); 444 } 445 } else if (bridge_in_acpi) { 446 /* 447 * device is coldplugged bridge, 448 * add child device descriptions into its scope 449 */ 450 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 451 452 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 453 } 454 /* slot descriptor has been composed, add it into parent context */ 455 aml_append(parent_scope, dev); 456 } 457 458 if (bsel) { 459 aml_append(parent_scope, notify_method); 460 } 461 462 /* Append PCNT method to notify about events on local and child buses. 463 * Add this method for root bus only when hotplug is enabled since DSDT 464 * expects it. 465 */ 466 if (bsel || pcihp_bridge_en) { 467 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 468 } 469 /* If bus supports hotplug select it and notify about local events */ 470 if (bsel) { 471 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 472 473 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 474 aml_append(method, 475 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 476 ); 477 aml_append(method, 478 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 479 ); 480 } 481 482 /* Notify about child bus events in any case */ 483 if (pcihp_bridge_en) { 484 QLIST_FOREACH(sec, &bus->child, sibling) { 485 int32_t devfn = sec->parent_dev->devfn; 486 487 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 488 continue; 489 } 490 491 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 492 } 493 } 494 495 if (bsel || pcihp_bridge_en) { 496 aml_append(parent_scope, method); 497 } 498 qobject_unref(bsel); 499 } 500 501 /** 502 * build_prt_entry: 503 * @link_name: link name for PCI route entry 504 * 505 * build AML package containing a PCI route entry for @link_name 506 */ 507 static Aml *build_prt_entry(const char *link_name) 508 { 509 Aml *a_zero = aml_int(0); 510 Aml *pkg = aml_package(4); 511 aml_append(pkg, a_zero); 512 aml_append(pkg, a_zero); 513 aml_append(pkg, aml_name("%s", link_name)); 514 aml_append(pkg, a_zero); 515 return pkg; 516 } 517 518 /* 519 * initialize_route - Initialize the interrupt routing rule 520 * through a specific LINK: 521 * if (lnk_idx == idx) 522 * route using link 'link_name' 523 */ 524 static Aml *initialize_route(Aml *route, const char *link_name, 525 Aml *lnk_idx, int idx) 526 { 527 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 528 Aml *pkg = build_prt_entry(link_name); 529 530 aml_append(if_ctx, aml_store(pkg, route)); 531 532 return if_ctx; 533 } 534 535 /* 536 * build_prt - Define interrupt rounting rules 537 * 538 * Returns an array of 128 routes, one for each device, 539 * based on device location. 540 * The main goal is to equaly distribute the interrupts 541 * over the 4 existing ACPI links (works only for i440fx). 542 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 543 * 544 */ 545 static Aml *build_prt(bool is_pci0_prt) 546 { 547 Aml *method, *while_ctx, *pin, *res; 548 549 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 550 res = aml_local(0); 551 pin = aml_local(1); 552 aml_append(method, aml_store(aml_package(128), res)); 553 aml_append(method, aml_store(aml_int(0), pin)); 554 555 /* while (pin < 128) */ 556 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 557 { 558 Aml *slot = aml_local(2); 559 Aml *lnk_idx = aml_local(3); 560 Aml *route = aml_local(4); 561 562 /* slot = pin >> 2 */ 563 aml_append(while_ctx, 564 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 565 /* lnk_idx = (slot + pin) & 3 */ 566 aml_append(while_ctx, 567 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 568 lnk_idx)); 569 570 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 571 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 572 if (is_pci0_prt) { 573 Aml *if_device_1, *if_pin_4, *else_pin_4; 574 575 /* device 1 is the power-management device, needs SCI */ 576 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 577 { 578 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 579 { 580 aml_append(if_pin_4, 581 aml_store(build_prt_entry("LNKS"), route)); 582 } 583 aml_append(if_device_1, if_pin_4); 584 else_pin_4 = aml_else(); 585 { 586 aml_append(else_pin_4, 587 aml_store(build_prt_entry("LNKA"), route)); 588 } 589 aml_append(if_device_1, else_pin_4); 590 } 591 aml_append(while_ctx, if_device_1); 592 } else { 593 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 594 } 595 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 596 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 597 598 /* route[0] = 0x[slot]FFFF */ 599 aml_append(while_ctx, 600 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 601 NULL), 602 aml_index(route, aml_int(0)))); 603 /* route[1] = pin & 3 */ 604 aml_append(while_ctx, 605 aml_store(aml_and(pin, aml_int(3), NULL), 606 aml_index(route, aml_int(1)))); 607 /* res[pin] = route */ 608 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 609 /* pin++ */ 610 aml_append(while_ctx, aml_increment(pin)); 611 } 612 aml_append(method, while_ctx); 613 /* return res*/ 614 aml_append(method, aml_return(res)); 615 616 return method; 617 } 618 619 typedef struct CrsRangeEntry { 620 uint64_t base; 621 uint64_t limit; 622 } CrsRangeEntry; 623 624 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 625 { 626 CrsRangeEntry *entry; 627 628 entry = g_malloc(sizeof(*entry)); 629 entry->base = base; 630 entry->limit = limit; 631 632 g_ptr_array_add(ranges, entry); 633 } 634 635 static void crs_range_free(gpointer data) 636 { 637 CrsRangeEntry *entry = (CrsRangeEntry *)data; 638 g_free(entry); 639 } 640 641 typedef struct CrsRangeSet { 642 GPtrArray *io_ranges; 643 GPtrArray *mem_ranges; 644 GPtrArray *mem_64bit_ranges; 645 } CrsRangeSet; 646 647 static void crs_range_set_init(CrsRangeSet *range_set) 648 { 649 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 650 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 651 range_set->mem_64bit_ranges = 652 g_ptr_array_new_with_free_func(crs_range_free); 653 } 654 655 static void crs_range_set_free(CrsRangeSet *range_set) 656 { 657 g_ptr_array_free(range_set->io_ranges, true); 658 g_ptr_array_free(range_set->mem_ranges, true); 659 g_ptr_array_free(range_set->mem_64bit_ranges, true); 660 } 661 662 static gint crs_range_compare(gconstpointer a, gconstpointer b) 663 { 664 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 665 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 666 667 if (entry_a->base < entry_b->base) { 668 return -1; 669 } else if (entry_a->base > entry_b->base) { 670 return 1; 671 } else { 672 return 0; 673 } 674 } 675 676 /* 677 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 678 * interval, computes the 'free' ranges from the same interval. 679 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 680 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 681 */ 682 static void crs_replace_with_free_ranges(GPtrArray *ranges, 683 uint64_t start, uint64_t end) 684 { 685 GPtrArray *free_ranges = g_ptr_array_new(); 686 uint64_t free_base = start; 687 int i; 688 689 g_ptr_array_sort(ranges, crs_range_compare); 690 for (i = 0; i < ranges->len; i++) { 691 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 692 693 if (free_base < used->base) { 694 crs_range_insert(free_ranges, free_base, used->base - 1); 695 } 696 697 free_base = used->limit + 1; 698 } 699 700 if (free_base < end) { 701 crs_range_insert(free_ranges, free_base, end); 702 } 703 704 g_ptr_array_set_size(ranges, 0); 705 for (i = 0; i < free_ranges->len; i++) { 706 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 707 } 708 709 g_ptr_array_free(free_ranges, true); 710 } 711 712 /* 713 * crs_range_merge - merges adjacent ranges in the given array. 714 * Array elements are deleted and replaced with the merged ranges. 715 */ 716 static void crs_range_merge(GPtrArray *range) 717 { 718 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 719 CrsRangeEntry *entry; 720 uint64_t range_base, range_limit; 721 int i; 722 723 if (!range->len) { 724 return; 725 } 726 727 g_ptr_array_sort(range, crs_range_compare); 728 729 entry = g_ptr_array_index(range, 0); 730 range_base = entry->base; 731 range_limit = entry->limit; 732 for (i = 1; i < range->len; i++) { 733 entry = g_ptr_array_index(range, i); 734 if (entry->base - 1 == range_limit) { 735 range_limit = entry->limit; 736 } else { 737 crs_range_insert(tmp, range_base, range_limit); 738 range_base = entry->base; 739 range_limit = entry->limit; 740 } 741 } 742 crs_range_insert(tmp, range_base, range_limit); 743 744 g_ptr_array_set_size(range, 0); 745 for (i = 0; i < tmp->len; i++) { 746 entry = g_ptr_array_index(tmp, i); 747 crs_range_insert(range, entry->base, entry->limit); 748 } 749 g_ptr_array_free(tmp, true); 750 } 751 752 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 753 { 754 Aml *crs = aml_resource_template(); 755 CrsRangeSet temp_range_set; 756 CrsRangeEntry *entry; 757 uint8_t max_bus = pci_bus_num(host->bus); 758 uint8_t type; 759 int devfn; 760 int i; 761 762 crs_range_set_init(&temp_range_set); 763 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 764 uint64_t range_base, range_limit; 765 PCIDevice *dev = host->bus->devices[devfn]; 766 767 if (!dev) { 768 continue; 769 } 770 771 for (i = 0; i < PCI_NUM_REGIONS; i++) { 772 PCIIORegion *r = &dev->io_regions[i]; 773 774 range_base = r->addr; 775 range_limit = r->addr + r->size - 1; 776 777 /* 778 * Work-around for old bioses 779 * that do not support multiple root buses 780 */ 781 if (!range_base || range_base > range_limit) { 782 continue; 783 } 784 785 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 786 crs_range_insert(temp_range_set.io_ranges, 787 range_base, range_limit); 788 } else { /* "memory" */ 789 crs_range_insert(temp_range_set.mem_ranges, 790 range_base, range_limit); 791 } 792 } 793 794 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 795 if (type == PCI_HEADER_TYPE_BRIDGE) { 796 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 797 if (subordinate > max_bus) { 798 max_bus = subordinate; 799 } 800 801 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 802 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 803 804 /* 805 * Work-around for old bioses 806 * that do not support multiple root buses 807 */ 808 if (range_base && range_base <= range_limit) { 809 crs_range_insert(temp_range_set.io_ranges, 810 range_base, range_limit); 811 } 812 813 range_base = 814 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 815 range_limit = 816 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 817 818 /* 819 * Work-around for old bioses 820 * that do not support multiple root buses 821 */ 822 if (range_base && range_base <= range_limit) { 823 uint64_t length = range_limit - range_base + 1; 824 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 825 crs_range_insert(temp_range_set.mem_ranges, 826 range_base, range_limit); 827 } else { 828 crs_range_insert(temp_range_set.mem_64bit_ranges, 829 range_base, range_limit); 830 } 831 } 832 833 range_base = 834 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 835 range_limit = 836 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 837 838 /* 839 * Work-around for old bioses 840 * that do not support multiple root buses 841 */ 842 if (range_base && range_base <= range_limit) { 843 uint64_t length = range_limit - range_base + 1; 844 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 845 crs_range_insert(temp_range_set.mem_ranges, 846 range_base, range_limit); 847 } else { 848 crs_range_insert(temp_range_set.mem_64bit_ranges, 849 range_base, range_limit); 850 } 851 } 852 } 853 } 854 855 crs_range_merge(temp_range_set.io_ranges); 856 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 857 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 858 aml_append(crs, 859 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 860 AML_POS_DECODE, AML_ENTIRE_RANGE, 861 0, entry->base, entry->limit, 0, 862 entry->limit - entry->base + 1)); 863 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 864 } 865 866 crs_range_merge(temp_range_set.mem_ranges); 867 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 868 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 869 aml_append(crs, 870 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 871 AML_MAX_FIXED, AML_NON_CACHEABLE, 872 AML_READ_WRITE, 873 0, entry->base, entry->limit, 0, 874 entry->limit - entry->base + 1)); 875 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 876 } 877 878 crs_range_merge(temp_range_set.mem_64bit_ranges); 879 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 880 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 881 aml_append(crs, 882 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 883 AML_MAX_FIXED, AML_NON_CACHEABLE, 884 AML_READ_WRITE, 885 0, entry->base, entry->limit, 0, 886 entry->limit - entry->base + 1)); 887 crs_range_insert(range_set->mem_64bit_ranges, 888 entry->base, entry->limit); 889 } 890 891 crs_range_set_free(&temp_range_set); 892 893 aml_append(crs, 894 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 895 0, 896 pci_bus_num(host->bus), 897 max_bus, 898 0, 899 max_bus - pci_bus_num(host->bus) + 1)); 900 901 return crs; 902 } 903 904 static void build_hpet_aml(Aml *table) 905 { 906 Aml *crs; 907 Aml *field; 908 Aml *method; 909 Aml *if_ctx; 910 Aml *scope = aml_scope("_SB"); 911 Aml *dev = aml_device("HPET"); 912 Aml *zero = aml_int(0); 913 Aml *id = aml_local(0); 914 Aml *period = aml_local(1); 915 916 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 917 aml_append(dev, aml_name_decl("_UID", zero)); 918 919 aml_append(dev, 920 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 921 HPET_LEN)); 922 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 923 aml_append(field, aml_named_field("VEND", 32)); 924 aml_append(field, aml_named_field("PRD", 32)); 925 aml_append(dev, field); 926 927 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 928 aml_append(method, aml_store(aml_name("VEND"), id)); 929 aml_append(method, aml_store(aml_name("PRD"), period)); 930 aml_append(method, aml_shiftright(id, aml_int(16), id)); 931 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 932 aml_equal(id, aml_int(0xffff)))); 933 { 934 aml_append(if_ctx, aml_return(zero)); 935 } 936 aml_append(method, if_ctx); 937 938 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 939 aml_lgreater(period, aml_int(100000000)))); 940 { 941 aml_append(if_ctx, aml_return(zero)); 942 } 943 aml_append(method, if_ctx); 944 945 aml_append(method, aml_return(aml_int(0x0F))); 946 aml_append(dev, method); 947 948 crs = aml_resource_template(); 949 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 950 aml_append(dev, aml_name_decl("_CRS", crs)); 951 952 aml_append(scope, dev); 953 aml_append(table, scope); 954 } 955 956 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 957 { 958 Aml *dev; 959 Aml *method; 960 Aml *crs; 961 962 dev = aml_device("VMBS"); 963 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 964 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 965 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 966 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 967 968 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 969 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 970 aml_name("STA"))); 971 aml_append(dev, method); 972 973 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 974 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 975 aml_name("STA"))); 976 aml_append(dev, method); 977 978 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 979 aml_append(method, aml_return(aml_name("STA"))); 980 aml_append(dev, method); 981 982 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 983 984 crs = aml_resource_template(); 985 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 986 aml_append(dev, aml_name_decl("_CRS", crs)); 987 988 return dev; 989 } 990 991 static void build_isa_devices_aml(Aml *table) 992 { 993 bool ambiguous; 994 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 995 Aml *scope; 996 997 assert(obj && !ambiguous); 998 999 scope = aml_scope("_SB.PCI0.ISA"); 1000 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 1001 isa_build_aml(ISA_BUS(obj), scope); 1002 1003 aml_append(table, scope); 1004 } 1005 1006 static void build_dbg_aml(Aml *table) 1007 { 1008 Aml *field; 1009 Aml *method; 1010 Aml *while_ctx; 1011 Aml *scope = aml_scope("\\"); 1012 Aml *buf = aml_local(0); 1013 Aml *len = aml_local(1); 1014 Aml *idx = aml_local(2); 1015 1016 aml_append(scope, 1017 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1018 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1019 aml_append(field, aml_named_field("DBGB", 8)); 1020 aml_append(scope, field); 1021 1022 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1023 1024 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1025 aml_append(method, aml_to_buffer(buf, buf)); 1026 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1027 aml_append(method, aml_store(aml_int(0), idx)); 1028 1029 while_ctx = aml_while(aml_lless(idx, len)); 1030 aml_append(while_ctx, 1031 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1032 aml_append(while_ctx, aml_increment(idx)); 1033 aml_append(method, while_ctx); 1034 1035 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1036 aml_append(scope, method); 1037 1038 aml_append(table, scope); 1039 } 1040 1041 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1042 { 1043 Aml *dev; 1044 Aml *crs; 1045 Aml *method; 1046 uint32_t irqs[] = {5, 10, 11}; 1047 1048 dev = aml_device("%s", name); 1049 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1050 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1051 1052 crs = aml_resource_template(); 1053 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1054 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1055 aml_append(dev, aml_name_decl("_PRS", crs)); 1056 1057 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_return(aml_call1("IQST", reg))); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1062 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1063 aml_append(dev, method); 1064 1065 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1066 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1067 aml_append(dev, method); 1068 1069 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1070 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1071 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1072 aml_append(dev, method); 1073 1074 return dev; 1075 } 1076 1077 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1078 { 1079 Aml *dev; 1080 Aml *crs; 1081 Aml *method; 1082 uint32_t irqs; 1083 1084 dev = aml_device("%s", name); 1085 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1086 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1087 1088 crs = aml_resource_template(); 1089 irqs = gsi; 1090 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1091 AML_SHARED, &irqs, 1)); 1092 aml_append(dev, aml_name_decl("_PRS", crs)); 1093 1094 aml_append(dev, aml_name_decl("_CRS", crs)); 1095 1096 /* 1097 * _DIS can be no-op because the interrupt cannot be disabled. 1098 */ 1099 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1100 aml_append(dev, method); 1101 1102 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1103 aml_append(dev, method); 1104 1105 return dev; 1106 } 1107 1108 /* _CRS method - get current settings */ 1109 static Aml *build_iqcr_method(bool is_piix4) 1110 { 1111 Aml *if_ctx; 1112 uint32_t irqs; 1113 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1114 Aml *crs = aml_resource_template(); 1115 1116 irqs = 0; 1117 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1118 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1119 aml_append(method, aml_name_decl("PRR0", crs)); 1120 1121 aml_append(method, 1122 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1123 1124 if (is_piix4) { 1125 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1126 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1127 aml_append(method, if_ctx); 1128 } else { 1129 aml_append(method, 1130 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1131 aml_name("PRRI"))); 1132 } 1133 1134 aml_append(method, aml_return(aml_name("PRR0"))); 1135 return method; 1136 } 1137 1138 /* _STA method - get status */ 1139 static Aml *build_irq_status_method(void) 1140 { 1141 Aml *if_ctx; 1142 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1143 1144 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1145 aml_append(if_ctx, aml_return(aml_int(0x09))); 1146 aml_append(method, if_ctx); 1147 aml_append(method, aml_return(aml_int(0x0B))); 1148 return method; 1149 } 1150 1151 static void build_piix4_pci0_int(Aml *table) 1152 { 1153 Aml *dev; 1154 Aml *crs; 1155 Aml *field; 1156 Aml *method; 1157 uint32_t irqs; 1158 Aml *sb_scope = aml_scope("_SB"); 1159 Aml *pci0_scope = aml_scope("PCI0"); 1160 1161 aml_append(pci0_scope, build_prt(true)); 1162 aml_append(sb_scope, pci0_scope); 1163 1164 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1165 aml_append(field, aml_named_field("PRQ0", 8)); 1166 aml_append(field, aml_named_field("PRQ1", 8)); 1167 aml_append(field, aml_named_field("PRQ2", 8)); 1168 aml_append(field, aml_named_field("PRQ3", 8)); 1169 aml_append(sb_scope, field); 1170 1171 aml_append(sb_scope, build_irq_status_method()); 1172 aml_append(sb_scope, build_iqcr_method(true)); 1173 1174 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1175 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1176 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1177 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1178 1179 dev = aml_device("LNKS"); 1180 { 1181 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1182 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1183 1184 crs = aml_resource_template(); 1185 irqs = 9; 1186 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1187 AML_ACTIVE_HIGH, AML_SHARED, 1188 &irqs, 1)); 1189 aml_append(dev, aml_name_decl("_PRS", crs)); 1190 1191 /* The SCI cannot be disabled and is always attached to GSI 9, 1192 * so these are no-ops. We only need this link to override the 1193 * polarity to active high and match the content of the MADT. 1194 */ 1195 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1196 aml_append(method, aml_return(aml_int(0x0b))); 1197 aml_append(dev, method); 1198 1199 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1200 aml_append(dev, method); 1201 1202 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1203 aml_append(method, aml_return(aml_name("_PRS"))); 1204 aml_append(dev, method); 1205 1206 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1207 aml_append(dev, method); 1208 } 1209 aml_append(sb_scope, dev); 1210 1211 aml_append(table, sb_scope); 1212 } 1213 1214 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1215 { 1216 int i; 1217 int head; 1218 Aml *pkg; 1219 char base = name[3] < 'E' ? 'A' : 'E'; 1220 char *s = g_strdup(name); 1221 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1222 1223 assert(strlen(s) == 4); 1224 1225 head = name[3] - base; 1226 for (i = 0; i < 4; i++) { 1227 if (head + i > 3) { 1228 head = i * -1; 1229 } 1230 s[3] = base + head + i; 1231 pkg = aml_package(4); 1232 aml_append(pkg, a_nr); 1233 aml_append(pkg, aml_int(i)); 1234 aml_append(pkg, aml_name("%s", s)); 1235 aml_append(pkg, aml_int(0)); 1236 aml_append(ctx, pkg); 1237 } 1238 g_free(s); 1239 } 1240 1241 static Aml *build_q35_routing_table(const char *str) 1242 { 1243 int i; 1244 Aml *pkg; 1245 char *name = g_strdup_printf("%s ", str); 1246 1247 pkg = aml_package(128); 1248 for (i = 0; i < 0x18; i++) { 1249 name[3] = 'E' + (i & 0x3); 1250 append_q35_prt_entry(pkg, i, name); 1251 } 1252 1253 name[3] = 'E'; 1254 append_q35_prt_entry(pkg, 0x18, name); 1255 1256 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1257 for (i = 0x0019; i < 0x1e; i++) { 1258 name[3] = 'A'; 1259 append_q35_prt_entry(pkg, i, name); 1260 } 1261 1262 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1263 name[3] = 'E'; 1264 append_q35_prt_entry(pkg, 0x1e, name); 1265 name[3] = 'A'; 1266 append_q35_prt_entry(pkg, 0x1f, name); 1267 1268 g_free(name); 1269 return pkg; 1270 } 1271 1272 static void build_q35_pci0_int(Aml *table) 1273 { 1274 Aml *field; 1275 Aml *method; 1276 Aml *sb_scope = aml_scope("_SB"); 1277 Aml *pci0_scope = aml_scope("PCI0"); 1278 1279 /* Zero => PIC mode, One => APIC Mode */ 1280 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1281 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1282 { 1283 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1284 } 1285 aml_append(table, method); 1286 1287 aml_append(pci0_scope, 1288 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1289 aml_append(pci0_scope, 1290 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1291 1292 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1293 { 1294 Aml *if_ctx; 1295 Aml *else_ctx; 1296 1297 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1298 section 6.2.8.1 */ 1299 /* Note: we provide the same info as the PCI routing 1300 table of the Bochs BIOS */ 1301 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1302 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1303 aml_append(method, if_ctx); 1304 else_ctx = aml_else(); 1305 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1306 aml_append(method, else_ctx); 1307 } 1308 aml_append(pci0_scope, method); 1309 aml_append(sb_scope, pci0_scope); 1310 1311 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1312 aml_append(field, aml_named_field("PRQA", 8)); 1313 aml_append(field, aml_named_field("PRQB", 8)); 1314 aml_append(field, aml_named_field("PRQC", 8)); 1315 aml_append(field, aml_named_field("PRQD", 8)); 1316 aml_append(field, aml_reserved_field(0x20)); 1317 aml_append(field, aml_named_field("PRQE", 8)); 1318 aml_append(field, aml_named_field("PRQF", 8)); 1319 aml_append(field, aml_named_field("PRQG", 8)); 1320 aml_append(field, aml_named_field("PRQH", 8)); 1321 aml_append(sb_scope, field); 1322 1323 aml_append(sb_scope, build_irq_status_method()); 1324 aml_append(sb_scope, build_iqcr_method(false)); 1325 1326 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1327 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1328 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1329 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1330 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1331 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1332 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1333 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1334 1335 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1336 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1337 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1338 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1339 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1340 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1341 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1342 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1343 1344 aml_append(table, sb_scope); 1345 } 1346 1347 static void build_q35_isa_bridge(Aml *table) 1348 { 1349 Aml *dev; 1350 Aml *scope; 1351 1352 scope = aml_scope("_SB.PCI0"); 1353 dev = aml_device("ISA"); 1354 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1355 1356 /* ICH9 PCI to ISA irq remapping */ 1357 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1358 aml_int(0x60), 0x0C)); 1359 1360 aml_append(scope, dev); 1361 aml_append(table, scope); 1362 } 1363 1364 static void build_piix4_isa_bridge(Aml *table) 1365 { 1366 Aml *dev; 1367 Aml *scope; 1368 1369 scope = aml_scope("_SB.PCI0"); 1370 dev = aml_device("ISA"); 1371 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1372 1373 /* PIIX PCI to ISA irq remapping */ 1374 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1375 aml_int(0x60), 0x04)); 1376 1377 aml_append(scope, dev); 1378 aml_append(table, scope); 1379 } 1380 1381 static void build_piix4_pci_hotplug(Aml *table) 1382 { 1383 Aml *scope; 1384 Aml *field; 1385 Aml *method; 1386 1387 scope = aml_scope("_SB.PCI0"); 1388 1389 aml_append(scope, 1390 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1391 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1392 aml_append(field, aml_named_field("PCIU", 32)); 1393 aml_append(field, aml_named_field("PCID", 32)); 1394 aml_append(scope, field); 1395 1396 aml_append(scope, 1397 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1398 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1399 aml_append(field, aml_named_field("B0EJ", 32)); 1400 aml_append(scope, field); 1401 1402 aml_append(scope, 1403 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1404 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1405 aml_append(field, aml_named_field("BNUM", 32)); 1406 aml_append(scope, field); 1407 1408 aml_append(scope, aml_mutex("BLCK", 0)); 1409 1410 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1411 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1412 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1413 aml_append(method, 1414 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1415 aml_append(method, aml_release(aml_name("BLCK"))); 1416 aml_append(method, aml_return(aml_int(0))); 1417 aml_append(scope, method); 1418 1419 aml_append(table, scope); 1420 } 1421 1422 static Aml *build_q35_osc_method(void) 1423 { 1424 Aml *if_ctx; 1425 Aml *if_ctx2; 1426 Aml *else_ctx; 1427 Aml *method; 1428 Aml *a_cwd1 = aml_name("CDW1"); 1429 Aml *a_ctrl = aml_local(0); 1430 1431 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1432 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1433 1434 if_ctx = aml_if(aml_equal( 1435 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1436 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1437 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1438 1439 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1440 1441 /* 1442 * Always allow native PME, AER (no dependencies) 1443 * Allow SHPC (PCI bridges can have SHPC controller) 1444 */ 1445 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1446 1447 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1448 /* Unknown revision */ 1449 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1450 aml_append(if_ctx, if_ctx2); 1451 1452 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1453 /* Capabilities bits were masked */ 1454 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1455 aml_append(if_ctx, if_ctx2); 1456 1457 /* Update DWORD3 in the buffer */ 1458 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1459 aml_append(method, if_ctx); 1460 1461 else_ctx = aml_else(); 1462 /* Unrecognized UUID */ 1463 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1464 aml_append(method, else_ctx); 1465 1466 aml_append(method, aml_return(aml_arg(3))); 1467 return method; 1468 } 1469 1470 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1471 { 1472 Aml *scope = aml_scope("_SB.PCI0"); 1473 Aml *dev = aml_device("SMB0"); 1474 1475 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1476 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1477 aml_append(scope, dev); 1478 aml_append(table, scope); 1479 } 1480 1481 static void 1482 build_dsdt(GArray *table_data, BIOSLinker *linker, 1483 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1484 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1485 { 1486 CrsRangeEntry *entry; 1487 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1488 CrsRangeSet crs_range_set; 1489 PCMachineState *pcms = PC_MACHINE(machine); 1490 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1491 X86MachineState *x86ms = X86_MACHINE(machine); 1492 AcpiMcfgInfo mcfg; 1493 uint32_t nr_mem = machine->ram_slots; 1494 int root_bus_limit = 0xFF; 1495 PCIBus *bus = NULL; 1496 TPMIf *tpm = tpm_find(); 1497 int i; 1498 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1499 1500 dsdt = init_aml_allocator(); 1501 1502 /* Reserve space for header */ 1503 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1504 1505 build_dbg_aml(dsdt); 1506 if (misc->is_piix4) { 1507 sb_scope = aml_scope("_SB"); 1508 dev = aml_device("PCI0"); 1509 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1510 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1511 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1512 aml_append(sb_scope, dev); 1513 aml_append(dsdt, sb_scope); 1514 1515 build_hpet_aml(dsdt); 1516 build_piix4_isa_bridge(dsdt); 1517 build_isa_devices_aml(dsdt); 1518 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1519 build_piix4_pci_hotplug(dsdt); 1520 } 1521 build_piix4_pci0_int(dsdt); 1522 } else { 1523 sb_scope = aml_scope("_SB"); 1524 dev = aml_device("PCI0"); 1525 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1526 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1527 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1528 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1529 aml_append(dev, build_q35_osc_method()); 1530 aml_append(sb_scope, dev); 1531 1532 if (pm->smi_on_cpuhp) { 1533 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1534 dev = aml_device("PCI0.SMI0"); 1535 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1536 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1537 crs = aml_resource_template(); 1538 aml_append(crs, 1539 aml_io( 1540 AML_DECODE16, 1541 ACPI_PORT_SMI_CMD, 1542 ACPI_PORT_SMI_CMD, 1543 1, 1544 2) 1545 ); 1546 aml_append(dev, aml_name_decl("_CRS", crs)); 1547 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1548 aml_int(ACPI_PORT_SMI_CMD), 2)); 1549 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1550 AML_WRITE_AS_ZEROS); 1551 aml_append(field, aml_named_field("SMIC", 8)); 1552 aml_append(field, aml_reserved_field(8)); 1553 aml_append(dev, field); 1554 aml_append(sb_scope, dev); 1555 } 1556 1557 aml_append(dsdt, sb_scope); 1558 1559 build_hpet_aml(dsdt); 1560 build_q35_isa_bridge(dsdt); 1561 build_isa_devices_aml(dsdt); 1562 build_q35_pci0_int(dsdt); 1563 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1564 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1565 } 1566 } 1567 1568 if (vmbus_bridge) { 1569 sb_scope = aml_scope("_SB"); 1570 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1571 aml_append(dsdt, sb_scope); 1572 } 1573 1574 if (pcmc->legacy_cpu_hotplug) { 1575 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1576 } else { 1577 CPUHotplugFeatures opts = { 1578 .acpi_1_compatible = true, .has_legacy_cphp = true, 1579 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1580 }; 1581 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1582 "\\_SB.PCI0", "\\_GPE._E02"); 1583 } 1584 1585 if (pcms->memhp_io_base && nr_mem) { 1586 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1587 "\\_GPE._E03", AML_SYSTEM_IO, 1588 pcms->memhp_io_base); 1589 } 1590 1591 scope = aml_scope("_GPE"); 1592 { 1593 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1594 1595 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1596 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1597 aml_append(method, 1598 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1599 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1600 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1601 aml_append(scope, method); 1602 } 1603 1604 if (machine->nvdimms_state->is_enabled) { 1605 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1606 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1607 aml_int(0x80))); 1608 aml_append(scope, method); 1609 } 1610 } 1611 aml_append(dsdt, scope); 1612 1613 crs_range_set_init(&crs_range_set); 1614 bus = PC_MACHINE(machine)->bus; 1615 if (bus) { 1616 QLIST_FOREACH(bus, &bus->child, sibling) { 1617 uint8_t bus_num = pci_bus_num(bus); 1618 uint8_t numa_node = pci_bus_numa_node(bus); 1619 1620 /* look only for expander root buses */ 1621 if (!pci_bus_is_root(bus)) { 1622 continue; 1623 } 1624 1625 if (bus_num < root_bus_limit) { 1626 root_bus_limit = bus_num - 1; 1627 } 1628 1629 scope = aml_scope("\\_SB"); 1630 dev = aml_device("PC%.02X", bus_num); 1631 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1632 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1633 if (pci_bus_is_express(bus)) { 1634 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1635 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1636 aml_append(dev, build_q35_osc_method()); 1637 } else { 1638 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1639 } 1640 1641 if (numa_node != NUMA_NODE_UNASSIGNED) { 1642 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1643 } 1644 1645 aml_append(dev, build_prt(false)); 1646 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1647 aml_append(dev, aml_name_decl("_CRS", crs)); 1648 aml_append(scope, dev); 1649 aml_append(dsdt, scope); 1650 } 1651 } 1652 1653 /* 1654 * At this point crs_range_set has all the ranges used by pci 1655 * busses *other* than PCI0. These ranges will be excluded from 1656 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1657 * too. 1658 */ 1659 if (acpi_get_mcfg(&mcfg)) { 1660 crs_range_insert(crs_range_set.mem_ranges, 1661 mcfg.base, mcfg.base + mcfg.size - 1); 1662 } 1663 1664 scope = aml_scope("\\_SB.PCI0"); 1665 /* build PCI0._CRS */ 1666 crs = aml_resource_template(); 1667 aml_append(crs, 1668 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1669 0x0000, 0x0, root_bus_limit, 1670 0x0000, root_bus_limit + 1)); 1671 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1672 1673 aml_append(crs, 1674 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1675 AML_POS_DECODE, AML_ENTIRE_RANGE, 1676 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1677 1678 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1679 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1680 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1681 aml_append(crs, 1682 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1683 AML_POS_DECODE, AML_ENTIRE_RANGE, 1684 0x0000, entry->base, entry->limit, 1685 0x0000, entry->limit - entry->base + 1)); 1686 } 1687 1688 aml_append(crs, 1689 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1690 AML_CACHEABLE, AML_READ_WRITE, 1691 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1692 1693 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1694 range_lob(pci_hole), 1695 range_upb(pci_hole)); 1696 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1697 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1698 aml_append(crs, 1699 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1700 AML_NON_CACHEABLE, AML_READ_WRITE, 1701 0, entry->base, entry->limit, 1702 0, entry->limit - entry->base + 1)); 1703 } 1704 1705 if (!range_is_empty(pci_hole64)) { 1706 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1707 range_lob(pci_hole64), 1708 range_upb(pci_hole64)); 1709 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1710 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1711 aml_append(crs, 1712 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1713 AML_MAX_FIXED, 1714 AML_CACHEABLE, AML_READ_WRITE, 1715 0, entry->base, entry->limit, 1716 0, entry->limit - entry->base + 1)); 1717 } 1718 } 1719 1720 if (TPM_IS_TIS_ISA(tpm_find())) { 1721 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1722 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1723 } 1724 aml_append(scope, aml_name_decl("_CRS", crs)); 1725 1726 /* reserve GPE0 block resources */ 1727 dev = aml_device("GPE0"); 1728 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1729 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1730 /* device present, functioning, decoding, not shown in UI */ 1731 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1732 crs = aml_resource_template(); 1733 aml_append(crs, 1734 aml_io( 1735 AML_DECODE16, 1736 pm->fadt.gpe0_blk.address, 1737 pm->fadt.gpe0_blk.address, 1738 1, 1739 pm->fadt.gpe0_blk.bit_width / 8) 1740 ); 1741 aml_append(dev, aml_name_decl("_CRS", crs)); 1742 aml_append(scope, dev); 1743 1744 crs_range_set_free(&crs_range_set); 1745 1746 /* reserve PCIHP resources */ 1747 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1748 dev = aml_device("PHPR"); 1749 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1750 aml_append(dev, 1751 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1752 /* device present, functioning, decoding, not shown in UI */ 1753 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1754 crs = aml_resource_template(); 1755 aml_append(crs, 1756 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1757 pm->pcihp_io_len) 1758 ); 1759 aml_append(dev, aml_name_decl("_CRS", crs)); 1760 aml_append(scope, dev); 1761 } 1762 aml_append(dsdt, scope); 1763 1764 /* create S3_ / S4_ / S5_ packages if necessary */ 1765 scope = aml_scope("\\"); 1766 if (!pm->s3_disabled) { 1767 pkg = aml_package(4); 1768 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1769 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1770 aml_append(pkg, aml_int(0)); /* reserved */ 1771 aml_append(pkg, aml_int(0)); /* reserved */ 1772 aml_append(scope, aml_name_decl("_S3", pkg)); 1773 } 1774 1775 if (!pm->s4_disabled) { 1776 pkg = aml_package(4); 1777 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1778 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1779 aml_append(pkg, aml_int(pm->s4_val)); 1780 aml_append(pkg, aml_int(0)); /* reserved */ 1781 aml_append(pkg, aml_int(0)); /* reserved */ 1782 aml_append(scope, aml_name_decl("_S4", pkg)); 1783 } 1784 1785 pkg = aml_package(4); 1786 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1787 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1788 aml_append(pkg, aml_int(0)); /* reserved */ 1789 aml_append(pkg, aml_int(0)); /* reserved */ 1790 aml_append(scope, aml_name_decl("_S5", pkg)); 1791 aml_append(dsdt, scope); 1792 1793 /* create fw_cfg node, unconditionally */ 1794 { 1795 scope = aml_scope("\\_SB.PCI0"); 1796 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1797 aml_append(dsdt, scope); 1798 } 1799 1800 if (misc->applesmc_io_base) { 1801 scope = aml_scope("\\_SB.PCI0.ISA"); 1802 dev = aml_device("SMC"); 1803 1804 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1805 /* device present, functioning, decoding, not shown in UI */ 1806 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1807 1808 crs = aml_resource_template(); 1809 aml_append(crs, 1810 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1811 0x01, APPLESMC_MAX_DATA_LENGTH) 1812 ); 1813 aml_append(crs, aml_irq_no_flags(6)); 1814 aml_append(dev, aml_name_decl("_CRS", crs)); 1815 1816 aml_append(scope, dev); 1817 aml_append(dsdt, scope); 1818 } 1819 1820 if (misc->pvpanic_port) { 1821 scope = aml_scope("\\_SB.PCI0.ISA"); 1822 1823 dev = aml_device("PEVT"); 1824 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1825 1826 crs = aml_resource_template(); 1827 aml_append(crs, 1828 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1829 ); 1830 aml_append(dev, aml_name_decl("_CRS", crs)); 1831 1832 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1833 aml_int(misc->pvpanic_port), 1)); 1834 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1835 aml_append(field, aml_named_field("PEPT", 8)); 1836 aml_append(dev, field); 1837 1838 /* device present, functioning, decoding, shown in UI */ 1839 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1840 1841 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1842 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1843 aml_append(method, aml_return(aml_local(0))); 1844 aml_append(dev, method); 1845 1846 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1847 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1848 aml_append(dev, method); 1849 1850 aml_append(scope, dev); 1851 aml_append(dsdt, scope); 1852 } 1853 1854 sb_scope = aml_scope("\\_SB"); 1855 { 1856 Object *pci_host; 1857 PCIBus *bus = NULL; 1858 1859 pci_host = acpi_get_i386_pci_host(); 1860 if (pci_host) { 1861 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1862 } 1863 1864 if (bus) { 1865 Aml *scope = aml_scope("PCI0"); 1866 /* Scan all PCI buses. Generate tables to support hotplug. */ 1867 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1868 1869 if (TPM_IS_TIS_ISA(tpm)) { 1870 if (misc->tpm_version == TPM_VERSION_2_0) { 1871 dev = aml_device("TPM"); 1872 aml_append(dev, aml_name_decl("_HID", 1873 aml_string("MSFT0101"))); 1874 } else { 1875 dev = aml_device("ISA.TPM"); 1876 aml_append(dev, aml_name_decl("_HID", 1877 aml_eisaid("PNP0C31"))); 1878 } 1879 1880 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1881 crs = aml_resource_template(); 1882 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1883 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1884 /* 1885 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1886 Rewrite to take IRQ from TPM device model and 1887 fix default IRQ value there to use some unused IRQ 1888 */ 1889 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1890 aml_append(dev, aml_name_decl("_CRS", crs)); 1891 1892 tpm_build_ppi_acpi(tpm, dev); 1893 1894 aml_append(scope, dev); 1895 } 1896 1897 aml_append(sb_scope, scope); 1898 } 1899 } 1900 1901 if (TPM_IS_CRB(tpm)) { 1902 dev = aml_device("TPM"); 1903 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1904 crs = aml_resource_template(); 1905 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1906 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1907 aml_append(dev, aml_name_decl("_CRS", crs)); 1908 1909 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1910 1911 tpm_build_ppi_acpi(tpm, dev); 1912 1913 aml_append(sb_scope, dev); 1914 } 1915 1916 aml_append(dsdt, sb_scope); 1917 1918 /* copy AML table into ACPI tables blob and patch header there */ 1919 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1920 build_header(linker, table_data, 1921 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1922 "DSDT", dsdt->buf->len, 1, NULL, NULL); 1923 free_aml_allocator(); 1924 } 1925 1926 static void 1927 build_hpet(GArray *table_data, BIOSLinker *linker) 1928 { 1929 Acpi20Hpet *hpet; 1930 1931 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1932 /* Note timer_block_id value must be kept in sync with value advertised by 1933 * emulated hpet 1934 */ 1935 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1936 hpet->addr.address = cpu_to_le64(HPET_BASE); 1937 build_header(linker, table_data, 1938 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 1939 } 1940 1941 static void 1942 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 1943 { 1944 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1945 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1946 unsigned log_addr_offset = 1947 (char *)&tcpa->log_area_start_address - table_data->data; 1948 1949 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1950 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1951 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1952 1953 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1954 false /* high memory */); 1955 1956 /* log area start address to be filled by Guest linker */ 1957 bios_linker_loader_add_pointer(linker, 1958 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1959 ACPI_BUILD_TPMLOG_FILE, 0); 1960 1961 build_header(linker, table_data, 1962 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 1963 } 1964 1965 #define HOLE_640K_START (640 * KiB) 1966 #define HOLE_640K_END (1 * MiB) 1967 1968 static void 1969 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1970 { 1971 AcpiSystemResourceAffinityTable *srat; 1972 AcpiSratMemoryAffinity *numamem; 1973 1974 int i; 1975 int srat_start, numa_start, slots; 1976 uint64_t mem_len, mem_base, next_base; 1977 MachineClass *mc = MACHINE_GET_CLASS(machine); 1978 X86MachineState *x86ms = X86_MACHINE(machine); 1979 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1980 PCMachineState *pcms = PC_MACHINE(machine); 1981 ram_addr_t hotplugabble_address_space_size = 1982 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1983 NULL); 1984 1985 srat_start = table_data->len; 1986 1987 srat = acpi_data_push(table_data, sizeof *srat); 1988 srat->reserved1 = cpu_to_le32(1); 1989 1990 for (i = 0; i < apic_ids->len; i++) { 1991 int node_id = apic_ids->cpus[i].props.node_id; 1992 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1993 1994 if (apic_id < 255) { 1995 AcpiSratProcessorAffinity *core; 1996 1997 core = acpi_data_push(table_data, sizeof *core); 1998 core->type = ACPI_SRAT_PROCESSOR_APIC; 1999 core->length = sizeof(*core); 2000 core->local_apic_id = apic_id; 2001 core->proximity_lo = node_id; 2002 memset(core->proximity_hi, 0, 3); 2003 core->local_sapic_eid = 0; 2004 core->flags = cpu_to_le32(1); 2005 } else { 2006 AcpiSratProcessorX2ApicAffinity *core; 2007 2008 core = acpi_data_push(table_data, sizeof *core); 2009 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2010 core->length = sizeof(*core); 2011 core->x2apic_id = cpu_to_le32(apic_id); 2012 core->proximity_domain = cpu_to_le32(node_id); 2013 core->flags = cpu_to_le32(1); 2014 } 2015 } 2016 2017 2018 /* the memory map is a bit tricky, it contains at least one hole 2019 * from 640k-1M and possibly another one from 3.5G-4G. 2020 */ 2021 next_base = 0; 2022 numa_start = table_data->len; 2023 2024 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2025 mem_base = next_base; 2026 mem_len = pcms->node_mem[i - 1]; 2027 next_base = mem_base + mem_len; 2028 2029 /* Cut out the 640K hole */ 2030 if (mem_base <= HOLE_640K_START && 2031 next_base > HOLE_640K_START) { 2032 mem_len -= next_base - HOLE_640K_START; 2033 if (mem_len > 0) { 2034 numamem = acpi_data_push(table_data, sizeof *numamem); 2035 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2036 MEM_AFFINITY_ENABLED); 2037 } 2038 2039 /* Check for the rare case: 640K < RAM < 1M */ 2040 if (next_base <= HOLE_640K_END) { 2041 next_base = HOLE_640K_END; 2042 continue; 2043 } 2044 mem_base = HOLE_640K_END; 2045 mem_len = next_base - HOLE_640K_END; 2046 } 2047 2048 /* Cut out the ACPI_PCI hole */ 2049 if (mem_base <= x86ms->below_4g_mem_size && 2050 next_base > x86ms->below_4g_mem_size) { 2051 mem_len -= next_base - x86ms->below_4g_mem_size; 2052 if (mem_len > 0) { 2053 numamem = acpi_data_push(table_data, sizeof *numamem); 2054 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2055 MEM_AFFINITY_ENABLED); 2056 } 2057 mem_base = 1ULL << 32; 2058 mem_len = next_base - x86ms->below_4g_mem_size; 2059 next_base = mem_base + mem_len; 2060 } 2061 2062 if (mem_len > 0) { 2063 numamem = acpi_data_push(table_data, sizeof *numamem); 2064 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2065 MEM_AFFINITY_ENABLED); 2066 } 2067 } 2068 2069 if (machine->nvdimms_state->is_enabled) { 2070 nvdimm_build_srat(table_data); 2071 } 2072 2073 slots = (table_data->len - numa_start) / sizeof *numamem; 2074 for (; slots < pcms->numa_nodes + 2; slots++) { 2075 numamem = acpi_data_push(table_data, sizeof *numamem); 2076 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2077 } 2078 2079 /* 2080 * Entry is required for Windows to enable memory hotplug in OS 2081 * and for Linux to enable SWIOTLB when booted with less than 2082 * 4G of RAM. Windows works better if the entry sets proximity 2083 * to the highest NUMA node in the machine. 2084 * Memory devices may override proximity set by this entry, 2085 * providing _PXM method if necessary. 2086 */ 2087 if (hotplugabble_address_space_size) { 2088 numamem = acpi_data_push(table_data, sizeof *numamem); 2089 build_srat_memory(numamem, machine->device_memory->base, 2090 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2091 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2092 } 2093 2094 build_header(linker, table_data, 2095 (void *)(table_data->data + srat_start), 2096 "SRAT", 2097 table_data->len - srat_start, 1, NULL, NULL); 2098 } 2099 2100 /* 2101 * VT-d spec 8.1 DMA Remapping Reporting Structure 2102 * (version Oct. 2014 or later) 2103 */ 2104 static void 2105 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2106 { 2107 int dmar_start = table_data->len; 2108 2109 AcpiTableDmar *dmar; 2110 AcpiDmarHardwareUnit *drhd; 2111 AcpiDmarRootPortATS *atsr; 2112 uint8_t dmar_flags = 0; 2113 X86IOMMUState *iommu = x86_iommu_get_default(); 2114 AcpiDmarDeviceScope *scope = NULL; 2115 /* Root complex IOAPIC use one path[0] only */ 2116 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2117 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2118 2119 assert(iommu); 2120 if (x86_iommu_ir_supported(iommu)) { 2121 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2122 } 2123 2124 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2125 dmar->host_address_width = intel_iommu->aw_bits - 1; 2126 dmar->flags = dmar_flags; 2127 2128 /* DMAR Remapping Hardware Unit Definition structure */ 2129 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2130 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2131 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2132 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2133 drhd->pci_segment = cpu_to_le16(0); 2134 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2135 2136 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2137 * 8.3.1 (version Oct. 2014 or later). */ 2138 scope = &drhd->scope[0]; 2139 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2140 scope->length = ioapic_scope_size; 2141 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2142 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2143 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2144 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2145 2146 if (iommu->dt_supported) { 2147 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2148 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2149 atsr->length = cpu_to_le16(sizeof(*atsr)); 2150 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2151 atsr->pci_segment = cpu_to_le16(0); 2152 } 2153 2154 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2155 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2156 } 2157 2158 /* 2159 * Windows ACPI Emulated Devices Table 2160 * (Version 1.0 - April 6, 2009) 2161 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2162 * 2163 * Helpful to speedup Windows guests and ignored by others. 2164 */ 2165 static void 2166 build_waet(GArray *table_data, BIOSLinker *linker) 2167 { 2168 int waet_start = table_data->len; 2169 2170 /* WAET header */ 2171 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2172 /* 2173 * Set "ACPI PM timer good" flag. 2174 * 2175 * Tells Windows guests that our ACPI PM timer is reliable in the 2176 * sense that guest can read it only once to obtain a reliable value. 2177 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2178 */ 2179 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2180 2181 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2182 "WAET", table_data->len - waet_start, 1, NULL, NULL); 2183 } 2184 2185 /* 2186 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2187 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2188 */ 2189 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2190 2191 /* 2192 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2193 * necessary for the PCI topology. 2194 */ 2195 static void 2196 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2197 { 2198 GArray *table_data = opaque; 2199 uint32_t entry; 2200 2201 /* "Select" IVHD entry, type 0x2 */ 2202 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2203 build_append_int_noprefix(table_data, entry, 4); 2204 2205 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2206 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2207 uint8_t sec = pci_bus_num(sec_bus); 2208 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2209 2210 if (pci_bus_is_express(sec_bus)) { 2211 /* 2212 * Walk the bus if there are subordinates, otherwise use a range 2213 * to cover an entire leaf bus. We could potentially also use a 2214 * range for traversed buses, but we'd need to take care not to 2215 * create both Select and Range entries covering the same device. 2216 * This is easier and potentially more compact. 2217 * 2218 * An example bare metal system seems to use Select entries for 2219 * root ports without a slot (ie. built-ins) and Range entries 2220 * when there is a slot. The same system also only hard-codes 2221 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2222 * making no effort to support nested bridges. We attempt to 2223 * be more thorough here. 2224 */ 2225 if (sec == sub) { /* leaf bus */ 2226 /* "Start of Range" IVHD entry, type 0x3 */ 2227 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2228 build_append_int_noprefix(table_data, entry, 4); 2229 /* "End of Range" IVHD entry, type 0x4 */ 2230 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2231 build_append_int_noprefix(table_data, entry, 4); 2232 } else { 2233 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2234 } 2235 } else { 2236 /* 2237 * If the secondary bus is conventional, then we need to create an 2238 * Alias range for everything downstream. The range covers the 2239 * first devfn on the secondary bus to the last devfn on the 2240 * subordinate bus. The alias target depends on legacy versus 2241 * express bridges, just as in pci_device_iommu_address_space(). 2242 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2243 */ 2244 uint16_t dev_id_a, dev_id_b; 2245 2246 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2247 2248 if (pci_is_express(dev) && 2249 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2250 dev_id_b = dev_id_a; 2251 } else { 2252 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2253 } 2254 2255 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2256 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2257 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2258 2259 /* "End of Range" IVHD entry, type 0x4 */ 2260 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2261 build_append_int_noprefix(table_data, entry, 4); 2262 } 2263 } 2264 } 2265 2266 /* For all PCI host bridges, walk and insert IVHD entries */ 2267 static int 2268 ivrs_host_bridges(Object *obj, void *opaque) 2269 { 2270 GArray *ivhd_blob = opaque; 2271 2272 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2273 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2274 2275 if (bus) { 2276 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2277 } 2278 } 2279 2280 return 0; 2281 } 2282 2283 static void 2284 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2285 { 2286 int ivhd_table_len = 24; 2287 int iommu_start = table_data->len; 2288 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2289 GArray *ivhd_blob = g_array_new(false, true, 1); 2290 2291 /* IVRS header */ 2292 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2293 /* IVinfo - IO virtualization information common to all 2294 * IOMMU units in a system 2295 */ 2296 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2297 /* reserved */ 2298 build_append_int_noprefix(table_data, 0, 8); 2299 2300 /* IVHD definition - type 10h */ 2301 build_append_int_noprefix(table_data, 0x10, 1); 2302 /* virtualization flags */ 2303 build_append_int_noprefix(table_data, 2304 (1UL << 0) | /* HtTunEn */ 2305 (1UL << 4) | /* iotblSup */ 2306 (1UL << 6) | /* PrefSup */ 2307 (1UL << 7), /* PPRSup */ 2308 1); 2309 2310 /* 2311 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2312 * complete set of IVHD entries. Do this into a separate blob so that we 2313 * can calculate the total IVRS table length here and then append the new 2314 * blob further below. Fall back to an entry covering all devices, which 2315 * is sufficient when no aliases are present. 2316 */ 2317 object_child_foreach_recursive(object_get_root(), 2318 ivrs_host_bridges, ivhd_blob); 2319 2320 if (!ivhd_blob->len) { 2321 /* 2322 * Type 1 device entry reporting all devices 2323 * These are 4-byte device entries currently reporting the range of 2324 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2325 */ 2326 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2327 } 2328 2329 ivhd_table_len += ivhd_blob->len; 2330 2331 /* 2332 * When interrupt remapping is supported, we add a special IVHD device 2333 * for type IO-APIC. 2334 */ 2335 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2336 ivhd_table_len += 8; 2337 } 2338 2339 /* IVHD length */ 2340 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2341 /* DeviceID */ 2342 build_append_int_noprefix(table_data, s->devid, 2); 2343 /* Capability offset */ 2344 build_append_int_noprefix(table_data, s->capab_offset, 2); 2345 /* IOMMU base address */ 2346 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2347 /* PCI Segment Group */ 2348 build_append_int_noprefix(table_data, 0, 2); 2349 /* IOMMU info */ 2350 build_append_int_noprefix(table_data, 0, 2); 2351 /* IOMMU Feature Reporting */ 2352 build_append_int_noprefix(table_data, 2353 (48UL << 30) | /* HATS */ 2354 (48UL << 28) | /* GATS */ 2355 (1UL << 2) | /* GTSup */ 2356 (1UL << 6), /* GASup */ 2357 4); 2358 2359 /* IVHD entries as found above */ 2360 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2361 g_array_free(ivhd_blob, TRUE); 2362 2363 /* 2364 * Add a special IVHD device type. 2365 * Refer to spec - Table 95: IVHD device entry type codes 2366 * 2367 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2368 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2369 */ 2370 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2371 build_append_int_noprefix(table_data, 2372 (0x1ull << 56) | /* type IOAPIC */ 2373 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2374 0x48, /* special device */ 2375 8); 2376 } 2377 2378 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2379 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2380 } 2381 2382 typedef 2383 struct AcpiBuildState { 2384 /* Copy of table in RAM (for patching). */ 2385 MemoryRegion *table_mr; 2386 /* Is table patched? */ 2387 uint8_t patched; 2388 void *rsdp; 2389 MemoryRegion *rsdp_mr; 2390 MemoryRegion *linker_mr; 2391 } AcpiBuildState; 2392 2393 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2394 { 2395 Object *pci_host; 2396 QObject *o; 2397 2398 pci_host = acpi_get_i386_pci_host(); 2399 g_assert(pci_host); 2400 2401 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2402 if (!o) { 2403 return false; 2404 } 2405 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2406 qobject_unref(o); 2407 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2408 return false; 2409 } 2410 2411 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2412 assert(o); 2413 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2414 qobject_unref(o); 2415 return true; 2416 } 2417 2418 static 2419 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2420 { 2421 PCMachineState *pcms = PC_MACHINE(machine); 2422 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2423 X86MachineState *x86ms = X86_MACHINE(machine); 2424 GArray *table_offsets; 2425 unsigned facs, dsdt, rsdt, fadt; 2426 AcpiPmInfo pm; 2427 AcpiMiscInfo misc; 2428 AcpiMcfgInfo mcfg; 2429 Range pci_hole, pci_hole64; 2430 uint8_t *u; 2431 size_t aml_len = 0; 2432 GArray *tables_blob = tables->table_data; 2433 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2434 Object *vmgenid_dev; 2435 2436 acpi_get_pm_info(machine, &pm); 2437 acpi_get_misc_info(&misc); 2438 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2439 acpi_get_slic_oem(&slic_oem); 2440 2441 table_offsets = g_array_new(false, true /* clear */, 2442 sizeof(uint32_t)); 2443 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2444 2445 bios_linker_loader_alloc(tables->linker, 2446 ACPI_BUILD_TABLE_FILE, tables_blob, 2447 64 /* Ensure FACS is aligned */, 2448 false /* high memory */); 2449 2450 /* 2451 * FACS is pointed to by FADT. 2452 * We place it first since it's the only table that has alignment 2453 * requirements. 2454 */ 2455 facs = tables_blob->len; 2456 build_facs(tables_blob); 2457 2458 /* DSDT is pointed to by FADT */ 2459 dsdt = tables_blob->len; 2460 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2461 &pci_hole, &pci_hole64, machine); 2462 2463 /* Count the size of the DSDT and SSDT, we will need it for legacy 2464 * sizing of ACPI tables. 2465 */ 2466 aml_len += tables_blob->len - dsdt; 2467 2468 /* ACPI tables pointed to by RSDT */ 2469 fadt = tables_blob->len; 2470 acpi_add_table(table_offsets, tables_blob); 2471 pm.fadt.facs_tbl_offset = &facs; 2472 pm.fadt.dsdt_tbl_offset = &dsdt; 2473 pm.fadt.xdsdt_tbl_offset = &dsdt; 2474 build_fadt(tables_blob, tables->linker, &pm.fadt, 2475 slic_oem.id, slic_oem.table_id); 2476 aml_len += tables_blob->len - fadt; 2477 2478 acpi_add_table(table_offsets, tables_blob); 2479 acpi_build_madt(tables_blob, tables->linker, x86ms, 2480 ACPI_DEVICE_IF(x86ms->acpi_dev)); 2481 2482 vmgenid_dev = find_vmgenid_dev(); 2483 if (vmgenid_dev) { 2484 acpi_add_table(table_offsets, tables_blob); 2485 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2486 tables->vmgenid, tables->linker); 2487 } 2488 2489 if (misc.has_hpet) { 2490 acpi_add_table(table_offsets, tables_blob); 2491 build_hpet(tables_blob, tables->linker); 2492 } 2493 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2494 if (misc.tpm_version == TPM_VERSION_1_2) { 2495 acpi_add_table(table_offsets, tables_blob); 2496 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2497 } else { /* TPM_VERSION_2_0 */ 2498 acpi_add_table(table_offsets, tables_blob); 2499 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2500 } 2501 } 2502 if (pcms->numa_nodes) { 2503 acpi_add_table(table_offsets, tables_blob); 2504 build_srat(tables_blob, tables->linker, machine); 2505 if (machine->numa_state->have_numa_distance) { 2506 acpi_add_table(table_offsets, tables_blob); 2507 build_slit(tables_blob, tables->linker, machine); 2508 } 2509 if (machine->numa_state->hmat_enabled) { 2510 acpi_add_table(table_offsets, tables_blob); 2511 build_hmat(tables_blob, tables->linker, machine->numa_state); 2512 } 2513 } 2514 if (acpi_get_mcfg(&mcfg)) { 2515 acpi_add_table(table_offsets, tables_blob); 2516 build_mcfg(tables_blob, tables->linker, &mcfg); 2517 } 2518 if (x86_iommu_get_default()) { 2519 IommuType IOMMUType = x86_iommu_get_type(); 2520 if (IOMMUType == TYPE_AMD) { 2521 acpi_add_table(table_offsets, tables_blob); 2522 build_amd_iommu(tables_blob, tables->linker); 2523 } else if (IOMMUType == TYPE_INTEL) { 2524 acpi_add_table(table_offsets, tables_blob); 2525 build_dmar_q35(tables_blob, tables->linker); 2526 } 2527 } 2528 if (machine->nvdimms_state->is_enabled) { 2529 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2530 machine->nvdimms_state, machine->ram_slots); 2531 } 2532 2533 acpi_add_table(table_offsets, tables_blob); 2534 build_waet(tables_blob, tables->linker); 2535 2536 /* Add tables supplied by user (if any) */ 2537 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2538 unsigned len = acpi_table_len(u); 2539 2540 acpi_add_table(table_offsets, tables_blob); 2541 g_array_append_vals(tables_blob, u, len); 2542 } 2543 2544 /* RSDT is pointed to by RSDP */ 2545 rsdt = tables_blob->len; 2546 build_rsdt(tables_blob, tables->linker, table_offsets, 2547 slic_oem.id, slic_oem.table_id); 2548 2549 /* RSDP is in FSEG memory, so allocate it separately */ 2550 { 2551 AcpiRsdpData rsdp_data = { 2552 .revision = 0, 2553 .oem_id = ACPI_BUILD_APPNAME6, 2554 .xsdt_tbl_offset = NULL, 2555 .rsdt_tbl_offset = &rsdt, 2556 }; 2557 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2558 if (!pcmc->rsdp_in_ram) { 2559 /* We used to allocate some extra space for RSDP revision 2 but 2560 * only used the RSDP revision 0 space. The extra bytes were 2561 * zeroed out and not used. 2562 * Here we continue wasting those extra 16 bytes to make sure we 2563 * don't break migration for machine types 2.2 and older due to 2564 * RSDP blob size mismatch. 2565 */ 2566 build_append_int_noprefix(tables->rsdp, 0, 16); 2567 } 2568 } 2569 2570 /* We'll expose it all to Guest so we want to reduce 2571 * chance of size changes. 2572 * 2573 * We used to align the tables to 4k, but of course this would 2574 * too simple to be enough. 4k turned out to be too small an 2575 * alignment very soon, and in fact it is almost impossible to 2576 * keep the table size stable for all (max_cpus, max_memory_slots) 2577 * combinations. So the table size is always 64k for pc-i440fx-2.1 2578 * and we give an error if the table grows beyond that limit. 2579 * 2580 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2581 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2582 * than 2.0 and we can always pad the smaller tables with zeros. We can 2583 * then use the exact size of the 2.0 tables. 2584 * 2585 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2586 */ 2587 if (pcmc->legacy_acpi_table_size) { 2588 /* Subtracting aml_len gives the size of fixed tables. Then add the 2589 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2590 */ 2591 int legacy_aml_len = 2592 pcmc->legacy_acpi_table_size + 2593 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2594 int legacy_table_size = 2595 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2596 ACPI_BUILD_ALIGN_SIZE); 2597 if (tables_blob->len > legacy_table_size) { 2598 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2599 warn_report("ACPI table size %u exceeds %d bytes," 2600 " migration may not work", 2601 tables_blob->len, legacy_table_size); 2602 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2603 " or PCI bridges."); 2604 } 2605 g_array_set_size(tables_blob, legacy_table_size); 2606 } else { 2607 /* Make sure we have a buffer in case we need to resize the tables. */ 2608 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2609 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2610 warn_report("ACPI table size %u exceeds %d bytes," 2611 " migration may not work", 2612 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2613 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2614 " or PCI bridges."); 2615 } 2616 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2617 } 2618 2619 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2620 2621 /* Cleanup memory that's no longer used. */ 2622 g_array_free(table_offsets, true); 2623 } 2624 2625 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2626 { 2627 uint32_t size = acpi_data_len(data); 2628 2629 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2630 memory_region_ram_resize(mr, size, &error_abort); 2631 2632 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2633 memory_region_set_dirty(mr, 0, size); 2634 } 2635 2636 static void acpi_build_update(void *build_opaque) 2637 { 2638 AcpiBuildState *build_state = build_opaque; 2639 AcpiBuildTables tables; 2640 2641 /* No state to update or already patched? Nothing to do. */ 2642 if (!build_state || build_state->patched) { 2643 return; 2644 } 2645 build_state->patched = 1; 2646 2647 acpi_build_tables_init(&tables); 2648 2649 acpi_build(&tables, MACHINE(qdev_get_machine())); 2650 2651 acpi_ram_update(build_state->table_mr, tables.table_data); 2652 2653 if (build_state->rsdp) { 2654 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2655 } else { 2656 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2657 } 2658 2659 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2660 acpi_build_tables_cleanup(&tables, true); 2661 } 2662 2663 static void acpi_build_reset(void *build_opaque) 2664 { 2665 AcpiBuildState *build_state = build_opaque; 2666 build_state->patched = 0; 2667 } 2668 2669 static const VMStateDescription vmstate_acpi_build = { 2670 .name = "acpi_build", 2671 .version_id = 1, 2672 .minimum_version_id = 1, 2673 .fields = (VMStateField[]) { 2674 VMSTATE_UINT8(patched, AcpiBuildState), 2675 VMSTATE_END_OF_LIST() 2676 }, 2677 }; 2678 2679 void acpi_setup(void) 2680 { 2681 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2682 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2683 X86MachineState *x86ms = X86_MACHINE(pcms); 2684 AcpiBuildTables tables; 2685 AcpiBuildState *build_state; 2686 Object *vmgenid_dev; 2687 TPMIf *tpm; 2688 static FwCfgTPMConfig tpm_config; 2689 2690 if (!x86ms->fw_cfg) { 2691 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2692 return; 2693 } 2694 2695 if (!pcms->acpi_build_enabled) { 2696 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2697 return; 2698 } 2699 2700 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2701 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2702 return; 2703 } 2704 2705 build_state = g_malloc0(sizeof *build_state); 2706 2707 acpi_build_tables_init(&tables); 2708 acpi_build(&tables, MACHINE(pcms)); 2709 2710 /* Now expose it all to Guest */ 2711 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2712 build_state, tables.table_data, 2713 ACPI_BUILD_TABLE_FILE, 2714 ACPI_BUILD_TABLE_MAX_SIZE); 2715 assert(build_state->table_mr != NULL); 2716 2717 build_state->linker_mr = 2718 acpi_add_rom_blob(acpi_build_update, build_state, 2719 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 2720 2721 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2722 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2723 2724 tpm = tpm_find(); 2725 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2726 tpm_config = (FwCfgTPMConfig) { 2727 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2728 .tpm_version = tpm_get_version(tpm), 2729 .tpmppi_version = TPM_PPI_VERSION_1_30 2730 }; 2731 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2732 &tpm_config, sizeof tpm_config); 2733 } 2734 2735 vmgenid_dev = find_vmgenid_dev(); 2736 if (vmgenid_dev) { 2737 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2738 tables.vmgenid); 2739 } 2740 2741 if (!pcmc->rsdp_in_ram) { 2742 /* 2743 * Keep for compatibility with old machine types. 2744 * Though RSDP is small, its contents isn't immutable, so 2745 * we'll update it along with the rest of tables on guest access. 2746 */ 2747 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2748 2749 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2750 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2751 acpi_build_update, NULL, build_state, 2752 build_state->rsdp, rsdp_size, true); 2753 build_state->rsdp_mr = NULL; 2754 } else { 2755 build_state->rsdp = NULL; 2756 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2757 build_state, tables.rsdp, 2758 ACPI_BUILD_RSDP_FILE, 0); 2759 } 2760 2761 qemu_register_reset(acpi_build_reset, build_state); 2762 acpi_build_reset(build_state); 2763 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2764 2765 /* Cleanup tables but don't free the memory: we track it 2766 * in build_state. 2767 */ 2768 acpi_build_tables_cleanup(&tables, false); 2769 } 2770