1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 69 #include "qom/qom-qobject.h" 70 #include "hw/i386/amd_iommu.h" 71 #include "hw/i386/intel_iommu.h" 72 73 #include "hw/acpi/ipmi.h" 74 #include "hw/acpi/hmat.h" 75 76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 78 * a little bit, there should be plenty of free space since the DSDT 79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 80 */ 81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 82 #define ACPI_BUILD_ALIGN_SIZE 0x1000 83 84 #define ACPI_BUILD_TABLE_SIZE 0x20000 85 86 /* #define DEBUG_ACPI_BUILD */ 87 #ifdef DEBUG_ACPI_BUILD 88 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 90 #else 91 #define ACPI_BUILD_DPRINTF(fmt, ...) 92 #endif 93 94 typedef struct AcpiPmInfo { 95 bool s3_disabled; 96 bool s4_disabled; 97 bool pcihp_bridge_en; 98 uint8_t s4_val; 99 AcpiFadtData fadt; 100 uint16_t cpu_hp_io_base; 101 uint16_t pcihp_io_base; 102 uint16_t pcihp_io_len; 103 } AcpiPmInfo; 104 105 typedef struct AcpiMiscInfo { 106 bool is_piix4; 107 bool has_hpet; 108 TPMVersion tpm_version; 109 const unsigned char *dsdt_code; 110 unsigned dsdt_size; 111 uint16_t pvpanic_port; 112 uint16_t applesmc_io_base; 113 } AcpiMiscInfo; 114 115 typedef struct AcpiBuildPciBusHotplugState { 116 GArray *device_table; 117 GArray *notify_table; 118 struct AcpiBuildPciBusHotplugState *parent; 119 bool pcihp_bridge_en; 120 } AcpiBuildPciBusHotplugState; 121 122 typedef struct FwCfgTPMConfig { 123 uint32_t tpmppi_address; 124 uint8_t tpm_version; 125 uint8_t tpmppi_version; 126 } QEMU_PACKED FwCfgTPMConfig; 127 128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 129 130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 131 .space_id = AML_AS_SYSTEM_IO, 132 .address = NVDIMM_ACPI_IO_BASE, 133 .bit_width = NVDIMM_ACPI_IO_LEN << 3 134 }; 135 136 static void init_common_fadt_data(MachineState *ms, Object *o, 137 AcpiFadtData *data) 138 { 139 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 140 AmlAddressSpace as = AML_AS_SYSTEM_IO; 141 AcpiFadtData fadt = { 142 .rev = 3, 143 .flags = 144 (1 << ACPI_FADT_F_WBINVD) | 145 (1 << ACPI_FADT_F_PROC_C1) | 146 (1 << ACPI_FADT_F_SLP_BUTTON) | 147 (1 << ACPI_FADT_F_RTC_S4) | 148 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 149 /* APIC destination mode ("Flat Logical") has an upper limit of 8 150 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 151 * used 152 */ 153 ((ms->smp.max_cpus > 8) ? 154 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 155 .int_model = 1 /* Multiple APIC */, 156 .rtc_century = RTC_CENTURY, 157 .plvl2_lat = 0xfff /* C2 state not supported */, 158 .plvl3_lat = 0xfff /* C3 state not supported */, 159 .smi_cmd = ACPI_PORT_SMI_CMD, 160 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 161 .acpi_enable_cmd = 162 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 163 .acpi_disable_cmd = 164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 165 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 166 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 167 .address = io + 0x04 }, 168 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 169 .gpe0_blk = { .space_id = as, .bit_width = 170 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 171 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 172 }, 173 }; 174 *data = fadt; 175 } 176 177 static Object *object_resolve_type_unambiguous(const char *typename) 178 { 179 bool ambig; 180 Object *o = object_resolve_path_type("", typename, &ambig); 181 182 if (ambig || !o) { 183 return NULL; 184 } 185 return o; 186 } 187 188 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 189 { 190 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 191 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 192 Object *obj = piix ? piix : lpc; 193 QObject *o; 194 pm->cpu_hp_io_base = 0; 195 pm->pcihp_io_base = 0; 196 pm->pcihp_io_len = 0; 197 198 assert(obj); 199 init_common_fadt_data(machine, obj, &pm->fadt); 200 if (piix) { 201 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 202 pm->fadt.rev = 1; 203 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 204 pm->pcihp_io_base = 205 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 206 pm->pcihp_io_len = 207 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 208 } 209 if (lpc) { 210 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 211 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 212 pm->fadt.reset_reg = r; 213 pm->fadt.reset_val = 0xf; 214 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 215 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 216 } 217 218 /* The above need not be conditional on machine type because the reset port 219 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 220 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 221 222 /* Fill in optional s3/s4 related properties */ 223 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 224 if (o) { 225 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 226 } else { 227 pm->s3_disabled = false; 228 } 229 qobject_unref(o); 230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 231 if (o) { 232 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 233 } else { 234 pm->s4_disabled = false; 235 } 236 qobject_unref(o); 237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 238 if (o) { 239 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 240 } else { 241 pm->s4_val = false; 242 } 243 qobject_unref(o); 244 245 pm->pcihp_bridge_en = 246 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 247 NULL); 248 } 249 250 static void acpi_get_misc_info(AcpiMiscInfo *info) 251 { 252 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 253 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 254 assert(!!piix != !!lpc); 255 256 if (piix) { 257 info->is_piix4 = true; 258 } 259 if (lpc) { 260 info->is_piix4 = false; 261 } 262 263 info->has_hpet = hpet_find(); 264 info->tpm_version = tpm_get_version(tpm_find()); 265 info->pvpanic_port = pvpanic_port(); 266 info->applesmc_io_base = applesmc_port(); 267 } 268 269 /* 270 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 271 * On i386 arch we only have two pci hosts, so we can look only for them. 272 */ 273 static Object *acpi_get_i386_pci_host(void) 274 { 275 PCIHostState *host; 276 277 host = OBJECT_CHECK(PCIHostState, 278 object_resolve_path("/machine/i440fx", NULL), 279 TYPE_PCI_HOST_BRIDGE); 280 if (!host) { 281 host = OBJECT_CHECK(PCIHostState, 282 object_resolve_path("/machine/q35", NULL), 283 TYPE_PCI_HOST_BRIDGE); 284 } 285 286 return OBJECT(host); 287 } 288 289 static void acpi_get_pci_holes(Range *hole, Range *hole64) 290 { 291 Object *pci_host; 292 293 pci_host = acpi_get_i386_pci_host(); 294 g_assert(pci_host); 295 296 range_set_bounds1(hole, 297 object_property_get_uint(pci_host, 298 PCI_HOST_PROP_PCI_HOLE_START, 299 NULL), 300 object_property_get_uint(pci_host, 301 PCI_HOST_PROP_PCI_HOLE_END, 302 NULL)); 303 range_set_bounds1(hole64, 304 object_property_get_uint(pci_host, 305 PCI_HOST_PROP_PCI_HOLE64_START, 306 NULL), 307 object_property_get_uint(pci_host, 308 PCI_HOST_PROP_PCI_HOLE64_END, 309 NULL)); 310 } 311 312 static void acpi_align_size(GArray *blob, unsigned align) 313 { 314 /* Align size to multiple of given size. This reduces the chance 315 * we need to change size in the future (breaking cross version migration). 316 */ 317 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 318 } 319 320 /* FACS */ 321 static void 322 build_facs(GArray *table_data) 323 { 324 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 325 memcpy(&facs->signature, "FACS", 4); 326 facs->length = cpu_to_le32(sizeof(*facs)); 327 } 328 329 static void build_append_pcihp_notify_entry(Aml *method, int slot) 330 { 331 Aml *if_ctx; 332 int32_t devfn = PCI_DEVFN(slot, 0); 333 334 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 335 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 336 aml_append(method, if_ctx); 337 } 338 339 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 340 bool pcihp_bridge_en) 341 { 342 Aml *dev, *notify_method = NULL, *method; 343 QObject *bsel; 344 PCIBus *sec; 345 int i; 346 347 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 348 if (bsel) { 349 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 350 351 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 352 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 353 } 354 355 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 356 DeviceClass *dc; 357 PCIDeviceClass *pc; 358 PCIDevice *pdev = bus->devices[i]; 359 int slot = PCI_SLOT(i); 360 bool hotplug_enabled_dev; 361 bool bridge_in_acpi; 362 363 if (!pdev) { 364 if (bsel) { /* add hotplug slots for non present devices */ 365 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 366 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 367 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 368 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 369 aml_append(method, 370 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 371 ); 372 aml_append(dev, method); 373 aml_append(parent_scope, dev); 374 375 build_append_pcihp_notify_entry(notify_method, slot); 376 } 377 continue; 378 } 379 380 pc = PCI_DEVICE_GET_CLASS(pdev); 381 dc = DEVICE_GET_CLASS(pdev); 382 383 /* When hotplug for bridges is enabled, bridges are 384 * described in ACPI separately (see build_pci_bus_end). 385 * In this case they aren't themselves hot-pluggable. 386 * Hotplugged bridges *are* hot-pluggable. 387 */ 388 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 389 !DEVICE(pdev)->hotplugged; 390 391 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 392 393 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 394 continue; 395 } 396 397 /* start to compose PCI slot descriptor */ 398 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 399 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 400 401 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 402 /* add VGA specific AML methods */ 403 int s3d; 404 405 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 406 s3d = 3; 407 } else { 408 s3d = 0; 409 } 410 411 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 412 aml_append(method, aml_return(aml_int(0))); 413 aml_append(dev, method); 414 415 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 416 aml_append(method, aml_return(aml_int(0))); 417 aml_append(dev, method); 418 419 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 420 aml_append(method, aml_return(aml_int(s3d))); 421 aml_append(dev, method); 422 } else if (hotplug_enabled_dev) { 423 /* add _SUN/_EJ0 to make slot hotpluggable */ 424 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 425 426 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 427 aml_append(method, 428 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 429 ); 430 aml_append(dev, method); 431 432 if (bsel) { 433 build_append_pcihp_notify_entry(notify_method, slot); 434 } 435 } else if (bridge_in_acpi) { 436 /* 437 * device is coldplugged bridge, 438 * add child device descriptions into its scope 439 */ 440 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 441 442 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 443 } 444 /* slot descriptor has been composed, add it into parent context */ 445 aml_append(parent_scope, dev); 446 } 447 448 if (bsel) { 449 aml_append(parent_scope, notify_method); 450 } 451 452 /* Append PCNT method to notify about events on local and child buses. 453 * Add unconditionally for root since DSDT expects it. 454 */ 455 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 456 457 /* If bus supports hotplug select it and notify about local events */ 458 if (bsel) { 459 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 460 461 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 462 aml_append(method, 463 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 464 ); 465 aml_append(method, 466 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 467 ); 468 } 469 470 /* Notify about child bus events in any case */ 471 if (pcihp_bridge_en) { 472 QLIST_FOREACH(sec, &bus->child, sibling) { 473 int32_t devfn = sec->parent_dev->devfn; 474 475 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 476 continue; 477 } 478 479 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 480 } 481 } 482 aml_append(parent_scope, method); 483 qobject_unref(bsel); 484 } 485 486 /** 487 * build_prt_entry: 488 * @link_name: link name for PCI route entry 489 * 490 * build AML package containing a PCI route entry for @link_name 491 */ 492 static Aml *build_prt_entry(const char *link_name) 493 { 494 Aml *a_zero = aml_int(0); 495 Aml *pkg = aml_package(4); 496 aml_append(pkg, a_zero); 497 aml_append(pkg, a_zero); 498 aml_append(pkg, aml_name("%s", link_name)); 499 aml_append(pkg, a_zero); 500 return pkg; 501 } 502 503 /* 504 * initialize_route - Initialize the interrupt routing rule 505 * through a specific LINK: 506 * if (lnk_idx == idx) 507 * route using link 'link_name' 508 */ 509 static Aml *initialize_route(Aml *route, const char *link_name, 510 Aml *lnk_idx, int idx) 511 { 512 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 513 Aml *pkg = build_prt_entry(link_name); 514 515 aml_append(if_ctx, aml_store(pkg, route)); 516 517 return if_ctx; 518 } 519 520 /* 521 * build_prt - Define interrupt rounting rules 522 * 523 * Returns an array of 128 routes, one for each device, 524 * based on device location. 525 * The main goal is to equaly distribute the interrupts 526 * over the 4 existing ACPI links (works only for i440fx). 527 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 528 * 529 */ 530 static Aml *build_prt(bool is_pci0_prt) 531 { 532 Aml *method, *while_ctx, *pin, *res; 533 534 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 535 res = aml_local(0); 536 pin = aml_local(1); 537 aml_append(method, aml_store(aml_package(128), res)); 538 aml_append(method, aml_store(aml_int(0), pin)); 539 540 /* while (pin < 128) */ 541 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 542 { 543 Aml *slot = aml_local(2); 544 Aml *lnk_idx = aml_local(3); 545 Aml *route = aml_local(4); 546 547 /* slot = pin >> 2 */ 548 aml_append(while_ctx, 549 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 550 /* lnk_idx = (slot + pin) & 3 */ 551 aml_append(while_ctx, 552 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 553 lnk_idx)); 554 555 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 556 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 557 if (is_pci0_prt) { 558 Aml *if_device_1, *if_pin_4, *else_pin_4; 559 560 /* device 1 is the power-management device, needs SCI */ 561 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 562 { 563 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 564 { 565 aml_append(if_pin_4, 566 aml_store(build_prt_entry("LNKS"), route)); 567 } 568 aml_append(if_device_1, if_pin_4); 569 else_pin_4 = aml_else(); 570 { 571 aml_append(else_pin_4, 572 aml_store(build_prt_entry("LNKA"), route)); 573 } 574 aml_append(if_device_1, else_pin_4); 575 } 576 aml_append(while_ctx, if_device_1); 577 } else { 578 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 579 } 580 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 581 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 582 583 /* route[0] = 0x[slot]FFFF */ 584 aml_append(while_ctx, 585 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 586 NULL), 587 aml_index(route, aml_int(0)))); 588 /* route[1] = pin & 3 */ 589 aml_append(while_ctx, 590 aml_store(aml_and(pin, aml_int(3), NULL), 591 aml_index(route, aml_int(1)))); 592 /* res[pin] = route */ 593 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 594 /* pin++ */ 595 aml_append(while_ctx, aml_increment(pin)); 596 } 597 aml_append(method, while_ctx); 598 /* return res*/ 599 aml_append(method, aml_return(res)); 600 601 return method; 602 } 603 604 typedef struct CrsRangeEntry { 605 uint64_t base; 606 uint64_t limit; 607 } CrsRangeEntry; 608 609 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 610 { 611 CrsRangeEntry *entry; 612 613 entry = g_malloc(sizeof(*entry)); 614 entry->base = base; 615 entry->limit = limit; 616 617 g_ptr_array_add(ranges, entry); 618 } 619 620 static void crs_range_free(gpointer data) 621 { 622 CrsRangeEntry *entry = (CrsRangeEntry *)data; 623 g_free(entry); 624 } 625 626 typedef struct CrsRangeSet { 627 GPtrArray *io_ranges; 628 GPtrArray *mem_ranges; 629 GPtrArray *mem_64bit_ranges; 630 } CrsRangeSet; 631 632 static void crs_range_set_init(CrsRangeSet *range_set) 633 { 634 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 635 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 636 range_set->mem_64bit_ranges = 637 g_ptr_array_new_with_free_func(crs_range_free); 638 } 639 640 static void crs_range_set_free(CrsRangeSet *range_set) 641 { 642 g_ptr_array_free(range_set->io_ranges, true); 643 g_ptr_array_free(range_set->mem_ranges, true); 644 g_ptr_array_free(range_set->mem_64bit_ranges, true); 645 } 646 647 static gint crs_range_compare(gconstpointer a, gconstpointer b) 648 { 649 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 650 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 651 652 if (entry_a->base < entry_b->base) { 653 return -1; 654 } else if (entry_a->base > entry_b->base) { 655 return 1; 656 } else { 657 return 0; 658 } 659 } 660 661 /* 662 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 663 * interval, computes the 'free' ranges from the same interval. 664 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 665 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 666 */ 667 static void crs_replace_with_free_ranges(GPtrArray *ranges, 668 uint64_t start, uint64_t end) 669 { 670 GPtrArray *free_ranges = g_ptr_array_new(); 671 uint64_t free_base = start; 672 int i; 673 674 g_ptr_array_sort(ranges, crs_range_compare); 675 for (i = 0; i < ranges->len; i++) { 676 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 677 678 if (free_base < used->base) { 679 crs_range_insert(free_ranges, free_base, used->base - 1); 680 } 681 682 free_base = used->limit + 1; 683 } 684 685 if (free_base < end) { 686 crs_range_insert(free_ranges, free_base, end); 687 } 688 689 g_ptr_array_set_size(ranges, 0); 690 for (i = 0; i < free_ranges->len; i++) { 691 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 692 } 693 694 g_ptr_array_free(free_ranges, true); 695 } 696 697 /* 698 * crs_range_merge - merges adjacent ranges in the given array. 699 * Array elements are deleted and replaced with the merged ranges. 700 */ 701 static void crs_range_merge(GPtrArray *range) 702 { 703 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 704 CrsRangeEntry *entry; 705 uint64_t range_base, range_limit; 706 int i; 707 708 if (!range->len) { 709 return; 710 } 711 712 g_ptr_array_sort(range, crs_range_compare); 713 714 entry = g_ptr_array_index(range, 0); 715 range_base = entry->base; 716 range_limit = entry->limit; 717 for (i = 1; i < range->len; i++) { 718 entry = g_ptr_array_index(range, i); 719 if (entry->base - 1 == range_limit) { 720 range_limit = entry->limit; 721 } else { 722 crs_range_insert(tmp, range_base, range_limit); 723 range_base = entry->base; 724 range_limit = entry->limit; 725 } 726 } 727 crs_range_insert(tmp, range_base, range_limit); 728 729 g_ptr_array_set_size(range, 0); 730 for (i = 0; i < tmp->len; i++) { 731 entry = g_ptr_array_index(tmp, i); 732 crs_range_insert(range, entry->base, entry->limit); 733 } 734 g_ptr_array_free(tmp, true); 735 } 736 737 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 738 { 739 Aml *crs = aml_resource_template(); 740 CrsRangeSet temp_range_set; 741 CrsRangeEntry *entry; 742 uint8_t max_bus = pci_bus_num(host->bus); 743 uint8_t type; 744 int devfn; 745 int i; 746 747 crs_range_set_init(&temp_range_set); 748 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 749 uint64_t range_base, range_limit; 750 PCIDevice *dev = host->bus->devices[devfn]; 751 752 if (!dev) { 753 continue; 754 } 755 756 for (i = 0; i < PCI_NUM_REGIONS; i++) { 757 PCIIORegion *r = &dev->io_regions[i]; 758 759 range_base = r->addr; 760 range_limit = r->addr + r->size - 1; 761 762 /* 763 * Work-around for old bioses 764 * that do not support multiple root buses 765 */ 766 if (!range_base || range_base > range_limit) { 767 continue; 768 } 769 770 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 771 crs_range_insert(temp_range_set.io_ranges, 772 range_base, range_limit); 773 } else { /* "memory" */ 774 crs_range_insert(temp_range_set.mem_ranges, 775 range_base, range_limit); 776 } 777 } 778 779 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 780 if (type == PCI_HEADER_TYPE_BRIDGE) { 781 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 782 if (subordinate > max_bus) { 783 max_bus = subordinate; 784 } 785 786 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 787 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 788 789 /* 790 * Work-around for old bioses 791 * that do not support multiple root buses 792 */ 793 if (range_base && range_base <= range_limit) { 794 crs_range_insert(temp_range_set.io_ranges, 795 range_base, range_limit); 796 } 797 798 range_base = 799 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 800 range_limit = 801 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 802 803 /* 804 * Work-around for old bioses 805 * that do not support multiple root buses 806 */ 807 if (range_base && range_base <= range_limit) { 808 uint64_t length = range_limit - range_base + 1; 809 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 810 crs_range_insert(temp_range_set.mem_ranges, 811 range_base, range_limit); 812 } else { 813 crs_range_insert(temp_range_set.mem_64bit_ranges, 814 range_base, range_limit); 815 } 816 } 817 818 range_base = 819 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 820 range_limit = 821 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 822 823 /* 824 * Work-around for old bioses 825 * that do not support multiple root buses 826 */ 827 if (range_base && range_base <= range_limit) { 828 uint64_t length = range_limit - range_base + 1; 829 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 830 crs_range_insert(temp_range_set.mem_ranges, 831 range_base, range_limit); 832 } else { 833 crs_range_insert(temp_range_set.mem_64bit_ranges, 834 range_base, range_limit); 835 } 836 } 837 } 838 } 839 840 crs_range_merge(temp_range_set.io_ranges); 841 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 842 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 843 aml_append(crs, 844 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 845 AML_POS_DECODE, AML_ENTIRE_RANGE, 846 0, entry->base, entry->limit, 0, 847 entry->limit - entry->base + 1)); 848 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 849 } 850 851 crs_range_merge(temp_range_set.mem_ranges); 852 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 853 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 854 aml_append(crs, 855 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 856 AML_MAX_FIXED, AML_NON_CACHEABLE, 857 AML_READ_WRITE, 858 0, entry->base, entry->limit, 0, 859 entry->limit - entry->base + 1)); 860 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 861 } 862 863 crs_range_merge(temp_range_set.mem_64bit_ranges); 864 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 865 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 866 aml_append(crs, 867 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 868 AML_MAX_FIXED, AML_NON_CACHEABLE, 869 AML_READ_WRITE, 870 0, entry->base, entry->limit, 0, 871 entry->limit - entry->base + 1)); 872 crs_range_insert(range_set->mem_64bit_ranges, 873 entry->base, entry->limit); 874 } 875 876 crs_range_set_free(&temp_range_set); 877 878 aml_append(crs, 879 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 880 0, 881 pci_bus_num(host->bus), 882 max_bus, 883 0, 884 max_bus - pci_bus_num(host->bus) + 1)); 885 886 return crs; 887 } 888 889 static void build_hpet_aml(Aml *table) 890 { 891 Aml *crs; 892 Aml *field; 893 Aml *method; 894 Aml *if_ctx; 895 Aml *scope = aml_scope("_SB"); 896 Aml *dev = aml_device("HPET"); 897 Aml *zero = aml_int(0); 898 Aml *id = aml_local(0); 899 Aml *period = aml_local(1); 900 901 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 902 aml_append(dev, aml_name_decl("_UID", zero)); 903 904 aml_append(dev, 905 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 906 HPET_LEN)); 907 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 908 aml_append(field, aml_named_field("VEND", 32)); 909 aml_append(field, aml_named_field("PRD", 32)); 910 aml_append(dev, field); 911 912 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 913 aml_append(method, aml_store(aml_name("VEND"), id)); 914 aml_append(method, aml_store(aml_name("PRD"), period)); 915 aml_append(method, aml_shiftright(id, aml_int(16), id)); 916 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 917 aml_equal(id, aml_int(0xffff)))); 918 { 919 aml_append(if_ctx, aml_return(zero)); 920 } 921 aml_append(method, if_ctx); 922 923 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 924 aml_lgreater(period, aml_int(100000000)))); 925 { 926 aml_append(if_ctx, aml_return(zero)); 927 } 928 aml_append(method, if_ctx); 929 930 aml_append(method, aml_return(aml_int(0x0F))); 931 aml_append(dev, method); 932 933 crs = aml_resource_template(); 934 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 935 aml_append(dev, aml_name_decl("_CRS", crs)); 936 937 aml_append(scope, dev); 938 aml_append(table, scope); 939 } 940 941 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 942 { 943 Aml *dev; 944 Aml *method; 945 Aml *crs; 946 947 dev = aml_device("VMBS"); 948 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 949 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 950 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 951 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 952 953 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 954 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 955 aml_name("STA"))); 956 aml_append(dev, method); 957 958 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 959 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 960 aml_name("STA"))); 961 aml_append(dev, method); 962 963 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 964 aml_append(method, aml_return(aml_name("STA"))); 965 aml_append(dev, method); 966 967 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 968 969 crs = aml_resource_template(); 970 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq0)); 971 /* FIXME: newer HyperV gets by with only one IRQ */ 972 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq1)); 973 aml_append(dev, aml_name_decl("_CRS", crs)); 974 975 return dev; 976 } 977 978 static void build_isa_devices_aml(Aml *table) 979 { 980 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 981 bool ambiguous; 982 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 983 Aml *scope; 984 985 assert(obj && !ambiguous); 986 987 scope = aml_scope("_SB.PCI0.ISA"); 988 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 989 isa_build_aml(ISA_BUS(obj), scope); 990 991 if (vmbus_bridge) { 992 aml_append(scope, build_vmbus_device_aml(vmbus_bridge)); 993 } 994 995 aml_append(table, scope); 996 } 997 998 static void build_dbg_aml(Aml *table) 999 { 1000 Aml *field; 1001 Aml *method; 1002 Aml *while_ctx; 1003 Aml *scope = aml_scope("\\"); 1004 Aml *buf = aml_local(0); 1005 Aml *len = aml_local(1); 1006 Aml *idx = aml_local(2); 1007 1008 aml_append(scope, 1009 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1010 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1011 aml_append(field, aml_named_field("DBGB", 8)); 1012 aml_append(scope, field); 1013 1014 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1015 1016 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1017 aml_append(method, aml_to_buffer(buf, buf)); 1018 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1019 aml_append(method, aml_store(aml_int(0), idx)); 1020 1021 while_ctx = aml_while(aml_lless(idx, len)); 1022 aml_append(while_ctx, 1023 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1024 aml_append(while_ctx, aml_increment(idx)); 1025 aml_append(method, while_ctx); 1026 1027 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1028 aml_append(scope, method); 1029 1030 aml_append(table, scope); 1031 } 1032 1033 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1034 { 1035 Aml *dev; 1036 Aml *crs; 1037 Aml *method; 1038 uint32_t irqs[] = {5, 10, 11}; 1039 1040 dev = aml_device("%s", name); 1041 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1042 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1043 1044 crs = aml_resource_template(); 1045 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1046 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1047 aml_append(dev, aml_name_decl("_PRS", crs)); 1048 1049 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1050 aml_append(method, aml_return(aml_call1("IQST", reg))); 1051 aml_append(dev, method); 1052 1053 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1054 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1055 aml_append(dev, method); 1056 1057 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1062 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1063 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1064 aml_append(dev, method); 1065 1066 return dev; 1067 } 1068 1069 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1070 { 1071 Aml *dev; 1072 Aml *crs; 1073 Aml *method; 1074 uint32_t irqs; 1075 1076 dev = aml_device("%s", name); 1077 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1078 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1079 1080 crs = aml_resource_template(); 1081 irqs = gsi; 1082 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1083 AML_SHARED, &irqs, 1)); 1084 aml_append(dev, aml_name_decl("_PRS", crs)); 1085 1086 aml_append(dev, aml_name_decl("_CRS", crs)); 1087 1088 /* 1089 * _DIS can be no-op because the interrupt cannot be disabled. 1090 */ 1091 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1092 aml_append(dev, method); 1093 1094 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1095 aml_append(dev, method); 1096 1097 return dev; 1098 } 1099 1100 /* _CRS method - get current settings */ 1101 static Aml *build_iqcr_method(bool is_piix4) 1102 { 1103 Aml *if_ctx; 1104 uint32_t irqs; 1105 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1106 Aml *crs = aml_resource_template(); 1107 1108 irqs = 0; 1109 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1110 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1111 aml_append(method, aml_name_decl("PRR0", crs)); 1112 1113 aml_append(method, 1114 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1115 1116 if (is_piix4) { 1117 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1118 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1119 aml_append(method, if_ctx); 1120 } else { 1121 aml_append(method, 1122 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1123 aml_name("PRRI"))); 1124 } 1125 1126 aml_append(method, aml_return(aml_name("PRR0"))); 1127 return method; 1128 } 1129 1130 /* _STA method - get status */ 1131 static Aml *build_irq_status_method(void) 1132 { 1133 Aml *if_ctx; 1134 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1135 1136 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1137 aml_append(if_ctx, aml_return(aml_int(0x09))); 1138 aml_append(method, if_ctx); 1139 aml_append(method, aml_return(aml_int(0x0B))); 1140 return method; 1141 } 1142 1143 static void build_piix4_pci0_int(Aml *table) 1144 { 1145 Aml *dev; 1146 Aml *crs; 1147 Aml *field; 1148 Aml *method; 1149 uint32_t irqs; 1150 Aml *sb_scope = aml_scope("_SB"); 1151 Aml *pci0_scope = aml_scope("PCI0"); 1152 1153 aml_append(pci0_scope, build_prt(true)); 1154 aml_append(sb_scope, pci0_scope); 1155 1156 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1157 aml_append(field, aml_named_field("PRQ0", 8)); 1158 aml_append(field, aml_named_field("PRQ1", 8)); 1159 aml_append(field, aml_named_field("PRQ2", 8)); 1160 aml_append(field, aml_named_field("PRQ3", 8)); 1161 aml_append(sb_scope, field); 1162 1163 aml_append(sb_scope, build_irq_status_method()); 1164 aml_append(sb_scope, build_iqcr_method(true)); 1165 1166 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1167 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1168 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1169 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1170 1171 dev = aml_device("LNKS"); 1172 { 1173 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1174 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1175 1176 crs = aml_resource_template(); 1177 irqs = 9; 1178 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1179 AML_ACTIVE_HIGH, AML_SHARED, 1180 &irqs, 1)); 1181 aml_append(dev, aml_name_decl("_PRS", crs)); 1182 1183 /* The SCI cannot be disabled and is always attached to GSI 9, 1184 * so these are no-ops. We only need this link to override the 1185 * polarity to active high and match the content of the MADT. 1186 */ 1187 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1188 aml_append(method, aml_return(aml_int(0x0b))); 1189 aml_append(dev, method); 1190 1191 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1192 aml_append(dev, method); 1193 1194 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1195 aml_append(method, aml_return(aml_name("_PRS"))); 1196 aml_append(dev, method); 1197 1198 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1199 aml_append(dev, method); 1200 } 1201 aml_append(sb_scope, dev); 1202 1203 aml_append(table, sb_scope); 1204 } 1205 1206 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1207 { 1208 int i; 1209 int head; 1210 Aml *pkg; 1211 char base = name[3] < 'E' ? 'A' : 'E'; 1212 char *s = g_strdup(name); 1213 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1214 1215 assert(strlen(s) == 4); 1216 1217 head = name[3] - base; 1218 for (i = 0; i < 4; i++) { 1219 if (head + i > 3) { 1220 head = i * -1; 1221 } 1222 s[3] = base + head + i; 1223 pkg = aml_package(4); 1224 aml_append(pkg, a_nr); 1225 aml_append(pkg, aml_int(i)); 1226 aml_append(pkg, aml_name("%s", s)); 1227 aml_append(pkg, aml_int(0)); 1228 aml_append(ctx, pkg); 1229 } 1230 g_free(s); 1231 } 1232 1233 static Aml *build_q35_routing_table(const char *str) 1234 { 1235 int i; 1236 Aml *pkg; 1237 char *name = g_strdup_printf("%s ", str); 1238 1239 pkg = aml_package(128); 1240 for (i = 0; i < 0x18; i++) { 1241 name[3] = 'E' + (i & 0x3); 1242 append_q35_prt_entry(pkg, i, name); 1243 } 1244 1245 name[3] = 'E'; 1246 append_q35_prt_entry(pkg, 0x18, name); 1247 1248 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1249 for (i = 0x0019; i < 0x1e; i++) { 1250 name[3] = 'A'; 1251 append_q35_prt_entry(pkg, i, name); 1252 } 1253 1254 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1255 name[3] = 'E'; 1256 append_q35_prt_entry(pkg, 0x1e, name); 1257 name[3] = 'A'; 1258 append_q35_prt_entry(pkg, 0x1f, name); 1259 1260 g_free(name); 1261 return pkg; 1262 } 1263 1264 static void build_q35_pci0_int(Aml *table) 1265 { 1266 Aml *field; 1267 Aml *method; 1268 Aml *sb_scope = aml_scope("_SB"); 1269 Aml *pci0_scope = aml_scope("PCI0"); 1270 1271 /* Zero => PIC mode, One => APIC Mode */ 1272 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1273 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1274 { 1275 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1276 } 1277 aml_append(table, method); 1278 1279 aml_append(pci0_scope, 1280 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1281 aml_append(pci0_scope, 1282 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1283 1284 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1285 { 1286 Aml *if_ctx; 1287 Aml *else_ctx; 1288 1289 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1290 section 6.2.8.1 */ 1291 /* Note: we provide the same info as the PCI routing 1292 table of the Bochs BIOS */ 1293 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1294 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1295 aml_append(method, if_ctx); 1296 else_ctx = aml_else(); 1297 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1298 aml_append(method, else_ctx); 1299 } 1300 aml_append(pci0_scope, method); 1301 aml_append(sb_scope, pci0_scope); 1302 1303 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1304 aml_append(field, aml_named_field("PRQA", 8)); 1305 aml_append(field, aml_named_field("PRQB", 8)); 1306 aml_append(field, aml_named_field("PRQC", 8)); 1307 aml_append(field, aml_named_field("PRQD", 8)); 1308 aml_append(field, aml_reserved_field(0x20)); 1309 aml_append(field, aml_named_field("PRQE", 8)); 1310 aml_append(field, aml_named_field("PRQF", 8)); 1311 aml_append(field, aml_named_field("PRQG", 8)); 1312 aml_append(field, aml_named_field("PRQH", 8)); 1313 aml_append(sb_scope, field); 1314 1315 aml_append(sb_scope, build_irq_status_method()); 1316 aml_append(sb_scope, build_iqcr_method(false)); 1317 1318 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1319 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1320 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1321 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1322 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1323 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1324 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1325 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1326 1327 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1328 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1329 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1330 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1331 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1332 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1333 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1334 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1335 1336 aml_append(table, sb_scope); 1337 } 1338 1339 static void build_q35_isa_bridge(Aml *table) 1340 { 1341 Aml *dev; 1342 Aml *scope; 1343 1344 scope = aml_scope("_SB.PCI0"); 1345 dev = aml_device("ISA"); 1346 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1347 1348 /* ICH9 PCI to ISA irq remapping */ 1349 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1350 aml_int(0x60), 0x0C)); 1351 1352 aml_append(scope, dev); 1353 aml_append(table, scope); 1354 } 1355 1356 static void build_piix4_isa_bridge(Aml *table) 1357 { 1358 Aml *dev; 1359 Aml *scope; 1360 1361 scope = aml_scope("_SB.PCI0"); 1362 dev = aml_device("ISA"); 1363 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1364 1365 /* PIIX PCI to ISA irq remapping */ 1366 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1367 aml_int(0x60), 0x04)); 1368 1369 aml_append(scope, dev); 1370 aml_append(table, scope); 1371 } 1372 1373 static void build_piix4_pci_hotplug(Aml *table) 1374 { 1375 Aml *scope; 1376 Aml *field; 1377 Aml *method; 1378 1379 scope = aml_scope("_SB.PCI0"); 1380 1381 aml_append(scope, 1382 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1383 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1384 aml_append(field, aml_named_field("PCIU", 32)); 1385 aml_append(field, aml_named_field("PCID", 32)); 1386 aml_append(scope, field); 1387 1388 aml_append(scope, 1389 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1390 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1391 aml_append(field, aml_named_field("B0EJ", 32)); 1392 aml_append(scope, field); 1393 1394 aml_append(scope, 1395 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1396 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1397 aml_append(field, aml_named_field("BNUM", 32)); 1398 aml_append(scope, field); 1399 1400 aml_append(scope, aml_mutex("BLCK", 0)); 1401 1402 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1403 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1404 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1405 aml_append(method, 1406 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1407 aml_append(method, aml_release(aml_name("BLCK"))); 1408 aml_append(method, aml_return(aml_int(0))); 1409 aml_append(scope, method); 1410 1411 aml_append(table, scope); 1412 } 1413 1414 static Aml *build_q35_osc_method(void) 1415 { 1416 Aml *if_ctx; 1417 Aml *if_ctx2; 1418 Aml *else_ctx; 1419 Aml *method; 1420 Aml *a_cwd1 = aml_name("CDW1"); 1421 Aml *a_ctrl = aml_local(0); 1422 1423 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1424 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1425 1426 if_ctx = aml_if(aml_equal( 1427 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1428 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1429 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1430 1431 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1432 1433 /* 1434 * Always allow native PME, AER (no dependencies) 1435 * Allow SHPC (PCI bridges can have SHPC controller) 1436 */ 1437 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1438 1439 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1440 /* Unknown revision */ 1441 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1442 aml_append(if_ctx, if_ctx2); 1443 1444 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1445 /* Capabilities bits were masked */ 1446 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1447 aml_append(if_ctx, if_ctx2); 1448 1449 /* Update DWORD3 in the buffer */ 1450 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1451 aml_append(method, if_ctx); 1452 1453 else_ctx = aml_else(); 1454 /* Unrecognized UUID */ 1455 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1456 aml_append(method, else_ctx); 1457 1458 aml_append(method, aml_return(aml_arg(3))); 1459 return method; 1460 } 1461 1462 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1463 { 1464 Aml *scope = aml_scope("_SB.PCI0"); 1465 Aml *dev = aml_device("SMB0"); 1466 1467 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1468 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1469 aml_append(scope, dev); 1470 aml_append(table, scope); 1471 } 1472 1473 static void 1474 build_dsdt(GArray *table_data, BIOSLinker *linker, 1475 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1476 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1477 { 1478 CrsRangeEntry *entry; 1479 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1480 CrsRangeSet crs_range_set; 1481 PCMachineState *pcms = PC_MACHINE(machine); 1482 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1483 X86MachineState *x86ms = X86_MACHINE(machine); 1484 AcpiMcfgInfo mcfg; 1485 uint32_t nr_mem = machine->ram_slots; 1486 int root_bus_limit = 0xFF; 1487 PCIBus *bus = NULL; 1488 TPMIf *tpm = tpm_find(); 1489 int i; 1490 1491 dsdt = init_aml_allocator(); 1492 1493 /* Reserve space for header */ 1494 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1495 1496 build_dbg_aml(dsdt); 1497 if (misc->is_piix4) { 1498 sb_scope = aml_scope("_SB"); 1499 dev = aml_device("PCI0"); 1500 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1501 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1502 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1503 aml_append(sb_scope, dev); 1504 aml_append(dsdt, sb_scope); 1505 1506 build_hpet_aml(dsdt); 1507 build_piix4_isa_bridge(dsdt); 1508 build_isa_devices_aml(dsdt); 1509 build_piix4_pci_hotplug(dsdt); 1510 build_piix4_pci0_int(dsdt); 1511 } else { 1512 sb_scope = aml_scope("_SB"); 1513 dev = aml_device("PCI0"); 1514 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1515 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1516 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1517 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1518 aml_append(dev, build_q35_osc_method()); 1519 aml_append(sb_scope, dev); 1520 aml_append(dsdt, sb_scope); 1521 1522 build_hpet_aml(dsdt); 1523 build_q35_isa_bridge(dsdt); 1524 build_isa_devices_aml(dsdt); 1525 build_q35_pci0_int(dsdt); 1526 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1527 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1528 } 1529 } 1530 1531 if (pcmc->legacy_cpu_hotplug) { 1532 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1533 } else { 1534 CPUHotplugFeatures opts = { 1535 .acpi_1_compatible = true, .has_legacy_cphp = true 1536 }; 1537 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1538 "\\_SB.PCI0", "\\_GPE._E02"); 1539 } 1540 1541 if (pcms->memhp_io_base && nr_mem) { 1542 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1543 "\\_GPE._E03", AML_SYSTEM_IO, 1544 pcms->memhp_io_base); 1545 } 1546 1547 scope = aml_scope("_GPE"); 1548 { 1549 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1550 1551 if (misc->is_piix4) { 1552 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1553 aml_append(method, 1554 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1555 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1556 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1557 aml_append(scope, method); 1558 } 1559 1560 if (machine->nvdimms_state->is_enabled) { 1561 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1562 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1563 aml_int(0x80))); 1564 aml_append(scope, method); 1565 } 1566 } 1567 aml_append(dsdt, scope); 1568 1569 crs_range_set_init(&crs_range_set); 1570 bus = PC_MACHINE(machine)->bus; 1571 if (bus) { 1572 QLIST_FOREACH(bus, &bus->child, sibling) { 1573 uint8_t bus_num = pci_bus_num(bus); 1574 uint8_t numa_node = pci_bus_numa_node(bus); 1575 1576 /* look only for expander root buses */ 1577 if (!pci_bus_is_root(bus)) { 1578 continue; 1579 } 1580 1581 if (bus_num < root_bus_limit) { 1582 root_bus_limit = bus_num - 1; 1583 } 1584 1585 scope = aml_scope("\\_SB"); 1586 dev = aml_device("PC%.02X", bus_num); 1587 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1588 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1589 if (pci_bus_is_express(bus)) { 1590 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1591 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1592 aml_append(dev, build_q35_osc_method()); 1593 } else { 1594 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1595 } 1596 1597 if (numa_node != NUMA_NODE_UNASSIGNED) { 1598 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1599 } 1600 1601 aml_append(dev, build_prt(false)); 1602 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1603 aml_append(dev, aml_name_decl("_CRS", crs)); 1604 aml_append(scope, dev); 1605 aml_append(dsdt, scope); 1606 } 1607 } 1608 1609 /* 1610 * At this point crs_range_set has all the ranges used by pci 1611 * busses *other* than PCI0. These ranges will be excluded from 1612 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1613 * too. 1614 */ 1615 if (acpi_get_mcfg(&mcfg)) { 1616 crs_range_insert(crs_range_set.mem_ranges, 1617 mcfg.base, mcfg.base + mcfg.size - 1); 1618 } 1619 1620 scope = aml_scope("\\_SB.PCI0"); 1621 /* build PCI0._CRS */ 1622 crs = aml_resource_template(); 1623 aml_append(crs, 1624 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1625 0x0000, 0x0, root_bus_limit, 1626 0x0000, root_bus_limit + 1)); 1627 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1628 1629 aml_append(crs, 1630 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1631 AML_POS_DECODE, AML_ENTIRE_RANGE, 1632 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1633 1634 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1635 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1636 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1637 aml_append(crs, 1638 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1639 AML_POS_DECODE, AML_ENTIRE_RANGE, 1640 0x0000, entry->base, entry->limit, 1641 0x0000, entry->limit - entry->base + 1)); 1642 } 1643 1644 aml_append(crs, 1645 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1646 AML_CACHEABLE, AML_READ_WRITE, 1647 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1648 1649 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1650 range_lob(pci_hole), 1651 range_upb(pci_hole)); 1652 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1653 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1654 aml_append(crs, 1655 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1656 AML_NON_CACHEABLE, AML_READ_WRITE, 1657 0, entry->base, entry->limit, 1658 0, entry->limit - entry->base + 1)); 1659 } 1660 1661 if (!range_is_empty(pci_hole64)) { 1662 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1663 range_lob(pci_hole64), 1664 range_upb(pci_hole64)); 1665 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1666 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1667 aml_append(crs, 1668 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1669 AML_MAX_FIXED, 1670 AML_CACHEABLE, AML_READ_WRITE, 1671 0, entry->base, entry->limit, 1672 0, entry->limit - entry->base + 1)); 1673 } 1674 } 1675 1676 if (TPM_IS_TIS_ISA(tpm_find())) { 1677 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1678 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1679 } 1680 aml_append(scope, aml_name_decl("_CRS", crs)); 1681 1682 /* reserve GPE0 block resources */ 1683 dev = aml_device("GPE0"); 1684 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1685 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1686 /* device present, functioning, decoding, not shown in UI */ 1687 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1688 crs = aml_resource_template(); 1689 aml_append(crs, 1690 aml_io( 1691 AML_DECODE16, 1692 pm->fadt.gpe0_blk.address, 1693 pm->fadt.gpe0_blk.address, 1694 1, 1695 pm->fadt.gpe0_blk.bit_width / 8) 1696 ); 1697 aml_append(dev, aml_name_decl("_CRS", crs)); 1698 aml_append(scope, dev); 1699 1700 crs_range_set_free(&crs_range_set); 1701 1702 /* reserve PCIHP resources */ 1703 if (pm->pcihp_io_len) { 1704 dev = aml_device("PHPR"); 1705 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1706 aml_append(dev, 1707 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1708 /* device present, functioning, decoding, not shown in UI */ 1709 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1710 crs = aml_resource_template(); 1711 aml_append(crs, 1712 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1713 pm->pcihp_io_len) 1714 ); 1715 aml_append(dev, aml_name_decl("_CRS", crs)); 1716 aml_append(scope, dev); 1717 } 1718 aml_append(dsdt, scope); 1719 1720 /* create S3_ / S4_ / S5_ packages if necessary */ 1721 scope = aml_scope("\\"); 1722 if (!pm->s3_disabled) { 1723 pkg = aml_package(4); 1724 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1725 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1726 aml_append(pkg, aml_int(0)); /* reserved */ 1727 aml_append(pkg, aml_int(0)); /* reserved */ 1728 aml_append(scope, aml_name_decl("_S3", pkg)); 1729 } 1730 1731 if (!pm->s4_disabled) { 1732 pkg = aml_package(4); 1733 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1734 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1735 aml_append(pkg, aml_int(pm->s4_val)); 1736 aml_append(pkg, aml_int(0)); /* reserved */ 1737 aml_append(pkg, aml_int(0)); /* reserved */ 1738 aml_append(scope, aml_name_decl("_S4", pkg)); 1739 } 1740 1741 pkg = aml_package(4); 1742 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1743 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1744 aml_append(pkg, aml_int(0)); /* reserved */ 1745 aml_append(pkg, aml_int(0)); /* reserved */ 1746 aml_append(scope, aml_name_decl("_S5", pkg)); 1747 aml_append(dsdt, scope); 1748 1749 /* create fw_cfg node, unconditionally */ 1750 { 1751 scope = aml_scope("\\_SB.PCI0"); 1752 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1753 aml_append(dsdt, scope); 1754 } 1755 1756 if (misc->applesmc_io_base) { 1757 scope = aml_scope("\\_SB.PCI0.ISA"); 1758 dev = aml_device("SMC"); 1759 1760 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1761 /* device present, functioning, decoding, not shown in UI */ 1762 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1763 1764 crs = aml_resource_template(); 1765 aml_append(crs, 1766 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1767 0x01, APPLESMC_MAX_DATA_LENGTH) 1768 ); 1769 aml_append(crs, aml_irq_no_flags(6)); 1770 aml_append(dev, aml_name_decl("_CRS", crs)); 1771 1772 aml_append(scope, dev); 1773 aml_append(dsdt, scope); 1774 } 1775 1776 if (misc->pvpanic_port) { 1777 scope = aml_scope("\\_SB.PCI0.ISA"); 1778 1779 dev = aml_device("PEVT"); 1780 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1781 1782 crs = aml_resource_template(); 1783 aml_append(crs, 1784 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1785 ); 1786 aml_append(dev, aml_name_decl("_CRS", crs)); 1787 1788 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1789 aml_int(misc->pvpanic_port), 1)); 1790 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1791 aml_append(field, aml_named_field("PEPT", 8)); 1792 aml_append(dev, field); 1793 1794 /* device present, functioning, decoding, shown in UI */ 1795 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1796 1797 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1798 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1799 aml_append(method, aml_return(aml_local(0))); 1800 aml_append(dev, method); 1801 1802 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1803 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1804 aml_append(dev, method); 1805 1806 aml_append(scope, dev); 1807 aml_append(dsdt, scope); 1808 } 1809 1810 sb_scope = aml_scope("\\_SB"); 1811 { 1812 Object *pci_host; 1813 PCIBus *bus = NULL; 1814 1815 pci_host = acpi_get_i386_pci_host(); 1816 if (pci_host) { 1817 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1818 } 1819 1820 if (bus) { 1821 Aml *scope = aml_scope("PCI0"); 1822 /* Scan all PCI buses. Generate tables to support hotplug. */ 1823 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1824 1825 if (TPM_IS_TIS_ISA(tpm)) { 1826 if (misc->tpm_version == TPM_VERSION_2_0) { 1827 dev = aml_device("TPM"); 1828 aml_append(dev, aml_name_decl("_HID", 1829 aml_string("MSFT0101"))); 1830 } else { 1831 dev = aml_device("ISA.TPM"); 1832 aml_append(dev, aml_name_decl("_HID", 1833 aml_eisaid("PNP0C31"))); 1834 } 1835 1836 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1837 crs = aml_resource_template(); 1838 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1839 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1840 /* 1841 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1842 Rewrite to take IRQ from TPM device model and 1843 fix default IRQ value there to use some unused IRQ 1844 */ 1845 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1846 aml_append(dev, aml_name_decl("_CRS", crs)); 1847 1848 tpm_build_ppi_acpi(tpm, dev); 1849 1850 aml_append(scope, dev); 1851 } 1852 1853 aml_append(sb_scope, scope); 1854 } 1855 } 1856 1857 if (TPM_IS_CRB(tpm)) { 1858 dev = aml_device("TPM"); 1859 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1860 crs = aml_resource_template(); 1861 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1862 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1863 aml_append(dev, aml_name_decl("_CRS", crs)); 1864 1865 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1866 1867 tpm_build_ppi_acpi(tpm, dev); 1868 1869 aml_append(sb_scope, dev); 1870 } 1871 1872 aml_append(dsdt, sb_scope); 1873 1874 /* copy AML table into ACPI tables blob and patch header there */ 1875 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1876 build_header(linker, table_data, 1877 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1878 "DSDT", dsdt->buf->len, 1, NULL, NULL); 1879 free_aml_allocator(); 1880 } 1881 1882 static void 1883 build_hpet(GArray *table_data, BIOSLinker *linker) 1884 { 1885 Acpi20Hpet *hpet; 1886 1887 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1888 /* Note timer_block_id value must be kept in sync with value advertised by 1889 * emulated hpet 1890 */ 1891 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1892 hpet->addr.address = cpu_to_le64(HPET_BASE); 1893 build_header(linker, table_data, 1894 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 1895 } 1896 1897 static void 1898 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 1899 { 1900 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1901 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1902 unsigned log_addr_offset = 1903 (char *)&tcpa->log_area_start_address - table_data->data; 1904 1905 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1906 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1907 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1908 1909 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1910 false /* high memory */); 1911 1912 /* log area start address to be filled by Guest linker */ 1913 bios_linker_loader_add_pointer(linker, 1914 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1915 ACPI_BUILD_TPMLOG_FILE, 0); 1916 1917 build_header(linker, table_data, 1918 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 1919 } 1920 1921 #define HOLE_640K_START (640 * KiB) 1922 #define HOLE_640K_END (1 * MiB) 1923 1924 static void 1925 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1926 { 1927 AcpiSystemResourceAffinityTable *srat; 1928 AcpiSratMemoryAffinity *numamem; 1929 1930 int i; 1931 int srat_start, numa_start, slots; 1932 uint64_t mem_len, mem_base, next_base; 1933 MachineClass *mc = MACHINE_GET_CLASS(machine); 1934 X86MachineState *x86ms = X86_MACHINE(machine); 1935 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1936 PCMachineState *pcms = PC_MACHINE(machine); 1937 ram_addr_t hotplugabble_address_space_size = 1938 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1939 NULL); 1940 1941 srat_start = table_data->len; 1942 1943 srat = acpi_data_push(table_data, sizeof *srat); 1944 srat->reserved1 = cpu_to_le32(1); 1945 1946 for (i = 0; i < apic_ids->len; i++) { 1947 int node_id = apic_ids->cpus[i].props.node_id; 1948 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1949 1950 if (apic_id < 255) { 1951 AcpiSratProcessorAffinity *core; 1952 1953 core = acpi_data_push(table_data, sizeof *core); 1954 core->type = ACPI_SRAT_PROCESSOR_APIC; 1955 core->length = sizeof(*core); 1956 core->local_apic_id = apic_id; 1957 core->proximity_lo = node_id; 1958 memset(core->proximity_hi, 0, 3); 1959 core->local_sapic_eid = 0; 1960 core->flags = cpu_to_le32(1); 1961 } else { 1962 AcpiSratProcessorX2ApicAffinity *core; 1963 1964 core = acpi_data_push(table_data, sizeof *core); 1965 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 1966 core->length = sizeof(*core); 1967 core->x2apic_id = cpu_to_le32(apic_id); 1968 core->proximity_domain = cpu_to_le32(node_id); 1969 core->flags = cpu_to_le32(1); 1970 } 1971 } 1972 1973 1974 /* the memory map is a bit tricky, it contains at least one hole 1975 * from 640k-1M and possibly another one from 3.5G-4G. 1976 */ 1977 next_base = 0; 1978 numa_start = table_data->len; 1979 1980 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 1981 mem_base = next_base; 1982 mem_len = pcms->node_mem[i - 1]; 1983 next_base = mem_base + mem_len; 1984 1985 /* Cut out the 640K hole */ 1986 if (mem_base <= HOLE_640K_START && 1987 next_base > HOLE_640K_START) { 1988 mem_len -= next_base - HOLE_640K_START; 1989 if (mem_len > 0) { 1990 numamem = acpi_data_push(table_data, sizeof *numamem); 1991 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1992 MEM_AFFINITY_ENABLED); 1993 } 1994 1995 /* Check for the rare case: 640K < RAM < 1M */ 1996 if (next_base <= HOLE_640K_END) { 1997 next_base = HOLE_640K_END; 1998 continue; 1999 } 2000 mem_base = HOLE_640K_END; 2001 mem_len = next_base - HOLE_640K_END; 2002 } 2003 2004 /* Cut out the ACPI_PCI hole */ 2005 if (mem_base <= x86ms->below_4g_mem_size && 2006 next_base > x86ms->below_4g_mem_size) { 2007 mem_len -= next_base - x86ms->below_4g_mem_size; 2008 if (mem_len > 0) { 2009 numamem = acpi_data_push(table_data, sizeof *numamem); 2010 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2011 MEM_AFFINITY_ENABLED); 2012 } 2013 mem_base = 1ULL << 32; 2014 mem_len = next_base - x86ms->below_4g_mem_size; 2015 next_base = mem_base + mem_len; 2016 } 2017 2018 if (mem_len > 0) { 2019 numamem = acpi_data_push(table_data, sizeof *numamem); 2020 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2021 MEM_AFFINITY_ENABLED); 2022 } 2023 } 2024 2025 if (machine->nvdimms_state->is_enabled) { 2026 nvdimm_build_srat(table_data); 2027 } 2028 2029 slots = (table_data->len - numa_start) / sizeof *numamem; 2030 for (; slots < pcms->numa_nodes + 2; slots++) { 2031 numamem = acpi_data_push(table_data, sizeof *numamem); 2032 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2033 } 2034 2035 /* 2036 * Entry is required for Windows to enable memory hotplug in OS 2037 * and for Linux to enable SWIOTLB when booted with less than 2038 * 4G of RAM. Windows works better if the entry sets proximity 2039 * to the highest NUMA node in the machine. 2040 * Memory devices may override proximity set by this entry, 2041 * providing _PXM method if necessary. 2042 */ 2043 if (hotplugabble_address_space_size) { 2044 numamem = acpi_data_push(table_data, sizeof *numamem); 2045 build_srat_memory(numamem, machine->device_memory->base, 2046 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2047 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2048 } 2049 2050 build_header(linker, table_data, 2051 (void *)(table_data->data + srat_start), 2052 "SRAT", 2053 table_data->len - srat_start, 1, NULL, NULL); 2054 } 2055 2056 /* 2057 * VT-d spec 8.1 DMA Remapping Reporting Structure 2058 * (version Oct. 2014 or later) 2059 */ 2060 static void 2061 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2062 { 2063 int dmar_start = table_data->len; 2064 2065 AcpiTableDmar *dmar; 2066 AcpiDmarHardwareUnit *drhd; 2067 AcpiDmarRootPortATS *atsr; 2068 uint8_t dmar_flags = 0; 2069 X86IOMMUState *iommu = x86_iommu_get_default(); 2070 AcpiDmarDeviceScope *scope = NULL; 2071 /* Root complex IOAPIC use one path[0] only */ 2072 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2073 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2074 2075 assert(iommu); 2076 if (x86_iommu_ir_supported(iommu)) { 2077 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2078 } 2079 2080 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2081 dmar->host_address_width = intel_iommu->aw_bits - 1; 2082 dmar->flags = dmar_flags; 2083 2084 /* DMAR Remapping Hardware Unit Definition structure */ 2085 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2086 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2087 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2088 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2089 drhd->pci_segment = cpu_to_le16(0); 2090 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2091 2092 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2093 * 8.3.1 (version Oct. 2014 or later). */ 2094 scope = &drhd->scope[0]; 2095 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2096 scope->length = ioapic_scope_size; 2097 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2098 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2099 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2100 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2101 2102 if (iommu->dt_supported) { 2103 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2104 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2105 atsr->length = cpu_to_le16(sizeof(*atsr)); 2106 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2107 atsr->pci_segment = cpu_to_le16(0); 2108 } 2109 2110 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2111 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2112 } 2113 2114 /* 2115 * Windows ACPI Emulated Devices Table 2116 * (Version 1.0 - April 6, 2009) 2117 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2118 * 2119 * Helpful to speedup Windows guests and ignored by others. 2120 */ 2121 static void 2122 build_waet(GArray *table_data, BIOSLinker *linker) 2123 { 2124 int waet_start = table_data->len; 2125 2126 /* WAET header */ 2127 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2128 /* 2129 * Set "ACPI PM timer good" flag. 2130 * 2131 * Tells Windows guests that our ACPI PM timer is reliable in the 2132 * sense that guest can read it only once to obtain a reliable value. 2133 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2134 */ 2135 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2136 2137 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2138 "WAET", table_data->len - waet_start, 1, NULL, NULL); 2139 } 2140 2141 /* 2142 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2143 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2144 */ 2145 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2146 2147 /* 2148 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2149 * necessary for the PCI topology. 2150 */ 2151 static void 2152 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2153 { 2154 GArray *table_data = opaque; 2155 uint32_t entry; 2156 2157 /* "Select" IVHD entry, type 0x2 */ 2158 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2159 build_append_int_noprefix(table_data, entry, 4); 2160 2161 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2162 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2163 uint8_t sec = pci_bus_num(sec_bus); 2164 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2165 2166 if (pci_bus_is_express(sec_bus)) { 2167 /* 2168 * Walk the bus if there are subordinates, otherwise use a range 2169 * to cover an entire leaf bus. We could potentially also use a 2170 * range for traversed buses, but we'd need to take care not to 2171 * create both Select and Range entries covering the same device. 2172 * This is easier and potentially more compact. 2173 * 2174 * An example bare metal system seems to use Select entries for 2175 * root ports without a slot (ie. built-ins) and Range entries 2176 * when there is a slot. The same system also only hard-codes 2177 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2178 * making no effort to support nested bridges. We attempt to 2179 * be more thorough here. 2180 */ 2181 if (sec == sub) { /* leaf bus */ 2182 /* "Start of Range" IVHD entry, type 0x3 */ 2183 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2184 build_append_int_noprefix(table_data, entry, 4); 2185 /* "End of Range" IVHD entry, type 0x4 */ 2186 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2187 build_append_int_noprefix(table_data, entry, 4); 2188 } else { 2189 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2190 } 2191 } else { 2192 /* 2193 * If the secondary bus is conventional, then we need to create an 2194 * Alias range for everything downstream. The range covers the 2195 * first devfn on the secondary bus to the last devfn on the 2196 * subordinate bus. The alias target depends on legacy versus 2197 * express bridges, just as in pci_device_iommu_address_space(). 2198 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2199 */ 2200 uint16_t dev_id_a, dev_id_b; 2201 2202 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2203 2204 if (pci_is_express(dev) && 2205 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2206 dev_id_b = dev_id_a; 2207 } else { 2208 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2209 } 2210 2211 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2212 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2213 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2214 2215 /* "End of Range" IVHD entry, type 0x4 */ 2216 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2217 build_append_int_noprefix(table_data, entry, 4); 2218 } 2219 } 2220 } 2221 2222 /* For all PCI host bridges, walk and insert IVHD entries */ 2223 static int 2224 ivrs_host_bridges(Object *obj, void *opaque) 2225 { 2226 GArray *ivhd_blob = opaque; 2227 2228 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2229 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2230 2231 if (bus) { 2232 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2233 } 2234 } 2235 2236 return 0; 2237 } 2238 2239 static void 2240 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2241 { 2242 int ivhd_table_len = 24; 2243 int iommu_start = table_data->len; 2244 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2245 GArray *ivhd_blob = g_array_new(false, true, 1); 2246 2247 /* IVRS header */ 2248 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2249 /* IVinfo - IO virtualization information common to all 2250 * IOMMU units in a system 2251 */ 2252 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2253 /* reserved */ 2254 build_append_int_noprefix(table_data, 0, 8); 2255 2256 /* IVHD definition - type 10h */ 2257 build_append_int_noprefix(table_data, 0x10, 1); 2258 /* virtualization flags */ 2259 build_append_int_noprefix(table_data, 2260 (1UL << 0) | /* HtTunEn */ 2261 (1UL << 4) | /* iotblSup */ 2262 (1UL << 6) | /* PrefSup */ 2263 (1UL << 7), /* PPRSup */ 2264 1); 2265 2266 /* 2267 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2268 * complete set of IVHD entries. Do this into a separate blob so that we 2269 * can calculate the total IVRS table length here and then append the new 2270 * blob further below. Fall back to an entry covering all devices, which 2271 * is sufficient when no aliases are present. 2272 */ 2273 object_child_foreach_recursive(object_get_root(), 2274 ivrs_host_bridges, ivhd_blob); 2275 2276 if (!ivhd_blob->len) { 2277 /* 2278 * Type 1 device entry reporting all devices 2279 * These are 4-byte device entries currently reporting the range of 2280 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2281 */ 2282 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2283 } 2284 2285 ivhd_table_len += ivhd_blob->len; 2286 2287 /* 2288 * When interrupt remapping is supported, we add a special IVHD device 2289 * for type IO-APIC. 2290 */ 2291 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2292 ivhd_table_len += 8; 2293 } 2294 2295 /* IVHD length */ 2296 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2297 /* DeviceID */ 2298 build_append_int_noprefix(table_data, s->devid, 2); 2299 /* Capability offset */ 2300 build_append_int_noprefix(table_data, s->capab_offset, 2); 2301 /* IOMMU base address */ 2302 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2303 /* PCI Segment Group */ 2304 build_append_int_noprefix(table_data, 0, 2); 2305 /* IOMMU info */ 2306 build_append_int_noprefix(table_data, 0, 2); 2307 /* IOMMU Feature Reporting */ 2308 build_append_int_noprefix(table_data, 2309 (48UL << 30) | /* HATS */ 2310 (48UL << 28) | /* GATS */ 2311 (1UL << 2) | /* GTSup */ 2312 (1UL << 6), /* GASup */ 2313 4); 2314 2315 /* IVHD entries as found above */ 2316 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2317 g_array_free(ivhd_blob, TRUE); 2318 2319 /* 2320 * Add a special IVHD device type. 2321 * Refer to spec - Table 95: IVHD device entry type codes 2322 * 2323 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2324 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2325 */ 2326 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2327 build_append_int_noprefix(table_data, 2328 (0x1ull << 56) | /* type IOAPIC */ 2329 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2330 0x48, /* special device */ 2331 8); 2332 } 2333 2334 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2335 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2336 } 2337 2338 typedef 2339 struct AcpiBuildState { 2340 /* Copy of table in RAM (for patching). */ 2341 MemoryRegion *table_mr; 2342 /* Is table patched? */ 2343 uint8_t patched; 2344 void *rsdp; 2345 MemoryRegion *rsdp_mr; 2346 MemoryRegion *linker_mr; 2347 } AcpiBuildState; 2348 2349 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2350 { 2351 Object *pci_host; 2352 QObject *o; 2353 2354 pci_host = acpi_get_i386_pci_host(); 2355 g_assert(pci_host); 2356 2357 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2358 if (!o) { 2359 return false; 2360 } 2361 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2362 qobject_unref(o); 2363 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2364 return false; 2365 } 2366 2367 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2368 assert(o); 2369 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2370 qobject_unref(o); 2371 return true; 2372 } 2373 2374 static 2375 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2376 { 2377 PCMachineState *pcms = PC_MACHINE(machine); 2378 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2379 X86MachineState *x86ms = X86_MACHINE(machine); 2380 GArray *table_offsets; 2381 unsigned facs, dsdt, rsdt, fadt; 2382 AcpiPmInfo pm; 2383 AcpiMiscInfo misc; 2384 AcpiMcfgInfo mcfg; 2385 Range pci_hole, pci_hole64; 2386 uint8_t *u; 2387 size_t aml_len = 0; 2388 GArray *tables_blob = tables->table_data; 2389 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2390 Object *vmgenid_dev; 2391 2392 acpi_get_pm_info(machine, &pm); 2393 acpi_get_misc_info(&misc); 2394 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2395 acpi_get_slic_oem(&slic_oem); 2396 2397 table_offsets = g_array_new(false, true /* clear */, 2398 sizeof(uint32_t)); 2399 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2400 2401 bios_linker_loader_alloc(tables->linker, 2402 ACPI_BUILD_TABLE_FILE, tables_blob, 2403 64 /* Ensure FACS is aligned */, 2404 false /* high memory */); 2405 2406 /* 2407 * FACS is pointed to by FADT. 2408 * We place it first since it's the only table that has alignment 2409 * requirements. 2410 */ 2411 facs = tables_blob->len; 2412 build_facs(tables_blob); 2413 2414 /* DSDT is pointed to by FADT */ 2415 dsdt = tables_blob->len; 2416 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2417 &pci_hole, &pci_hole64, machine); 2418 2419 /* Count the size of the DSDT and SSDT, we will need it for legacy 2420 * sizing of ACPI tables. 2421 */ 2422 aml_len += tables_blob->len - dsdt; 2423 2424 /* ACPI tables pointed to by RSDT */ 2425 fadt = tables_blob->len; 2426 acpi_add_table(table_offsets, tables_blob); 2427 pm.fadt.facs_tbl_offset = &facs; 2428 pm.fadt.dsdt_tbl_offset = &dsdt; 2429 pm.fadt.xdsdt_tbl_offset = &dsdt; 2430 build_fadt(tables_blob, tables->linker, &pm.fadt, 2431 slic_oem.id, slic_oem.table_id); 2432 aml_len += tables_blob->len - fadt; 2433 2434 acpi_add_table(table_offsets, tables_blob); 2435 acpi_build_madt(tables_blob, tables->linker, x86ms, 2436 ACPI_DEVICE_IF(pcms->acpi_dev), true); 2437 2438 vmgenid_dev = find_vmgenid_dev(); 2439 if (vmgenid_dev) { 2440 acpi_add_table(table_offsets, tables_blob); 2441 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2442 tables->vmgenid, tables->linker); 2443 } 2444 2445 if (misc.has_hpet) { 2446 acpi_add_table(table_offsets, tables_blob); 2447 build_hpet(tables_blob, tables->linker); 2448 } 2449 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2450 if (misc.tpm_version == TPM_VERSION_1_2) { 2451 acpi_add_table(table_offsets, tables_blob); 2452 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2453 } else { /* TPM_VERSION_2_0 */ 2454 acpi_add_table(table_offsets, tables_blob); 2455 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2456 } 2457 } 2458 if (pcms->numa_nodes) { 2459 acpi_add_table(table_offsets, tables_blob); 2460 build_srat(tables_blob, tables->linker, machine); 2461 if (machine->numa_state->have_numa_distance) { 2462 acpi_add_table(table_offsets, tables_blob); 2463 build_slit(tables_blob, tables->linker, machine); 2464 } 2465 if (machine->numa_state->hmat_enabled) { 2466 acpi_add_table(table_offsets, tables_blob); 2467 build_hmat(tables_blob, tables->linker, machine->numa_state); 2468 } 2469 } 2470 if (acpi_get_mcfg(&mcfg)) { 2471 acpi_add_table(table_offsets, tables_blob); 2472 build_mcfg(tables_blob, tables->linker, &mcfg); 2473 } 2474 if (x86_iommu_get_default()) { 2475 IommuType IOMMUType = x86_iommu_get_type(); 2476 if (IOMMUType == TYPE_AMD) { 2477 acpi_add_table(table_offsets, tables_blob); 2478 build_amd_iommu(tables_blob, tables->linker); 2479 } else if (IOMMUType == TYPE_INTEL) { 2480 acpi_add_table(table_offsets, tables_blob); 2481 build_dmar_q35(tables_blob, tables->linker); 2482 } 2483 } 2484 if (machine->nvdimms_state->is_enabled) { 2485 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2486 machine->nvdimms_state, machine->ram_slots); 2487 } 2488 2489 acpi_add_table(table_offsets, tables_blob); 2490 build_waet(tables_blob, tables->linker); 2491 2492 /* Add tables supplied by user (if any) */ 2493 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2494 unsigned len = acpi_table_len(u); 2495 2496 acpi_add_table(table_offsets, tables_blob); 2497 g_array_append_vals(tables_blob, u, len); 2498 } 2499 2500 /* RSDT is pointed to by RSDP */ 2501 rsdt = tables_blob->len; 2502 build_rsdt(tables_blob, tables->linker, table_offsets, 2503 slic_oem.id, slic_oem.table_id); 2504 2505 /* RSDP is in FSEG memory, so allocate it separately */ 2506 { 2507 AcpiRsdpData rsdp_data = { 2508 .revision = 0, 2509 .oem_id = ACPI_BUILD_APPNAME6, 2510 .xsdt_tbl_offset = NULL, 2511 .rsdt_tbl_offset = &rsdt, 2512 }; 2513 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2514 if (!pcmc->rsdp_in_ram) { 2515 /* We used to allocate some extra space for RSDP revision 2 but 2516 * only used the RSDP revision 0 space. The extra bytes were 2517 * zeroed out and not used. 2518 * Here we continue wasting those extra 16 bytes to make sure we 2519 * don't break migration for machine types 2.2 and older due to 2520 * RSDP blob size mismatch. 2521 */ 2522 build_append_int_noprefix(tables->rsdp, 0, 16); 2523 } 2524 } 2525 2526 /* We'll expose it all to Guest so we want to reduce 2527 * chance of size changes. 2528 * 2529 * We used to align the tables to 4k, but of course this would 2530 * too simple to be enough. 4k turned out to be too small an 2531 * alignment very soon, and in fact it is almost impossible to 2532 * keep the table size stable for all (max_cpus, max_memory_slots) 2533 * combinations. So the table size is always 64k for pc-i440fx-2.1 2534 * and we give an error if the table grows beyond that limit. 2535 * 2536 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2537 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2538 * than 2.0 and we can always pad the smaller tables with zeros. We can 2539 * then use the exact size of the 2.0 tables. 2540 * 2541 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2542 */ 2543 if (pcmc->legacy_acpi_table_size) { 2544 /* Subtracting aml_len gives the size of fixed tables. Then add the 2545 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2546 */ 2547 int legacy_aml_len = 2548 pcmc->legacy_acpi_table_size + 2549 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2550 int legacy_table_size = 2551 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2552 ACPI_BUILD_ALIGN_SIZE); 2553 if (tables_blob->len > legacy_table_size) { 2554 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2555 warn_report("ACPI table size %u exceeds %d bytes," 2556 " migration may not work", 2557 tables_blob->len, legacy_table_size); 2558 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2559 " or PCI bridges."); 2560 } 2561 g_array_set_size(tables_blob, legacy_table_size); 2562 } else { 2563 /* Make sure we have a buffer in case we need to resize the tables. */ 2564 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2565 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2566 warn_report("ACPI table size %u exceeds %d bytes," 2567 " migration may not work", 2568 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2569 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2570 " or PCI bridges."); 2571 } 2572 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2573 } 2574 2575 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2576 2577 /* Cleanup memory that's no longer used. */ 2578 g_array_free(table_offsets, true); 2579 } 2580 2581 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2582 { 2583 uint32_t size = acpi_data_len(data); 2584 2585 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2586 memory_region_ram_resize(mr, size, &error_abort); 2587 2588 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2589 memory_region_set_dirty(mr, 0, size); 2590 } 2591 2592 static void acpi_build_update(void *build_opaque) 2593 { 2594 AcpiBuildState *build_state = build_opaque; 2595 AcpiBuildTables tables; 2596 2597 /* No state to update or already patched? Nothing to do. */ 2598 if (!build_state || build_state->patched) { 2599 return; 2600 } 2601 build_state->patched = 1; 2602 2603 acpi_build_tables_init(&tables); 2604 2605 acpi_build(&tables, MACHINE(qdev_get_machine())); 2606 2607 acpi_ram_update(build_state->table_mr, tables.table_data); 2608 2609 if (build_state->rsdp) { 2610 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2611 } else { 2612 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2613 } 2614 2615 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2616 acpi_build_tables_cleanup(&tables, true); 2617 } 2618 2619 static void acpi_build_reset(void *build_opaque) 2620 { 2621 AcpiBuildState *build_state = build_opaque; 2622 build_state->patched = 0; 2623 } 2624 2625 static const VMStateDescription vmstate_acpi_build = { 2626 .name = "acpi_build", 2627 .version_id = 1, 2628 .minimum_version_id = 1, 2629 .fields = (VMStateField[]) { 2630 VMSTATE_UINT8(patched, AcpiBuildState), 2631 VMSTATE_END_OF_LIST() 2632 }, 2633 }; 2634 2635 void acpi_setup(void) 2636 { 2637 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2638 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2639 X86MachineState *x86ms = X86_MACHINE(pcms); 2640 AcpiBuildTables tables; 2641 AcpiBuildState *build_state; 2642 Object *vmgenid_dev; 2643 TPMIf *tpm; 2644 static FwCfgTPMConfig tpm_config; 2645 2646 if (!x86ms->fw_cfg) { 2647 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2648 return; 2649 } 2650 2651 if (!pcms->acpi_build_enabled) { 2652 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2653 return; 2654 } 2655 2656 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2657 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2658 return; 2659 } 2660 2661 build_state = g_malloc0(sizeof *build_state); 2662 2663 acpi_build_tables_init(&tables); 2664 acpi_build(&tables, MACHINE(pcms)); 2665 2666 /* Now expose it all to Guest */ 2667 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2668 build_state, tables.table_data, 2669 ACPI_BUILD_TABLE_FILE, 2670 ACPI_BUILD_TABLE_MAX_SIZE); 2671 assert(build_state->table_mr != NULL); 2672 2673 build_state->linker_mr = 2674 acpi_add_rom_blob(acpi_build_update, build_state, 2675 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 2676 2677 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2678 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2679 2680 tpm = tpm_find(); 2681 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2682 tpm_config = (FwCfgTPMConfig) { 2683 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2684 .tpm_version = tpm_get_version(tpm), 2685 .tpmppi_version = TPM_PPI_VERSION_1_30 2686 }; 2687 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2688 &tpm_config, sizeof tpm_config); 2689 } 2690 2691 vmgenid_dev = find_vmgenid_dev(); 2692 if (vmgenid_dev) { 2693 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2694 tables.vmgenid); 2695 } 2696 2697 if (!pcmc->rsdp_in_ram) { 2698 /* 2699 * Keep for compatibility with old machine types. 2700 * Though RSDP is small, its contents isn't immutable, so 2701 * we'll update it along with the rest of tables on guest access. 2702 */ 2703 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2704 2705 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2706 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2707 acpi_build_update, NULL, build_state, 2708 build_state->rsdp, rsdp_size, true); 2709 build_state->rsdp_mr = NULL; 2710 } else { 2711 build_state->rsdp = NULL; 2712 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2713 build_state, tables.rsdp, 2714 ACPI_BUILD_RSDP_FILE, 0); 2715 } 2716 2717 qemu_register_reset(acpi_build_reset, build_state); 2718 acpi_build_reset(build_state); 2719 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2720 2721 /* Cleanup tables but don't free the memory: we track it 2722 * in build_state. 2723 */ 2724 acpi_build_tables_cleanup(&tables, false); 2725 } 2726