1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "qom/cpu.h" 32 #include "hw/i386/pc.h" 33 #include "target-i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "hw/mem/nvdimm.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "sysemu/tpm_backend.h" 46 #include "hw/timer/mc146818rtc_regs.h" 47 48 /* Supported chipsets: */ 49 #include "hw/acpi/piix4.h" 50 #include "hw/acpi/pcihp.h" 51 #include "hw/i386/ich9.h" 52 #include "hw/pci/pci_bus.h" 53 #include "hw/pci-host/q35.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/timer/hpet.h" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 64 * a little bit, there should be plenty of free space since the DSDT 65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 66 */ 67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 68 #define ACPI_BUILD_ALIGN_SIZE 0x1000 69 70 #define ACPI_BUILD_TABLE_SIZE 0x20000 71 72 /* #define DEBUG_ACPI_BUILD */ 73 #ifdef DEBUG_ACPI_BUILD 74 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 76 #else 77 #define ACPI_BUILD_DPRINTF(fmt, ...) 78 #endif 79 80 typedef struct AcpiCpuInfo { 81 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 82 } AcpiCpuInfo; 83 84 typedef struct AcpiMcfgInfo { 85 uint64_t mcfg_base; 86 uint32_t mcfg_size; 87 } AcpiMcfgInfo; 88 89 typedef struct AcpiPmInfo { 90 bool s3_disabled; 91 bool s4_disabled; 92 bool pcihp_bridge_en; 93 uint8_t s4_val; 94 uint16_t sci_int; 95 uint8_t acpi_enable_cmd; 96 uint8_t acpi_disable_cmd; 97 uint32_t gpe0_blk; 98 uint32_t gpe0_blk_len; 99 uint32_t io_base; 100 uint16_t cpu_hp_io_base; 101 uint16_t cpu_hp_io_len; 102 uint16_t mem_hp_io_base; 103 uint16_t mem_hp_io_len; 104 uint16_t pcihp_io_base; 105 uint16_t pcihp_io_len; 106 } AcpiPmInfo; 107 108 typedef struct AcpiMiscInfo { 109 bool is_piix4; 110 bool has_hpet; 111 TPMVersion tpm_version; 112 const unsigned char *dsdt_code; 113 unsigned dsdt_size; 114 uint16_t pvpanic_port; 115 uint16_t applesmc_io_base; 116 } AcpiMiscInfo; 117 118 typedef struct AcpiBuildPciBusHotplugState { 119 GArray *device_table; 120 GArray *notify_table; 121 struct AcpiBuildPciBusHotplugState *parent; 122 bool pcihp_bridge_en; 123 } AcpiBuildPciBusHotplugState; 124 125 static 126 int acpi_add_cpu_info(Object *o, void *opaque) 127 { 128 AcpiCpuInfo *cpu = opaque; 129 uint64_t apic_id; 130 131 if (object_dynamic_cast(o, TYPE_CPU)) { 132 apic_id = object_property_get_int(o, "apic-id", NULL); 133 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 134 135 set_bit(apic_id, cpu->found_cpus); 136 } 137 138 object_child_foreach(o, acpi_add_cpu_info, opaque); 139 return 0; 140 } 141 142 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 143 { 144 Object *root = object_get_root(); 145 146 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 147 object_child_foreach(root, acpi_add_cpu_info, cpu); 148 } 149 150 static void acpi_get_pm_info(AcpiPmInfo *pm) 151 { 152 Object *piix = piix4_pm_find(); 153 Object *lpc = ich9_lpc_find(); 154 Object *obj = NULL; 155 QObject *o; 156 157 pm->cpu_hp_io_base = 0; 158 pm->pcihp_io_base = 0; 159 pm->pcihp_io_len = 0; 160 if (piix) { 161 obj = piix; 162 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 163 pm->pcihp_io_base = 164 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 165 pm->pcihp_io_len = 166 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 167 } 168 if (lpc) { 169 obj = lpc; 170 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 171 } 172 assert(obj); 173 174 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 175 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 176 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 177 178 /* Fill in optional s3/s4 related properties */ 179 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 180 if (o) { 181 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 182 } else { 183 pm->s3_disabled = false; 184 } 185 qobject_decref(o); 186 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 187 if (o) { 188 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 189 } else { 190 pm->s4_disabled = false; 191 } 192 qobject_decref(o); 193 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 194 if (o) { 195 pm->s4_val = qint_get_int(qobject_to_qint(o)); 196 } else { 197 pm->s4_val = false; 198 } 199 qobject_decref(o); 200 201 /* Fill in mandatory properties */ 202 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 203 204 pm->acpi_enable_cmd = object_property_get_int(obj, 205 ACPI_PM_PROP_ACPI_ENABLE_CMD, 206 NULL); 207 pm->acpi_disable_cmd = object_property_get_int(obj, 208 ACPI_PM_PROP_ACPI_DISABLE_CMD, 209 NULL); 210 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 211 NULL); 212 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 213 NULL); 214 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 215 NULL); 216 pm->pcihp_bridge_en = 217 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 218 NULL); 219 } 220 221 static void acpi_get_misc_info(AcpiMiscInfo *info) 222 { 223 Object *piix = piix4_pm_find(); 224 Object *lpc = ich9_lpc_find(); 225 assert(!!piix != !!lpc); 226 227 if (piix) { 228 info->is_piix4 = true; 229 } 230 if (lpc) { 231 info->is_piix4 = false; 232 } 233 234 info->has_hpet = hpet_find(); 235 info->tpm_version = tpm_get_version(); 236 info->pvpanic_port = pvpanic_port(); 237 info->applesmc_io_base = applesmc_port(); 238 } 239 240 /* 241 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 242 * On i386 arch we only have two pci hosts, so we can look only for them. 243 */ 244 static Object *acpi_get_i386_pci_host(void) 245 { 246 PCIHostState *host; 247 248 host = OBJECT_CHECK(PCIHostState, 249 object_resolve_path("/machine/i440fx", NULL), 250 TYPE_PCI_HOST_BRIDGE); 251 if (!host) { 252 host = OBJECT_CHECK(PCIHostState, 253 object_resolve_path("/machine/q35", NULL), 254 TYPE_PCI_HOST_BRIDGE); 255 } 256 257 return OBJECT(host); 258 } 259 260 static void acpi_get_pci_info(PcPciInfo *info) 261 { 262 Object *pci_host; 263 264 265 pci_host = acpi_get_i386_pci_host(); 266 g_assert(pci_host); 267 268 info->w32.begin = object_property_get_int(pci_host, 269 PCI_HOST_PROP_PCI_HOLE_START, 270 NULL); 271 info->w32.end = object_property_get_int(pci_host, 272 PCI_HOST_PROP_PCI_HOLE_END, 273 NULL); 274 info->w64.begin = object_property_get_int(pci_host, 275 PCI_HOST_PROP_PCI_HOLE64_START, 276 NULL); 277 info->w64.end = object_property_get_int(pci_host, 278 PCI_HOST_PROP_PCI_HOLE64_END, 279 NULL); 280 } 281 282 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 283 284 static void acpi_align_size(GArray *blob, unsigned align) 285 { 286 /* Align size to multiple of given size. This reduces the chance 287 * we need to change size in the future (breaking cross version migration). 288 */ 289 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 290 } 291 292 /* FACS */ 293 static void 294 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 295 { 296 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 297 memcpy(&facs->signature, "FACS", 4); 298 facs->length = cpu_to_le32(sizeof(*facs)); 299 } 300 301 /* Load chipset information in FADT */ 302 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 303 { 304 fadt->model = 1; 305 fadt->reserved1 = 0; 306 fadt->sci_int = cpu_to_le16(pm->sci_int); 307 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 308 fadt->acpi_enable = pm->acpi_enable_cmd; 309 fadt->acpi_disable = pm->acpi_disable_cmd; 310 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 311 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 312 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 313 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 314 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 315 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 316 fadt->pm1_evt_len = 4; 317 fadt->pm1_cnt_len = 2; 318 fadt->pm_tmr_len = 4; 319 fadt->gpe0_blk_len = pm->gpe0_blk_len; 320 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 321 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 322 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 323 (1 << ACPI_FADT_F_PROC_C1) | 324 (1 << ACPI_FADT_F_SLP_BUTTON) | 325 (1 << ACPI_FADT_F_RTC_S4)); 326 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 327 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 328 * For more than 8 CPUs, "Clustered Logical" mode has to be used 329 */ 330 if (max_cpus > 8) { 331 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 332 } 333 fadt->century = RTC_CENTURY; 334 } 335 336 337 /* FADT */ 338 static void 339 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 340 unsigned facs, unsigned dsdt) 341 { 342 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 343 344 fadt->firmware_ctrl = cpu_to_le32(facs); 345 /* FACS address to be filled by Guest linker */ 346 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 347 ACPI_BUILD_TABLE_FILE, 348 table_data, &fadt->firmware_ctrl, 349 sizeof fadt->firmware_ctrl); 350 351 fadt->dsdt = cpu_to_le32(dsdt); 352 /* DSDT address to be filled by Guest linker */ 353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 354 ACPI_BUILD_TABLE_FILE, 355 table_data, &fadt->dsdt, 356 sizeof fadt->dsdt); 357 358 fadt_setup(fadt, pm); 359 360 build_header(linker, table_data, 361 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL); 362 } 363 364 static void 365 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 366 PcGuestInfo *guest_info) 367 { 368 int madt_start = table_data->len; 369 370 AcpiMultipleApicTable *madt; 371 AcpiMadtIoApic *io_apic; 372 AcpiMadtIntsrcovr *intsrcovr; 373 AcpiMadtLocalNmi *local_nmi; 374 int i; 375 376 madt = acpi_data_push(table_data, sizeof *madt); 377 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 378 madt->flags = cpu_to_le32(1); 379 380 for (i = 0; i < guest_info->apic_id_limit; i++) { 381 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 382 apic->type = ACPI_APIC_PROCESSOR; 383 apic->length = sizeof(*apic); 384 apic->processor_id = i; 385 apic->local_apic_id = i; 386 if (test_bit(i, cpu->found_cpus)) { 387 apic->flags = cpu_to_le32(1); 388 } else { 389 apic->flags = cpu_to_le32(0); 390 } 391 } 392 io_apic = acpi_data_push(table_data, sizeof *io_apic); 393 io_apic->type = ACPI_APIC_IO; 394 io_apic->length = sizeof(*io_apic); 395 #define ACPI_BUILD_IOAPIC_ID 0x0 396 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 397 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 398 io_apic->interrupt = cpu_to_le32(0); 399 400 if (guest_info->apic_xrupt_override) { 401 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 402 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 403 intsrcovr->length = sizeof(*intsrcovr); 404 intsrcovr->source = 0; 405 intsrcovr->gsi = cpu_to_le32(2); 406 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 407 } 408 for (i = 1; i < 16; i++) { 409 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 410 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 411 /* No need for a INT source override structure. */ 412 continue; 413 } 414 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 415 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 416 intsrcovr->length = sizeof(*intsrcovr); 417 intsrcovr->source = i; 418 intsrcovr->gsi = cpu_to_le32(i); 419 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 420 } 421 422 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 423 local_nmi->type = ACPI_APIC_LOCAL_NMI; 424 local_nmi->length = sizeof(*local_nmi); 425 local_nmi->processor_id = 0xff; /* all processors */ 426 local_nmi->flags = cpu_to_le16(0); 427 local_nmi->lint = 1; /* ACPI_LINT1 */ 428 429 build_header(linker, table_data, 430 (void *)(table_data->data + madt_start), "APIC", 431 table_data->len - madt_start, 1, NULL); 432 } 433 434 /* Assign BSEL property to all buses. In the future, this can be changed 435 * to only assign to buses that support hotplug. 436 */ 437 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 438 { 439 unsigned *bsel_alloc = opaque; 440 unsigned *bus_bsel; 441 442 if (qbus_is_hotpluggable(BUS(bus))) { 443 bus_bsel = g_malloc(sizeof *bus_bsel); 444 445 *bus_bsel = (*bsel_alloc)++; 446 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 447 bus_bsel, NULL); 448 } 449 450 return bsel_alloc; 451 } 452 453 static void acpi_set_pci_info(void) 454 { 455 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 456 unsigned bsel_alloc = 0; 457 458 if (bus) { 459 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 460 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 461 } 462 } 463 464 static void build_append_pcihp_notify_entry(Aml *method, int slot) 465 { 466 Aml *if_ctx; 467 int32_t devfn = PCI_DEVFN(slot, 0); 468 469 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 470 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 471 aml_append(method, if_ctx); 472 } 473 474 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 475 bool pcihp_bridge_en) 476 { 477 Aml *dev, *notify_method, *method; 478 QObject *bsel; 479 PCIBus *sec; 480 int i; 481 482 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 483 if (bsel) { 484 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 485 486 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 487 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 488 } 489 490 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 491 DeviceClass *dc; 492 PCIDeviceClass *pc; 493 PCIDevice *pdev = bus->devices[i]; 494 int slot = PCI_SLOT(i); 495 bool hotplug_enabled_dev; 496 bool bridge_in_acpi; 497 498 if (!pdev) { 499 if (bsel) { /* add hotplug slots for non present devices */ 500 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 501 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 502 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 503 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 504 aml_append(method, 505 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 506 ); 507 aml_append(dev, method); 508 aml_append(parent_scope, dev); 509 510 build_append_pcihp_notify_entry(notify_method, slot); 511 } 512 continue; 513 } 514 515 pc = PCI_DEVICE_GET_CLASS(pdev); 516 dc = DEVICE_GET_CLASS(pdev); 517 518 /* When hotplug for bridges is enabled, bridges are 519 * described in ACPI separately (see build_pci_bus_end). 520 * In this case they aren't themselves hot-pluggable. 521 * Hotplugged bridges *are* hot-pluggable. 522 */ 523 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 524 !DEVICE(pdev)->hotplugged; 525 526 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 527 528 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 529 continue; 530 } 531 532 /* start to compose PCI slot descriptor */ 533 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 534 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 535 536 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 537 /* add VGA specific AML methods */ 538 int s3d; 539 540 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 541 s3d = 3; 542 } else { 543 s3d = 0; 544 } 545 546 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 547 aml_append(method, aml_return(aml_int(0))); 548 aml_append(dev, method); 549 550 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 551 aml_append(method, aml_return(aml_int(0))); 552 aml_append(dev, method); 553 554 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 555 aml_append(method, aml_return(aml_int(s3d))); 556 aml_append(dev, method); 557 } else if (hotplug_enabled_dev) { 558 /* add _SUN/_EJ0 to make slot hotpluggable */ 559 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 560 561 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 562 aml_append(method, 563 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 564 ); 565 aml_append(dev, method); 566 567 if (bsel) { 568 build_append_pcihp_notify_entry(notify_method, slot); 569 } 570 } else if (bridge_in_acpi) { 571 /* 572 * device is coldplugged bridge, 573 * add child device descriptions into its scope 574 */ 575 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 576 577 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 578 } 579 /* slot descriptor has been composed, add it into parent context */ 580 aml_append(parent_scope, dev); 581 } 582 583 if (bsel) { 584 aml_append(parent_scope, notify_method); 585 } 586 587 /* Append PCNT method to notify about events on local and child buses. 588 * Add unconditionally for root since DSDT expects it. 589 */ 590 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 591 592 /* If bus supports hotplug select it and notify about local events */ 593 if (bsel) { 594 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 595 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 596 aml_append(method, 597 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 598 ); 599 aml_append(method, 600 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 601 ); 602 } 603 604 /* Notify about child bus events in any case */ 605 if (pcihp_bridge_en) { 606 QLIST_FOREACH(sec, &bus->child, sibling) { 607 int32_t devfn = sec->parent_dev->devfn; 608 609 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 610 } 611 } 612 aml_append(parent_scope, method); 613 qobject_decref(bsel); 614 } 615 616 /** 617 * build_prt_entry: 618 * @link_name: link name for PCI route entry 619 * 620 * build AML package containing a PCI route entry for @link_name 621 */ 622 static Aml *build_prt_entry(const char *link_name) 623 { 624 Aml *a_zero = aml_int(0); 625 Aml *pkg = aml_package(4); 626 aml_append(pkg, a_zero); 627 aml_append(pkg, a_zero); 628 aml_append(pkg, aml_name("%s", link_name)); 629 aml_append(pkg, a_zero); 630 return pkg; 631 } 632 633 /* 634 * initialize_route - Initialize the interrupt routing rule 635 * through a specific LINK: 636 * if (lnk_idx == idx) 637 * route using link 'link_name' 638 */ 639 static Aml *initialize_route(Aml *route, const char *link_name, 640 Aml *lnk_idx, int idx) 641 { 642 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 643 Aml *pkg = build_prt_entry(link_name); 644 645 aml_append(if_ctx, aml_store(pkg, route)); 646 647 return if_ctx; 648 } 649 650 /* 651 * build_prt - Define interrupt rounting rules 652 * 653 * Returns an array of 128 routes, one for each device, 654 * based on device location. 655 * The main goal is to equaly distribute the interrupts 656 * over the 4 existing ACPI links (works only for i440fx). 657 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 658 * 659 */ 660 static Aml *build_prt(bool is_pci0_prt) 661 { 662 Aml *method, *while_ctx, *pin, *res; 663 664 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 665 res = aml_local(0); 666 pin = aml_local(1); 667 aml_append(method, aml_store(aml_package(128), res)); 668 aml_append(method, aml_store(aml_int(0), pin)); 669 670 /* while (pin < 128) */ 671 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 672 { 673 Aml *slot = aml_local(2); 674 Aml *lnk_idx = aml_local(3); 675 Aml *route = aml_local(4); 676 677 /* slot = pin >> 2 */ 678 aml_append(while_ctx, 679 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 680 /* lnk_idx = (slot + pin) & 3 */ 681 aml_append(while_ctx, 682 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 683 lnk_idx)); 684 685 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 686 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 687 if (is_pci0_prt) { 688 Aml *if_device_1, *if_pin_4, *else_pin_4; 689 690 /* device 1 is the power-management device, needs SCI */ 691 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 692 { 693 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 694 { 695 aml_append(if_pin_4, 696 aml_store(build_prt_entry("LNKS"), route)); 697 } 698 aml_append(if_device_1, if_pin_4); 699 else_pin_4 = aml_else(); 700 { 701 aml_append(else_pin_4, 702 aml_store(build_prt_entry("LNKA"), route)); 703 } 704 aml_append(if_device_1, else_pin_4); 705 } 706 aml_append(while_ctx, if_device_1); 707 } else { 708 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 709 } 710 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 711 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 712 713 /* route[0] = 0x[slot]FFFF */ 714 aml_append(while_ctx, 715 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 716 NULL), 717 aml_index(route, aml_int(0)))); 718 /* route[1] = pin & 3 */ 719 aml_append(while_ctx, 720 aml_store(aml_and(pin, aml_int(3), NULL), 721 aml_index(route, aml_int(1)))); 722 /* res[pin] = route */ 723 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 724 /* pin++ */ 725 aml_append(while_ctx, aml_increment(pin)); 726 } 727 aml_append(method, while_ctx); 728 /* return res*/ 729 aml_append(method, aml_return(res)); 730 731 return method; 732 } 733 734 typedef struct CrsRangeEntry { 735 uint64_t base; 736 uint64_t limit; 737 } CrsRangeEntry; 738 739 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 740 { 741 CrsRangeEntry *entry; 742 743 entry = g_malloc(sizeof(*entry)); 744 entry->base = base; 745 entry->limit = limit; 746 747 g_ptr_array_add(ranges, entry); 748 } 749 750 static void crs_range_free(gpointer data) 751 { 752 CrsRangeEntry *entry = (CrsRangeEntry *)data; 753 g_free(entry); 754 } 755 756 static gint crs_range_compare(gconstpointer a, gconstpointer b) 757 { 758 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 759 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 760 761 return (int64_t)entry_a->base - (int64_t)entry_b->base; 762 } 763 764 /* 765 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 766 * interval, computes the 'free' ranges from the same interval. 767 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 768 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 769 */ 770 static void crs_replace_with_free_ranges(GPtrArray *ranges, 771 uint64_t start, uint64_t end) 772 { 773 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free); 774 uint64_t free_base = start; 775 int i; 776 777 g_ptr_array_sort(ranges, crs_range_compare); 778 for (i = 0; i < ranges->len; i++) { 779 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 780 781 if (free_base < used->base) { 782 crs_range_insert(free_ranges, free_base, used->base - 1); 783 } 784 785 free_base = used->limit + 1; 786 } 787 788 if (free_base < end) { 789 crs_range_insert(free_ranges, free_base, end); 790 } 791 792 g_ptr_array_set_size(ranges, 0); 793 for (i = 0; i < free_ranges->len; i++) { 794 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 795 } 796 797 g_ptr_array_free(free_ranges, false); 798 } 799 800 /* 801 * crs_range_merge - merges adjacent ranges in the given array. 802 * Array elements are deleted and replaced with the merged ranges. 803 */ 804 static void crs_range_merge(GPtrArray *range) 805 { 806 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 807 CrsRangeEntry *entry; 808 uint64_t range_base, range_limit; 809 int i; 810 811 if (!range->len) { 812 return; 813 } 814 815 g_ptr_array_sort(range, crs_range_compare); 816 817 entry = g_ptr_array_index(range, 0); 818 range_base = entry->base; 819 range_limit = entry->limit; 820 for (i = 1; i < range->len; i++) { 821 entry = g_ptr_array_index(range, i); 822 if (entry->base - 1 == range_limit) { 823 range_limit = entry->limit; 824 } else { 825 crs_range_insert(tmp, range_base, range_limit); 826 range_base = entry->base; 827 range_limit = entry->limit; 828 } 829 } 830 crs_range_insert(tmp, range_base, range_limit); 831 832 g_ptr_array_set_size(range, 0); 833 for (i = 0; i < tmp->len; i++) { 834 entry = g_ptr_array_index(tmp, i); 835 crs_range_insert(range, entry->base, entry->limit); 836 } 837 g_ptr_array_free(tmp, true); 838 } 839 840 static Aml *build_crs(PCIHostState *host, 841 GPtrArray *io_ranges, GPtrArray *mem_ranges) 842 { 843 Aml *crs = aml_resource_template(); 844 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 845 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 846 CrsRangeEntry *entry; 847 uint8_t max_bus = pci_bus_num(host->bus); 848 uint8_t type; 849 int devfn; 850 int i; 851 852 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 853 uint64_t range_base, range_limit; 854 PCIDevice *dev = host->bus->devices[devfn]; 855 856 if (!dev) { 857 continue; 858 } 859 860 for (i = 0; i < PCI_NUM_REGIONS; i++) { 861 PCIIORegion *r = &dev->io_regions[i]; 862 863 range_base = r->addr; 864 range_limit = r->addr + r->size - 1; 865 866 /* 867 * Work-around for old bioses 868 * that do not support multiple root buses 869 */ 870 if (!range_base || range_base > range_limit) { 871 continue; 872 } 873 874 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 875 crs_range_insert(host_io_ranges, range_base, range_limit); 876 } else { /* "memory" */ 877 crs_range_insert(host_mem_ranges, range_base, range_limit); 878 } 879 } 880 881 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 882 if (type == PCI_HEADER_TYPE_BRIDGE) { 883 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 884 if (subordinate > max_bus) { 885 max_bus = subordinate; 886 } 887 888 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 889 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 890 891 /* 892 * Work-around for old bioses 893 * that do not support multiple root buses 894 */ 895 if (range_base && range_base <= range_limit) { 896 crs_range_insert(host_io_ranges, range_base, range_limit); 897 } 898 899 range_base = 900 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 901 range_limit = 902 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 903 904 /* 905 * Work-around for old bioses 906 * that do not support multiple root buses 907 */ 908 if (range_base && range_base <= range_limit) { 909 crs_range_insert(host_mem_ranges, range_base, range_limit); 910 } 911 912 range_base = 913 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 914 range_limit = 915 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 916 917 /* 918 * Work-around for old bioses 919 * that do not support multiple root buses 920 */ 921 if (range_base && range_base <= range_limit) { 922 crs_range_insert(host_mem_ranges, range_base, range_limit); 923 } 924 } 925 } 926 927 crs_range_merge(host_io_ranges); 928 for (i = 0; i < host_io_ranges->len; i++) { 929 entry = g_ptr_array_index(host_io_ranges, i); 930 aml_append(crs, 931 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 932 AML_POS_DECODE, AML_ENTIRE_RANGE, 933 0, entry->base, entry->limit, 0, 934 entry->limit - entry->base + 1)); 935 crs_range_insert(io_ranges, entry->base, entry->limit); 936 } 937 g_ptr_array_free(host_io_ranges, true); 938 939 crs_range_merge(host_mem_ranges); 940 for (i = 0; i < host_mem_ranges->len; i++) { 941 entry = g_ptr_array_index(host_mem_ranges, i); 942 aml_append(crs, 943 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 944 AML_MAX_FIXED, AML_NON_CACHEABLE, 945 AML_READ_WRITE, 946 0, entry->base, entry->limit, 0, 947 entry->limit - entry->base + 1)); 948 crs_range_insert(mem_ranges, entry->base, entry->limit); 949 } 950 g_ptr_array_free(host_mem_ranges, true); 951 952 aml_append(crs, 953 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 954 0, 955 pci_bus_num(host->bus), 956 max_bus, 957 0, 958 max_bus - pci_bus_num(host->bus) + 1)); 959 960 return crs; 961 } 962 963 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus, 964 AcpiCpuInfo *cpu, AcpiPmInfo *pm) 965 { 966 int i; 967 Aml *dev; 968 Aml *crs; 969 Aml *pkg; 970 Aml *field; 971 Aml *ifctx; 972 Aml *method; 973 974 /* The current AML generator can cover the APIC ID range [0..255], 975 * inclusive, for VCPU hotplug. */ 976 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 977 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 978 979 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 980 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 981 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 982 aml_append(dev, 983 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 984 ); 985 /* device present, functioning, decoding, not shown in UI */ 986 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 987 crs = aml_resource_template(); 988 aml_append(crs, 989 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 990 pm->cpu_hp_io_len) 991 ); 992 aml_append(dev, aml_name_decl("_CRS", crs)); 993 aml_append(sb_scope, dev); 994 /* declare CPU hotplug MMIO region and PRS field to access it */ 995 aml_append(sb_scope, aml_operation_region( 996 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 997 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 998 aml_append(field, aml_named_field("PRS", 256)); 999 aml_append(sb_scope, field); 1000 1001 /* build Processor object for each processor */ 1002 for (i = 0; i < acpi_cpus; i++) { 1003 dev = aml_processor(i, 0, 0, "CP%.02X", i); 1004 1005 method = aml_method("_MAT", 0, AML_NOTSERIALIZED); 1006 aml_append(method, 1007 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i)))); 1008 aml_append(dev, method); 1009 1010 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1011 aml_append(method, 1012 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i)))); 1013 aml_append(dev, method); 1014 1015 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1016 aml_append(method, 1017 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0))) 1018 ); 1019 aml_append(dev, method); 1020 1021 aml_append(sb_scope, dev); 1022 } 1023 1024 /* build this code: 1025 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 1026 */ 1027 /* Arg0 = Processor ID = APIC ID */ 1028 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1029 for (i = 0; i < acpi_cpus; i++) { 1030 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1031 aml_append(ifctx, 1032 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 1033 ); 1034 aml_append(method, ifctx); 1035 } 1036 aml_append(sb_scope, method); 1037 1038 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 1039 * 1040 * Note: The ability to create variable-sized packages was first 1041 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 1042 * ith up to 255 elements. Windows guests up to win2k8 fail when 1043 * VarPackageOp is used. 1044 */ 1045 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 1046 aml_varpackage(acpi_cpus); 1047 1048 for (i = 0; i < acpi_cpus; i++) { 1049 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 1050 aml_append(pkg, aml_int(b)); 1051 } 1052 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); 1053 } 1054 1055 static void build_memory_devices(Aml *sb_scope, int nr_mem, 1056 uint16_t io_base, uint16_t io_len) 1057 { 1058 int i; 1059 Aml *scope; 1060 Aml *crs; 1061 Aml *field; 1062 Aml *dev; 1063 Aml *method; 1064 Aml *ifctx; 1065 1066 /* build memory devices */ 1067 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 1068 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE); 1069 aml_append(scope, 1070 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem)) 1071 ); 1072 1073 crs = aml_resource_template(); 1074 aml_append(crs, 1075 aml_io(AML_DECODE16, io_base, io_base, 0, io_len) 1076 ); 1077 aml_append(scope, aml_name_decl("_CRS", crs)); 1078 1079 aml_append(scope, aml_operation_region( 1080 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO, 1081 io_base, io_len) 1082 ); 1083 1084 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1085 AML_NOLOCK, AML_PRESERVE); 1086 aml_append(field, /* read only */ 1087 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32)); 1088 aml_append(field, /* read only */ 1089 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32)); 1090 aml_append(field, /* read only */ 1091 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32)); 1092 aml_append(field, /* read only */ 1093 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32)); 1094 aml_append(field, /* read only */ 1095 aml_named_field(MEMORY_SLOT_PROXIMITY, 32)); 1096 aml_append(scope, field); 1097 1098 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC, 1099 AML_NOLOCK, AML_WRITE_AS_ZEROS); 1100 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 1101 aml_append(field, /* 1 if enabled, read only */ 1102 aml_named_field(MEMORY_SLOT_ENABLED, 1)); 1103 aml_append(field, 1104 /*(read) 1 if has a insert event. (write) 1 to clear event */ 1105 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1)); 1106 aml_append(field, 1107 /* (read) 1 if has a remove event. (write) 1 to clear event */ 1108 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1)); 1109 aml_append(field, 1110 /* initiates device eject, write only */ 1111 aml_named_field(MEMORY_SLOT_EJECT, 1)); 1112 aml_append(scope, field); 1113 1114 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1115 AML_NOLOCK, AML_PRESERVE); 1116 aml_append(field, /* DIMM selector, write only */ 1117 aml_named_field(MEMORY_SLOT_SLECTOR, 32)); 1118 aml_append(field, /* _OST event code, write only */ 1119 aml_named_field(MEMORY_SLOT_OST_EVENT, 32)); 1120 aml_append(field, /* _OST status code, write only */ 1121 aml_named_field(MEMORY_SLOT_OST_STATUS, 32)); 1122 aml_append(scope, field); 1123 aml_append(sb_scope, scope); 1124 1125 for (i = 0; i < nr_mem; i++) { 1126 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "." 1127 const char *s; 1128 1129 dev = aml_device("MP%02X", i); 1130 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 1131 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 1132 1133 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1134 s = BASEPATH MEMORY_SLOT_CRS_METHOD; 1135 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1136 aml_append(dev, method); 1137 1138 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1139 s = BASEPATH MEMORY_SLOT_STATUS_METHOD; 1140 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1141 aml_append(dev, method); 1142 1143 method = aml_method("_PXM", 0, AML_NOTSERIALIZED); 1144 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD; 1145 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1146 aml_append(dev, method); 1147 1148 method = aml_method("_OST", 3, AML_NOTSERIALIZED); 1149 s = BASEPATH MEMORY_SLOT_OST_METHOD; 1150 1151 aml_append(method, aml_return(aml_call4( 1152 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 1153 ))); 1154 aml_append(dev, method); 1155 1156 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1157 s = BASEPATH MEMORY_SLOT_EJECT_METHOD; 1158 aml_append(method, aml_return(aml_call2( 1159 s, aml_name("_UID"), aml_arg(0)))); 1160 aml_append(dev, method); 1161 1162 aml_append(sb_scope, dev); 1163 } 1164 1165 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 1166 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 1167 */ 1168 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1169 for (i = 0; i < nr_mem; i++) { 1170 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1171 aml_append(ifctx, 1172 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 1173 ); 1174 aml_append(method, ifctx); 1175 } 1176 aml_append(sb_scope, method); 1177 } 1178 1179 static void build_hpet_aml(Aml *table) 1180 { 1181 Aml *crs; 1182 Aml *field; 1183 Aml *method; 1184 Aml *if_ctx; 1185 Aml *scope = aml_scope("_SB"); 1186 Aml *dev = aml_device("HPET"); 1187 Aml *zero = aml_int(0); 1188 Aml *id = aml_local(0); 1189 Aml *period = aml_local(1); 1190 1191 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1192 aml_append(dev, aml_name_decl("_UID", zero)); 1193 1194 aml_append(dev, 1195 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, HPET_BASE, HPET_LEN)); 1196 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1197 aml_append(field, aml_named_field("VEND", 32)); 1198 aml_append(field, aml_named_field("PRD", 32)); 1199 aml_append(dev, field); 1200 1201 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1202 aml_append(method, aml_store(aml_name("VEND"), id)); 1203 aml_append(method, aml_store(aml_name("PRD"), period)); 1204 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1205 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1206 aml_equal(id, aml_int(0xffff)))); 1207 { 1208 aml_append(if_ctx, aml_return(zero)); 1209 } 1210 aml_append(method, if_ctx); 1211 1212 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1213 aml_lgreater(period, aml_int(100000000)))); 1214 { 1215 aml_append(if_ctx, aml_return(zero)); 1216 } 1217 aml_append(method, if_ctx); 1218 1219 aml_append(method, aml_return(aml_int(0x0F))); 1220 aml_append(dev, method); 1221 1222 crs = aml_resource_template(); 1223 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1224 aml_append(dev, aml_name_decl("_CRS", crs)); 1225 1226 aml_append(scope, dev); 1227 aml_append(table, scope); 1228 } 1229 1230 static Aml *build_fdc_device_aml(void) 1231 { 1232 Aml *dev; 1233 Aml *crs; 1234 Aml *method; 1235 Aml *if_ctx; 1236 Aml *else_ctx; 1237 Aml *zero = aml_int(0); 1238 Aml *is_present = aml_local(0); 1239 1240 dev = aml_device("FDC0"); 1241 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1242 1243 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1244 aml_append(method, aml_store(aml_name("FDEN"), is_present)); 1245 if_ctx = aml_if(aml_equal(is_present, zero)); 1246 { 1247 aml_append(if_ctx, aml_return(aml_int(0x00))); 1248 } 1249 aml_append(method, if_ctx); 1250 else_ctx = aml_else(); 1251 { 1252 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1253 } 1254 aml_append(method, else_ctx); 1255 aml_append(dev, method); 1256 1257 crs = aml_resource_template(); 1258 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1259 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1260 aml_append(crs, aml_irq_no_flags(6)); 1261 aml_append(crs, 1262 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1263 aml_append(dev, aml_name_decl("_CRS", crs)); 1264 1265 return dev; 1266 } 1267 1268 static Aml *build_rtc_device_aml(void) 1269 { 1270 Aml *dev; 1271 Aml *crs; 1272 1273 dev = aml_device("RTC"); 1274 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1275 crs = aml_resource_template(); 1276 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1277 aml_append(crs, aml_irq_no_flags(8)); 1278 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1279 aml_append(dev, aml_name_decl("_CRS", crs)); 1280 1281 return dev; 1282 } 1283 1284 static Aml *build_kbd_device_aml(void) 1285 { 1286 Aml *dev; 1287 Aml *crs; 1288 Aml *method; 1289 1290 dev = aml_device("KBD"); 1291 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1292 1293 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1294 aml_append(method, aml_return(aml_int(0x0f))); 1295 aml_append(dev, method); 1296 1297 crs = aml_resource_template(); 1298 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1299 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1300 aml_append(crs, aml_irq_no_flags(1)); 1301 aml_append(dev, aml_name_decl("_CRS", crs)); 1302 1303 return dev; 1304 } 1305 1306 static Aml *build_mouse_device_aml(void) 1307 { 1308 Aml *dev; 1309 Aml *crs; 1310 Aml *method; 1311 1312 dev = aml_device("MOU"); 1313 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1314 1315 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1316 aml_append(method, aml_return(aml_int(0x0f))); 1317 aml_append(dev, method); 1318 1319 crs = aml_resource_template(); 1320 aml_append(crs, aml_irq_no_flags(12)); 1321 aml_append(dev, aml_name_decl("_CRS", crs)); 1322 1323 return dev; 1324 } 1325 1326 static Aml *build_lpt_device_aml(void) 1327 { 1328 Aml *dev; 1329 Aml *crs; 1330 Aml *method; 1331 Aml *if_ctx; 1332 Aml *else_ctx; 1333 Aml *zero = aml_int(0); 1334 Aml *is_present = aml_local(0); 1335 1336 dev = aml_device("LPT"); 1337 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1338 1339 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1340 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1341 if_ctx = aml_if(aml_equal(is_present, zero)); 1342 { 1343 aml_append(if_ctx, aml_return(aml_int(0x00))); 1344 } 1345 aml_append(method, if_ctx); 1346 else_ctx = aml_else(); 1347 { 1348 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1349 } 1350 aml_append(method, else_ctx); 1351 aml_append(dev, method); 1352 1353 crs = aml_resource_template(); 1354 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1355 aml_append(crs, aml_irq_no_flags(7)); 1356 aml_append(dev, aml_name_decl("_CRS", crs)); 1357 1358 return dev; 1359 } 1360 1361 static Aml *build_com_device_aml(uint8_t uid) 1362 { 1363 Aml *dev; 1364 Aml *crs; 1365 Aml *method; 1366 Aml *if_ctx; 1367 Aml *else_ctx; 1368 Aml *zero = aml_int(0); 1369 Aml *is_present = aml_local(0); 1370 const char *enabled_field = "CAEN"; 1371 uint8_t irq = 4; 1372 uint16_t io_port = 0x03F8; 1373 1374 assert(uid == 1 || uid == 2); 1375 if (uid == 2) { 1376 enabled_field = "CBEN"; 1377 irq = 3; 1378 io_port = 0x02F8; 1379 } 1380 1381 dev = aml_device("COM%d", uid); 1382 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1383 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1384 1385 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1386 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1387 if_ctx = aml_if(aml_equal(is_present, zero)); 1388 { 1389 aml_append(if_ctx, aml_return(aml_int(0x00))); 1390 } 1391 aml_append(method, if_ctx); 1392 else_ctx = aml_else(); 1393 { 1394 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1395 } 1396 aml_append(method, else_ctx); 1397 aml_append(dev, method); 1398 1399 crs = aml_resource_template(); 1400 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1401 aml_append(crs, aml_irq_no_flags(irq)); 1402 aml_append(dev, aml_name_decl("_CRS", crs)); 1403 1404 return dev; 1405 } 1406 1407 static void build_isa_devices_aml(Aml *table) 1408 { 1409 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1410 1411 aml_append(scope, build_rtc_device_aml()); 1412 aml_append(scope, build_kbd_device_aml()); 1413 aml_append(scope, build_mouse_device_aml()); 1414 aml_append(scope, build_fdc_device_aml()); 1415 aml_append(scope, build_lpt_device_aml()); 1416 aml_append(scope, build_com_device_aml(1)); 1417 aml_append(scope, build_com_device_aml(2)); 1418 1419 aml_append(table, scope); 1420 } 1421 1422 static void build_dbg_aml(Aml *table) 1423 { 1424 Aml *field; 1425 Aml *method; 1426 Aml *while_ctx; 1427 Aml *scope = aml_scope("\\"); 1428 Aml *buf = aml_local(0); 1429 Aml *len = aml_local(1); 1430 Aml *idx = aml_local(2); 1431 1432 aml_append(scope, 1433 aml_operation_region("DBG", AML_SYSTEM_IO, 0x0402, 0x01)); 1434 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1435 aml_append(field, aml_named_field("DBGB", 8)); 1436 aml_append(scope, field); 1437 1438 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1439 1440 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1441 aml_append(method, aml_to_buffer(buf, buf)); 1442 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1443 aml_append(method, aml_store(aml_int(0), idx)); 1444 1445 while_ctx = aml_while(aml_lless(idx, len)); 1446 aml_append(while_ctx, 1447 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1448 aml_append(while_ctx, aml_increment(idx)); 1449 aml_append(method, while_ctx); 1450 1451 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1452 aml_append(scope, method); 1453 1454 aml_append(table, scope); 1455 } 1456 1457 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1458 { 1459 Aml *dev; 1460 Aml *crs; 1461 Aml *method; 1462 uint32_t irqs[] = {5, 10, 11}; 1463 1464 dev = aml_device("%s", name); 1465 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1466 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1467 1468 crs = aml_resource_template(); 1469 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1470 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1471 aml_append(dev, aml_name_decl("_PRS", crs)); 1472 1473 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1474 aml_append(method, aml_return(aml_call1("IQST", reg))); 1475 aml_append(dev, method); 1476 1477 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1478 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1479 aml_append(dev, method); 1480 1481 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1482 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1483 aml_append(dev, method); 1484 1485 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1486 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1487 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1488 aml_append(dev, method); 1489 1490 return dev; 1491 } 1492 1493 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1494 { 1495 Aml *dev; 1496 Aml *crs; 1497 Aml *method; 1498 uint32_t irqs; 1499 1500 dev = aml_device("%s", name); 1501 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1502 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1503 1504 crs = aml_resource_template(); 1505 irqs = gsi; 1506 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1507 AML_SHARED, &irqs, 1)); 1508 aml_append(dev, aml_name_decl("_PRS", crs)); 1509 1510 aml_append(dev, aml_name_decl("_CRS", crs)); 1511 1512 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1513 aml_append(dev, method); 1514 1515 return dev; 1516 } 1517 1518 /* _CRS method - get current settings */ 1519 static Aml *build_iqcr_method(bool is_piix4) 1520 { 1521 Aml *if_ctx; 1522 uint32_t irqs; 1523 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1524 Aml *crs = aml_resource_template(); 1525 1526 irqs = 0; 1527 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1528 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1529 aml_append(method, aml_name_decl("PRR0", crs)); 1530 1531 aml_append(method, 1532 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1533 1534 if (is_piix4) { 1535 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1536 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1537 aml_append(method, if_ctx); 1538 } else { 1539 aml_append(method, 1540 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1541 aml_name("PRRI"))); 1542 } 1543 1544 aml_append(method, aml_return(aml_name("PRR0"))); 1545 return method; 1546 } 1547 1548 /* _STA method - get status */ 1549 static Aml *build_irq_status_method(void) 1550 { 1551 Aml *if_ctx; 1552 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1553 1554 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1555 aml_append(if_ctx, aml_return(aml_int(0x09))); 1556 aml_append(method, if_ctx); 1557 aml_append(method, aml_return(aml_int(0x0B))); 1558 return method; 1559 } 1560 1561 static void build_piix4_pci0_int(Aml *table) 1562 { 1563 Aml *dev; 1564 Aml *crs; 1565 Aml *field; 1566 Aml *method; 1567 uint32_t irqs; 1568 Aml *sb_scope = aml_scope("_SB"); 1569 Aml *pci0_scope = aml_scope("PCI0"); 1570 1571 aml_append(pci0_scope, build_prt(true)); 1572 aml_append(sb_scope, pci0_scope); 1573 1574 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1575 aml_append(field, aml_named_field("PRQ0", 8)); 1576 aml_append(field, aml_named_field("PRQ1", 8)); 1577 aml_append(field, aml_named_field("PRQ2", 8)); 1578 aml_append(field, aml_named_field("PRQ3", 8)); 1579 aml_append(sb_scope, field); 1580 1581 aml_append(sb_scope, build_irq_status_method()); 1582 aml_append(sb_scope, build_iqcr_method(true)); 1583 1584 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1585 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1586 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1587 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1588 1589 dev = aml_device("LNKS"); 1590 { 1591 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1592 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1593 1594 crs = aml_resource_template(); 1595 irqs = 9; 1596 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1597 AML_ACTIVE_HIGH, AML_SHARED, 1598 &irqs, 1)); 1599 aml_append(dev, aml_name_decl("_PRS", crs)); 1600 1601 /* The SCI cannot be disabled and is always attached to GSI 9, 1602 * so these are no-ops. We only need this link to override the 1603 * polarity to active high and match the content of the MADT. 1604 */ 1605 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1606 aml_append(method, aml_return(aml_int(0x0b))); 1607 aml_append(dev, method); 1608 1609 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1610 aml_append(dev, method); 1611 1612 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1613 aml_append(method, aml_return(aml_name("_PRS"))); 1614 aml_append(dev, method); 1615 1616 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1617 aml_append(dev, method); 1618 } 1619 aml_append(sb_scope, dev); 1620 1621 aml_append(table, sb_scope); 1622 } 1623 1624 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1625 { 1626 int i; 1627 int head; 1628 Aml *pkg; 1629 char base = name[3] < 'E' ? 'A' : 'E'; 1630 char *s = g_strdup(name); 1631 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1632 1633 assert(strlen(s) == 4); 1634 1635 head = name[3] - base; 1636 for (i = 0; i < 4; i++) { 1637 if (head + i > 3) { 1638 head = i * -1; 1639 } 1640 s[3] = base + head + i; 1641 pkg = aml_package(4); 1642 aml_append(pkg, a_nr); 1643 aml_append(pkg, aml_int(i)); 1644 aml_append(pkg, aml_name("%s", s)); 1645 aml_append(pkg, aml_int(0)); 1646 aml_append(ctx, pkg); 1647 } 1648 g_free(s); 1649 } 1650 1651 static Aml *build_q35_routing_table(const char *str) 1652 { 1653 int i; 1654 Aml *pkg; 1655 char *name = g_strdup_printf("%s ", str); 1656 1657 pkg = aml_package(128); 1658 for (i = 0; i < 0x18; i++) { 1659 name[3] = 'E' + (i & 0x3); 1660 append_q35_prt_entry(pkg, i, name); 1661 } 1662 1663 name[3] = 'E'; 1664 append_q35_prt_entry(pkg, 0x18, name); 1665 1666 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1667 for (i = 0x0019; i < 0x1e; i++) { 1668 name[3] = 'A'; 1669 append_q35_prt_entry(pkg, i, name); 1670 } 1671 1672 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1673 name[3] = 'E'; 1674 append_q35_prt_entry(pkg, 0x1e, name); 1675 name[3] = 'A'; 1676 append_q35_prt_entry(pkg, 0x1f, name); 1677 1678 g_free(name); 1679 return pkg; 1680 } 1681 1682 static void build_q35_pci0_int(Aml *table) 1683 { 1684 Aml *field; 1685 Aml *method; 1686 Aml *sb_scope = aml_scope("_SB"); 1687 Aml *pci0_scope = aml_scope("PCI0"); 1688 1689 /* Zero => PIC mode, One => APIC Mode */ 1690 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1691 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1692 { 1693 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1694 } 1695 aml_append(table, method); 1696 1697 aml_append(pci0_scope, 1698 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1699 aml_append(pci0_scope, 1700 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1701 1702 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1703 { 1704 Aml *if_ctx; 1705 Aml *else_ctx; 1706 1707 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1708 section 6.2.8.1 */ 1709 /* Note: we provide the same info as the PCI routing 1710 table of the Bochs BIOS */ 1711 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1712 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1713 aml_append(method, if_ctx); 1714 else_ctx = aml_else(); 1715 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1716 aml_append(method, else_ctx); 1717 } 1718 aml_append(pci0_scope, method); 1719 aml_append(sb_scope, pci0_scope); 1720 1721 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1722 aml_append(field, aml_named_field("PRQA", 8)); 1723 aml_append(field, aml_named_field("PRQB", 8)); 1724 aml_append(field, aml_named_field("PRQC", 8)); 1725 aml_append(field, aml_named_field("PRQD", 8)); 1726 aml_append(field, aml_reserved_field(0x20)); 1727 aml_append(field, aml_named_field("PRQE", 8)); 1728 aml_append(field, aml_named_field("PRQF", 8)); 1729 aml_append(field, aml_named_field("PRQG", 8)); 1730 aml_append(field, aml_named_field("PRQH", 8)); 1731 aml_append(sb_scope, field); 1732 1733 aml_append(sb_scope, build_irq_status_method()); 1734 aml_append(sb_scope, build_iqcr_method(false)); 1735 1736 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1737 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1738 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1739 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1740 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1741 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1742 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1743 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1744 1745 /* 1746 * TODO: UID probably shouldn't be the same for GSIx devices 1747 * but that's how it was in original ASL so keep it for now 1748 */ 1749 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10)); 1750 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11)); 1751 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12)); 1752 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13)); 1753 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14)); 1754 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15)); 1755 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16)); 1756 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17)); 1757 1758 aml_append(table, sb_scope); 1759 } 1760 1761 static void build_q35_isa_bridge(Aml *table) 1762 { 1763 Aml *dev; 1764 Aml *scope; 1765 Aml *field; 1766 1767 scope = aml_scope("_SB.PCI0"); 1768 dev = aml_device("ISA"); 1769 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1770 1771 /* ICH9 PCI to ISA irq remapping */ 1772 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1773 0x60, 0x0C)); 1774 1775 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1776 0x80, 0x02)); 1777 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1778 aml_append(field, aml_named_field("COMA", 3)); 1779 aml_append(field, aml_reserved_field(1)); 1780 aml_append(field, aml_named_field("COMB", 3)); 1781 aml_append(field, aml_reserved_field(1)); 1782 aml_append(field, aml_named_field("LPTD", 2)); 1783 aml_append(field, aml_reserved_field(2)); 1784 aml_append(field, aml_named_field("FDCD", 2)); 1785 aml_append(dev, field); 1786 1787 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1788 0x82, 0x02)); 1789 /* enable bits */ 1790 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1791 aml_append(field, aml_named_field("CAEN", 1)); 1792 aml_append(field, aml_named_field("CBEN", 1)); 1793 aml_append(field, aml_named_field("LPEN", 1)); 1794 aml_append(field, aml_named_field("FDEN", 1)); 1795 aml_append(dev, field); 1796 1797 aml_append(scope, dev); 1798 aml_append(table, scope); 1799 } 1800 1801 static void build_piix4_pm(Aml *table) 1802 { 1803 Aml *dev; 1804 Aml *scope; 1805 1806 scope = aml_scope("_SB.PCI0"); 1807 dev = aml_device("PX13"); 1808 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1809 1810 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1811 0x00, 0xff)); 1812 aml_append(scope, dev); 1813 aml_append(table, scope); 1814 } 1815 1816 static void build_piix4_isa_bridge(Aml *table) 1817 { 1818 Aml *dev; 1819 Aml *scope; 1820 Aml *field; 1821 1822 scope = aml_scope("_SB.PCI0"); 1823 dev = aml_device("ISA"); 1824 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1825 1826 /* PIIX PCI to ISA irq remapping */ 1827 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1828 0x60, 0x04)); 1829 /* enable bits */ 1830 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1831 /* Offset(0x5f),, 7, */ 1832 aml_append(field, aml_reserved_field(0x2f8)); 1833 aml_append(field, aml_reserved_field(7)); 1834 aml_append(field, aml_named_field("LPEN", 1)); 1835 /* Offset(0x67),, 3, */ 1836 aml_append(field, aml_reserved_field(0x38)); 1837 aml_append(field, aml_reserved_field(3)); 1838 aml_append(field, aml_named_field("CAEN", 1)); 1839 aml_append(field, aml_reserved_field(3)); 1840 aml_append(field, aml_named_field("CBEN", 1)); 1841 aml_append(dev, field); 1842 aml_append(dev, aml_name_decl("FDEN", aml_int(1))); 1843 1844 aml_append(scope, dev); 1845 aml_append(table, scope); 1846 } 1847 1848 static void build_piix4_pci_hotplug(Aml *table) 1849 { 1850 Aml *scope; 1851 Aml *field; 1852 Aml *method; 1853 1854 scope = aml_scope("_SB.PCI0"); 1855 1856 aml_append(scope, 1857 aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x08)); 1858 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1859 aml_append(field, aml_named_field("PCIU", 32)); 1860 aml_append(field, aml_named_field("PCID", 32)); 1861 aml_append(scope, field); 1862 1863 aml_append(scope, 1864 aml_operation_region("SEJ", AML_SYSTEM_IO, 0xae08, 0x04)); 1865 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1866 aml_append(field, aml_named_field("B0EJ", 32)); 1867 aml_append(scope, field); 1868 1869 aml_append(scope, 1870 aml_operation_region("BNMR", AML_SYSTEM_IO, 0xae10, 0x04)); 1871 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1872 aml_append(field, aml_named_field("BNUM", 32)); 1873 aml_append(scope, field); 1874 1875 aml_append(scope, aml_mutex("BLCK", 0)); 1876 1877 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1878 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1879 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1880 aml_append(method, 1881 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1882 aml_append(method, aml_release(aml_name("BLCK"))); 1883 aml_append(method, aml_return(aml_int(0))); 1884 aml_append(scope, method); 1885 1886 aml_append(table, scope); 1887 } 1888 1889 static Aml *build_q35_osc_method(void) 1890 { 1891 Aml *if_ctx; 1892 Aml *if_ctx2; 1893 Aml *else_ctx; 1894 Aml *method; 1895 Aml *a_cwd1 = aml_name("CDW1"); 1896 Aml *a_ctrl = aml_name("CTRL"); 1897 1898 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1899 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1900 1901 if_ctx = aml_if(aml_equal( 1902 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1903 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1904 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1905 1906 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 1907 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1908 1909 /* 1910 * Always allow native PME, AER (no dependencies) 1911 * Never allow SHPC (no SHPC controller in this system) 1912 */ 1913 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); 1914 1915 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1916 /* Unknown revision */ 1917 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1918 aml_append(if_ctx, if_ctx2); 1919 1920 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1921 /* Capabilities bits were masked */ 1922 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1923 aml_append(if_ctx, if_ctx2); 1924 1925 /* Update DWORD3 in the buffer */ 1926 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1927 aml_append(method, if_ctx); 1928 1929 else_ctx = aml_else(); 1930 /* Unrecognized UUID */ 1931 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1932 aml_append(method, else_ctx); 1933 1934 aml_append(method, aml_return(aml_arg(3))); 1935 return method; 1936 } 1937 1938 static void 1939 build_ssdt(GArray *table_data, GArray *linker, 1940 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 1941 PcPciInfo *pci, PcGuestInfo *guest_info) 1942 { 1943 MachineState *machine = MACHINE(qdev_get_machine()); 1944 uint32_t nr_mem = machine->ram_slots; 1945 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field; 1946 PCIBus *bus = NULL; 1947 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1948 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1949 CrsRangeEntry *entry; 1950 int root_bus_limit = 0xFF; 1951 int i; 1952 1953 ssdt = init_aml_allocator(); 1954 1955 /* Reserve space for header */ 1956 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 1957 1958 bus = PC_MACHINE(machine)->bus; 1959 if (bus) { 1960 QLIST_FOREACH(bus, &bus->child, sibling) { 1961 uint8_t bus_num = pci_bus_num(bus); 1962 uint8_t numa_node = pci_bus_numa_node(bus); 1963 1964 /* look only for expander root buses */ 1965 if (!pci_bus_is_root(bus)) { 1966 continue; 1967 } 1968 1969 if (bus_num < root_bus_limit) { 1970 root_bus_limit = bus_num - 1; 1971 } 1972 1973 scope = aml_scope("\\_SB"); 1974 dev = aml_device("PC%.02X", bus_num); 1975 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1976 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1977 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1978 1979 if (numa_node != NUMA_NODE_UNASSIGNED) { 1980 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1981 } 1982 1983 aml_append(dev, build_prt(false)); 1984 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), 1985 io_ranges, mem_ranges); 1986 aml_append(dev, aml_name_decl("_CRS", crs)); 1987 aml_append(scope, dev); 1988 aml_append(ssdt, scope); 1989 } 1990 } 1991 1992 scope = aml_scope("\\_SB.PCI0"); 1993 /* build PCI0._CRS */ 1994 crs = aml_resource_template(); 1995 aml_append(crs, 1996 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1997 0x0000, 0x0, root_bus_limit, 1998 0x0000, root_bus_limit + 1)); 1999 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 2000 2001 aml_append(crs, 2002 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2003 AML_POS_DECODE, AML_ENTIRE_RANGE, 2004 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 2005 2006 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF); 2007 for (i = 0; i < io_ranges->len; i++) { 2008 entry = g_ptr_array_index(io_ranges, i); 2009 aml_append(crs, 2010 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2011 AML_POS_DECODE, AML_ENTIRE_RANGE, 2012 0x0000, entry->base, entry->limit, 2013 0x0000, entry->limit - entry->base + 1)); 2014 } 2015 2016 aml_append(crs, 2017 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2018 AML_CACHEABLE, AML_READ_WRITE, 2019 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2020 2021 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1); 2022 for (i = 0; i < mem_ranges->len; i++) { 2023 entry = g_ptr_array_index(mem_ranges, i); 2024 aml_append(crs, 2025 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2026 AML_NON_CACHEABLE, AML_READ_WRITE, 2027 0, entry->base, entry->limit, 2028 0, entry->limit - entry->base + 1)); 2029 } 2030 2031 if (pci->w64.begin) { 2032 aml_append(crs, 2033 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2034 AML_CACHEABLE, AML_READ_WRITE, 2035 0, pci->w64.begin, pci->w64.end - 1, 0, 2036 pci->w64.end - pci->w64.begin)); 2037 } 2038 aml_append(scope, aml_name_decl("_CRS", crs)); 2039 2040 /* reserve GPE0 block resources */ 2041 dev = aml_device("GPE0"); 2042 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2043 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2044 /* device present, functioning, decoding, not shown in UI */ 2045 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2046 crs = aml_resource_template(); 2047 aml_append(crs, 2048 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 2049 ); 2050 aml_append(dev, aml_name_decl("_CRS", crs)); 2051 aml_append(scope, dev); 2052 2053 g_ptr_array_free(io_ranges, true); 2054 g_ptr_array_free(mem_ranges, true); 2055 2056 /* reserve PCIHP resources */ 2057 if (pm->pcihp_io_len) { 2058 dev = aml_device("PHPR"); 2059 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2060 aml_append(dev, 2061 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2062 /* device present, functioning, decoding, not shown in UI */ 2063 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2064 crs = aml_resource_template(); 2065 aml_append(crs, 2066 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2067 pm->pcihp_io_len) 2068 ); 2069 aml_append(dev, aml_name_decl("_CRS", crs)); 2070 aml_append(scope, dev); 2071 } 2072 aml_append(ssdt, scope); 2073 2074 /* create S3_ / S4_ / S5_ packages if necessary */ 2075 scope = aml_scope("\\"); 2076 if (!pm->s3_disabled) { 2077 pkg = aml_package(4); 2078 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2079 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2080 aml_append(pkg, aml_int(0)); /* reserved */ 2081 aml_append(pkg, aml_int(0)); /* reserved */ 2082 aml_append(scope, aml_name_decl("_S3", pkg)); 2083 } 2084 2085 if (!pm->s4_disabled) { 2086 pkg = aml_package(4); 2087 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2088 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2089 aml_append(pkg, aml_int(pm->s4_val)); 2090 aml_append(pkg, aml_int(0)); /* reserved */ 2091 aml_append(pkg, aml_int(0)); /* reserved */ 2092 aml_append(scope, aml_name_decl("_S4", pkg)); 2093 } 2094 2095 pkg = aml_package(4); 2096 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2097 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2098 aml_append(pkg, aml_int(0)); /* reserved */ 2099 aml_append(pkg, aml_int(0)); /* reserved */ 2100 aml_append(scope, aml_name_decl("_S5", pkg)); 2101 aml_append(ssdt, scope); 2102 2103 if (misc->applesmc_io_base) { 2104 scope = aml_scope("\\_SB.PCI0.ISA"); 2105 dev = aml_device("SMC"); 2106 2107 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2108 /* device present, functioning, decoding, not shown in UI */ 2109 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2110 2111 crs = aml_resource_template(); 2112 aml_append(crs, 2113 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2114 0x01, APPLESMC_MAX_DATA_LENGTH) 2115 ); 2116 aml_append(crs, aml_irq_no_flags(6)); 2117 aml_append(dev, aml_name_decl("_CRS", crs)); 2118 2119 aml_append(scope, dev); 2120 aml_append(ssdt, scope); 2121 } 2122 2123 if (misc->pvpanic_port) { 2124 scope = aml_scope("\\_SB.PCI0.ISA"); 2125 2126 dev = aml_device("PEVT"); 2127 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2128 2129 crs = aml_resource_template(); 2130 aml_append(crs, 2131 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2132 ); 2133 aml_append(dev, aml_name_decl("_CRS", crs)); 2134 2135 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2136 misc->pvpanic_port, 1)); 2137 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2138 aml_append(field, aml_named_field("PEPT", 8)); 2139 aml_append(dev, field); 2140 2141 /* device present, functioning, decoding, shown in UI */ 2142 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2143 2144 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2145 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2146 aml_append(method, aml_return(aml_local(0))); 2147 aml_append(dev, method); 2148 2149 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2150 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2151 aml_append(dev, method); 2152 2153 aml_append(scope, dev); 2154 aml_append(ssdt, scope); 2155 } 2156 2157 sb_scope = aml_scope("\\_SB"); 2158 { 2159 build_processor_devices(sb_scope, guest_info->apic_id_limit, cpu, pm); 2160 2161 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base, 2162 pm->mem_hp_io_len); 2163 2164 { 2165 Object *pci_host; 2166 PCIBus *bus = NULL; 2167 2168 pci_host = acpi_get_i386_pci_host(); 2169 if (pci_host) { 2170 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2171 } 2172 2173 if (bus) { 2174 Aml *scope = aml_scope("PCI0"); 2175 /* Scan all PCI buses. Generate tables to support hotplug. */ 2176 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2177 2178 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2179 dev = aml_device("ISA.TPM"); 2180 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2181 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2182 crs = aml_resource_template(); 2183 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2184 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2185 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); 2186 aml_append(dev, aml_name_decl("_CRS", crs)); 2187 aml_append(scope, dev); 2188 } 2189 2190 aml_append(sb_scope, scope); 2191 } 2192 } 2193 aml_append(ssdt, sb_scope); 2194 } 2195 2196 /* copy AML table into ACPI tables blob and patch header there */ 2197 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 2198 build_header(linker, table_data, 2199 (void *)(table_data->data + table_data->len - ssdt->buf->len), 2200 "SSDT", ssdt->buf->len, 1, NULL); 2201 free_aml_allocator(); 2202 } 2203 2204 static void 2205 build_hpet(GArray *table_data, GArray *linker) 2206 { 2207 Acpi20Hpet *hpet; 2208 2209 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2210 /* Note timer_block_id value must be kept in sync with value advertised by 2211 * emulated hpet 2212 */ 2213 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2214 hpet->addr.address = cpu_to_le64(HPET_BASE); 2215 build_header(linker, table_data, 2216 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL); 2217 } 2218 2219 static void 2220 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 2221 { 2222 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2223 uint64_t log_area_start_address = acpi_data_len(tcpalog); 2224 2225 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2226 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2227 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 2228 2229 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 2230 false /* high memory */); 2231 2232 /* log area start address to be filled by Guest linker */ 2233 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2234 ACPI_BUILD_TPMLOG_FILE, 2235 table_data, &tcpa->log_area_start_address, 2236 sizeof(tcpa->log_area_start_address)); 2237 2238 build_header(linker, table_data, 2239 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL); 2240 2241 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 2242 } 2243 2244 static void 2245 build_tpm2(GArray *table_data, GArray *linker) 2246 { 2247 Acpi20TPM2 *tpm2_ptr; 2248 2249 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2250 2251 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2252 tpm2_ptr->control_area_address = cpu_to_le64(0); 2253 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2254 2255 build_header(linker, table_data, 2256 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL); 2257 } 2258 2259 typedef enum { 2260 MEM_AFFINITY_NOFLAGS = 0, 2261 MEM_AFFINITY_ENABLED = (1 << 0), 2262 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 2263 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 2264 } MemoryAffinityFlags; 2265 2266 static void 2267 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 2268 uint64_t len, int node, MemoryAffinityFlags flags) 2269 { 2270 numamem->type = ACPI_SRAT_MEMORY; 2271 numamem->length = sizeof(*numamem); 2272 memset(numamem->proximity, 0, 4); 2273 numamem->proximity[0] = node; 2274 numamem->flags = cpu_to_le32(flags); 2275 numamem->base_addr = cpu_to_le64(base); 2276 numamem->range_length = cpu_to_le64(len); 2277 } 2278 2279 static void 2280 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 2281 { 2282 AcpiSystemResourceAffinityTable *srat; 2283 AcpiSratProcessorAffinity *core; 2284 AcpiSratMemoryAffinity *numamem; 2285 2286 int i; 2287 uint64_t curnode; 2288 int srat_start, numa_start, slots; 2289 uint64_t mem_len, mem_base, next_base; 2290 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2291 ram_addr_t hotplugabble_address_space_size = 2292 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2293 NULL); 2294 2295 srat_start = table_data->len; 2296 2297 srat = acpi_data_push(table_data, sizeof *srat); 2298 srat->reserved1 = cpu_to_le32(1); 2299 core = (void *)(srat + 1); 2300 2301 for (i = 0; i < guest_info->apic_id_limit; ++i) { 2302 core = acpi_data_push(table_data, sizeof *core); 2303 core->type = ACPI_SRAT_PROCESSOR; 2304 core->length = sizeof(*core); 2305 core->local_apic_id = i; 2306 curnode = guest_info->node_cpu[i]; 2307 core->proximity_lo = curnode; 2308 memset(core->proximity_hi, 0, 3); 2309 core->local_sapic_eid = 0; 2310 core->flags = cpu_to_le32(1); 2311 } 2312 2313 2314 /* the memory map is a bit tricky, it contains at least one hole 2315 * from 640k-1M and possibly another one from 3.5G-4G. 2316 */ 2317 next_base = 0; 2318 numa_start = table_data->len; 2319 2320 numamem = acpi_data_push(table_data, sizeof *numamem); 2321 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 2322 next_base = 1024 * 1024; 2323 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 2324 mem_base = next_base; 2325 mem_len = guest_info->node_mem[i - 1]; 2326 if (i == 1) { 2327 mem_len -= 1024 * 1024; 2328 } 2329 next_base = mem_base + mem_len; 2330 2331 /* Cut out the ACPI_PCI hole */ 2332 if (mem_base <= guest_info->ram_size_below_4g && 2333 next_base > guest_info->ram_size_below_4g) { 2334 mem_len -= next_base - guest_info->ram_size_below_4g; 2335 if (mem_len > 0) { 2336 numamem = acpi_data_push(table_data, sizeof *numamem); 2337 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2338 MEM_AFFINITY_ENABLED); 2339 } 2340 mem_base = 1ULL << 32; 2341 mem_len = next_base - guest_info->ram_size_below_4g; 2342 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 2343 } 2344 numamem = acpi_data_push(table_data, sizeof *numamem); 2345 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2346 MEM_AFFINITY_ENABLED); 2347 } 2348 slots = (table_data->len - numa_start) / sizeof *numamem; 2349 for (; slots < guest_info->numa_nodes + 2; slots++) { 2350 numamem = acpi_data_push(table_data, sizeof *numamem); 2351 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2352 } 2353 2354 /* 2355 * Entry is required for Windows to enable memory hotplug in OS. 2356 * Memory devices may override proximity set by this entry, 2357 * providing _PXM method if necessary. 2358 */ 2359 if (hotplugabble_address_space_size) { 2360 numamem = acpi_data_push(table_data, sizeof *numamem); 2361 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base, 2362 hotplugabble_address_space_size, 0, 2363 MEM_AFFINITY_HOTPLUGGABLE | 2364 MEM_AFFINITY_ENABLED); 2365 } 2366 2367 build_header(linker, table_data, 2368 (void *)(table_data->data + srat_start), 2369 "SRAT", 2370 table_data->len - srat_start, 1, NULL); 2371 } 2372 2373 static void 2374 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 2375 { 2376 AcpiTableMcfg *mcfg; 2377 const char *sig; 2378 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2379 2380 mcfg = acpi_data_push(table_data, len); 2381 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2382 /* Only a single allocation so no need to play with segments */ 2383 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2384 mcfg->allocation[0].start_bus_number = 0; 2385 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2386 2387 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2388 * To avoid table size changes (which create migration issues), 2389 * always create the table even if there are no allocations, 2390 * but set the signature to a reserved value in this case. 2391 * ACPI spec requires OSPMs to ignore such tables. 2392 */ 2393 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2394 /* Reserved signature: ignored by OSPM */ 2395 sig = "QEMU"; 2396 } else { 2397 sig = "MCFG"; 2398 } 2399 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL); 2400 } 2401 2402 static void 2403 build_dmar_q35(GArray *table_data, GArray *linker) 2404 { 2405 int dmar_start = table_data->len; 2406 2407 AcpiTableDmar *dmar; 2408 AcpiDmarHardwareUnit *drhd; 2409 2410 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2411 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 2412 dmar->flags = 0; /* No intr_remap for now */ 2413 2414 /* DMAR Remapping Hardware Unit Definition structure */ 2415 drhd = acpi_data_push(table_data, sizeof(*drhd)); 2416 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2417 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 2418 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2419 drhd->pci_segment = cpu_to_le16(0); 2420 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2421 2422 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2423 "DMAR", table_data->len - dmar_start, 1, NULL); 2424 } 2425 2426 static void 2427 build_dsdt(GArray *table_data, GArray *linker, 2428 AcpiPmInfo *pm, AcpiMiscInfo *misc) 2429 { 2430 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field; 2431 MachineState *machine = MACHINE(qdev_get_machine()); 2432 uint32_t nr_mem = machine->ram_slots; 2433 2434 dsdt = init_aml_allocator(); 2435 2436 /* Reserve space for header */ 2437 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 2438 2439 build_dbg_aml(dsdt); 2440 if (misc->is_piix4) { 2441 sb_scope = aml_scope("_SB"); 2442 dev = aml_device("PCI0"); 2443 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2444 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2445 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2446 aml_append(sb_scope, dev); 2447 aml_append(dsdt, sb_scope); 2448 2449 build_hpet_aml(dsdt); 2450 build_piix4_pm(dsdt); 2451 build_piix4_isa_bridge(dsdt); 2452 build_isa_devices_aml(dsdt); 2453 build_piix4_pci_hotplug(dsdt); 2454 build_piix4_pci0_int(dsdt); 2455 } else { 2456 sb_scope = aml_scope("_SB"); 2457 aml_append(sb_scope, 2458 aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x0c)); 2459 aml_append(sb_scope, 2460 aml_operation_region("PCSB", AML_SYSTEM_IO, 0xae0c, 0x01)); 2461 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 2462 aml_append(field, aml_named_field("PCIB", 8)); 2463 aml_append(sb_scope, field); 2464 aml_append(dsdt, sb_scope); 2465 2466 sb_scope = aml_scope("_SB"); 2467 dev = aml_device("PCI0"); 2468 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 2469 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 2470 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2471 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2472 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 2473 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 2474 aml_append(dev, build_q35_osc_method()); 2475 aml_append(sb_scope, dev); 2476 aml_append(dsdt, sb_scope); 2477 2478 build_hpet_aml(dsdt); 2479 build_q35_isa_bridge(dsdt); 2480 build_isa_devices_aml(dsdt); 2481 build_q35_pci0_int(dsdt); 2482 } 2483 2484 build_cpu_hotplug_aml(dsdt); 2485 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base, 2486 pm->mem_hp_io_len); 2487 2488 scope = aml_scope("_GPE"); 2489 { 2490 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 2491 2492 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED)); 2493 2494 if (misc->is_piix4) { 2495 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 2496 aml_append(method, 2497 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 2498 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 2499 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 2500 aml_append(scope, method); 2501 } else { 2502 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED)); 2503 } 2504 2505 method = aml_method("_E02", 0, AML_NOTSERIALIZED); 2506 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); 2507 aml_append(scope, method); 2508 2509 method = aml_method("_E03", 0, AML_NOTSERIALIZED); 2510 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH)); 2511 aml_append(scope, method); 2512 2513 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED)); 2514 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED)); 2515 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED)); 2516 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED)); 2517 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED)); 2518 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED)); 2519 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED)); 2520 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED)); 2521 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED)); 2522 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED)); 2523 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED)); 2524 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED)); 2525 } 2526 aml_append(dsdt, scope); 2527 2528 /* copy AML table into ACPI tables blob and patch header there */ 2529 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2530 build_header(linker, table_data, 2531 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2532 "DSDT", dsdt->buf->len, 1, NULL); 2533 free_aml_allocator(); 2534 } 2535 2536 static GArray * 2537 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 2538 { 2539 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2540 2541 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 2542 true /* fseg memory */); 2543 2544 memcpy(&rsdp->signature, "RSD PTR ", 8); 2545 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2546 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 2547 /* Address to be filled by Guest linker */ 2548 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 2549 ACPI_BUILD_TABLE_FILE, 2550 rsdp_table, &rsdp->rsdt_physical_address, 2551 sizeof rsdp->rsdt_physical_address); 2552 rsdp->checksum = 0; 2553 /* Checksum to be filled by Guest linker */ 2554 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2555 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 2556 2557 return rsdp_table; 2558 } 2559 2560 typedef 2561 struct AcpiBuildState { 2562 /* Copy of table in RAM (for patching). */ 2563 MemoryRegion *table_mr; 2564 /* Is table patched? */ 2565 uint8_t patched; 2566 PcGuestInfo *guest_info; 2567 void *rsdp; 2568 MemoryRegion *rsdp_mr; 2569 MemoryRegion *linker_mr; 2570 } AcpiBuildState; 2571 2572 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2573 { 2574 Object *pci_host; 2575 QObject *o; 2576 2577 pci_host = acpi_get_i386_pci_host(); 2578 g_assert(pci_host); 2579 2580 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2581 if (!o) { 2582 return false; 2583 } 2584 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 2585 qobject_decref(o); 2586 2587 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2588 assert(o); 2589 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 2590 qobject_decref(o); 2591 return true; 2592 } 2593 2594 static bool acpi_has_iommu(void) 2595 { 2596 bool ambiguous; 2597 Object *intel_iommu; 2598 2599 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 2600 &ambiguous); 2601 return intel_iommu && !ambiguous; 2602 } 2603 2604 static bool acpi_has_nvdimm(void) 2605 { 2606 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2607 2608 return pcms->nvdimm; 2609 } 2610 2611 static 2612 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 2613 { 2614 GArray *table_offsets; 2615 unsigned facs, ssdt, dsdt, rsdt; 2616 AcpiCpuInfo cpu; 2617 AcpiPmInfo pm; 2618 AcpiMiscInfo misc; 2619 AcpiMcfgInfo mcfg; 2620 PcPciInfo pci; 2621 uint8_t *u; 2622 size_t aml_len = 0; 2623 GArray *tables_blob = tables->table_data; 2624 2625 acpi_get_cpu_info(&cpu); 2626 acpi_get_pm_info(&pm); 2627 acpi_get_misc_info(&misc); 2628 acpi_get_pci_info(&pci); 2629 2630 table_offsets = g_array_new(false, true /* clear */, 2631 sizeof(uint32_t)); 2632 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2633 2634 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 2635 64 /* Ensure FACS is aligned */, 2636 false /* high memory */); 2637 2638 /* 2639 * FACS is pointed to by FADT. 2640 * We place it first since it's the only table that has alignment 2641 * requirements. 2642 */ 2643 facs = tables_blob->len; 2644 build_facs(tables_blob, tables->linker, guest_info); 2645 2646 /* DSDT is pointed to by FADT */ 2647 dsdt = tables_blob->len; 2648 build_dsdt(tables_blob, tables->linker, &pm, &misc); 2649 2650 /* Count the size of the DSDT and SSDT, we will need it for legacy 2651 * sizing of ACPI tables. 2652 */ 2653 aml_len += tables_blob->len - dsdt; 2654 2655 /* ACPI tables pointed to by RSDT */ 2656 acpi_add_table(table_offsets, tables_blob); 2657 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 2658 2659 ssdt = tables_blob->len; 2660 acpi_add_table(table_offsets, tables_blob); 2661 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 2662 guest_info); 2663 aml_len += tables_blob->len - ssdt; 2664 2665 acpi_add_table(table_offsets, tables_blob); 2666 build_madt(tables_blob, tables->linker, &cpu, guest_info); 2667 2668 if (misc.has_hpet) { 2669 acpi_add_table(table_offsets, tables_blob); 2670 build_hpet(tables_blob, tables->linker); 2671 } 2672 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2673 acpi_add_table(table_offsets, tables_blob); 2674 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2675 2676 if (misc.tpm_version == TPM_VERSION_2_0) { 2677 acpi_add_table(table_offsets, tables_blob); 2678 build_tpm2(tables_blob, tables->linker); 2679 } 2680 } 2681 if (guest_info->numa_nodes) { 2682 acpi_add_table(table_offsets, tables_blob); 2683 build_srat(tables_blob, tables->linker, guest_info); 2684 } 2685 if (acpi_get_mcfg(&mcfg)) { 2686 acpi_add_table(table_offsets, tables_blob); 2687 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2688 } 2689 if (acpi_has_iommu()) { 2690 acpi_add_table(table_offsets, tables_blob); 2691 build_dmar_q35(tables_blob, tables->linker); 2692 } 2693 2694 if (acpi_has_nvdimm()) { 2695 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); 2696 } 2697 2698 /* Add tables supplied by user (if any) */ 2699 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2700 unsigned len = acpi_table_len(u); 2701 2702 acpi_add_table(table_offsets, tables_blob); 2703 g_array_append_vals(tables_blob, u, len); 2704 } 2705 2706 /* RSDT is pointed to by RSDP */ 2707 rsdt = tables_blob->len; 2708 build_rsdt(tables_blob, tables->linker, table_offsets); 2709 2710 /* RSDP is in FSEG memory, so allocate it separately */ 2711 build_rsdp(tables->rsdp, tables->linker, rsdt); 2712 2713 /* We'll expose it all to Guest so we want to reduce 2714 * chance of size changes. 2715 * 2716 * We used to align the tables to 4k, but of course this would 2717 * too simple to be enough. 4k turned out to be too small an 2718 * alignment very soon, and in fact it is almost impossible to 2719 * keep the table size stable for all (max_cpus, max_memory_slots) 2720 * combinations. So the table size is always 64k for pc-i440fx-2.1 2721 * and we give an error if the table grows beyond that limit. 2722 * 2723 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2724 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2725 * than 2.0 and we can always pad the smaller tables with zeros. We can 2726 * then use the exact size of the 2.0 tables. 2727 * 2728 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2729 */ 2730 if (guest_info->legacy_acpi_table_size) { 2731 /* Subtracting aml_len gives the size of fixed tables. Then add the 2732 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2733 */ 2734 int legacy_aml_len = 2735 guest_info->legacy_acpi_table_size + 2736 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 2737 int legacy_table_size = 2738 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2739 ACPI_BUILD_ALIGN_SIZE); 2740 if (tables_blob->len > legacy_table_size) { 2741 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2742 error_report("Warning: migration may not work."); 2743 } 2744 g_array_set_size(tables_blob, legacy_table_size); 2745 } else { 2746 /* Make sure we have a buffer in case we need to resize the tables. */ 2747 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2748 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2749 error_report("Warning: ACPI tables are larger than 64k."); 2750 error_report("Warning: migration may not work."); 2751 error_report("Warning: please remove CPUs, NUMA nodes, " 2752 "memory slots or PCI bridges."); 2753 } 2754 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2755 } 2756 2757 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 2758 2759 /* Cleanup memory that's no longer used. */ 2760 g_array_free(table_offsets, true); 2761 } 2762 2763 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2764 { 2765 uint32_t size = acpi_data_len(data); 2766 2767 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2768 memory_region_ram_resize(mr, size, &error_abort); 2769 2770 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2771 memory_region_set_dirty(mr, 0, size); 2772 } 2773 2774 static void acpi_build_update(void *build_opaque) 2775 { 2776 AcpiBuildState *build_state = build_opaque; 2777 AcpiBuildTables tables; 2778 2779 /* No state to update or already patched? Nothing to do. */ 2780 if (!build_state || build_state->patched) { 2781 return; 2782 } 2783 build_state->patched = 1; 2784 2785 acpi_build_tables_init(&tables); 2786 2787 acpi_build(build_state->guest_info, &tables); 2788 2789 acpi_ram_update(build_state->table_mr, tables.table_data); 2790 2791 if (build_state->rsdp) { 2792 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2793 } else { 2794 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2795 } 2796 2797 acpi_ram_update(build_state->linker_mr, tables.linker); 2798 acpi_build_tables_cleanup(&tables, true); 2799 } 2800 2801 static void acpi_build_reset(void *build_opaque) 2802 { 2803 AcpiBuildState *build_state = build_opaque; 2804 build_state->patched = 0; 2805 } 2806 2807 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2808 GArray *blob, const char *name, 2809 uint64_t max_size) 2810 { 2811 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2812 name, acpi_build_update, build_state); 2813 } 2814 2815 static const VMStateDescription vmstate_acpi_build = { 2816 .name = "acpi_build", 2817 .version_id = 1, 2818 .minimum_version_id = 1, 2819 .fields = (VMStateField[]) { 2820 VMSTATE_UINT8(patched, AcpiBuildState), 2821 VMSTATE_END_OF_LIST() 2822 }, 2823 }; 2824 2825 void acpi_setup(PcGuestInfo *guest_info) 2826 { 2827 AcpiBuildTables tables; 2828 AcpiBuildState *build_state; 2829 2830 if (!guest_info->fw_cfg) { 2831 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2832 return; 2833 } 2834 2835 if (!guest_info->has_acpi_build) { 2836 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2837 return; 2838 } 2839 2840 if (!acpi_enabled) { 2841 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2842 return; 2843 } 2844 2845 build_state = g_malloc0(sizeof *build_state); 2846 2847 build_state->guest_info = guest_info; 2848 2849 acpi_set_pci_info(); 2850 2851 acpi_build_tables_init(&tables); 2852 acpi_build(build_state->guest_info, &tables); 2853 2854 /* Now expose it all to Guest */ 2855 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2856 ACPI_BUILD_TABLE_FILE, 2857 ACPI_BUILD_TABLE_MAX_SIZE); 2858 assert(build_state->table_mr != NULL); 2859 2860 build_state->linker_mr = 2861 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 2862 2863 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2864 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2865 2866 if (!guest_info->rsdp_in_ram) { 2867 /* 2868 * Keep for compatibility with old machine types. 2869 * Though RSDP is small, its contents isn't immutable, so 2870 * we'll update it along with the rest of tables on guest access. 2871 */ 2872 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2873 2874 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2875 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 2876 acpi_build_update, build_state, 2877 build_state->rsdp, rsdp_size); 2878 build_state->rsdp_mr = NULL; 2879 } else { 2880 build_state->rsdp = NULL; 2881 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2882 ACPI_BUILD_RSDP_FILE, 0); 2883 } 2884 2885 qemu_register_reset(acpi_build_reset, build_state); 2886 acpi_build_reset(build_state); 2887 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2888 2889 /* Cleanup tables but don't free the memory: we track it 2890 * in build_state. 2891 */ 2892 acpi_build_tables_cleanup(&tables, false); 2893 } 2894