1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 69 #include "qom/qom-qobject.h" 70 #include "hw/i386/amd_iommu.h" 71 #include "hw/i386/intel_iommu.h" 72 73 #include "hw/acpi/ipmi.h" 74 #include "hw/acpi/hmat.h" 75 76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 78 * a little bit, there should be plenty of free space since the DSDT 79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 80 */ 81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 82 #define ACPI_BUILD_ALIGN_SIZE 0x1000 83 84 #define ACPI_BUILD_TABLE_SIZE 0x20000 85 86 /* #define DEBUG_ACPI_BUILD */ 87 #ifdef DEBUG_ACPI_BUILD 88 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 90 #else 91 #define ACPI_BUILD_DPRINTF(fmt, ...) 92 #endif 93 94 typedef struct AcpiPmInfo { 95 bool s3_disabled; 96 bool s4_disabled; 97 bool pcihp_bridge_en; 98 bool smi_on_cpuhp; 99 bool smi_on_cpu_unplug; 100 bool pcihp_root_en; 101 uint8_t s4_val; 102 AcpiFadtData fadt; 103 uint16_t cpu_hp_io_base; 104 uint16_t pcihp_io_base; 105 uint16_t pcihp_io_len; 106 } AcpiPmInfo; 107 108 typedef struct AcpiMiscInfo { 109 bool is_piix4; 110 bool has_hpet; 111 TPMVersion tpm_version; 112 const unsigned char *dsdt_code; 113 unsigned dsdt_size; 114 uint16_t pvpanic_port; 115 uint16_t applesmc_io_base; 116 } AcpiMiscInfo; 117 118 typedef struct AcpiBuildPciBusHotplugState { 119 GArray *device_table; 120 GArray *notify_table; 121 struct AcpiBuildPciBusHotplugState *parent; 122 bool pcihp_bridge_en; 123 } AcpiBuildPciBusHotplugState; 124 125 typedef struct FwCfgTPMConfig { 126 uint32_t tpmppi_address; 127 uint8_t tpm_version; 128 uint8_t tpmppi_version; 129 } QEMU_PACKED FwCfgTPMConfig; 130 131 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 132 133 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 134 .space_id = AML_AS_SYSTEM_IO, 135 .address = NVDIMM_ACPI_IO_BASE, 136 .bit_width = NVDIMM_ACPI_IO_LEN << 3 137 }; 138 139 static void init_common_fadt_data(MachineState *ms, Object *o, 140 AcpiFadtData *data) 141 { 142 X86MachineState *x86ms = X86_MACHINE(ms); 143 /* 144 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 145 * behavior for compatibility irrelevant to smm_enabled, which doesn't 146 * comforms to ACPI spec. 147 */ 148 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 149 true : x86_machine_is_smm_enabled(x86ms); 150 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 151 AmlAddressSpace as = AML_AS_SYSTEM_IO; 152 AcpiFadtData fadt = { 153 .rev = 3, 154 .flags = 155 (1 << ACPI_FADT_F_WBINVD) | 156 (1 << ACPI_FADT_F_PROC_C1) | 157 (1 << ACPI_FADT_F_SLP_BUTTON) | 158 (1 << ACPI_FADT_F_RTC_S4) | 159 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 160 /* APIC destination mode ("Flat Logical") has an upper limit of 8 161 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 162 * used 163 */ 164 ((ms->smp.max_cpus > 8) ? 165 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 166 .int_model = 1 /* Multiple APIC */, 167 .rtc_century = RTC_CENTURY, 168 .plvl2_lat = 0xfff /* C2 state not supported */, 169 .plvl3_lat = 0xfff /* C3 state not supported */, 170 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 171 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 172 .acpi_enable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 175 0, 176 .acpi_disable_cmd = 177 smm_enabled ? 178 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 179 0, 180 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 181 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 182 .address = io + 0x04 }, 183 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 184 .gpe0_blk = { .space_id = as, .bit_width = 185 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 186 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 187 }, 188 }; 189 *data = fadt; 190 } 191 192 static Object *object_resolve_type_unambiguous(const char *typename) 193 { 194 bool ambig; 195 Object *o = object_resolve_path_type("", typename, &ambig); 196 197 if (ambig || !o) { 198 return NULL; 199 } 200 return o; 201 } 202 203 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 204 { 205 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 206 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 207 Object *obj = piix ? piix : lpc; 208 QObject *o; 209 pm->cpu_hp_io_base = 0; 210 pm->pcihp_io_base = 0; 211 pm->pcihp_io_len = 0; 212 pm->smi_on_cpuhp = false; 213 pm->smi_on_cpu_unplug = false; 214 215 assert(obj); 216 init_common_fadt_data(machine, obj, &pm->fadt); 217 if (piix) { 218 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 219 pm->fadt.rev = 1; 220 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 221 pm->pcihp_io_base = 222 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 223 pm->pcihp_io_len = 224 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 225 } 226 if (lpc) { 227 uint64_t smi_features = object_property_get_uint(lpc, 228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 231 pm->fadt.reset_reg = r; 232 pm->fadt.reset_val = 0xf; 233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 235 pm->smi_on_cpuhp = 236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 237 pm->smi_on_cpu_unplug = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 239 } 240 241 /* The above need not be conditional on machine type because the reset port 242 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 243 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 244 245 /* Fill in optional s3/s4 related properties */ 246 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 247 if (o) { 248 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 249 } else { 250 pm->s3_disabled = false; 251 } 252 qobject_unref(o); 253 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 254 if (o) { 255 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 256 } else { 257 pm->s4_disabled = false; 258 } 259 qobject_unref(o); 260 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 261 if (o) { 262 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 263 } else { 264 pm->s4_val = false; 265 } 266 qobject_unref(o); 267 268 pm->pcihp_bridge_en = 269 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 270 NULL); 271 pm->pcihp_root_en = 272 object_property_get_bool(obj, "acpi-root-pci-hotplug", 273 NULL); 274 } 275 276 static void acpi_get_misc_info(AcpiMiscInfo *info) 277 { 278 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 279 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 280 assert(!!piix != !!lpc); 281 282 if (piix) { 283 info->is_piix4 = true; 284 } 285 if (lpc) { 286 info->is_piix4 = false; 287 } 288 289 info->has_hpet = hpet_find(); 290 info->tpm_version = tpm_get_version(tpm_find()); 291 info->pvpanic_port = pvpanic_port(); 292 info->applesmc_io_base = applesmc_port(); 293 } 294 295 /* 296 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 297 * On i386 arch we only have two pci hosts, so we can look only for them. 298 */ 299 static Object *acpi_get_i386_pci_host(void) 300 { 301 PCIHostState *host; 302 303 host = OBJECT_CHECK(PCIHostState, 304 object_resolve_path("/machine/i440fx", NULL), 305 TYPE_PCI_HOST_BRIDGE); 306 if (!host) { 307 host = OBJECT_CHECK(PCIHostState, 308 object_resolve_path("/machine/q35", NULL), 309 TYPE_PCI_HOST_BRIDGE); 310 } 311 312 return OBJECT(host); 313 } 314 315 static void acpi_get_pci_holes(Range *hole, Range *hole64) 316 { 317 Object *pci_host; 318 319 pci_host = acpi_get_i386_pci_host(); 320 g_assert(pci_host); 321 322 range_set_bounds1(hole, 323 object_property_get_uint(pci_host, 324 PCI_HOST_PROP_PCI_HOLE_START, 325 NULL), 326 object_property_get_uint(pci_host, 327 PCI_HOST_PROP_PCI_HOLE_END, 328 NULL)); 329 range_set_bounds1(hole64, 330 object_property_get_uint(pci_host, 331 PCI_HOST_PROP_PCI_HOLE64_START, 332 NULL), 333 object_property_get_uint(pci_host, 334 PCI_HOST_PROP_PCI_HOLE64_END, 335 NULL)); 336 } 337 338 static void acpi_align_size(GArray *blob, unsigned align) 339 { 340 /* Align size to multiple of given size. This reduces the chance 341 * we need to change size in the future (breaking cross version migration). 342 */ 343 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 344 } 345 346 /* FACS */ 347 static void 348 build_facs(GArray *table_data) 349 { 350 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 351 memcpy(&facs->signature, "FACS", 4); 352 facs->length = cpu_to_le32(sizeof(*facs)); 353 } 354 355 static void build_append_pcihp_notify_entry(Aml *method, int slot) 356 { 357 Aml *if_ctx; 358 int32_t devfn = PCI_DEVFN(slot, 0); 359 360 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 361 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 362 aml_append(method, if_ctx); 363 } 364 365 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 366 bool pcihp_bridge_en) 367 { 368 Aml *dev, *notify_method = NULL, *method; 369 QObject *bsel; 370 PCIBus *sec; 371 int i; 372 373 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 374 if (bsel) { 375 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 376 377 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 378 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 379 } 380 381 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 382 DeviceClass *dc; 383 PCIDeviceClass *pc; 384 PCIDevice *pdev = bus->devices[i]; 385 int slot = PCI_SLOT(i); 386 bool hotplug_enabled_dev; 387 bool bridge_in_acpi; 388 bool cold_plugged_bridge; 389 390 if (!pdev) { 391 if (bsel) { /* add hotplug slots for non present devices */ 392 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 393 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 394 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 395 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 396 aml_append(method, 397 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 398 ); 399 aml_append(dev, method); 400 aml_append(parent_scope, dev); 401 402 build_append_pcihp_notify_entry(notify_method, slot); 403 } 404 continue; 405 } 406 407 pc = PCI_DEVICE_GET_CLASS(pdev); 408 dc = DEVICE_GET_CLASS(pdev); 409 410 /* 411 * Cold plugged bridges aren't themselves hot-pluggable. 412 * Hotplugged bridges *are* hot-pluggable. 413 */ 414 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 415 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 416 417 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 418 419 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 420 continue; 421 } 422 423 /* start to compose PCI slot descriptor */ 424 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 425 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 426 427 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 428 /* add VGA specific AML methods */ 429 int s3d; 430 431 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 432 s3d = 3; 433 } else { 434 s3d = 0; 435 } 436 437 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 438 aml_append(method, aml_return(aml_int(0))); 439 aml_append(dev, method); 440 441 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 442 aml_append(method, aml_return(aml_int(0))); 443 aml_append(dev, method); 444 445 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 446 aml_append(method, aml_return(aml_int(s3d))); 447 aml_append(dev, method); 448 } else if (hotplug_enabled_dev) { 449 /* add _SUN/_EJ0 to make slot hotpluggable */ 450 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 451 452 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 453 aml_append(method, 454 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 455 ); 456 aml_append(dev, method); 457 458 if (bsel) { 459 build_append_pcihp_notify_entry(notify_method, slot); 460 } 461 } else if (bridge_in_acpi) { 462 /* 463 * device is coldplugged bridge, 464 * add child device descriptions into its scope 465 */ 466 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 467 468 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 469 } 470 /* slot descriptor has been composed, add it into parent context */ 471 aml_append(parent_scope, dev); 472 } 473 474 if (bsel) { 475 aml_append(parent_scope, notify_method); 476 } 477 478 /* Append PCNT method to notify about events on local and child buses. 479 * Add this method for root bus only when hotplug is enabled since DSDT 480 * expects it. 481 */ 482 if (bsel || pcihp_bridge_en) { 483 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 484 485 /* If bus supports hotplug select it and notify about local events */ 486 if (bsel) { 487 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 488 489 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 490 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 491 aml_int(1))); /* Device Check */ 492 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 493 aml_int(3))); /* Eject Request */ 494 } 495 496 /* Notify about child bus events in any case */ 497 if (pcihp_bridge_en) { 498 QLIST_FOREACH(sec, &bus->child, sibling) { 499 int32_t devfn = sec->parent_dev->devfn; 500 501 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 502 continue; 503 } 504 505 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 506 } 507 } 508 509 aml_append(parent_scope, method); 510 } 511 qobject_unref(bsel); 512 } 513 514 /** 515 * build_prt_entry: 516 * @link_name: link name for PCI route entry 517 * 518 * build AML package containing a PCI route entry for @link_name 519 */ 520 static Aml *build_prt_entry(const char *link_name) 521 { 522 Aml *a_zero = aml_int(0); 523 Aml *pkg = aml_package(4); 524 aml_append(pkg, a_zero); 525 aml_append(pkg, a_zero); 526 aml_append(pkg, aml_name("%s", link_name)); 527 aml_append(pkg, a_zero); 528 return pkg; 529 } 530 531 /* 532 * initialize_route - Initialize the interrupt routing rule 533 * through a specific LINK: 534 * if (lnk_idx == idx) 535 * route using link 'link_name' 536 */ 537 static Aml *initialize_route(Aml *route, const char *link_name, 538 Aml *lnk_idx, int idx) 539 { 540 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 541 Aml *pkg = build_prt_entry(link_name); 542 543 aml_append(if_ctx, aml_store(pkg, route)); 544 545 return if_ctx; 546 } 547 548 /* 549 * build_prt - Define interrupt rounting rules 550 * 551 * Returns an array of 128 routes, one for each device, 552 * based on device location. 553 * The main goal is to equaly distribute the interrupts 554 * over the 4 existing ACPI links (works only for i440fx). 555 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 556 * 557 */ 558 static Aml *build_prt(bool is_pci0_prt) 559 { 560 Aml *method, *while_ctx, *pin, *res; 561 562 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 563 res = aml_local(0); 564 pin = aml_local(1); 565 aml_append(method, aml_store(aml_package(128), res)); 566 aml_append(method, aml_store(aml_int(0), pin)); 567 568 /* while (pin < 128) */ 569 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 570 { 571 Aml *slot = aml_local(2); 572 Aml *lnk_idx = aml_local(3); 573 Aml *route = aml_local(4); 574 575 /* slot = pin >> 2 */ 576 aml_append(while_ctx, 577 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 578 /* lnk_idx = (slot + pin) & 3 */ 579 aml_append(while_ctx, 580 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 581 lnk_idx)); 582 583 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 584 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 585 if (is_pci0_prt) { 586 Aml *if_device_1, *if_pin_4, *else_pin_4; 587 588 /* device 1 is the power-management device, needs SCI */ 589 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 590 { 591 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 592 { 593 aml_append(if_pin_4, 594 aml_store(build_prt_entry("LNKS"), route)); 595 } 596 aml_append(if_device_1, if_pin_4); 597 else_pin_4 = aml_else(); 598 { 599 aml_append(else_pin_4, 600 aml_store(build_prt_entry("LNKA"), route)); 601 } 602 aml_append(if_device_1, else_pin_4); 603 } 604 aml_append(while_ctx, if_device_1); 605 } else { 606 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 607 } 608 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 609 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 610 611 /* route[0] = 0x[slot]FFFF */ 612 aml_append(while_ctx, 613 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 614 NULL), 615 aml_index(route, aml_int(0)))); 616 /* route[1] = pin & 3 */ 617 aml_append(while_ctx, 618 aml_store(aml_and(pin, aml_int(3), NULL), 619 aml_index(route, aml_int(1)))); 620 /* res[pin] = route */ 621 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 622 /* pin++ */ 623 aml_append(while_ctx, aml_increment(pin)); 624 } 625 aml_append(method, while_ctx); 626 /* return res*/ 627 aml_append(method, aml_return(res)); 628 629 return method; 630 } 631 632 static void build_hpet_aml(Aml *table) 633 { 634 Aml *crs; 635 Aml *field; 636 Aml *method; 637 Aml *if_ctx; 638 Aml *scope = aml_scope("_SB"); 639 Aml *dev = aml_device("HPET"); 640 Aml *zero = aml_int(0); 641 Aml *id = aml_local(0); 642 Aml *period = aml_local(1); 643 644 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 645 aml_append(dev, aml_name_decl("_UID", zero)); 646 647 aml_append(dev, 648 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 649 HPET_LEN)); 650 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 651 aml_append(field, aml_named_field("VEND", 32)); 652 aml_append(field, aml_named_field("PRD", 32)); 653 aml_append(dev, field); 654 655 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 656 aml_append(method, aml_store(aml_name("VEND"), id)); 657 aml_append(method, aml_store(aml_name("PRD"), period)); 658 aml_append(method, aml_shiftright(id, aml_int(16), id)); 659 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 660 aml_equal(id, aml_int(0xffff)))); 661 { 662 aml_append(if_ctx, aml_return(zero)); 663 } 664 aml_append(method, if_ctx); 665 666 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 667 aml_lgreater(period, aml_int(100000000)))); 668 { 669 aml_append(if_ctx, aml_return(zero)); 670 } 671 aml_append(method, if_ctx); 672 673 aml_append(method, aml_return(aml_int(0x0F))); 674 aml_append(dev, method); 675 676 crs = aml_resource_template(); 677 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 678 aml_append(dev, aml_name_decl("_CRS", crs)); 679 680 aml_append(scope, dev); 681 aml_append(table, scope); 682 } 683 684 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 685 { 686 Aml *dev; 687 Aml *method; 688 Aml *crs; 689 690 dev = aml_device("VMBS"); 691 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 692 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 693 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 694 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 695 696 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 697 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 698 aml_name("STA"))); 699 aml_append(dev, method); 700 701 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 702 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 703 aml_name("STA"))); 704 aml_append(dev, method); 705 706 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 707 aml_append(method, aml_return(aml_name("STA"))); 708 aml_append(dev, method); 709 710 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 711 712 crs = aml_resource_template(); 713 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 714 aml_append(dev, aml_name_decl("_CRS", crs)); 715 716 return dev; 717 } 718 719 static void build_isa_devices_aml(Aml *table) 720 { 721 bool ambiguous; 722 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 723 Aml *scope; 724 725 assert(obj && !ambiguous); 726 727 scope = aml_scope("_SB.PCI0.ISA"); 728 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 729 isa_build_aml(ISA_BUS(obj), scope); 730 731 aml_append(table, scope); 732 } 733 734 static void build_dbg_aml(Aml *table) 735 { 736 Aml *field; 737 Aml *method; 738 Aml *while_ctx; 739 Aml *scope = aml_scope("\\"); 740 Aml *buf = aml_local(0); 741 Aml *len = aml_local(1); 742 Aml *idx = aml_local(2); 743 744 aml_append(scope, 745 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 746 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 747 aml_append(field, aml_named_field("DBGB", 8)); 748 aml_append(scope, field); 749 750 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 751 752 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 753 aml_append(method, aml_to_buffer(buf, buf)); 754 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 755 aml_append(method, aml_store(aml_int(0), idx)); 756 757 while_ctx = aml_while(aml_lless(idx, len)); 758 aml_append(while_ctx, 759 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 760 aml_append(while_ctx, aml_increment(idx)); 761 aml_append(method, while_ctx); 762 763 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 764 aml_append(scope, method); 765 766 aml_append(table, scope); 767 } 768 769 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 770 { 771 Aml *dev; 772 Aml *crs; 773 Aml *method; 774 uint32_t irqs[] = {5, 10, 11}; 775 776 dev = aml_device("%s", name); 777 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 778 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 779 780 crs = aml_resource_template(); 781 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 782 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 783 aml_append(dev, aml_name_decl("_PRS", crs)); 784 785 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 786 aml_append(method, aml_return(aml_call1("IQST", reg))); 787 aml_append(dev, method); 788 789 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 790 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 791 aml_append(dev, method); 792 793 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 794 aml_append(method, aml_return(aml_call1("IQCR", reg))); 795 aml_append(dev, method); 796 797 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 798 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 799 aml_append(method, aml_store(aml_name("PRRI"), reg)); 800 aml_append(dev, method); 801 802 return dev; 803 } 804 805 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 806 { 807 Aml *dev; 808 Aml *crs; 809 Aml *method; 810 uint32_t irqs; 811 812 dev = aml_device("%s", name); 813 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 814 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 815 816 crs = aml_resource_template(); 817 irqs = gsi; 818 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 819 AML_SHARED, &irqs, 1)); 820 aml_append(dev, aml_name_decl("_PRS", crs)); 821 822 aml_append(dev, aml_name_decl("_CRS", crs)); 823 824 /* 825 * _DIS can be no-op because the interrupt cannot be disabled. 826 */ 827 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 828 aml_append(dev, method); 829 830 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 831 aml_append(dev, method); 832 833 return dev; 834 } 835 836 /* _CRS method - get current settings */ 837 static Aml *build_iqcr_method(bool is_piix4) 838 { 839 Aml *if_ctx; 840 uint32_t irqs; 841 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 842 Aml *crs = aml_resource_template(); 843 844 irqs = 0; 845 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 846 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 847 aml_append(method, aml_name_decl("PRR0", crs)); 848 849 aml_append(method, 850 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 851 852 if (is_piix4) { 853 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 854 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 855 aml_append(method, if_ctx); 856 } else { 857 aml_append(method, 858 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 859 aml_name("PRRI"))); 860 } 861 862 aml_append(method, aml_return(aml_name("PRR0"))); 863 return method; 864 } 865 866 /* _STA method - get status */ 867 static Aml *build_irq_status_method(void) 868 { 869 Aml *if_ctx; 870 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 871 872 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 873 aml_append(if_ctx, aml_return(aml_int(0x09))); 874 aml_append(method, if_ctx); 875 aml_append(method, aml_return(aml_int(0x0B))); 876 return method; 877 } 878 879 static void build_piix4_pci0_int(Aml *table) 880 { 881 Aml *dev; 882 Aml *crs; 883 Aml *field; 884 Aml *method; 885 uint32_t irqs; 886 Aml *sb_scope = aml_scope("_SB"); 887 Aml *pci0_scope = aml_scope("PCI0"); 888 889 aml_append(pci0_scope, build_prt(true)); 890 aml_append(sb_scope, pci0_scope); 891 892 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 893 aml_append(field, aml_named_field("PRQ0", 8)); 894 aml_append(field, aml_named_field("PRQ1", 8)); 895 aml_append(field, aml_named_field("PRQ2", 8)); 896 aml_append(field, aml_named_field("PRQ3", 8)); 897 aml_append(sb_scope, field); 898 899 aml_append(sb_scope, build_irq_status_method()); 900 aml_append(sb_scope, build_iqcr_method(true)); 901 902 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 903 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 904 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 905 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 906 907 dev = aml_device("LNKS"); 908 { 909 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 910 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 911 912 crs = aml_resource_template(); 913 irqs = 9; 914 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 915 AML_ACTIVE_HIGH, AML_SHARED, 916 &irqs, 1)); 917 aml_append(dev, aml_name_decl("_PRS", crs)); 918 919 /* The SCI cannot be disabled and is always attached to GSI 9, 920 * so these are no-ops. We only need this link to override the 921 * polarity to active high and match the content of the MADT. 922 */ 923 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 924 aml_append(method, aml_return(aml_int(0x0b))); 925 aml_append(dev, method); 926 927 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 928 aml_append(dev, method); 929 930 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 931 aml_append(method, aml_return(aml_name("_PRS"))); 932 aml_append(dev, method); 933 934 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 935 aml_append(dev, method); 936 } 937 aml_append(sb_scope, dev); 938 939 aml_append(table, sb_scope); 940 } 941 942 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 943 { 944 int i; 945 int head; 946 Aml *pkg; 947 char base = name[3] < 'E' ? 'A' : 'E'; 948 char *s = g_strdup(name); 949 Aml *a_nr = aml_int((nr << 16) | 0xffff); 950 951 assert(strlen(s) == 4); 952 953 head = name[3] - base; 954 for (i = 0; i < 4; i++) { 955 if (head + i > 3) { 956 head = i * -1; 957 } 958 s[3] = base + head + i; 959 pkg = aml_package(4); 960 aml_append(pkg, a_nr); 961 aml_append(pkg, aml_int(i)); 962 aml_append(pkg, aml_name("%s", s)); 963 aml_append(pkg, aml_int(0)); 964 aml_append(ctx, pkg); 965 } 966 g_free(s); 967 } 968 969 static Aml *build_q35_routing_table(const char *str) 970 { 971 int i; 972 Aml *pkg; 973 char *name = g_strdup_printf("%s ", str); 974 975 pkg = aml_package(128); 976 for (i = 0; i < 0x18; i++) { 977 name[3] = 'E' + (i & 0x3); 978 append_q35_prt_entry(pkg, i, name); 979 } 980 981 name[3] = 'E'; 982 append_q35_prt_entry(pkg, 0x18, name); 983 984 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 985 for (i = 0x0019; i < 0x1e; i++) { 986 name[3] = 'A'; 987 append_q35_prt_entry(pkg, i, name); 988 } 989 990 /* PCIe->PCI bridge. use PIRQ[E-H] */ 991 name[3] = 'E'; 992 append_q35_prt_entry(pkg, 0x1e, name); 993 name[3] = 'A'; 994 append_q35_prt_entry(pkg, 0x1f, name); 995 996 g_free(name); 997 return pkg; 998 } 999 1000 static void build_q35_pci0_int(Aml *table) 1001 { 1002 Aml *field; 1003 Aml *method; 1004 Aml *sb_scope = aml_scope("_SB"); 1005 Aml *pci0_scope = aml_scope("PCI0"); 1006 1007 /* Zero => PIC mode, One => APIC Mode */ 1008 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1009 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1010 { 1011 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1012 } 1013 aml_append(table, method); 1014 1015 aml_append(pci0_scope, 1016 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1017 aml_append(pci0_scope, 1018 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1019 1020 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1021 { 1022 Aml *if_ctx; 1023 Aml *else_ctx; 1024 1025 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1026 section 6.2.8.1 */ 1027 /* Note: we provide the same info as the PCI routing 1028 table of the Bochs BIOS */ 1029 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1030 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1031 aml_append(method, if_ctx); 1032 else_ctx = aml_else(); 1033 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1034 aml_append(method, else_ctx); 1035 } 1036 aml_append(pci0_scope, method); 1037 aml_append(sb_scope, pci0_scope); 1038 1039 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1040 aml_append(field, aml_named_field("PRQA", 8)); 1041 aml_append(field, aml_named_field("PRQB", 8)); 1042 aml_append(field, aml_named_field("PRQC", 8)); 1043 aml_append(field, aml_named_field("PRQD", 8)); 1044 aml_append(field, aml_reserved_field(0x20)); 1045 aml_append(field, aml_named_field("PRQE", 8)); 1046 aml_append(field, aml_named_field("PRQF", 8)); 1047 aml_append(field, aml_named_field("PRQG", 8)); 1048 aml_append(field, aml_named_field("PRQH", 8)); 1049 aml_append(sb_scope, field); 1050 1051 aml_append(sb_scope, build_irq_status_method()); 1052 aml_append(sb_scope, build_iqcr_method(false)); 1053 1054 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1055 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1056 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1057 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1058 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1059 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1060 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1061 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1062 1063 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1064 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1065 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1066 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1067 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1068 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1069 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1070 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1071 1072 aml_append(table, sb_scope); 1073 } 1074 1075 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1076 { 1077 Aml *dev; 1078 Aml *resource_template; 1079 1080 /* DRAM controller */ 1081 dev = aml_device("DRAC"); 1082 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1083 1084 resource_template = aml_resource_template(); 1085 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1086 aml_append(resource_template, 1087 aml_qword_memory(AML_POS_DECODE, 1088 AML_MIN_FIXED, 1089 AML_MAX_FIXED, 1090 AML_NON_CACHEABLE, 1091 AML_READ_WRITE, 1092 0x0000000000000000, 1093 mcfg->base, 1094 mcfg->base + mcfg->size - 1, 1095 0x0000000000000000, 1096 mcfg->size)); 1097 } else { 1098 aml_append(resource_template, 1099 aml_dword_memory(AML_POS_DECODE, 1100 AML_MIN_FIXED, 1101 AML_MAX_FIXED, 1102 AML_NON_CACHEABLE, 1103 AML_READ_WRITE, 1104 0x0000000000000000, 1105 mcfg->base, 1106 mcfg->base + mcfg->size - 1, 1107 0x0000000000000000, 1108 mcfg->size)); 1109 } 1110 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1111 1112 return dev; 1113 } 1114 1115 static void build_q35_isa_bridge(Aml *table) 1116 { 1117 Aml *dev; 1118 Aml *scope; 1119 1120 scope = aml_scope("_SB.PCI0"); 1121 dev = aml_device("ISA"); 1122 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1123 1124 /* ICH9 PCI to ISA irq remapping */ 1125 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1126 aml_int(0x60), 0x0C)); 1127 1128 aml_append(scope, dev); 1129 aml_append(table, scope); 1130 } 1131 1132 static void build_piix4_isa_bridge(Aml *table) 1133 { 1134 Aml *dev; 1135 Aml *scope; 1136 1137 scope = aml_scope("_SB.PCI0"); 1138 dev = aml_device("ISA"); 1139 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1140 1141 /* PIIX PCI to ISA irq remapping */ 1142 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1143 aml_int(0x60), 0x04)); 1144 1145 aml_append(scope, dev); 1146 aml_append(table, scope); 1147 } 1148 1149 static void build_piix4_pci_hotplug(Aml *table) 1150 { 1151 Aml *scope; 1152 Aml *field; 1153 Aml *method; 1154 1155 scope = aml_scope("_SB.PCI0"); 1156 1157 aml_append(scope, 1158 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1159 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1160 aml_append(field, aml_named_field("PCIU", 32)); 1161 aml_append(field, aml_named_field("PCID", 32)); 1162 aml_append(scope, field); 1163 1164 aml_append(scope, 1165 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1166 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1167 aml_append(field, aml_named_field("B0EJ", 32)); 1168 aml_append(scope, field); 1169 1170 aml_append(scope, 1171 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1172 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1173 aml_append(field, aml_named_field("BNUM", 32)); 1174 aml_append(scope, field); 1175 1176 aml_append(scope, aml_mutex("BLCK", 0)); 1177 1178 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1179 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1180 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1181 aml_append(method, 1182 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1183 aml_append(method, aml_release(aml_name("BLCK"))); 1184 aml_append(method, aml_return(aml_int(0))); 1185 aml_append(scope, method); 1186 1187 aml_append(table, scope); 1188 } 1189 1190 static Aml *build_q35_osc_method(void) 1191 { 1192 Aml *if_ctx; 1193 Aml *if_ctx2; 1194 Aml *else_ctx; 1195 Aml *method; 1196 Aml *a_cwd1 = aml_name("CDW1"); 1197 Aml *a_ctrl = aml_local(0); 1198 1199 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1200 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1201 1202 if_ctx = aml_if(aml_equal( 1203 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1204 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1205 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1206 1207 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1208 1209 /* 1210 * Always allow native PME, AER (no dependencies) 1211 * Allow SHPC (PCI bridges can have SHPC controller) 1212 */ 1213 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1214 1215 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1216 /* Unknown revision */ 1217 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1218 aml_append(if_ctx, if_ctx2); 1219 1220 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1221 /* Capabilities bits were masked */ 1222 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1223 aml_append(if_ctx, if_ctx2); 1224 1225 /* Update DWORD3 in the buffer */ 1226 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1227 aml_append(method, if_ctx); 1228 1229 else_ctx = aml_else(); 1230 /* Unrecognized UUID */ 1231 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1232 aml_append(method, else_ctx); 1233 1234 aml_append(method, aml_return(aml_arg(3))); 1235 return method; 1236 } 1237 1238 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1239 { 1240 Aml *scope = aml_scope("_SB.PCI0"); 1241 Aml *dev = aml_device("SMB0"); 1242 1243 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1244 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1245 aml_append(scope, dev); 1246 aml_append(table, scope); 1247 } 1248 1249 static void 1250 build_dsdt(GArray *table_data, BIOSLinker *linker, 1251 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1252 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1253 { 1254 CrsRangeEntry *entry; 1255 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1256 CrsRangeSet crs_range_set; 1257 PCMachineState *pcms = PC_MACHINE(machine); 1258 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1259 X86MachineState *x86ms = X86_MACHINE(machine); 1260 AcpiMcfgInfo mcfg; 1261 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1262 uint32_t nr_mem = machine->ram_slots; 1263 int root_bus_limit = 0xFF; 1264 PCIBus *bus = NULL; 1265 TPMIf *tpm = tpm_find(); 1266 int i; 1267 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1268 1269 dsdt = init_aml_allocator(); 1270 1271 /* Reserve space for header */ 1272 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1273 1274 build_dbg_aml(dsdt); 1275 if (misc->is_piix4) { 1276 sb_scope = aml_scope("_SB"); 1277 dev = aml_device("PCI0"); 1278 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1279 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1280 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1281 aml_append(sb_scope, dev); 1282 aml_append(dsdt, sb_scope); 1283 1284 if (misc->has_hpet) { 1285 build_hpet_aml(dsdt); 1286 } 1287 build_piix4_isa_bridge(dsdt); 1288 build_isa_devices_aml(dsdt); 1289 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1290 build_piix4_pci_hotplug(dsdt); 1291 } 1292 build_piix4_pci0_int(dsdt); 1293 } else { 1294 sb_scope = aml_scope("_SB"); 1295 dev = aml_device("PCI0"); 1296 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1297 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1298 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1299 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1300 aml_append(dev, build_q35_osc_method()); 1301 aml_append(sb_scope, dev); 1302 if (mcfg_valid) { 1303 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1304 } 1305 1306 if (pm->smi_on_cpuhp) { 1307 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1308 dev = aml_device("PCI0.SMI0"); 1309 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1310 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1311 crs = aml_resource_template(); 1312 aml_append(crs, 1313 aml_io( 1314 AML_DECODE16, 1315 ACPI_PORT_SMI_CMD, 1316 ACPI_PORT_SMI_CMD, 1317 1, 1318 2) 1319 ); 1320 aml_append(dev, aml_name_decl("_CRS", crs)); 1321 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1322 aml_int(ACPI_PORT_SMI_CMD), 2)); 1323 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1324 AML_WRITE_AS_ZEROS); 1325 aml_append(field, aml_named_field("SMIC", 8)); 1326 aml_append(field, aml_reserved_field(8)); 1327 aml_append(dev, field); 1328 aml_append(sb_scope, dev); 1329 } 1330 1331 aml_append(dsdt, sb_scope); 1332 1333 if (misc->has_hpet) { 1334 build_hpet_aml(dsdt); 1335 } 1336 build_q35_isa_bridge(dsdt); 1337 build_isa_devices_aml(dsdt); 1338 build_q35_pci0_int(dsdt); 1339 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1340 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1341 } 1342 } 1343 1344 if (vmbus_bridge) { 1345 sb_scope = aml_scope("_SB"); 1346 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1347 aml_append(dsdt, sb_scope); 1348 } 1349 1350 if (pcmc->legacy_cpu_hotplug) { 1351 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1352 } else { 1353 CPUHotplugFeatures opts = { 1354 .acpi_1_compatible = true, .has_legacy_cphp = true, 1355 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1356 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1357 }; 1358 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1359 "\\_SB.PCI0", "\\_GPE._E02"); 1360 } 1361 1362 if (pcms->memhp_io_base && nr_mem) { 1363 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1364 "\\_GPE._E03", AML_SYSTEM_IO, 1365 pcms->memhp_io_base); 1366 } 1367 1368 scope = aml_scope("_GPE"); 1369 { 1370 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1371 1372 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1373 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1374 aml_append(method, 1375 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1376 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1377 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1378 aml_append(scope, method); 1379 } 1380 1381 if (machine->nvdimms_state->is_enabled) { 1382 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1383 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1384 aml_int(0x80))); 1385 aml_append(scope, method); 1386 } 1387 } 1388 aml_append(dsdt, scope); 1389 1390 crs_range_set_init(&crs_range_set); 1391 bus = PC_MACHINE(machine)->bus; 1392 if (bus) { 1393 QLIST_FOREACH(bus, &bus->child, sibling) { 1394 uint8_t bus_num = pci_bus_num(bus); 1395 uint8_t numa_node = pci_bus_numa_node(bus); 1396 1397 /* look only for expander root buses */ 1398 if (!pci_bus_is_root(bus)) { 1399 continue; 1400 } 1401 1402 if (bus_num < root_bus_limit) { 1403 root_bus_limit = bus_num - 1; 1404 } 1405 1406 scope = aml_scope("\\_SB"); 1407 dev = aml_device("PC%.02X", bus_num); 1408 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1409 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1410 if (pci_bus_is_express(bus)) { 1411 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1412 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1413 aml_append(dev, build_q35_osc_method()); 1414 } else { 1415 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1416 } 1417 1418 if (numa_node != NUMA_NODE_UNASSIGNED) { 1419 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1420 } 1421 1422 aml_append(dev, build_prt(false)); 1423 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1424 0, 0, 0, 0); 1425 aml_append(dev, aml_name_decl("_CRS", crs)); 1426 aml_append(scope, dev); 1427 aml_append(dsdt, scope); 1428 } 1429 } 1430 1431 /* 1432 * At this point crs_range_set has all the ranges used by pci 1433 * busses *other* than PCI0. These ranges will be excluded from 1434 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1435 * too. 1436 */ 1437 if (mcfg_valid) { 1438 crs_range_insert(crs_range_set.mem_ranges, 1439 mcfg.base, mcfg.base + mcfg.size - 1); 1440 } 1441 1442 scope = aml_scope("\\_SB.PCI0"); 1443 /* build PCI0._CRS */ 1444 crs = aml_resource_template(); 1445 aml_append(crs, 1446 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1447 0x0000, 0x0, root_bus_limit, 1448 0x0000, root_bus_limit + 1)); 1449 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1450 1451 aml_append(crs, 1452 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1453 AML_POS_DECODE, AML_ENTIRE_RANGE, 1454 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1455 1456 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1457 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1458 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1459 aml_append(crs, 1460 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1461 AML_POS_DECODE, AML_ENTIRE_RANGE, 1462 0x0000, entry->base, entry->limit, 1463 0x0000, entry->limit - entry->base + 1)); 1464 } 1465 1466 aml_append(crs, 1467 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1468 AML_CACHEABLE, AML_READ_WRITE, 1469 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1470 1471 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1472 range_lob(pci_hole), 1473 range_upb(pci_hole)); 1474 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1475 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1476 aml_append(crs, 1477 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1478 AML_NON_CACHEABLE, AML_READ_WRITE, 1479 0, entry->base, entry->limit, 1480 0, entry->limit - entry->base + 1)); 1481 } 1482 1483 if (!range_is_empty(pci_hole64)) { 1484 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1485 range_lob(pci_hole64), 1486 range_upb(pci_hole64)); 1487 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1488 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1489 aml_append(crs, 1490 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1491 AML_MAX_FIXED, 1492 AML_CACHEABLE, AML_READ_WRITE, 1493 0, entry->base, entry->limit, 1494 0, entry->limit - entry->base + 1)); 1495 } 1496 } 1497 1498 if (TPM_IS_TIS_ISA(tpm_find())) { 1499 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1500 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1501 } 1502 aml_append(scope, aml_name_decl("_CRS", crs)); 1503 1504 /* reserve GPE0 block resources */ 1505 dev = aml_device("GPE0"); 1506 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1507 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1508 /* device present, functioning, decoding, not shown in UI */ 1509 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1510 crs = aml_resource_template(); 1511 aml_append(crs, 1512 aml_io( 1513 AML_DECODE16, 1514 pm->fadt.gpe0_blk.address, 1515 pm->fadt.gpe0_blk.address, 1516 1, 1517 pm->fadt.gpe0_blk.bit_width / 8) 1518 ); 1519 aml_append(dev, aml_name_decl("_CRS", crs)); 1520 aml_append(scope, dev); 1521 1522 crs_range_set_free(&crs_range_set); 1523 1524 /* reserve PCIHP resources */ 1525 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1526 dev = aml_device("PHPR"); 1527 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1528 aml_append(dev, 1529 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1530 /* device present, functioning, decoding, not shown in UI */ 1531 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1532 crs = aml_resource_template(); 1533 aml_append(crs, 1534 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1535 pm->pcihp_io_len) 1536 ); 1537 aml_append(dev, aml_name_decl("_CRS", crs)); 1538 aml_append(scope, dev); 1539 } 1540 aml_append(dsdt, scope); 1541 1542 /* create S3_ / S4_ / S5_ packages if necessary */ 1543 scope = aml_scope("\\"); 1544 if (!pm->s3_disabled) { 1545 pkg = aml_package(4); 1546 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1547 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1548 aml_append(pkg, aml_int(0)); /* reserved */ 1549 aml_append(pkg, aml_int(0)); /* reserved */ 1550 aml_append(scope, aml_name_decl("_S3", pkg)); 1551 } 1552 1553 if (!pm->s4_disabled) { 1554 pkg = aml_package(4); 1555 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1556 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1557 aml_append(pkg, aml_int(pm->s4_val)); 1558 aml_append(pkg, aml_int(0)); /* reserved */ 1559 aml_append(pkg, aml_int(0)); /* reserved */ 1560 aml_append(scope, aml_name_decl("_S4", pkg)); 1561 } 1562 1563 pkg = aml_package(4); 1564 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1565 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1566 aml_append(pkg, aml_int(0)); /* reserved */ 1567 aml_append(pkg, aml_int(0)); /* reserved */ 1568 aml_append(scope, aml_name_decl("_S5", pkg)); 1569 aml_append(dsdt, scope); 1570 1571 /* create fw_cfg node, unconditionally */ 1572 { 1573 scope = aml_scope("\\_SB.PCI0"); 1574 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1575 aml_append(dsdt, scope); 1576 } 1577 1578 if (misc->applesmc_io_base) { 1579 scope = aml_scope("\\_SB.PCI0.ISA"); 1580 dev = aml_device("SMC"); 1581 1582 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1583 /* device present, functioning, decoding, not shown in UI */ 1584 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1585 1586 crs = aml_resource_template(); 1587 aml_append(crs, 1588 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1589 0x01, APPLESMC_MAX_DATA_LENGTH) 1590 ); 1591 aml_append(crs, aml_irq_no_flags(6)); 1592 aml_append(dev, aml_name_decl("_CRS", crs)); 1593 1594 aml_append(scope, dev); 1595 aml_append(dsdt, scope); 1596 } 1597 1598 if (misc->pvpanic_port) { 1599 scope = aml_scope("\\_SB.PCI0.ISA"); 1600 1601 dev = aml_device("PEVT"); 1602 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1603 1604 crs = aml_resource_template(); 1605 aml_append(crs, 1606 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1607 ); 1608 aml_append(dev, aml_name_decl("_CRS", crs)); 1609 1610 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1611 aml_int(misc->pvpanic_port), 1)); 1612 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1613 aml_append(field, aml_named_field("PEPT", 8)); 1614 aml_append(dev, field); 1615 1616 /* device present, functioning, decoding, shown in UI */ 1617 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1618 1619 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1620 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1621 aml_append(method, aml_return(aml_local(0))); 1622 aml_append(dev, method); 1623 1624 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1625 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1626 aml_append(dev, method); 1627 1628 aml_append(scope, dev); 1629 aml_append(dsdt, scope); 1630 } 1631 1632 sb_scope = aml_scope("\\_SB"); 1633 { 1634 Object *pci_host; 1635 PCIBus *bus = NULL; 1636 1637 pci_host = acpi_get_i386_pci_host(); 1638 if (pci_host) { 1639 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1640 } 1641 1642 if (bus) { 1643 Aml *scope = aml_scope("PCI0"); 1644 /* Scan all PCI buses. Generate tables to support hotplug. */ 1645 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1646 1647 if (TPM_IS_TIS_ISA(tpm)) { 1648 if (misc->tpm_version == TPM_VERSION_2_0) { 1649 dev = aml_device("TPM"); 1650 aml_append(dev, aml_name_decl("_HID", 1651 aml_string("MSFT0101"))); 1652 } else { 1653 dev = aml_device("ISA.TPM"); 1654 aml_append(dev, aml_name_decl("_HID", 1655 aml_eisaid("PNP0C31"))); 1656 } 1657 1658 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1659 crs = aml_resource_template(); 1660 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1661 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1662 /* 1663 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1664 Rewrite to take IRQ from TPM device model and 1665 fix default IRQ value there to use some unused IRQ 1666 */ 1667 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1668 aml_append(dev, aml_name_decl("_CRS", crs)); 1669 1670 tpm_build_ppi_acpi(tpm, dev); 1671 1672 aml_append(scope, dev); 1673 } 1674 1675 aml_append(sb_scope, scope); 1676 } 1677 } 1678 1679 if (TPM_IS_CRB(tpm)) { 1680 dev = aml_device("TPM"); 1681 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1682 crs = aml_resource_template(); 1683 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1684 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1685 aml_append(dev, aml_name_decl("_CRS", crs)); 1686 1687 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1688 1689 tpm_build_ppi_acpi(tpm, dev); 1690 1691 aml_append(sb_scope, dev); 1692 } 1693 1694 aml_append(dsdt, sb_scope); 1695 1696 /* copy AML table into ACPI tables blob and patch header there */ 1697 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1698 build_header(linker, table_data, 1699 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1700 "DSDT", dsdt->buf->len, 1, pcms->oem_id, pcms->oem_table_id); 1701 free_aml_allocator(); 1702 } 1703 1704 static void 1705 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1706 const char *oem_table_id) 1707 { 1708 Acpi20Hpet *hpet; 1709 1710 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1711 /* Note timer_block_id value must be kept in sync with value advertised by 1712 * emulated hpet 1713 */ 1714 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1715 hpet->addr.address = cpu_to_le64(HPET_BASE); 1716 build_header(linker, table_data, 1717 (void *)hpet, "HPET", sizeof(*hpet), 1, oem_id, oem_table_id); 1718 } 1719 1720 static void 1721 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1722 const char *oem_id, const char *oem_table_id) 1723 { 1724 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1725 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1726 unsigned log_addr_offset = 1727 (char *)&tcpa->log_area_start_address - table_data->data; 1728 1729 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1730 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1731 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1732 1733 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1734 false /* high memory */); 1735 1736 /* log area start address to be filled by Guest linker */ 1737 bios_linker_loader_add_pointer(linker, 1738 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1739 ACPI_BUILD_TPMLOG_FILE, 0); 1740 1741 build_header(linker, table_data, 1742 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id); 1743 } 1744 1745 #define HOLE_640K_START (640 * KiB) 1746 #define HOLE_640K_END (1 * MiB) 1747 1748 static void 1749 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1750 { 1751 AcpiSystemResourceAffinityTable *srat; 1752 AcpiSratMemoryAffinity *numamem; 1753 1754 int i; 1755 int srat_start, numa_start, slots; 1756 uint64_t mem_len, mem_base, next_base; 1757 MachineClass *mc = MACHINE_GET_CLASS(machine); 1758 X86MachineState *x86ms = X86_MACHINE(machine); 1759 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1760 PCMachineState *pcms = PC_MACHINE(machine); 1761 ram_addr_t hotplugabble_address_space_size = 1762 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1763 NULL); 1764 1765 srat_start = table_data->len; 1766 1767 srat = acpi_data_push(table_data, sizeof *srat); 1768 srat->reserved1 = cpu_to_le32(1); 1769 1770 for (i = 0; i < apic_ids->len; i++) { 1771 int node_id = apic_ids->cpus[i].props.node_id; 1772 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1773 1774 if (apic_id < 255) { 1775 AcpiSratProcessorAffinity *core; 1776 1777 core = acpi_data_push(table_data, sizeof *core); 1778 core->type = ACPI_SRAT_PROCESSOR_APIC; 1779 core->length = sizeof(*core); 1780 core->local_apic_id = apic_id; 1781 core->proximity_lo = node_id; 1782 memset(core->proximity_hi, 0, 3); 1783 core->local_sapic_eid = 0; 1784 core->flags = cpu_to_le32(1); 1785 } else { 1786 AcpiSratProcessorX2ApicAffinity *core; 1787 1788 core = acpi_data_push(table_data, sizeof *core); 1789 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 1790 core->length = sizeof(*core); 1791 core->x2apic_id = cpu_to_le32(apic_id); 1792 core->proximity_domain = cpu_to_le32(node_id); 1793 core->flags = cpu_to_le32(1); 1794 } 1795 } 1796 1797 1798 /* the memory map is a bit tricky, it contains at least one hole 1799 * from 640k-1M and possibly another one from 3.5G-4G. 1800 */ 1801 next_base = 0; 1802 numa_start = table_data->len; 1803 1804 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 1805 mem_base = next_base; 1806 mem_len = pcms->node_mem[i - 1]; 1807 next_base = mem_base + mem_len; 1808 1809 /* Cut out the 640K hole */ 1810 if (mem_base <= HOLE_640K_START && 1811 next_base > HOLE_640K_START) { 1812 mem_len -= next_base - HOLE_640K_START; 1813 if (mem_len > 0) { 1814 numamem = acpi_data_push(table_data, sizeof *numamem); 1815 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1816 MEM_AFFINITY_ENABLED); 1817 } 1818 1819 /* Check for the rare case: 640K < RAM < 1M */ 1820 if (next_base <= HOLE_640K_END) { 1821 next_base = HOLE_640K_END; 1822 continue; 1823 } 1824 mem_base = HOLE_640K_END; 1825 mem_len = next_base - HOLE_640K_END; 1826 } 1827 1828 /* Cut out the ACPI_PCI hole */ 1829 if (mem_base <= x86ms->below_4g_mem_size && 1830 next_base > x86ms->below_4g_mem_size) { 1831 mem_len -= next_base - x86ms->below_4g_mem_size; 1832 if (mem_len > 0) { 1833 numamem = acpi_data_push(table_data, sizeof *numamem); 1834 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1835 MEM_AFFINITY_ENABLED); 1836 } 1837 mem_base = 1ULL << 32; 1838 mem_len = next_base - x86ms->below_4g_mem_size; 1839 next_base = mem_base + mem_len; 1840 } 1841 1842 if (mem_len > 0) { 1843 numamem = acpi_data_push(table_data, sizeof *numamem); 1844 build_srat_memory(numamem, mem_base, mem_len, i - 1, 1845 MEM_AFFINITY_ENABLED); 1846 } 1847 } 1848 1849 if (machine->nvdimms_state->is_enabled) { 1850 nvdimm_build_srat(table_data); 1851 } 1852 1853 slots = (table_data->len - numa_start) / sizeof *numamem; 1854 for (; slots < pcms->numa_nodes + 2; slots++) { 1855 numamem = acpi_data_push(table_data, sizeof *numamem); 1856 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1857 } 1858 1859 /* 1860 * Entry is required for Windows to enable memory hotplug in OS 1861 * and for Linux to enable SWIOTLB when booted with less than 1862 * 4G of RAM. Windows works better if the entry sets proximity 1863 * to the highest NUMA node in the machine. 1864 * Memory devices may override proximity set by this entry, 1865 * providing _PXM method if necessary. 1866 */ 1867 if (hotplugabble_address_space_size) { 1868 numamem = acpi_data_push(table_data, sizeof *numamem); 1869 build_srat_memory(numamem, machine->device_memory->base, 1870 hotplugabble_address_space_size, pcms->numa_nodes - 1, 1871 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1872 } 1873 1874 build_header(linker, table_data, 1875 (void *)(table_data->data + srat_start), 1876 "SRAT", 1877 table_data->len - srat_start, 1, pcms->oem_id, 1878 pcms->oem_table_id); 1879 } 1880 1881 /* 1882 * VT-d spec 8.1 DMA Remapping Reporting Structure 1883 * (version Oct. 2014 or later) 1884 */ 1885 static void 1886 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1887 const char *oem_table_id) 1888 { 1889 int dmar_start = table_data->len; 1890 1891 AcpiTableDmar *dmar; 1892 AcpiDmarHardwareUnit *drhd; 1893 AcpiDmarRootPortATS *atsr; 1894 uint8_t dmar_flags = 0; 1895 X86IOMMUState *iommu = x86_iommu_get_default(); 1896 AcpiDmarDeviceScope *scope = NULL; 1897 /* Root complex IOAPIC use one path[0] only */ 1898 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 1899 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1900 1901 assert(iommu); 1902 if (x86_iommu_ir_supported(iommu)) { 1903 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 1904 } 1905 1906 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1907 dmar->host_address_width = intel_iommu->aw_bits - 1; 1908 dmar->flags = dmar_flags; 1909 1910 /* DMAR Remapping Hardware Unit Definition structure */ 1911 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 1912 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1913 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 1914 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1915 drhd->pci_segment = cpu_to_le16(0); 1916 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1917 1918 /* Scope definition for the root-complex IOAPIC. See VT-d spec 1919 * 8.3.1 (version Oct. 2014 or later). */ 1920 scope = &drhd->scope[0]; 1921 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 1922 scope->length = ioapic_scope_size; 1923 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 1924 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 1925 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 1926 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 1927 1928 if (iommu->dt_supported) { 1929 atsr = acpi_data_push(table_data, sizeof(*atsr)); 1930 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 1931 atsr->length = cpu_to_le16(sizeof(*atsr)); 1932 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 1933 atsr->pci_segment = cpu_to_le16(0); 1934 } 1935 1936 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1937 "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id); 1938 } 1939 1940 /* 1941 * Windows ACPI Emulated Devices Table 1942 * (Version 1.0 - April 6, 2009) 1943 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 1944 * 1945 * Helpful to speedup Windows guests and ignored by others. 1946 */ 1947 static void 1948 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1949 const char *oem_table_id) 1950 { 1951 int waet_start = table_data->len; 1952 1953 /* WAET header */ 1954 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 1955 /* 1956 * Set "ACPI PM timer good" flag. 1957 * 1958 * Tells Windows guests that our ACPI PM timer is reliable in the 1959 * sense that guest can read it only once to obtain a reliable value. 1960 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 1961 */ 1962 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 1963 1964 build_header(linker, table_data, (void *)(table_data->data + waet_start), 1965 "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id); 1966 } 1967 1968 /* 1969 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 1970 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 1971 */ 1972 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 1973 1974 /* 1975 * Insert IVHD entry for device and recurse, insert alias, or insert range as 1976 * necessary for the PCI topology. 1977 */ 1978 static void 1979 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 1980 { 1981 GArray *table_data = opaque; 1982 uint32_t entry; 1983 1984 /* "Select" IVHD entry, type 0x2 */ 1985 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 1986 build_append_int_noprefix(table_data, entry, 4); 1987 1988 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 1989 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1990 uint8_t sec = pci_bus_num(sec_bus); 1991 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 1992 1993 if (pci_bus_is_express(sec_bus)) { 1994 /* 1995 * Walk the bus if there are subordinates, otherwise use a range 1996 * to cover an entire leaf bus. We could potentially also use a 1997 * range for traversed buses, but we'd need to take care not to 1998 * create both Select and Range entries covering the same device. 1999 * This is easier and potentially more compact. 2000 * 2001 * An example bare metal system seems to use Select entries for 2002 * root ports without a slot (ie. built-ins) and Range entries 2003 * when there is a slot. The same system also only hard-codes 2004 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2005 * making no effort to support nested bridges. We attempt to 2006 * be more thorough here. 2007 */ 2008 if (sec == sub) { /* leaf bus */ 2009 /* "Start of Range" IVHD entry, type 0x3 */ 2010 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2011 build_append_int_noprefix(table_data, entry, 4); 2012 /* "End of Range" IVHD entry, type 0x4 */ 2013 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2014 build_append_int_noprefix(table_data, entry, 4); 2015 } else { 2016 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2017 } 2018 } else { 2019 /* 2020 * If the secondary bus is conventional, then we need to create an 2021 * Alias range for everything downstream. The range covers the 2022 * first devfn on the secondary bus to the last devfn on the 2023 * subordinate bus. The alias target depends on legacy versus 2024 * express bridges, just as in pci_device_iommu_address_space(). 2025 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2026 */ 2027 uint16_t dev_id_a, dev_id_b; 2028 2029 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2030 2031 if (pci_is_express(dev) && 2032 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2033 dev_id_b = dev_id_a; 2034 } else { 2035 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2036 } 2037 2038 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2039 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2040 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2041 2042 /* "End of Range" IVHD entry, type 0x4 */ 2043 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2044 build_append_int_noprefix(table_data, entry, 4); 2045 } 2046 } 2047 } 2048 2049 /* For all PCI host bridges, walk and insert IVHD entries */ 2050 static int 2051 ivrs_host_bridges(Object *obj, void *opaque) 2052 { 2053 GArray *ivhd_blob = opaque; 2054 2055 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2056 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2057 2058 if (bus) { 2059 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2060 } 2061 } 2062 2063 return 0; 2064 } 2065 2066 static void 2067 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2068 const char *oem_table_id) 2069 { 2070 int ivhd_table_len = 24; 2071 int iommu_start = table_data->len; 2072 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2073 GArray *ivhd_blob = g_array_new(false, true, 1); 2074 2075 /* IVRS header */ 2076 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2077 /* IVinfo - IO virtualization information common to all 2078 * IOMMU units in a system 2079 */ 2080 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2081 /* reserved */ 2082 build_append_int_noprefix(table_data, 0, 8); 2083 2084 /* IVHD definition - type 10h */ 2085 build_append_int_noprefix(table_data, 0x10, 1); 2086 /* virtualization flags */ 2087 build_append_int_noprefix(table_data, 2088 (1UL << 0) | /* HtTunEn */ 2089 (1UL << 4) | /* iotblSup */ 2090 (1UL << 6) | /* PrefSup */ 2091 (1UL << 7), /* PPRSup */ 2092 1); 2093 2094 /* 2095 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2096 * complete set of IVHD entries. Do this into a separate blob so that we 2097 * can calculate the total IVRS table length here and then append the new 2098 * blob further below. Fall back to an entry covering all devices, which 2099 * is sufficient when no aliases are present. 2100 */ 2101 object_child_foreach_recursive(object_get_root(), 2102 ivrs_host_bridges, ivhd_blob); 2103 2104 if (!ivhd_blob->len) { 2105 /* 2106 * Type 1 device entry reporting all devices 2107 * These are 4-byte device entries currently reporting the range of 2108 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2109 */ 2110 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2111 } 2112 2113 ivhd_table_len += ivhd_blob->len; 2114 2115 /* 2116 * When interrupt remapping is supported, we add a special IVHD device 2117 * for type IO-APIC. 2118 */ 2119 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2120 ivhd_table_len += 8; 2121 } 2122 2123 /* IVHD length */ 2124 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2125 /* DeviceID */ 2126 build_append_int_noprefix(table_data, s->devid, 2); 2127 /* Capability offset */ 2128 build_append_int_noprefix(table_data, s->capab_offset, 2); 2129 /* IOMMU base address */ 2130 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2131 /* PCI Segment Group */ 2132 build_append_int_noprefix(table_data, 0, 2); 2133 /* IOMMU info */ 2134 build_append_int_noprefix(table_data, 0, 2); 2135 /* IOMMU Feature Reporting */ 2136 build_append_int_noprefix(table_data, 2137 (48UL << 30) | /* HATS */ 2138 (48UL << 28) | /* GATS */ 2139 (1UL << 2) | /* GTSup */ 2140 (1UL << 6), /* GASup */ 2141 4); 2142 2143 /* IVHD entries as found above */ 2144 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2145 g_array_free(ivhd_blob, TRUE); 2146 2147 /* 2148 * Add a special IVHD device type. 2149 * Refer to spec - Table 95: IVHD device entry type codes 2150 * 2151 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2152 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2153 */ 2154 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2155 build_append_int_noprefix(table_data, 2156 (0x1ull << 56) | /* type IOAPIC */ 2157 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2158 0x48, /* special device */ 2159 8); 2160 } 2161 2162 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2163 "IVRS", table_data->len - iommu_start, 1, oem_id, 2164 oem_table_id); 2165 } 2166 2167 typedef 2168 struct AcpiBuildState { 2169 /* Copy of table in RAM (for patching). */ 2170 MemoryRegion *table_mr; 2171 /* Is table patched? */ 2172 uint8_t patched; 2173 void *rsdp; 2174 MemoryRegion *rsdp_mr; 2175 MemoryRegion *linker_mr; 2176 } AcpiBuildState; 2177 2178 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2179 { 2180 Object *pci_host; 2181 QObject *o; 2182 2183 pci_host = acpi_get_i386_pci_host(); 2184 g_assert(pci_host); 2185 2186 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2187 if (!o) { 2188 return false; 2189 } 2190 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2191 qobject_unref(o); 2192 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2193 return false; 2194 } 2195 2196 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2197 assert(o); 2198 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2199 qobject_unref(o); 2200 return true; 2201 } 2202 2203 static 2204 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2205 { 2206 PCMachineState *pcms = PC_MACHINE(machine); 2207 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2208 X86MachineState *x86ms = X86_MACHINE(machine); 2209 GArray *table_offsets; 2210 unsigned facs, dsdt, rsdt, fadt; 2211 AcpiPmInfo pm; 2212 AcpiMiscInfo misc; 2213 AcpiMcfgInfo mcfg; 2214 Range pci_hole, pci_hole64; 2215 uint8_t *u; 2216 size_t aml_len = 0; 2217 GArray *tables_blob = tables->table_data; 2218 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2219 Object *vmgenid_dev; 2220 char *oem_id; 2221 char *oem_table_id; 2222 2223 acpi_get_pm_info(machine, &pm); 2224 acpi_get_misc_info(&misc); 2225 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2226 acpi_get_slic_oem(&slic_oem); 2227 2228 if (slic_oem.id) { 2229 oem_id = slic_oem.id; 2230 } else { 2231 oem_id = pcms->oem_id; 2232 } 2233 2234 if (slic_oem.table_id) { 2235 oem_table_id = slic_oem.table_id; 2236 } else { 2237 oem_table_id = pcms->oem_table_id; 2238 } 2239 2240 table_offsets = g_array_new(false, true /* clear */, 2241 sizeof(uint32_t)); 2242 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2243 2244 bios_linker_loader_alloc(tables->linker, 2245 ACPI_BUILD_TABLE_FILE, tables_blob, 2246 64 /* Ensure FACS is aligned */, 2247 false /* high memory */); 2248 2249 /* 2250 * FACS is pointed to by FADT. 2251 * We place it first since it's the only table that has alignment 2252 * requirements. 2253 */ 2254 facs = tables_blob->len; 2255 build_facs(tables_blob); 2256 2257 /* DSDT is pointed to by FADT */ 2258 dsdt = tables_blob->len; 2259 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2260 &pci_hole, &pci_hole64, machine); 2261 2262 /* Count the size of the DSDT and SSDT, we will need it for legacy 2263 * sizing of ACPI tables. 2264 */ 2265 aml_len += tables_blob->len - dsdt; 2266 2267 /* ACPI tables pointed to by RSDT */ 2268 fadt = tables_blob->len; 2269 acpi_add_table(table_offsets, tables_blob); 2270 pm.fadt.facs_tbl_offset = &facs; 2271 pm.fadt.dsdt_tbl_offset = &dsdt; 2272 pm.fadt.xdsdt_tbl_offset = &dsdt; 2273 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2274 aml_len += tables_blob->len - fadt; 2275 2276 acpi_add_table(table_offsets, tables_blob); 2277 acpi_build_madt(tables_blob, tables->linker, x86ms, 2278 ACPI_DEVICE_IF(x86ms->acpi_dev), pcms->oem_id, 2279 pcms->oem_table_id); 2280 2281 vmgenid_dev = find_vmgenid_dev(); 2282 if (vmgenid_dev) { 2283 acpi_add_table(table_offsets, tables_blob); 2284 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2285 tables->vmgenid, tables->linker, pcms->oem_id); 2286 } 2287 2288 if (misc.has_hpet) { 2289 acpi_add_table(table_offsets, tables_blob); 2290 build_hpet(tables_blob, tables->linker, pcms->oem_id, 2291 pcms->oem_table_id); 2292 } 2293 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2294 if (misc.tpm_version == TPM_VERSION_1_2) { 2295 acpi_add_table(table_offsets, tables_blob); 2296 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2297 pcms->oem_id, pcms->oem_table_id); 2298 } else { /* TPM_VERSION_2_0 */ 2299 acpi_add_table(table_offsets, tables_blob); 2300 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2301 pcms->oem_id, pcms->oem_table_id); 2302 } 2303 } 2304 if (pcms->numa_nodes) { 2305 acpi_add_table(table_offsets, tables_blob); 2306 build_srat(tables_blob, tables->linker, machine); 2307 if (machine->numa_state->have_numa_distance) { 2308 acpi_add_table(table_offsets, tables_blob); 2309 build_slit(tables_blob, tables->linker, machine, pcms->oem_id, 2310 pcms->oem_table_id); 2311 } 2312 if (machine->numa_state->hmat_enabled) { 2313 acpi_add_table(table_offsets, tables_blob); 2314 build_hmat(tables_blob, tables->linker, machine->numa_state, 2315 pcms->oem_id, pcms->oem_table_id); 2316 } 2317 } 2318 if (acpi_get_mcfg(&mcfg)) { 2319 acpi_add_table(table_offsets, tables_blob); 2320 build_mcfg(tables_blob, tables->linker, &mcfg, pcms->oem_id, 2321 pcms->oem_table_id); 2322 } 2323 if (x86_iommu_get_default()) { 2324 IommuType IOMMUType = x86_iommu_get_type(); 2325 if (IOMMUType == TYPE_AMD) { 2326 acpi_add_table(table_offsets, tables_blob); 2327 build_amd_iommu(tables_blob, tables->linker, pcms->oem_id, 2328 pcms->oem_table_id); 2329 } else if (IOMMUType == TYPE_INTEL) { 2330 acpi_add_table(table_offsets, tables_blob); 2331 build_dmar_q35(tables_blob, tables->linker, pcms->oem_id, 2332 pcms->oem_table_id); 2333 } 2334 } 2335 if (machine->nvdimms_state->is_enabled) { 2336 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2337 machine->nvdimms_state, machine->ram_slots, 2338 pcms->oem_id, pcms->oem_table_id); 2339 } 2340 2341 acpi_add_table(table_offsets, tables_blob); 2342 build_waet(tables_blob, tables->linker, pcms->oem_id, pcms->oem_table_id); 2343 2344 /* Add tables supplied by user (if any) */ 2345 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2346 unsigned len = acpi_table_len(u); 2347 2348 acpi_add_table(table_offsets, tables_blob); 2349 g_array_append_vals(tables_blob, u, len); 2350 } 2351 2352 /* RSDT is pointed to by RSDP */ 2353 rsdt = tables_blob->len; 2354 build_rsdt(tables_blob, tables->linker, table_offsets, 2355 oem_id, oem_table_id); 2356 2357 /* RSDP is in FSEG memory, so allocate it separately */ 2358 { 2359 AcpiRsdpData rsdp_data = { 2360 .revision = 0, 2361 .oem_id = pcms->oem_id, 2362 .xsdt_tbl_offset = NULL, 2363 .rsdt_tbl_offset = &rsdt, 2364 }; 2365 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2366 if (!pcmc->rsdp_in_ram) { 2367 /* We used to allocate some extra space for RSDP revision 2 but 2368 * only used the RSDP revision 0 space. The extra bytes were 2369 * zeroed out and not used. 2370 * Here we continue wasting those extra 16 bytes to make sure we 2371 * don't break migration for machine types 2.2 and older due to 2372 * RSDP blob size mismatch. 2373 */ 2374 build_append_int_noprefix(tables->rsdp, 0, 16); 2375 } 2376 } 2377 2378 /* We'll expose it all to Guest so we want to reduce 2379 * chance of size changes. 2380 * 2381 * We used to align the tables to 4k, but of course this would 2382 * too simple to be enough. 4k turned out to be too small an 2383 * alignment very soon, and in fact it is almost impossible to 2384 * keep the table size stable for all (max_cpus, max_memory_slots) 2385 * combinations. So the table size is always 64k for pc-i440fx-2.1 2386 * and we give an error if the table grows beyond that limit. 2387 * 2388 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2389 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2390 * than 2.0 and we can always pad the smaller tables with zeros. We can 2391 * then use the exact size of the 2.0 tables. 2392 * 2393 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2394 */ 2395 if (pcmc->legacy_acpi_table_size) { 2396 /* Subtracting aml_len gives the size of fixed tables. Then add the 2397 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2398 */ 2399 int legacy_aml_len = 2400 pcmc->legacy_acpi_table_size + 2401 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2402 int legacy_table_size = 2403 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2404 ACPI_BUILD_ALIGN_SIZE); 2405 if (tables_blob->len > legacy_table_size) { 2406 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2407 warn_report("ACPI table size %u exceeds %d bytes," 2408 " migration may not work", 2409 tables_blob->len, legacy_table_size); 2410 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2411 " or PCI bridges."); 2412 } 2413 g_array_set_size(tables_blob, legacy_table_size); 2414 } else { 2415 /* Make sure we have a buffer in case we need to resize the tables. */ 2416 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2417 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2418 warn_report("ACPI table size %u exceeds %d bytes," 2419 " migration may not work", 2420 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2421 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2422 " or PCI bridges."); 2423 } 2424 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2425 } 2426 2427 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2428 2429 /* Cleanup memory that's no longer used. */ 2430 g_array_free(table_offsets, true); 2431 } 2432 2433 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2434 { 2435 uint32_t size = acpi_data_len(data); 2436 2437 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2438 memory_region_ram_resize(mr, size, &error_abort); 2439 2440 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2441 memory_region_set_dirty(mr, 0, size); 2442 } 2443 2444 static void acpi_build_update(void *build_opaque) 2445 { 2446 AcpiBuildState *build_state = build_opaque; 2447 AcpiBuildTables tables; 2448 2449 /* No state to update or already patched? Nothing to do. */ 2450 if (!build_state || build_state->patched) { 2451 return; 2452 } 2453 build_state->patched = 1; 2454 2455 acpi_build_tables_init(&tables); 2456 2457 acpi_build(&tables, MACHINE(qdev_get_machine())); 2458 2459 acpi_ram_update(build_state->table_mr, tables.table_data); 2460 2461 if (build_state->rsdp) { 2462 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2463 } else { 2464 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2465 } 2466 2467 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2468 acpi_build_tables_cleanup(&tables, true); 2469 } 2470 2471 static void acpi_build_reset(void *build_opaque) 2472 { 2473 AcpiBuildState *build_state = build_opaque; 2474 build_state->patched = 0; 2475 } 2476 2477 static const VMStateDescription vmstate_acpi_build = { 2478 .name = "acpi_build", 2479 .version_id = 1, 2480 .minimum_version_id = 1, 2481 .fields = (VMStateField[]) { 2482 VMSTATE_UINT8(patched, AcpiBuildState), 2483 VMSTATE_END_OF_LIST() 2484 }, 2485 }; 2486 2487 void acpi_setup(void) 2488 { 2489 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2490 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2491 X86MachineState *x86ms = X86_MACHINE(pcms); 2492 AcpiBuildTables tables; 2493 AcpiBuildState *build_state; 2494 Object *vmgenid_dev; 2495 TPMIf *tpm; 2496 static FwCfgTPMConfig tpm_config; 2497 2498 if (!x86ms->fw_cfg) { 2499 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2500 return; 2501 } 2502 2503 if (!pcms->acpi_build_enabled) { 2504 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2505 return; 2506 } 2507 2508 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2509 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2510 return; 2511 } 2512 2513 build_state = g_malloc0(sizeof *build_state); 2514 2515 acpi_build_tables_init(&tables); 2516 acpi_build(&tables, MACHINE(pcms)); 2517 2518 /* Now expose it all to Guest */ 2519 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2520 build_state, tables.table_data, 2521 ACPI_BUILD_TABLE_FILE, 2522 ACPI_BUILD_TABLE_MAX_SIZE); 2523 assert(build_state->table_mr != NULL); 2524 2525 build_state->linker_mr = 2526 acpi_add_rom_blob(acpi_build_update, build_state, 2527 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 2528 2529 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2530 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2531 2532 tpm = tpm_find(); 2533 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2534 tpm_config = (FwCfgTPMConfig) { 2535 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2536 .tpm_version = tpm_get_version(tpm), 2537 .tpmppi_version = TPM_PPI_VERSION_1_30 2538 }; 2539 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2540 &tpm_config, sizeof tpm_config); 2541 } 2542 2543 vmgenid_dev = find_vmgenid_dev(); 2544 if (vmgenid_dev) { 2545 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2546 tables.vmgenid); 2547 } 2548 2549 if (!pcmc->rsdp_in_ram) { 2550 /* 2551 * Keep for compatibility with old machine types. 2552 * Though RSDP is small, its contents isn't immutable, so 2553 * we'll update it along with the rest of tables on guest access. 2554 */ 2555 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2556 2557 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2558 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2559 acpi_build_update, NULL, build_state, 2560 build_state->rsdp, rsdp_size, true); 2561 build_state->rsdp_mr = NULL; 2562 } else { 2563 build_state->rsdp = NULL; 2564 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2565 build_state, tables.rsdp, 2566 ACPI_BUILD_RSDP_FILE, 0); 2567 } 2568 2569 qemu_register_reset(acpi_build_reset, build_state); 2570 acpi_build_reset(build_state); 2571 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2572 2573 /* Cleanup tables but don't free the memory: we track it 2574 * in build_state. 2575 */ 2576 acpi_build_tables_cleanup(&tables, false); 2577 } 2578