1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "acpi-build.h" 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "hw/i386/pc.h" 32 #include "target/i386/cpu.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/acpi/bios-linker-loader.h" 39 #include "hw/loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "sysemu/tpm_backend.h" 47 #include "hw/timer/mc146818rtc_regs.h" 48 #include "sysemu/numa.h" 49 50 /* Supported chipsets: */ 51 #include "hw/acpi/piix4.h" 52 #include "hw/acpi/pcihp.h" 53 #include "hw/i386/ich9.h" 54 #include "hw/pci/pci_bus.h" 55 #include "hw/pci-host/q35.h" 56 #include "hw/i386/x86-iommu.h" 57 58 #include "hw/acpi/aml-build.h" 59 60 #include "qapi/qmp/qint.h" 61 #include "qom/qom-qobject.h" 62 #include "hw/i386/amd_iommu.h" 63 #include "hw/i386/intel_iommu.h" 64 65 #include "hw/acpi/ipmi.h" 66 67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 69 * a little bit, there should be plenty of free space since the DSDT 70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 71 */ 72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 73 #define ACPI_BUILD_ALIGN_SIZE 0x1000 74 75 #define ACPI_BUILD_TABLE_SIZE 0x20000 76 77 /* #define DEBUG_ACPI_BUILD */ 78 #ifdef DEBUG_ACPI_BUILD 79 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 81 #else 82 #define ACPI_BUILD_DPRINTF(fmt, ...) 83 #endif 84 85 /* Default IOAPIC ID */ 86 #define ACPI_BUILD_IOAPIC_ID 0x0 87 88 typedef struct AcpiMcfgInfo { 89 uint64_t mcfg_base; 90 uint32_t mcfg_size; 91 } AcpiMcfgInfo; 92 93 typedef struct AcpiPmInfo { 94 bool s3_disabled; 95 bool s4_disabled; 96 bool pcihp_bridge_en; 97 uint8_t s4_val; 98 uint16_t sci_int; 99 uint8_t acpi_enable_cmd; 100 uint8_t acpi_disable_cmd; 101 uint32_t gpe0_blk; 102 uint32_t gpe0_blk_len; 103 uint32_t io_base; 104 uint16_t cpu_hp_io_base; 105 uint16_t pcihp_io_base; 106 uint16_t pcihp_io_len; 107 } AcpiPmInfo; 108 109 typedef struct AcpiMiscInfo { 110 bool is_piix4; 111 bool has_hpet; 112 TPMVersion tpm_version; 113 const unsigned char *dsdt_code; 114 unsigned dsdt_size; 115 uint16_t pvpanic_port; 116 uint16_t applesmc_io_base; 117 } AcpiMiscInfo; 118 119 typedef struct AcpiBuildPciBusHotplugState { 120 GArray *device_table; 121 GArray *notify_table; 122 struct AcpiBuildPciBusHotplugState *parent; 123 bool pcihp_bridge_en; 124 } AcpiBuildPciBusHotplugState; 125 126 static void acpi_get_pm_info(AcpiPmInfo *pm) 127 { 128 Object *piix = piix4_pm_find(); 129 Object *lpc = ich9_lpc_find(); 130 Object *obj = NULL; 131 QObject *o; 132 133 pm->cpu_hp_io_base = 0; 134 pm->pcihp_io_base = 0; 135 pm->pcihp_io_len = 0; 136 if (piix) { 137 obj = piix; 138 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 139 pm->pcihp_io_base = 140 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 141 pm->pcihp_io_len = 142 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 143 } 144 if (lpc) { 145 obj = lpc; 146 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 147 } 148 assert(obj); 149 150 /* Fill in optional s3/s4 related properties */ 151 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 152 if (o) { 153 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 154 } else { 155 pm->s3_disabled = false; 156 } 157 qobject_decref(o); 158 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 159 if (o) { 160 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 161 } else { 162 pm->s4_disabled = false; 163 } 164 qobject_decref(o); 165 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 166 if (o) { 167 pm->s4_val = qint_get_int(qobject_to_qint(o)); 168 } else { 169 pm->s4_val = false; 170 } 171 qobject_decref(o); 172 173 /* Fill in mandatory properties */ 174 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 175 176 pm->acpi_enable_cmd = object_property_get_int(obj, 177 ACPI_PM_PROP_ACPI_ENABLE_CMD, 178 NULL); 179 pm->acpi_disable_cmd = object_property_get_int(obj, 180 ACPI_PM_PROP_ACPI_DISABLE_CMD, 181 NULL); 182 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 183 NULL); 184 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 185 NULL); 186 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 187 NULL); 188 pm->pcihp_bridge_en = 189 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 190 NULL); 191 } 192 193 static void acpi_get_misc_info(AcpiMiscInfo *info) 194 { 195 Object *piix = piix4_pm_find(); 196 Object *lpc = ich9_lpc_find(); 197 assert(!!piix != !!lpc); 198 199 if (piix) { 200 info->is_piix4 = true; 201 } 202 if (lpc) { 203 info->is_piix4 = false; 204 } 205 206 info->has_hpet = hpet_find(); 207 info->tpm_version = tpm_get_version(); 208 info->pvpanic_port = pvpanic_port(); 209 info->applesmc_io_base = applesmc_port(); 210 } 211 212 /* 213 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 214 * On i386 arch we only have two pci hosts, so we can look only for them. 215 */ 216 static Object *acpi_get_i386_pci_host(void) 217 { 218 PCIHostState *host; 219 220 host = OBJECT_CHECK(PCIHostState, 221 object_resolve_path("/machine/i440fx", NULL), 222 TYPE_PCI_HOST_BRIDGE); 223 if (!host) { 224 host = OBJECT_CHECK(PCIHostState, 225 object_resolve_path("/machine/q35", NULL), 226 TYPE_PCI_HOST_BRIDGE); 227 } 228 229 return OBJECT(host); 230 } 231 232 static void acpi_get_pci_holes(Range *hole, Range *hole64) 233 { 234 Object *pci_host; 235 236 pci_host = acpi_get_i386_pci_host(); 237 g_assert(pci_host); 238 239 range_set_bounds1(hole, 240 object_property_get_int(pci_host, 241 PCI_HOST_PROP_PCI_HOLE_START, 242 NULL), 243 object_property_get_int(pci_host, 244 PCI_HOST_PROP_PCI_HOLE_END, 245 NULL)); 246 range_set_bounds1(hole64, 247 object_property_get_int(pci_host, 248 PCI_HOST_PROP_PCI_HOLE64_START, 249 NULL), 250 object_property_get_int(pci_host, 251 PCI_HOST_PROP_PCI_HOLE64_END, 252 NULL)); 253 } 254 255 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 256 257 static void acpi_align_size(GArray *blob, unsigned align) 258 { 259 /* Align size to multiple of given size. This reduces the chance 260 * we need to change size in the future (breaking cross version migration). 261 */ 262 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 263 } 264 265 /* FACS */ 266 static void 267 build_facs(GArray *table_data, BIOSLinker *linker) 268 { 269 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 270 memcpy(&facs->signature, "FACS", 4); 271 facs->length = cpu_to_le32(sizeof(*facs)); 272 } 273 274 /* Load chipset information in FADT */ 275 static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiPmInfo *pm) 276 { 277 fadt->model = 1; 278 fadt->reserved1 = 0; 279 fadt->sci_int = cpu_to_le16(pm->sci_int); 280 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 281 fadt->acpi_enable = pm->acpi_enable_cmd; 282 fadt->acpi_disable = pm->acpi_disable_cmd; 283 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 284 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 285 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 286 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 287 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 288 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 289 fadt->pm1_evt_len = 4; 290 fadt->pm1_cnt_len = 2; 291 fadt->pm_tmr_len = 4; 292 fadt->gpe0_blk_len = pm->gpe0_blk_len; 293 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 294 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 295 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 296 (1 << ACPI_FADT_F_PROC_C1) | 297 (1 << ACPI_FADT_F_SLP_BUTTON) | 298 (1 << ACPI_FADT_F_RTC_S4)); 299 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 300 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 301 * For more than 8 CPUs, "Clustered Logical" mode has to be used 302 */ 303 if (max_cpus > 8) { 304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 305 } 306 fadt->century = RTC_CENTURY; 307 308 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_RESET_REG_SUP); 309 fadt->reset_value = 0xf; 310 fadt->reset_register.space_id = AML_SYSTEM_IO; 311 fadt->reset_register.bit_width = 8; 312 fadt->reset_register.address = cpu_to_le64(ICH9_RST_CNT_IOPORT); 313 /* The above need not be conditional on machine type because the reset port 314 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 315 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); 316 317 fadt->xpm1a_event_block.space_id = AML_SYSTEM_IO; 318 fadt->xpm1a_event_block.bit_width = fadt->pm1_evt_len * 8; 319 fadt->xpm1a_event_block.address = cpu_to_le64(pm->io_base); 320 321 fadt->xpm1a_control_block.space_id = AML_SYSTEM_IO; 322 fadt->xpm1a_control_block.bit_width = fadt->pm1_cnt_len * 8; 323 fadt->xpm1a_control_block.address = cpu_to_le64(pm->io_base + 0x4); 324 325 fadt->xpm_timer_block.space_id = AML_SYSTEM_IO; 326 fadt->xpm_timer_block.bit_width = fadt->pm_tmr_len * 8; 327 fadt->xpm_timer_block.address = cpu_to_le64(pm->io_base + 0x8); 328 329 fadt->xgpe0_block.space_id = AML_SYSTEM_IO; 330 fadt->xgpe0_block.bit_width = pm->gpe0_blk_len * 8; 331 fadt->xgpe0_block.address = cpu_to_le64(pm->gpe0_blk); 332 } 333 334 335 /* FADT */ 336 static void 337 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, 338 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset, 339 const char *oem_id, const char *oem_table_id) 340 { 341 AcpiFadtDescriptorRev3 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 342 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data; 343 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data; 344 unsigned xdsdt_entry_offset = (char *)&fadt->Xdsdt - table_data->data; 345 346 /* FACS address to be filled by Guest linker */ 347 bios_linker_loader_add_pointer(linker, 348 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl), 349 ACPI_BUILD_TABLE_FILE, facs_tbl_offset); 350 351 /* DSDT address to be filled by Guest linker */ 352 fadt_setup(fadt, pm); 353 bios_linker_loader_add_pointer(linker, 354 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt), 355 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); 356 bios_linker_loader_add_pointer(linker, 357 ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->Xdsdt), 358 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset); 359 360 build_header(linker, table_data, 361 (void *)fadt, "FACP", sizeof(*fadt), 3, oem_id, oem_table_id); 362 } 363 364 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 365 const CPUArchIdList *apic_ids, GArray *entry) 366 { 367 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 368 369 /* ACPI spec says that LAPIC entry for non present 370 * CPU may be omitted from MADT or it must be marked 371 * as disabled. However omitting non present CPU from 372 * MADT breaks hotplug on linux. So possible CPUs 373 * should be put in MADT but kept disabled. 374 */ 375 if (apic_id < 255) { 376 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 377 378 apic->type = ACPI_APIC_PROCESSOR; 379 apic->length = sizeof(*apic); 380 apic->processor_id = uid; 381 apic->local_apic_id = apic_id; 382 if (apic_ids->cpus[uid].cpu != NULL) { 383 apic->flags = cpu_to_le32(1); 384 } else { 385 apic->flags = cpu_to_le32(0); 386 } 387 } else { 388 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 389 390 apic->type = ACPI_APIC_LOCAL_X2APIC; 391 apic->length = sizeof(*apic); 392 apic->uid = cpu_to_le32(uid); 393 apic->x2apic_id = cpu_to_le32(apic_id); 394 if (apic_ids->cpus[uid].cpu != NULL) { 395 apic->flags = cpu_to_le32(1); 396 } else { 397 apic->flags = cpu_to_le32(0); 398 } 399 } 400 } 401 402 static void 403 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 404 { 405 MachineClass *mc = MACHINE_GET_CLASS(pcms); 406 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 407 int madt_start = table_data->len; 408 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 409 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 410 bool x2apic_mode = false; 411 412 AcpiMultipleApicTable *madt; 413 AcpiMadtIoApic *io_apic; 414 AcpiMadtIntsrcovr *intsrcovr; 415 int i; 416 417 madt = acpi_data_push(table_data, sizeof *madt); 418 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 419 madt->flags = cpu_to_le32(1); 420 421 for (i = 0; i < apic_ids->len; i++) { 422 adevc->madt_cpu(adev, i, apic_ids, table_data); 423 if (apic_ids->cpus[i].arch_id > 254) { 424 x2apic_mode = true; 425 } 426 } 427 428 io_apic = acpi_data_push(table_data, sizeof *io_apic); 429 io_apic->type = ACPI_APIC_IO; 430 io_apic->length = sizeof(*io_apic); 431 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 432 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 433 io_apic->interrupt = cpu_to_le32(0); 434 435 if (pcms->apic_xrupt_override) { 436 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 437 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 438 intsrcovr->length = sizeof(*intsrcovr); 439 intsrcovr->source = 0; 440 intsrcovr->gsi = cpu_to_le32(2); 441 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 442 } 443 for (i = 1; i < 16; i++) { 444 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 445 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 446 /* No need for a INT source override structure. */ 447 continue; 448 } 449 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 450 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 451 intsrcovr->length = sizeof(*intsrcovr); 452 intsrcovr->source = i; 453 intsrcovr->gsi = cpu_to_le32(i); 454 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 455 } 456 457 if (x2apic_mode) { 458 AcpiMadtLocalX2ApicNmi *local_nmi; 459 460 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 461 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 462 local_nmi->length = sizeof(*local_nmi); 463 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 464 local_nmi->flags = cpu_to_le16(0); 465 local_nmi->lint = 1; /* ACPI_LINT1 */ 466 } else { 467 AcpiMadtLocalNmi *local_nmi; 468 469 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 470 local_nmi->type = ACPI_APIC_LOCAL_NMI; 471 local_nmi->length = sizeof(*local_nmi); 472 local_nmi->processor_id = 0xff; /* all processors */ 473 local_nmi->flags = cpu_to_le16(0); 474 local_nmi->lint = 1; /* ACPI_LINT1 */ 475 } 476 477 build_header(linker, table_data, 478 (void *)(table_data->data + madt_start), "APIC", 479 table_data->len - madt_start, 1, NULL, NULL); 480 } 481 482 /* Assign BSEL property to all buses. In the future, this can be changed 483 * to only assign to buses that support hotplug. 484 */ 485 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 486 { 487 unsigned *bsel_alloc = opaque; 488 unsigned *bus_bsel; 489 490 if (qbus_is_hotpluggable(BUS(bus))) { 491 bus_bsel = g_malloc(sizeof *bus_bsel); 492 493 *bus_bsel = (*bsel_alloc)++; 494 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 495 bus_bsel, &error_abort); 496 } 497 498 return bsel_alloc; 499 } 500 501 static void acpi_set_pci_info(void) 502 { 503 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 504 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT; 505 506 if (bus) { 507 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 508 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 509 } 510 } 511 512 static void build_append_pcihp_notify_entry(Aml *method, int slot) 513 { 514 Aml *if_ctx; 515 int32_t devfn = PCI_DEVFN(slot, 0); 516 517 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 518 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 519 aml_append(method, if_ctx); 520 } 521 522 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 523 bool pcihp_bridge_en) 524 { 525 Aml *dev, *notify_method, *method; 526 QObject *bsel; 527 PCIBus *sec; 528 int i; 529 530 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 531 if (bsel) { 532 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 533 534 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 535 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 536 } 537 538 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 539 DeviceClass *dc; 540 PCIDeviceClass *pc; 541 PCIDevice *pdev = bus->devices[i]; 542 int slot = PCI_SLOT(i); 543 bool hotplug_enabled_dev; 544 bool bridge_in_acpi; 545 546 if (!pdev) { 547 if (bsel) { /* add hotplug slots for non present devices */ 548 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 549 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 550 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 551 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 552 aml_append(method, 553 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 554 ); 555 aml_append(dev, method); 556 aml_append(parent_scope, dev); 557 558 build_append_pcihp_notify_entry(notify_method, slot); 559 } 560 continue; 561 } 562 563 pc = PCI_DEVICE_GET_CLASS(pdev); 564 dc = DEVICE_GET_CLASS(pdev); 565 566 /* When hotplug for bridges is enabled, bridges are 567 * described in ACPI separately (see build_pci_bus_end). 568 * In this case they aren't themselves hot-pluggable. 569 * Hotplugged bridges *are* hot-pluggable. 570 */ 571 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 572 !DEVICE(pdev)->hotplugged; 573 574 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 575 576 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 577 continue; 578 } 579 580 /* start to compose PCI slot descriptor */ 581 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 582 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 583 584 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 585 /* add VGA specific AML methods */ 586 int s3d; 587 588 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 589 s3d = 3; 590 } else { 591 s3d = 0; 592 } 593 594 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 595 aml_append(method, aml_return(aml_int(0))); 596 aml_append(dev, method); 597 598 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 599 aml_append(method, aml_return(aml_int(0))); 600 aml_append(dev, method); 601 602 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 603 aml_append(method, aml_return(aml_int(s3d))); 604 aml_append(dev, method); 605 } else if (hotplug_enabled_dev) { 606 /* add _SUN/_EJ0 to make slot hotpluggable */ 607 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 608 609 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 610 aml_append(method, 611 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 612 ); 613 aml_append(dev, method); 614 615 if (bsel) { 616 build_append_pcihp_notify_entry(notify_method, slot); 617 } 618 } else if (bridge_in_acpi) { 619 /* 620 * device is coldplugged bridge, 621 * add child device descriptions into its scope 622 */ 623 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 624 625 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 626 } 627 /* slot descriptor has been composed, add it into parent context */ 628 aml_append(parent_scope, dev); 629 } 630 631 if (bsel) { 632 aml_append(parent_scope, notify_method); 633 } 634 635 /* Append PCNT method to notify about events on local and child buses. 636 * Add unconditionally for root since DSDT expects it. 637 */ 638 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 639 640 /* If bus supports hotplug select it and notify about local events */ 641 if (bsel) { 642 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 643 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 644 aml_append(method, 645 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 646 ); 647 aml_append(method, 648 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 649 ); 650 } 651 652 /* Notify about child bus events in any case */ 653 if (pcihp_bridge_en) { 654 QLIST_FOREACH(sec, &bus->child, sibling) { 655 int32_t devfn = sec->parent_dev->devfn; 656 657 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 658 continue; 659 } 660 661 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 662 } 663 } 664 aml_append(parent_scope, method); 665 qobject_decref(bsel); 666 } 667 668 /** 669 * build_prt_entry: 670 * @link_name: link name for PCI route entry 671 * 672 * build AML package containing a PCI route entry for @link_name 673 */ 674 static Aml *build_prt_entry(const char *link_name) 675 { 676 Aml *a_zero = aml_int(0); 677 Aml *pkg = aml_package(4); 678 aml_append(pkg, a_zero); 679 aml_append(pkg, a_zero); 680 aml_append(pkg, aml_name("%s", link_name)); 681 aml_append(pkg, a_zero); 682 return pkg; 683 } 684 685 /* 686 * initialize_route - Initialize the interrupt routing rule 687 * through a specific LINK: 688 * if (lnk_idx == idx) 689 * route using link 'link_name' 690 */ 691 static Aml *initialize_route(Aml *route, const char *link_name, 692 Aml *lnk_idx, int idx) 693 { 694 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 695 Aml *pkg = build_prt_entry(link_name); 696 697 aml_append(if_ctx, aml_store(pkg, route)); 698 699 return if_ctx; 700 } 701 702 /* 703 * build_prt - Define interrupt rounting rules 704 * 705 * Returns an array of 128 routes, one for each device, 706 * based on device location. 707 * The main goal is to equaly distribute the interrupts 708 * over the 4 existing ACPI links (works only for i440fx). 709 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 710 * 711 */ 712 static Aml *build_prt(bool is_pci0_prt) 713 { 714 Aml *method, *while_ctx, *pin, *res; 715 716 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 717 res = aml_local(0); 718 pin = aml_local(1); 719 aml_append(method, aml_store(aml_package(128), res)); 720 aml_append(method, aml_store(aml_int(0), pin)); 721 722 /* while (pin < 128) */ 723 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 724 { 725 Aml *slot = aml_local(2); 726 Aml *lnk_idx = aml_local(3); 727 Aml *route = aml_local(4); 728 729 /* slot = pin >> 2 */ 730 aml_append(while_ctx, 731 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 732 /* lnk_idx = (slot + pin) & 3 */ 733 aml_append(while_ctx, 734 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 735 lnk_idx)); 736 737 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 738 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 739 if (is_pci0_prt) { 740 Aml *if_device_1, *if_pin_4, *else_pin_4; 741 742 /* device 1 is the power-management device, needs SCI */ 743 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 744 { 745 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 746 { 747 aml_append(if_pin_4, 748 aml_store(build_prt_entry("LNKS"), route)); 749 } 750 aml_append(if_device_1, if_pin_4); 751 else_pin_4 = aml_else(); 752 { 753 aml_append(else_pin_4, 754 aml_store(build_prt_entry("LNKA"), route)); 755 } 756 aml_append(if_device_1, else_pin_4); 757 } 758 aml_append(while_ctx, if_device_1); 759 } else { 760 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 761 } 762 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 763 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 764 765 /* route[0] = 0x[slot]FFFF */ 766 aml_append(while_ctx, 767 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 768 NULL), 769 aml_index(route, aml_int(0)))); 770 /* route[1] = pin & 3 */ 771 aml_append(while_ctx, 772 aml_store(aml_and(pin, aml_int(3), NULL), 773 aml_index(route, aml_int(1)))); 774 /* res[pin] = route */ 775 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 776 /* pin++ */ 777 aml_append(while_ctx, aml_increment(pin)); 778 } 779 aml_append(method, while_ctx); 780 /* return res*/ 781 aml_append(method, aml_return(res)); 782 783 return method; 784 } 785 786 typedef struct CrsRangeEntry { 787 uint64_t base; 788 uint64_t limit; 789 } CrsRangeEntry; 790 791 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 792 { 793 CrsRangeEntry *entry; 794 795 entry = g_malloc(sizeof(*entry)); 796 entry->base = base; 797 entry->limit = limit; 798 799 g_ptr_array_add(ranges, entry); 800 } 801 802 static void crs_range_free(gpointer data) 803 { 804 CrsRangeEntry *entry = (CrsRangeEntry *)data; 805 g_free(entry); 806 } 807 808 typedef struct CrsRangeSet { 809 GPtrArray *io_ranges; 810 GPtrArray *mem_ranges; 811 GPtrArray *mem_64bit_ranges; 812 } CrsRangeSet; 813 814 static void crs_range_set_init(CrsRangeSet *range_set) 815 { 816 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 817 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 818 range_set->mem_64bit_ranges = 819 g_ptr_array_new_with_free_func(crs_range_free); 820 } 821 822 static void crs_range_set_free(CrsRangeSet *range_set) 823 { 824 g_ptr_array_free(range_set->io_ranges, true); 825 g_ptr_array_free(range_set->mem_ranges, true); 826 g_ptr_array_free(range_set->mem_64bit_ranges, true); 827 } 828 829 static gint crs_range_compare(gconstpointer a, gconstpointer b) 830 { 831 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 832 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 833 834 return (int64_t)entry_a->base - (int64_t)entry_b->base; 835 } 836 837 /* 838 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 839 * interval, computes the 'free' ranges from the same interval. 840 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 841 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 842 */ 843 static void crs_replace_with_free_ranges(GPtrArray *ranges, 844 uint64_t start, uint64_t end) 845 { 846 GPtrArray *free_ranges = g_ptr_array_new(); 847 uint64_t free_base = start; 848 int i; 849 850 g_ptr_array_sort(ranges, crs_range_compare); 851 for (i = 0; i < ranges->len; i++) { 852 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 853 854 if (free_base < used->base) { 855 crs_range_insert(free_ranges, free_base, used->base - 1); 856 } 857 858 free_base = used->limit + 1; 859 } 860 861 if (free_base < end) { 862 crs_range_insert(free_ranges, free_base, end); 863 } 864 865 g_ptr_array_set_size(ranges, 0); 866 for (i = 0; i < free_ranges->len; i++) { 867 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 868 } 869 870 g_ptr_array_free(free_ranges, true); 871 } 872 873 /* 874 * crs_range_merge - merges adjacent ranges in the given array. 875 * Array elements are deleted and replaced with the merged ranges. 876 */ 877 static void crs_range_merge(GPtrArray *range) 878 { 879 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 880 CrsRangeEntry *entry; 881 uint64_t range_base, range_limit; 882 int i; 883 884 if (!range->len) { 885 return; 886 } 887 888 g_ptr_array_sort(range, crs_range_compare); 889 890 entry = g_ptr_array_index(range, 0); 891 range_base = entry->base; 892 range_limit = entry->limit; 893 for (i = 1; i < range->len; i++) { 894 entry = g_ptr_array_index(range, i); 895 if (entry->base - 1 == range_limit) { 896 range_limit = entry->limit; 897 } else { 898 crs_range_insert(tmp, range_base, range_limit); 899 range_base = entry->base; 900 range_limit = entry->limit; 901 } 902 } 903 crs_range_insert(tmp, range_base, range_limit); 904 905 g_ptr_array_set_size(range, 0); 906 for (i = 0; i < tmp->len; i++) { 907 entry = g_ptr_array_index(tmp, i); 908 crs_range_insert(range, entry->base, entry->limit); 909 } 910 g_ptr_array_free(tmp, true); 911 } 912 913 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 914 { 915 Aml *crs = aml_resource_template(); 916 CrsRangeSet temp_range_set; 917 CrsRangeEntry *entry; 918 uint8_t max_bus = pci_bus_num(host->bus); 919 uint8_t type; 920 int devfn; 921 int i; 922 923 crs_range_set_init(&temp_range_set); 924 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 925 uint64_t range_base, range_limit; 926 PCIDevice *dev = host->bus->devices[devfn]; 927 928 if (!dev) { 929 continue; 930 } 931 932 for (i = 0; i < PCI_NUM_REGIONS; i++) { 933 PCIIORegion *r = &dev->io_regions[i]; 934 935 range_base = r->addr; 936 range_limit = r->addr + r->size - 1; 937 938 /* 939 * Work-around for old bioses 940 * that do not support multiple root buses 941 */ 942 if (!range_base || range_base > range_limit) { 943 continue; 944 } 945 946 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 947 crs_range_insert(temp_range_set.io_ranges, 948 range_base, range_limit); 949 } else { /* "memory" */ 950 crs_range_insert(temp_range_set.mem_ranges, 951 range_base, range_limit); 952 } 953 } 954 955 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 956 if (type == PCI_HEADER_TYPE_BRIDGE) { 957 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 958 if (subordinate > max_bus) { 959 max_bus = subordinate; 960 } 961 962 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 963 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 964 965 /* 966 * Work-around for old bioses 967 * that do not support multiple root buses 968 */ 969 if (range_base && range_base <= range_limit) { 970 crs_range_insert(temp_range_set.io_ranges, 971 range_base, range_limit); 972 } 973 974 range_base = 975 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 976 range_limit = 977 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 978 979 /* 980 * Work-around for old bioses 981 * that do not support multiple root buses 982 */ 983 if (range_base && range_base <= range_limit) { 984 uint64_t length = range_limit - range_base + 1; 985 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 986 crs_range_insert(temp_range_set.mem_ranges, 987 range_base, range_limit); 988 } else { 989 crs_range_insert(temp_range_set.mem_64bit_ranges, 990 range_base, range_limit); 991 } 992 } 993 994 range_base = 995 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 996 range_limit = 997 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 998 999 /* 1000 * Work-around for old bioses 1001 * that do not support multiple root buses 1002 */ 1003 if (range_base && range_base <= range_limit) { 1004 uint64_t length = range_limit - range_base + 1; 1005 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 1006 crs_range_insert(temp_range_set.mem_ranges, 1007 range_base, range_limit); 1008 } else { 1009 crs_range_insert(temp_range_set.mem_64bit_ranges, 1010 range_base, range_limit); 1011 } 1012 } 1013 } 1014 } 1015 1016 crs_range_merge(temp_range_set.io_ranges); 1017 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 1018 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 1019 aml_append(crs, 1020 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1021 AML_POS_DECODE, AML_ENTIRE_RANGE, 1022 0, entry->base, entry->limit, 0, 1023 entry->limit - entry->base + 1)); 1024 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 1025 } 1026 1027 crs_range_merge(temp_range_set.mem_ranges); 1028 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 1029 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 1030 aml_append(crs, 1031 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1032 AML_MAX_FIXED, AML_NON_CACHEABLE, 1033 AML_READ_WRITE, 1034 0, entry->base, entry->limit, 0, 1035 entry->limit - entry->base + 1)); 1036 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 1037 } 1038 1039 crs_range_merge(temp_range_set.mem_64bit_ranges); 1040 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 1041 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 1042 aml_append(crs, 1043 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1044 AML_MAX_FIXED, AML_NON_CACHEABLE, 1045 AML_READ_WRITE, 1046 0, entry->base, entry->limit, 0, 1047 entry->limit - entry->base + 1)); 1048 crs_range_insert(range_set->mem_64bit_ranges, 1049 entry->base, entry->limit); 1050 } 1051 1052 crs_range_set_free(&temp_range_set); 1053 1054 aml_append(crs, 1055 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1056 0, 1057 pci_bus_num(host->bus), 1058 max_bus, 1059 0, 1060 max_bus - pci_bus_num(host->bus) + 1)); 1061 1062 return crs; 1063 } 1064 1065 static void build_hpet_aml(Aml *table) 1066 { 1067 Aml *crs; 1068 Aml *field; 1069 Aml *method; 1070 Aml *if_ctx; 1071 Aml *scope = aml_scope("_SB"); 1072 Aml *dev = aml_device("HPET"); 1073 Aml *zero = aml_int(0); 1074 Aml *id = aml_local(0); 1075 Aml *period = aml_local(1); 1076 1077 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1078 aml_append(dev, aml_name_decl("_UID", zero)); 1079 1080 aml_append(dev, 1081 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1082 HPET_LEN)); 1083 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1084 aml_append(field, aml_named_field("VEND", 32)); 1085 aml_append(field, aml_named_field("PRD", 32)); 1086 aml_append(dev, field); 1087 1088 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1089 aml_append(method, aml_store(aml_name("VEND"), id)); 1090 aml_append(method, aml_store(aml_name("PRD"), period)); 1091 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1092 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1093 aml_equal(id, aml_int(0xffff)))); 1094 { 1095 aml_append(if_ctx, aml_return(zero)); 1096 } 1097 aml_append(method, if_ctx); 1098 1099 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1100 aml_lgreater(period, aml_int(100000000)))); 1101 { 1102 aml_append(if_ctx, aml_return(zero)); 1103 } 1104 aml_append(method, if_ctx); 1105 1106 aml_append(method, aml_return(aml_int(0x0F))); 1107 aml_append(dev, method); 1108 1109 crs = aml_resource_template(); 1110 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1111 aml_append(dev, aml_name_decl("_CRS", crs)); 1112 1113 aml_append(scope, dev); 1114 aml_append(table, scope); 1115 } 1116 1117 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1118 { 1119 Aml *dev, *fdi; 1120 uint8_t maxc, maxh, maxs; 1121 1122 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1123 1124 dev = aml_device("FLP%c", 'A' + idx); 1125 1126 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1127 1128 fdi = aml_package(16); 1129 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1130 aml_append(fdi, 1131 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1132 /* 1133 * the values below are the limits of the drive, and are thus independent 1134 * of the inserted media 1135 */ 1136 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1137 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1138 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1139 /* 1140 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1141 * the drive type, so shall we 1142 */ 1143 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1144 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1145 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1146 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1147 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1148 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1149 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1150 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1151 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1152 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1153 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1154 1155 aml_append(dev, aml_name_decl("_FDI", fdi)); 1156 return dev; 1157 } 1158 1159 static Aml *build_fdc_device_aml(ISADevice *fdc) 1160 { 1161 int i; 1162 Aml *dev; 1163 Aml *crs; 1164 1165 #define ACPI_FDE_MAX_FD 4 1166 uint32_t fde_buf[5] = { 1167 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1168 cpu_to_le32(2) /* tape presence (2 == never present) */ 1169 }; 1170 1171 dev = aml_device("FDC0"); 1172 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1173 1174 crs = aml_resource_template(); 1175 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1176 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1177 aml_append(crs, aml_irq_no_flags(6)); 1178 aml_append(crs, 1179 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1180 aml_append(dev, aml_name_decl("_CRS", crs)); 1181 1182 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1183 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1184 1185 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1186 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1187 aml_append(dev, build_fdinfo_aml(i, type)); 1188 } 1189 } 1190 aml_append(dev, aml_name_decl("_FDE", 1191 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1192 1193 return dev; 1194 } 1195 1196 static Aml *build_rtc_device_aml(void) 1197 { 1198 Aml *dev; 1199 Aml *crs; 1200 1201 dev = aml_device("RTC"); 1202 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1203 crs = aml_resource_template(); 1204 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1205 aml_append(crs, aml_irq_no_flags(8)); 1206 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1207 aml_append(dev, aml_name_decl("_CRS", crs)); 1208 1209 return dev; 1210 } 1211 1212 static Aml *build_kbd_device_aml(void) 1213 { 1214 Aml *dev; 1215 Aml *crs; 1216 Aml *method; 1217 1218 dev = aml_device("KBD"); 1219 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1220 1221 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1222 aml_append(method, aml_return(aml_int(0x0f))); 1223 aml_append(dev, method); 1224 1225 crs = aml_resource_template(); 1226 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1227 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1228 aml_append(crs, aml_irq_no_flags(1)); 1229 aml_append(dev, aml_name_decl("_CRS", crs)); 1230 1231 return dev; 1232 } 1233 1234 static Aml *build_mouse_device_aml(void) 1235 { 1236 Aml *dev; 1237 Aml *crs; 1238 Aml *method; 1239 1240 dev = aml_device("MOU"); 1241 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1242 1243 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1244 aml_append(method, aml_return(aml_int(0x0f))); 1245 aml_append(dev, method); 1246 1247 crs = aml_resource_template(); 1248 aml_append(crs, aml_irq_no_flags(12)); 1249 aml_append(dev, aml_name_decl("_CRS", crs)); 1250 1251 return dev; 1252 } 1253 1254 static Aml *build_lpt_device_aml(void) 1255 { 1256 Aml *dev; 1257 Aml *crs; 1258 Aml *method; 1259 Aml *if_ctx; 1260 Aml *else_ctx; 1261 Aml *zero = aml_int(0); 1262 Aml *is_present = aml_local(0); 1263 1264 dev = aml_device("LPT"); 1265 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1266 1267 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1268 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1269 if_ctx = aml_if(aml_equal(is_present, zero)); 1270 { 1271 aml_append(if_ctx, aml_return(aml_int(0x00))); 1272 } 1273 aml_append(method, if_ctx); 1274 else_ctx = aml_else(); 1275 { 1276 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1277 } 1278 aml_append(method, else_ctx); 1279 aml_append(dev, method); 1280 1281 crs = aml_resource_template(); 1282 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1283 aml_append(crs, aml_irq_no_flags(7)); 1284 aml_append(dev, aml_name_decl("_CRS", crs)); 1285 1286 return dev; 1287 } 1288 1289 static Aml *build_com_device_aml(uint8_t uid) 1290 { 1291 Aml *dev; 1292 Aml *crs; 1293 Aml *method; 1294 Aml *if_ctx; 1295 Aml *else_ctx; 1296 Aml *zero = aml_int(0); 1297 Aml *is_present = aml_local(0); 1298 const char *enabled_field = "CAEN"; 1299 uint8_t irq = 4; 1300 uint16_t io_port = 0x03F8; 1301 1302 assert(uid == 1 || uid == 2); 1303 if (uid == 2) { 1304 enabled_field = "CBEN"; 1305 irq = 3; 1306 io_port = 0x02F8; 1307 } 1308 1309 dev = aml_device("COM%d", uid); 1310 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1311 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1312 1313 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1314 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1315 if_ctx = aml_if(aml_equal(is_present, zero)); 1316 { 1317 aml_append(if_ctx, aml_return(aml_int(0x00))); 1318 } 1319 aml_append(method, if_ctx); 1320 else_ctx = aml_else(); 1321 { 1322 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1323 } 1324 aml_append(method, else_ctx); 1325 aml_append(dev, method); 1326 1327 crs = aml_resource_template(); 1328 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1329 aml_append(crs, aml_irq_no_flags(irq)); 1330 aml_append(dev, aml_name_decl("_CRS", crs)); 1331 1332 return dev; 1333 } 1334 1335 static void build_isa_devices_aml(Aml *table) 1336 { 1337 ISADevice *fdc = pc_find_fdc0(); 1338 bool ambiguous; 1339 1340 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1341 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1342 1343 aml_append(scope, build_rtc_device_aml()); 1344 aml_append(scope, build_kbd_device_aml()); 1345 aml_append(scope, build_mouse_device_aml()); 1346 if (fdc) { 1347 aml_append(scope, build_fdc_device_aml(fdc)); 1348 } 1349 aml_append(scope, build_lpt_device_aml()); 1350 aml_append(scope, build_com_device_aml(1)); 1351 aml_append(scope, build_com_device_aml(2)); 1352 1353 if (ambiguous) { 1354 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1355 } else if (!obj) { 1356 error_report("No ISA bus, unable to define IPMI ACPI data"); 1357 } else { 1358 build_acpi_ipmi_devices(scope, BUS(obj)); 1359 } 1360 1361 aml_append(table, scope); 1362 } 1363 1364 static void build_dbg_aml(Aml *table) 1365 { 1366 Aml *field; 1367 Aml *method; 1368 Aml *while_ctx; 1369 Aml *scope = aml_scope("\\"); 1370 Aml *buf = aml_local(0); 1371 Aml *len = aml_local(1); 1372 Aml *idx = aml_local(2); 1373 1374 aml_append(scope, 1375 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1376 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1377 aml_append(field, aml_named_field("DBGB", 8)); 1378 aml_append(scope, field); 1379 1380 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1381 1382 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1383 aml_append(method, aml_to_buffer(buf, buf)); 1384 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1385 aml_append(method, aml_store(aml_int(0), idx)); 1386 1387 while_ctx = aml_while(aml_lless(idx, len)); 1388 aml_append(while_ctx, 1389 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1390 aml_append(while_ctx, aml_increment(idx)); 1391 aml_append(method, while_ctx); 1392 1393 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1394 aml_append(scope, method); 1395 1396 aml_append(table, scope); 1397 } 1398 1399 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1400 { 1401 Aml *dev; 1402 Aml *crs; 1403 Aml *method; 1404 uint32_t irqs[] = {5, 10, 11}; 1405 1406 dev = aml_device("%s", name); 1407 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1408 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1409 1410 crs = aml_resource_template(); 1411 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1412 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1413 aml_append(dev, aml_name_decl("_PRS", crs)); 1414 1415 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1416 aml_append(method, aml_return(aml_call1("IQST", reg))); 1417 aml_append(dev, method); 1418 1419 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1420 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1421 aml_append(dev, method); 1422 1423 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1424 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1425 aml_append(dev, method); 1426 1427 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1428 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1429 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1430 aml_append(dev, method); 1431 1432 return dev; 1433 } 1434 1435 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1436 { 1437 Aml *dev; 1438 Aml *crs; 1439 Aml *method; 1440 uint32_t irqs; 1441 1442 dev = aml_device("%s", name); 1443 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1444 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1445 1446 crs = aml_resource_template(); 1447 irqs = gsi; 1448 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1449 AML_SHARED, &irqs, 1)); 1450 aml_append(dev, aml_name_decl("_PRS", crs)); 1451 1452 aml_append(dev, aml_name_decl("_CRS", crs)); 1453 1454 /* 1455 * _DIS can be no-op because the interrupt cannot be disabled. 1456 */ 1457 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1458 aml_append(dev, method); 1459 1460 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1461 aml_append(dev, method); 1462 1463 return dev; 1464 } 1465 1466 /* _CRS method - get current settings */ 1467 static Aml *build_iqcr_method(bool is_piix4) 1468 { 1469 Aml *if_ctx; 1470 uint32_t irqs; 1471 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1472 Aml *crs = aml_resource_template(); 1473 1474 irqs = 0; 1475 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1476 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1477 aml_append(method, aml_name_decl("PRR0", crs)); 1478 1479 aml_append(method, 1480 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1481 1482 if (is_piix4) { 1483 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1484 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1485 aml_append(method, if_ctx); 1486 } else { 1487 aml_append(method, 1488 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1489 aml_name("PRRI"))); 1490 } 1491 1492 aml_append(method, aml_return(aml_name("PRR0"))); 1493 return method; 1494 } 1495 1496 /* _STA method - get status */ 1497 static Aml *build_irq_status_method(void) 1498 { 1499 Aml *if_ctx; 1500 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1501 1502 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1503 aml_append(if_ctx, aml_return(aml_int(0x09))); 1504 aml_append(method, if_ctx); 1505 aml_append(method, aml_return(aml_int(0x0B))); 1506 return method; 1507 } 1508 1509 static void build_piix4_pci0_int(Aml *table) 1510 { 1511 Aml *dev; 1512 Aml *crs; 1513 Aml *field; 1514 Aml *method; 1515 uint32_t irqs; 1516 Aml *sb_scope = aml_scope("_SB"); 1517 Aml *pci0_scope = aml_scope("PCI0"); 1518 1519 aml_append(pci0_scope, build_prt(true)); 1520 aml_append(sb_scope, pci0_scope); 1521 1522 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1523 aml_append(field, aml_named_field("PRQ0", 8)); 1524 aml_append(field, aml_named_field("PRQ1", 8)); 1525 aml_append(field, aml_named_field("PRQ2", 8)); 1526 aml_append(field, aml_named_field("PRQ3", 8)); 1527 aml_append(sb_scope, field); 1528 1529 aml_append(sb_scope, build_irq_status_method()); 1530 aml_append(sb_scope, build_iqcr_method(true)); 1531 1532 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1533 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1534 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1535 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1536 1537 dev = aml_device("LNKS"); 1538 { 1539 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1540 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1541 1542 crs = aml_resource_template(); 1543 irqs = 9; 1544 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1545 AML_ACTIVE_HIGH, AML_SHARED, 1546 &irqs, 1)); 1547 aml_append(dev, aml_name_decl("_PRS", crs)); 1548 1549 /* The SCI cannot be disabled and is always attached to GSI 9, 1550 * so these are no-ops. We only need this link to override the 1551 * polarity to active high and match the content of the MADT. 1552 */ 1553 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1554 aml_append(method, aml_return(aml_int(0x0b))); 1555 aml_append(dev, method); 1556 1557 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1558 aml_append(dev, method); 1559 1560 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1561 aml_append(method, aml_return(aml_name("_PRS"))); 1562 aml_append(dev, method); 1563 1564 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1565 aml_append(dev, method); 1566 } 1567 aml_append(sb_scope, dev); 1568 1569 aml_append(table, sb_scope); 1570 } 1571 1572 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1573 { 1574 int i; 1575 int head; 1576 Aml *pkg; 1577 char base = name[3] < 'E' ? 'A' : 'E'; 1578 char *s = g_strdup(name); 1579 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1580 1581 assert(strlen(s) == 4); 1582 1583 head = name[3] - base; 1584 for (i = 0; i < 4; i++) { 1585 if (head + i > 3) { 1586 head = i * -1; 1587 } 1588 s[3] = base + head + i; 1589 pkg = aml_package(4); 1590 aml_append(pkg, a_nr); 1591 aml_append(pkg, aml_int(i)); 1592 aml_append(pkg, aml_name("%s", s)); 1593 aml_append(pkg, aml_int(0)); 1594 aml_append(ctx, pkg); 1595 } 1596 g_free(s); 1597 } 1598 1599 static Aml *build_q35_routing_table(const char *str) 1600 { 1601 int i; 1602 Aml *pkg; 1603 char *name = g_strdup_printf("%s ", str); 1604 1605 pkg = aml_package(128); 1606 for (i = 0; i < 0x18; i++) { 1607 name[3] = 'E' + (i & 0x3); 1608 append_q35_prt_entry(pkg, i, name); 1609 } 1610 1611 name[3] = 'E'; 1612 append_q35_prt_entry(pkg, 0x18, name); 1613 1614 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1615 for (i = 0x0019; i < 0x1e; i++) { 1616 name[3] = 'A'; 1617 append_q35_prt_entry(pkg, i, name); 1618 } 1619 1620 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1621 name[3] = 'E'; 1622 append_q35_prt_entry(pkg, 0x1e, name); 1623 name[3] = 'A'; 1624 append_q35_prt_entry(pkg, 0x1f, name); 1625 1626 g_free(name); 1627 return pkg; 1628 } 1629 1630 static void build_q35_pci0_int(Aml *table) 1631 { 1632 Aml *field; 1633 Aml *method; 1634 Aml *sb_scope = aml_scope("_SB"); 1635 Aml *pci0_scope = aml_scope("PCI0"); 1636 1637 /* Zero => PIC mode, One => APIC Mode */ 1638 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1639 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1640 { 1641 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1642 } 1643 aml_append(table, method); 1644 1645 aml_append(pci0_scope, 1646 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1647 aml_append(pci0_scope, 1648 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1649 1650 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1651 { 1652 Aml *if_ctx; 1653 Aml *else_ctx; 1654 1655 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1656 section 6.2.8.1 */ 1657 /* Note: we provide the same info as the PCI routing 1658 table of the Bochs BIOS */ 1659 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1660 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1661 aml_append(method, if_ctx); 1662 else_ctx = aml_else(); 1663 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1664 aml_append(method, else_ctx); 1665 } 1666 aml_append(pci0_scope, method); 1667 aml_append(sb_scope, pci0_scope); 1668 1669 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1670 aml_append(field, aml_named_field("PRQA", 8)); 1671 aml_append(field, aml_named_field("PRQB", 8)); 1672 aml_append(field, aml_named_field("PRQC", 8)); 1673 aml_append(field, aml_named_field("PRQD", 8)); 1674 aml_append(field, aml_reserved_field(0x20)); 1675 aml_append(field, aml_named_field("PRQE", 8)); 1676 aml_append(field, aml_named_field("PRQF", 8)); 1677 aml_append(field, aml_named_field("PRQG", 8)); 1678 aml_append(field, aml_named_field("PRQH", 8)); 1679 aml_append(sb_scope, field); 1680 1681 aml_append(sb_scope, build_irq_status_method()); 1682 aml_append(sb_scope, build_iqcr_method(false)); 1683 1684 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1685 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1686 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1687 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1688 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1689 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1690 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1691 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1692 1693 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1694 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1695 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1696 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1697 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1698 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1699 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1700 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1701 1702 aml_append(table, sb_scope); 1703 } 1704 1705 static void build_q35_isa_bridge(Aml *table) 1706 { 1707 Aml *dev; 1708 Aml *scope; 1709 Aml *field; 1710 1711 scope = aml_scope("_SB.PCI0"); 1712 dev = aml_device("ISA"); 1713 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1714 1715 /* ICH9 PCI to ISA irq remapping */ 1716 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1717 aml_int(0x60), 0x0C)); 1718 1719 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1720 aml_int(0x80), 0x02)); 1721 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1722 aml_append(field, aml_named_field("COMA", 3)); 1723 aml_append(field, aml_reserved_field(1)); 1724 aml_append(field, aml_named_field("COMB", 3)); 1725 aml_append(field, aml_reserved_field(1)); 1726 aml_append(field, aml_named_field("LPTD", 2)); 1727 aml_append(dev, field); 1728 1729 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1730 aml_int(0x82), 0x02)); 1731 /* enable bits */ 1732 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1733 aml_append(field, aml_named_field("CAEN", 1)); 1734 aml_append(field, aml_named_field("CBEN", 1)); 1735 aml_append(field, aml_named_field("LPEN", 1)); 1736 aml_append(dev, field); 1737 1738 aml_append(scope, dev); 1739 aml_append(table, scope); 1740 } 1741 1742 static void build_piix4_pm(Aml *table) 1743 { 1744 Aml *dev; 1745 Aml *scope; 1746 1747 scope = aml_scope("_SB.PCI0"); 1748 dev = aml_device("PX13"); 1749 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1750 1751 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1752 aml_int(0x00), 0xff)); 1753 aml_append(scope, dev); 1754 aml_append(table, scope); 1755 } 1756 1757 static void build_piix4_isa_bridge(Aml *table) 1758 { 1759 Aml *dev; 1760 Aml *scope; 1761 Aml *field; 1762 1763 scope = aml_scope("_SB.PCI0"); 1764 dev = aml_device("ISA"); 1765 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1766 1767 /* PIIX PCI to ISA irq remapping */ 1768 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1769 aml_int(0x60), 0x04)); 1770 /* enable bits */ 1771 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1772 /* Offset(0x5f),, 7, */ 1773 aml_append(field, aml_reserved_field(0x2f8)); 1774 aml_append(field, aml_reserved_field(7)); 1775 aml_append(field, aml_named_field("LPEN", 1)); 1776 /* Offset(0x67),, 3, */ 1777 aml_append(field, aml_reserved_field(0x38)); 1778 aml_append(field, aml_reserved_field(3)); 1779 aml_append(field, aml_named_field("CAEN", 1)); 1780 aml_append(field, aml_reserved_field(3)); 1781 aml_append(field, aml_named_field("CBEN", 1)); 1782 aml_append(dev, field); 1783 1784 aml_append(scope, dev); 1785 aml_append(table, scope); 1786 } 1787 1788 static void build_piix4_pci_hotplug(Aml *table) 1789 { 1790 Aml *scope; 1791 Aml *field; 1792 Aml *method; 1793 1794 scope = aml_scope("_SB.PCI0"); 1795 1796 aml_append(scope, 1797 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1798 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1799 aml_append(field, aml_named_field("PCIU", 32)); 1800 aml_append(field, aml_named_field("PCID", 32)); 1801 aml_append(scope, field); 1802 1803 aml_append(scope, 1804 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1805 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1806 aml_append(field, aml_named_field("B0EJ", 32)); 1807 aml_append(scope, field); 1808 1809 aml_append(scope, 1810 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1811 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1812 aml_append(field, aml_named_field("BNUM", 32)); 1813 aml_append(scope, field); 1814 1815 aml_append(scope, aml_mutex("BLCK", 0)); 1816 1817 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1818 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1819 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1820 aml_append(method, 1821 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1822 aml_append(method, aml_release(aml_name("BLCK"))); 1823 aml_append(method, aml_return(aml_int(0))); 1824 aml_append(scope, method); 1825 1826 aml_append(table, scope); 1827 } 1828 1829 static Aml *build_q35_osc_method(void) 1830 { 1831 Aml *if_ctx; 1832 Aml *if_ctx2; 1833 Aml *else_ctx; 1834 Aml *method; 1835 Aml *a_cwd1 = aml_name("CDW1"); 1836 Aml *a_ctrl = aml_local(0); 1837 1838 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1839 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1840 1841 if_ctx = aml_if(aml_equal( 1842 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1843 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1844 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1845 1846 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1847 1848 /* 1849 * Always allow native PME, AER (no dependencies) 1850 * Never allow SHPC (no SHPC controller in this system) 1851 */ 1852 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); 1853 1854 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1855 /* Unknown revision */ 1856 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1857 aml_append(if_ctx, if_ctx2); 1858 1859 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1860 /* Capabilities bits were masked */ 1861 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1862 aml_append(if_ctx, if_ctx2); 1863 1864 /* Update DWORD3 in the buffer */ 1865 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1866 aml_append(method, if_ctx); 1867 1868 else_ctx = aml_else(); 1869 /* Unrecognized UUID */ 1870 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1871 aml_append(method, else_ctx); 1872 1873 aml_append(method, aml_return(aml_arg(3))); 1874 return method; 1875 } 1876 1877 static void 1878 build_dsdt(GArray *table_data, BIOSLinker *linker, 1879 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1880 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1881 { 1882 CrsRangeEntry *entry; 1883 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1884 CrsRangeSet crs_range_set; 1885 PCMachineState *pcms = PC_MACHINE(machine); 1886 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1887 uint32_t nr_mem = machine->ram_slots; 1888 int root_bus_limit = 0xFF; 1889 PCIBus *bus = NULL; 1890 int i; 1891 1892 dsdt = init_aml_allocator(); 1893 1894 /* Reserve space for header */ 1895 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1896 1897 build_dbg_aml(dsdt); 1898 if (misc->is_piix4) { 1899 sb_scope = aml_scope("_SB"); 1900 dev = aml_device("PCI0"); 1901 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1902 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1903 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1904 aml_append(sb_scope, dev); 1905 aml_append(dsdt, sb_scope); 1906 1907 build_hpet_aml(dsdt); 1908 build_piix4_pm(dsdt); 1909 build_piix4_isa_bridge(dsdt); 1910 build_isa_devices_aml(dsdt); 1911 build_piix4_pci_hotplug(dsdt); 1912 build_piix4_pci0_int(dsdt); 1913 } else { 1914 sb_scope = aml_scope("_SB"); 1915 aml_append(sb_scope, 1916 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c)); 1917 aml_append(sb_scope, 1918 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01)); 1919 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1920 aml_append(field, aml_named_field("PCIB", 8)); 1921 aml_append(sb_scope, field); 1922 aml_append(dsdt, sb_scope); 1923 1924 sb_scope = aml_scope("_SB"); 1925 dev = aml_device("PCI0"); 1926 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1927 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1928 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1929 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1930 aml_append(dev, build_q35_osc_method()); 1931 aml_append(sb_scope, dev); 1932 aml_append(dsdt, sb_scope); 1933 1934 build_hpet_aml(dsdt); 1935 build_q35_isa_bridge(dsdt); 1936 build_isa_devices_aml(dsdt); 1937 build_q35_pci0_int(dsdt); 1938 } 1939 1940 if (pcmc->legacy_cpu_hotplug) { 1941 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1942 } else { 1943 CPUHotplugFeatures opts = { 1944 .apci_1_compatible = true, .has_legacy_cphp = true 1945 }; 1946 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1947 "\\_SB.PCI0", "\\_GPE._E02"); 1948 } 1949 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03"); 1950 1951 scope = aml_scope("_GPE"); 1952 { 1953 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1954 1955 if (misc->is_piix4) { 1956 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1957 aml_append(method, 1958 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1959 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1960 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1961 aml_append(scope, method); 1962 } 1963 1964 if (pcms->acpi_nvdimm_state.is_enabled) { 1965 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1966 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1967 aml_int(0x80))); 1968 aml_append(scope, method); 1969 } 1970 } 1971 aml_append(dsdt, scope); 1972 1973 crs_range_set_init(&crs_range_set); 1974 bus = PC_MACHINE(machine)->bus; 1975 if (bus) { 1976 QLIST_FOREACH(bus, &bus->child, sibling) { 1977 uint8_t bus_num = pci_bus_num(bus); 1978 uint8_t numa_node = pci_bus_numa_node(bus); 1979 1980 /* look only for expander root buses */ 1981 if (!pci_bus_is_root(bus)) { 1982 continue; 1983 } 1984 1985 if (bus_num < root_bus_limit) { 1986 root_bus_limit = bus_num - 1; 1987 } 1988 1989 scope = aml_scope("\\_SB"); 1990 dev = aml_device("PC%.02X", bus_num); 1991 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1992 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1993 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1994 if (pci_bus_is_express(bus)) { 1995 aml_append(dev, build_q35_osc_method()); 1996 } 1997 1998 if (numa_node != NUMA_NODE_UNASSIGNED) { 1999 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 2000 } 2001 2002 aml_append(dev, build_prt(false)); 2003 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 2004 aml_append(dev, aml_name_decl("_CRS", crs)); 2005 aml_append(scope, dev); 2006 aml_append(dsdt, scope); 2007 } 2008 } 2009 2010 scope = aml_scope("\\_SB.PCI0"); 2011 /* build PCI0._CRS */ 2012 crs = aml_resource_template(); 2013 aml_append(crs, 2014 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 2015 0x0000, 0x0, root_bus_limit, 2016 0x0000, root_bus_limit + 1)); 2017 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 2018 2019 aml_append(crs, 2020 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2021 AML_POS_DECODE, AML_ENTIRE_RANGE, 2022 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 2023 2024 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 2025 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 2026 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 2027 aml_append(crs, 2028 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2029 AML_POS_DECODE, AML_ENTIRE_RANGE, 2030 0x0000, entry->base, entry->limit, 2031 0x0000, entry->limit - entry->base + 1)); 2032 } 2033 2034 aml_append(crs, 2035 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2036 AML_CACHEABLE, AML_READ_WRITE, 2037 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2038 2039 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 2040 range_lob(pci_hole), 2041 range_upb(pci_hole)); 2042 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 2043 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 2044 aml_append(crs, 2045 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2046 AML_NON_CACHEABLE, AML_READ_WRITE, 2047 0, entry->base, entry->limit, 2048 0, entry->limit - entry->base + 1)); 2049 } 2050 2051 if (!range_is_empty(pci_hole64)) { 2052 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 2053 range_lob(pci_hole64), 2054 range_upb(pci_hole64)); 2055 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 2056 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 2057 aml_append(crs, 2058 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 2059 AML_MAX_FIXED, 2060 AML_CACHEABLE, AML_READ_WRITE, 2061 0, entry->base, entry->limit, 2062 0, entry->limit - entry->base + 1)); 2063 } 2064 } 2065 2066 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2067 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2068 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2069 } 2070 aml_append(scope, aml_name_decl("_CRS", crs)); 2071 2072 /* reserve GPE0 block resources */ 2073 dev = aml_device("GPE0"); 2074 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2075 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2076 /* device present, functioning, decoding, not shown in UI */ 2077 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2078 crs = aml_resource_template(); 2079 aml_append(crs, 2080 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 2081 ); 2082 aml_append(dev, aml_name_decl("_CRS", crs)); 2083 aml_append(scope, dev); 2084 2085 crs_range_set_free(&crs_range_set); 2086 2087 /* reserve PCIHP resources */ 2088 if (pm->pcihp_io_len) { 2089 dev = aml_device("PHPR"); 2090 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2091 aml_append(dev, 2092 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2093 /* device present, functioning, decoding, not shown in UI */ 2094 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2095 crs = aml_resource_template(); 2096 aml_append(crs, 2097 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2098 pm->pcihp_io_len) 2099 ); 2100 aml_append(dev, aml_name_decl("_CRS", crs)); 2101 aml_append(scope, dev); 2102 } 2103 aml_append(dsdt, scope); 2104 2105 /* create S3_ / S4_ / S5_ packages if necessary */ 2106 scope = aml_scope("\\"); 2107 if (!pm->s3_disabled) { 2108 pkg = aml_package(4); 2109 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2110 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2111 aml_append(pkg, aml_int(0)); /* reserved */ 2112 aml_append(pkg, aml_int(0)); /* reserved */ 2113 aml_append(scope, aml_name_decl("_S3", pkg)); 2114 } 2115 2116 if (!pm->s4_disabled) { 2117 pkg = aml_package(4); 2118 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2119 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2120 aml_append(pkg, aml_int(pm->s4_val)); 2121 aml_append(pkg, aml_int(0)); /* reserved */ 2122 aml_append(pkg, aml_int(0)); /* reserved */ 2123 aml_append(scope, aml_name_decl("_S4", pkg)); 2124 } 2125 2126 pkg = aml_package(4); 2127 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2128 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2129 aml_append(pkg, aml_int(0)); /* reserved */ 2130 aml_append(pkg, aml_int(0)); /* reserved */ 2131 aml_append(scope, aml_name_decl("_S5", pkg)); 2132 aml_append(dsdt, scope); 2133 2134 /* create fw_cfg node, unconditionally */ 2135 { 2136 /* when using port i/o, the 8-bit data register *always* overlaps 2137 * with half of the 16-bit control register. Hence, the total size 2138 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2139 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2140 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2141 "dma_enabled", NULL) ? 2142 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2143 FW_CFG_CTL_SIZE; 2144 2145 scope = aml_scope("\\_SB.PCI0"); 2146 dev = aml_device("FWCF"); 2147 2148 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2149 2150 /* device present, functioning, decoding, not shown in UI */ 2151 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2152 2153 crs = aml_resource_template(); 2154 aml_append(crs, 2155 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2156 ); 2157 aml_append(dev, aml_name_decl("_CRS", crs)); 2158 2159 aml_append(scope, dev); 2160 aml_append(dsdt, scope); 2161 } 2162 2163 if (misc->applesmc_io_base) { 2164 scope = aml_scope("\\_SB.PCI0.ISA"); 2165 dev = aml_device("SMC"); 2166 2167 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2168 /* device present, functioning, decoding, not shown in UI */ 2169 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2170 2171 crs = aml_resource_template(); 2172 aml_append(crs, 2173 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2174 0x01, APPLESMC_MAX_DATA_LENGTH) 2175 ); 2176 aml_append(crs, aml_irq_no_flags(6)); 2177 aml_append(dev, aml_name_decl("_CRS", crs)); 2178 2179 aml_append(scope, dev); 2180 aml_append(dsdt, scope); 2181 } 2182 2183 if (misc->pvpanic_port) { 2184 scope = aml_scope("\\_SB.PCI0.ISA"); 2185 2186 dev = aml_device("PEVT"); 2187 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2188 2189 crs = aml_resource_template(); 2190 aml_append(crs, 2191 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2192 ); 2193 aml_append(dev, aml_name_decl("_CRS", crs)); 2194 2195 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2196 aml_int(misc->pvpanic_port), 1)); 2197 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2198 aml_append(field, aml_named_field("PEPT", 8)); 2199 aml_append(dev, field); 2200 2201 /* device present, functioning, decoding, shown in UI */ 2202 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2203 2204 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2205 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2206 aml_append(method, aml_return(aml_local(0))); 2207 aml_append(dev, method); 2208 2209 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2210 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2211 aml_append(dev, method); 2212 2213 aml_append(scope, dev); 2214 aml_append(dsdt, scope); 2215 } 2216 2217 sb_scope = aml_scope("\\_SB"); 2218 { 2219 Object *pci_host; 2220 PCIBus *bus = NULL; 2221 2222 pci_host = acpi_get_i386_pci_host(); 2223 if (pci_host) { 2224 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2225 } 2226 2227 if (bus) { 2228 Aml *scope = aml_scope("PCI0"); 2229 /* Scan all PCI buses. Generate tables to support hotplug. */ 2230 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2231 2232 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2233 dev = aml_device("ISA.TPM"); 2234 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2235 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2236 crs = aml_resource_template(); 2237 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2238 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2239 /* 2240 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2241 Rewrite to take IRQ from TPM device model and 2242 fix default IRQ value there to use some unused IRQ 2243 */ 2244 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2245 aml_append(dev, aml_name_decl("_CRS", crs)); 2246 aml_append(scope, dev); 2247 } 2248 2249 aml_append(sb_scope, scope); 2250 } 2251 } 2252 aml_append(dsdt, sb_scope); 2253 2254 /* copy AML table into ACPI tables blob and patch header there */ 2255 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2256 build_header(linker, table_data, 2257 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2258 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2259 free_aml_allocator(); 2260 } 2261 2262 static void 2263 build_hpet(GArray *table_data, BIOSLinker *linker) 2264 { 2265 Acpi20Hpet *hpet; 2266 2267 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2268 /* Note timer_block_id value must be kept in sync with value advertised by 2269 * emulated hpet 2270 */ 2271 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2272 hpet->addr.address = cpu_to_le64(HPET_BASE); 2273 build_header(linker, table_data, 2274 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2275 } 2276 2277 static void 2278 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2279 { 2280 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2281 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2282 unsigned log_addr_offset = 2283 (char *)&tcpa->log_area_start_address - table_data->data; 2284 2285 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2286 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2287 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2288 2289 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2290 false /* high memory */); 2291 2292 /* log area start address to be filled by Guest linker */ 2293 bios_linker_loader_add_pointer(linker, 2294 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2295 ACPI_BUILD_TPMLOG_FILE, 0); 2296 2297 build_header(linker, table_data, 2298 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2299 } 2300 2301 static void 2302 build_tpm2(GArray *table_data, BIOSLinker *linker) 2303 { 2304 Acpi20TPM2 *tpm2_ptr; 2305 2306 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2307 2308 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2309 tpm2_ptr->control_area_address = cpu_to_le64(0); 2310 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2311 2312 build_header(linker, table_data, 2313 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2314 } 2315 2316 static void 2317 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2318 { 2319 AcpiSystemResourceAffinityTable *srat; 2320 AcpiSratMemoryAffinity *numamem; 2321 2322 int i; 2323 int srat_start, numa_start, slots; 2324 uint64_t mem_len, mem_base, next_base; 2325 MachineClass *mc = MACHINE_GET_CLASS(machine); 2326 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2327 PCMachineState *pcms = PC_MACHINE(machine); 2328 ram_addr_t hotplugabble_address_space_size = 2329 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2330 NULL); 2331 2332 srat_start = table_data->len; 2333 2334 srat = acpi_data_push(table_data, sizeof *srat); 2335 srat->reserved1 = cpu_to_le32(1); 2336 2337 for (i = 0; i < apic_ids->len; i++) { 2338 int node_id = apic_ids->cpus[i].props.has_node_id ? 2339 apic_ids->cpus[i].props.node_id : 0; 2340 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2341 2342 if (apic_id < 255) { 2343 AcpiSratProcessorAffinity *core; 2344 2345 core = acpi_data_push(table_data, sizeof *core); 2346 core->type = ACPI_SRAT_PROCESSOR_APIC; 2347 core->length = sizeof(*core); 2348 core->local_apic_id = apic_id; 2349 core->proximity_lo = node_id; 2350 memset(core->proximity_hi, 0, 3); 2351 core->local_sapic_eid = 0; 2352 core->flags = cpu_to_le32(1); 2353 } else { 2354 AcpiSratProcessorX2ApicAffinity *core; 2355 2356 core = acpi_data_push(table_data, sizeof *core); 2357 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2358 core->length = sizeof(*core); 2359 core->x2apic_id = cpu_to_le32(apic_id); 2360 core->proximity_domain = cpu_to_le32(node_id); 2361 core->flags = cpu_to_le32(1); 2362 } 2363 } 2364 2365 2366 /* the memory map is a bit tricky, it contains at least one hole 2367 * from 640k-1M and possibly another one from 3.5G-4G. 2368 */ 2369 next_base = 0; 2370 numa_start = table_data->len; 2371 2372 numamem = acpi_data_push(table_data, sizeof *numamem); 2373 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED); 2374 next_base = 1024 * 1024; 2375 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2376 mem_base = next_base; 2377 mem_len = pcms->node_mem[i - 1]; 2378 if (i == 1) { 2379 mem_len -= 1024 * 1024; 2380 } 2381 next_base = mem_base + mem_len; 2382 2383 /* Cut out the ACPI_PCI hole */ 2384 if (mem_base <= pcms->below_4g_mem_size && 2385 next_base > pcms->below_4g_mem_size) { 2386 mem_len -= next_base - pcms->below_4g_mem_size; 2387 if (mem_len > 0) { 2388 numamem = acpi_data_push(table_data, sizeof *numamem); 2389 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2390 MEM_AFFINITY_ENABLED); 2391 } 2392 mem_base = 1ULL << 32; 2393 mem_len = next_base - pcms->below_4g_mem_size; 2394 next_base += (1ULL << 32) - pcms->below_4g_mem_size; 2395 } 2396 numamem = acpi_data_push(table_data, sizeof *numamem); 2397 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2398 MEM_AFFINITY_ENABLED); 2399 } 2400 slots = (table_data->len - numa_start) / sizeof *numamem; 2401 for (; slots < pcms->numa_nodes + 2; slots++) { 2402 numamem = acpi_data_push(table_data, sizeof *numamem); 2403 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2404 } 2405 2406 /* 2407 * Entry is required for Windows to enable memory hotplug in OS. 2408 * Memory devices may override proximity set by this entry, 2409 * providing _PXM method if necessary. 2410 */ 2411 if (hotplugabble_address_space_size) { 2412 numamem = acpi_data_push(table_data, sizeof *numamem); 2413 build_srat_memory(numamem, pcms->hotplug_memory.base, 2414 hotplugabble_address_space_size, 0, 2415 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2416 } 2417 2418 build_header(linker, table_data, 2419 (void *)(table_data->data + srat_start), 2420 "SRAT", 2421 table_data->len - srat_start, 1, NULL, NULL); 2422 } 2423 2424 static void 2425 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) 2426 { 2427 AcpiTableMcfg *mcfg; 2428 const char *sig; 2429 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2430 2431 mcfg = acpi_data_push(table_data, len); 2432 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2433 /* Only a single allocation so no need to play with segments */ 2434 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2435 mcfg->allocation[0].start_bus_number = 0; 2436 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2437 2438 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2439 * To avoid table size changes (which create migration issues), 2440 * always create the table even if there are no allocations, 2441 * but set the signature to a reserved value in this case. 2442 * ACPI spec requires OSPMs to ignore such tables. 2443 */ 2444 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2445 /* Reserved signature: ignored by OSPM */ 2446 sig = "QEMU"; 2447 } else { 2448 sig = "MCFG"; 2449 } 2450 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL); 2451 } 2452 2453 /* 2454 * VT-d spec 8.1 DMA Remapping Reporting Structure 2455 * (version Oct. 2014 or later) 2456 */ 2457 static void 2458 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2459 { 2460 int dmar_start = table_data->len; 2461 2462 AcpiTableDmar *dmar; 2463 AcpiDmarHardwareUnit *drhd; 2464 AcpiDmarRootPortATS *atsr; 2465 uint8_t dmar_flags = 0; 2466 X86IOMMUState *iommu = x86_iommu_get_default(); 2467 AcpiDmarDeviceScope *scope = NULL; 2468 /* Root complex IOAPIC use one path[0] only */ 2469 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2470 2471 assert(iommu); 2472 if (iommu->intr_supported) { 2473 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2474 } 2475 2476 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2477 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 2478 dmar->flags = dmar_flags; 2479 2480 /* DMAR Remapping Hardware Unit Definition structure */ 2481 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2482 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2483 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2484 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2485 drhd->pci_segment = cpu_to_le16(0); 2486 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2487 2488 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2489 * 8.3.1 (version Oct. 2014 or later). */ 2490 scope = &drhd->scope[0]; 2491 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2492 scope->length = ioapic_scope_size; 2493 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2494 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2495 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2496 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2497 2498 if (iommu->dt_supported) { 2499 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2500 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2501 atsr->length = cpu_to_le16(sizeof(*atsr)); 2502 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2503 atsr->pci_segment = cpu_to_le16(0); 2504 } 2505 2506 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2507 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2508 } 2509 /* 2510 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2511 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2512 */ 2513 static void 2514 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2515 { 2516 int iommu_start = table_data->len; 2517 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2518 2519 /* IVRS header */ 2520 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2521 /* IVinfo - IO virtualization information common to all 2522 * IOMMU units in a system 2523 */ 2524 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2525 /* reserved */ 2526 build_append_int_noprefix(table_data, 0, 8); 2527 2528 /* IVHD definition - type 10h */ 2529 build_append_int_noprefix(table_data, 0x10, 1); 2530 /* virtualization flags */ 2531 build_append_int_noprefix(table_data, 2532 (1UL << 0) | /* HtTunEn */ 2533 (1UL << 4) | /* iotblSup */ 2534 (1UL << 6) | /* PrefSup */ 2535 (1UL << 7), /* PPRSup */ 2536 1); 2537 /* IVHD length */ 2538 build_append_int_noprefix(table_data, 0x24, 2); 2539 /* DeviceID */ 2540 build_append_int_noprefix(table_data, s->devid, 2); 2541 /* Capability offset */ 2542 build_append_int_noprefix(table_data, s->capab_offset, 2); 2543 /* IOMMU base address */ 2544 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2545 /* PCI Segment Group */ 2546 build_append_int_noprefix(table_data, 0, 2); 2547 /* IOMMU info */ 2548 build_append_int_noprefix(table_data, 0, 2); 2549 /* IOMMU Feature Reporting */ 2550 build_append_int_noprefix(table_data, 2551 (48UL << 30) | /* HATS */ 2552 (48UL << 28) | /* GATS */ 2553 (1UL << 2), /* GTSup */ 2554 4); 2555 /* 2556 * Type 1 device entry reporting all devices 2557 * These are 4-byte device entries currently reporting the range of 2558 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2559 */ 2560 build_append_int_noprefix(table_data, 0x0000001, 4); 2561 2562 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2563 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2564 } 2565 2566 static GArray * 2567 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset) 2568 { 2569 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2570 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address); 2571 unsigned rsdt_pa_offset = 2572 (char *)&rsdp->rsdt_physical_address - rsdp_table->data; 2573 2574 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16, 2575 true /* fseg memory */); 2576 2577 memcpy(&rsdp->signature, "RSD PTR ", 8); 2578 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2579 /* Address to be filled by Guest linker */ 2580 bios_linker_loader_add_pointer(linker, 2581 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size, 2582 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset); 2583 2584 /* Checksum to be filled by Guest linker */ 2585 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2586 (char *)rsdp - rsdp_table->data, sizeof *rsdp, 2587 (char *)&rsdp->checksum - rsdp_table->data); 2588 2589 return rsdp_table; 2590 } 2591 2592 typedef 2593 struct AcpiBuildState { 2594 /* Copy of table in RAM (for patching). */ 2595 MemoryRegion *table_mr; 2596 /* Is table patched? */ 2597 uint8_t patched; 2598 void *rsdp; 2599 MemoryRegion *rsdp_mr; 2600 MemoryRegion *linker_mr; 2601 } AcpiBuildState; 2602 2603 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2604 { 2605 Object *pci_host; 2606 QObject *o; 2607 2608 pci_host = acpi_get_i386_pci_host(); 2609 g_assert(pci_host); 2610 2611 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2612 if (!o) { 2613 return false; 2614 } 2615 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 2616 qobject_decref(o); 2617 2618 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2619 assert(o); 2620 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 2621 qobject_decref(o); 2622 return true; 2623 } 2624 2625 static 2626 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2627 { 2628 PCMachineState *pcms = PC_MACHINE(machine); 2629 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2630 GArray *table_offsets; 2631 unsigned facs, dsdt, rsdt, fadt; 2632 AcpiPmInfo pm; 2633 AcpiMiscInfo misc; 2634 AcpiMcfgInfo mcfg; 2635 Range pci_hole, pci_hole64; 2636 uint8_t *u; 2637 size_t aml_len = 0; 2638 GArray *tables_blob = tables->table_data; 2639 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2640 Object *vmgenid_dev; 2641 2642 acpi_get_pm_info(&pm); 2643 acpi_get_misc_info(&misc); 2644 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2645 acpi_get_slic_oem(&slic_oem); 2646 2647 table_offsets = g_array_new(false, true /* clear */, 2648 sizeof(uint32_t)); 2649 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2650 2651 bios_linker_loader_alloc(tables->linker, 2652 ACPI_BUILD_TABLE_FILE, tables_blob, 2653 64 /* Ensure FACS is aligned */, 2654 false /* high memory */); 2655 2656 /* 2657 * FACS is pointed to by FADT. 2658 * We place it first since it's the only table that has alignment 2659 * requirements. 2660 */ 2661 facs = tables_blob->len; 2662 build_facs(tables_blob, tables->linker); 2663 2664 /* DSDT is pointed to by FADT */ 2665 dsdt = tables_blob->len; 2666 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2667 &pci_hole, &pci_hole64, machine); 2668 2669 /* Count the size of the DSDT and SSDT, we will need it for legacy 2670 * sizing of ACPI tables. 2671 */ 2672 aml_len += tables_blob->len - dsdt; 2673 2674 /* ACPI tables pointed to by RSDT */ 2675 fadt = tables_blob->len; 2676 acpi_add_table(table_offsets, tables_blob); 2677 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt, 2678 slic_oem.id, slic_oem.table_id); 2679 aml_len += tables_blob->len - fadt; 2680 2681 acpi_add_table(table_offsets, tables_blob); 2682 build_madt(tables_blob, tables->linker, pcms); 2683 2684 vmgenid_dev = find_vmgenid_dev(); 2685 if (vmgenid_dev) { 2686 acpi_add_table(table_offsets, tables_blob); 2687 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2688 tables->vmgenid, tables->linker); 2689 } 2690 2691 if (misc.has_hpet) { 2692 acpi_add_table(table_offsets, tables_blob); 2693 build_hpet(tables_blob, tables->linker); 2694 } 2695 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2696 acpi_add_table(table_offsets, tables_blob); 2697 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2698 2699 if (misc.tpm_version == TPM_VERSION_2_0) { 2700 acpi_add_table(table_offsets, tables_blob); 2701 build_tpm2(tables_blob, tables->linker); 2702 } 2703 } 2704 if (pcms->numa_nodes) { 2705 acpi_add_table(table_offsets, tables_blob); 2706 build_srat(tables_blob, tables->linker, machine); 2707 if (have_numa_distance) { 2708 acpi_add_table(table_offsets, tables_blob); 2709 build_slit(tables_blob, tables->linker); 2710 } 2711 } 2712 if (acpi_get_mcfg(&mcfg)) { 2713 acpi_add_table(table_offsets, tables_blob); 2714 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2715 } 2716 if (x86_iommu_get_default()) { 2717 IommuType IOMMUType = x86_iommu_get_type(); 2718 if (IOMMUType == TYPE_AMD) { 2719 acpi_add_table(table_offsets, tables_blob); 2720 build_amd_iommu(tables_blob, tables->linker); 2721 } else if (IOMMUType == TYPE_INTEL) { 2722 acpi_add_table(table_offsets, tables_blob); 2723 build_dmar_q35(tables_blob, tables->linker); 2724 } 2725 } 2726 if (pcms->acpi_nvdimm_state.is_enabled) { 2727 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2728 &pcms->acpi_nvdimm_state, machine->ram_slots); 2729 } 2730 2731 /* Add tables supplied by user (if any) */ 2732 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2733 unsigned len = acpi_table_len(u); 2734 2735 acpi_add_table(table_offsets, tables_blob); 2736 g_array_append_vals(tables_blob, u, len); 2737 } 2738 2739 /* RSDT is pointed to by RSDP */ 2740 rsdt = tables_blob->len; 2741 build_rsdt(tables_blob, tables->linker, table_offsets, 2742 slic_oem.id, slic_oem.table_id); 2743 2744 /* RSDP is in FSEG memory, so allocate it separately */ 2745 build_rsdp(tables->rsdp, tables->linker, rsdt); 2746 2747 /* We'll expose it all to Guest so we want to reduce 2748 * chance of size changes. 2749 * 2750 * We used to align the tables to 4k, but of course this would 2751 * too simple to be enough. 4k turned out to be too small an 2752 * alignment very soon, and in fact it is almost impossible to 2753 * keep the table size stable for all (max_cpus, max_memory_slots) 2754 * combinations. So the table size is always 64k for pc-i440fx-2.1 2755 * and we give an error if the table grows beyond that limit. 2756 * 2757 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2758 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2759 * than 2.0 and we can always pad the smaller tables with zeros. We can 2760 * then use the exact size of the 2.0 tables. 2761 * 2762 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2763 */ 2764 if (pcmc->legacy_acpi_table_size) { 2765 /* Subtracting aml_len gives the size of fixed tables. Then add the 2766 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2767 */ 2768 int legacy_aml_len = 2769 pcmc->legacy_acpi_table_size + 2770 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit; 2771 int legacy_table_size = 2772 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2773 ACPI_BUILD_ALIGN_SIZE); 2774 if (tables_blob->len > legacy_table_size) { 2775 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2776 error_report("Warning: migration may not work."); 2777 } 2778 g_array_set_size(tables_blob, legacy_table_size); 2779 } else { 2780 /* Make sure we have a buffer in case we need to resize the tables. */ 2781 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2782 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2783 error_report("Warning: ACPI tables are larger than 64k."); 2784 error_report("Warning: migration may not work."); 2785 error_report("Warning: please remove CPUs, NUMA nodes, " 2786 "memory slots or PCI bridges."); 2787 } 2788 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2789 } 2790 2791 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2792 2793 /* Cleanup memory that's no longer used. */ 2794 g_array_free(table_offsets, true); 2795 } 2796 2797 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2798 { 2799 uint32_t size = acpi_data_len(data); 2800 2801 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2802 memory_region_ram_resize(mr, size, &error_abort); 2803 2804 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2805 memory_region_set_dirty(mr, 0, size); 2806 } 2807 2808 static void acpi_build_update(void *build_opaque) 2809 { 2810 AcpiBuildState *build_state = build_opaque; 2811 AcpiBuildTables tables; 2812 2813 /* No state to update or already patched? Nothing to do. */ 2814 if (!build_state || build_state->patched) { 2815 return; 2816 } 2817 build_state->patched = 1; 2818 2819 acpi_build_tables_init(&tables); 2820 2821 acpi_build(&tables, MACHINE(qdev_get_machine())); 2822 2823 acpi_ram_update(build_state->table_mr, tables.table_data); 2824 2825 if (build_state->rsdp) { 2826 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2827 } else { 2828 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2829 } 2830 2831 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2832 acpi_build_tables_cleanup(&tables, true); 2833 } 2834 2835 static void acpi_build_reset(void *build_opaque) 2836 { 2837 AcpiBuildState *build_state = build_opaque; 2838 build_state->patched = 0; 2839 } 2840 2841 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2842 GArray *blob, const char *name, 2843 uint64_t max_size) 2844 { 2845 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2846 name, acpi_build_update, build_state, NULL, true); 2847 } 2848 2849 static const VMStateDescription vmstate_acpi_build = { 2850 .name = "acpi_build", 2851 .version_id = 1, 2852 .minimum_version_id = 1, 2853 .fields = (VMStateField[]) { 2854 VMSTATE_UINT8(patched, AcpiBuildState), 2855 VMSTATE_END_OF_LIST() 2856 }, 2857 }; 2858 2859 void acpi_setup(void) 2860 { 2861 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2862 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2863 AcpiBuildTables tables; 2864 AcpiBuildState *build_state; 2865 Object *vmgenid_dev; 2866 2867 if (!pcms->fw_cfg) { 2868 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2869 return; 2870 } 2871 2872 if (!pcms->acpi_build_enabled) { 2873 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2874 return; 2875 } 2876 2877 if (!acpi_enabled) { 2878 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2879 return; 2880 } 2881 2882 build_state = g_malloc0(sizeof *build_state); 2883 2884 acpi_set_pci_info(); 2885 2886 acpi_build_tables_init(&tables); 2887 acpi_build(&tables, MACHINE(pcms)); 2888 2889 /* Now expose it all to Guest */ 2890 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2891 ACPI_BUILD_TABLE_FILE, 2892 ACPI_BUILD_TABLE_MAX_SIZE); 2893 assert(build_state->table_mr != NULL); 2894 2895 build_state->linker_mr = 2896 acpi_add_rom_blob(build_state, tables.linker->cmd_blob, 2897 "etc/table-loader", 0); 2898 2899 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2900 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2901 2902 vmgenid_dev = find_vmgenid_dev(); 2903 if (vmgenid_dev) { 2904 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, 2905 tables.vmgenid); 2906 } 2907 2908 if (!pcmc->rsdp_in_ram) { 2909 /* 2910 * Keep for compatibility with old machine types. 2911 * Though RSDP is small, its contents isn't immutable, so 2912 * we'll update it along with the rest of tables on guest access. 2913 */ 2914 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2915 2916 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2917 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2918 acpi_build_update, build_state, 2919 build_state->rsdp, rsdp_size, true); 2920 build_state->rsdp_mr = NULL; 2921 } else { 2922 build_state->rsdp = NULL; 2923 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2924 ACPI_BUILD_RSDP_FILE, 0); 2925 } 2926 2927 qemu_register_reset(acpi_build_reset, build_state); 2928 acpi_build_reset(build_state); 2929 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2930 2931 /* Cleanup tables but don't free the memory: we track it 2932 * in build_state. 2933 */ 2934 acpi_build_tables_cleanup(&tables, false); 2935 } 2936